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EtronTech
Features
* * * * * * * * Fast clock rate: 300/275/250/200MHz Differential Clock CK & /CK Bi-directional DQS DLL enable/disable by EMRS Fully synchronous operation Internal pipeline architecture Four internal banks, 1M x 16-bit for each bank Programmable Mode and Extended Mode registers - /CAS Latency: 3, 4 - Burst length: 2, 4, 8 - Burst Type: Sequential & Interleaved Individual byte write mask control DM Write Latency = 0 Auto Refresh and Self Refresh 4096 refresh cycles / 32ms Precharge & active power down Power supplies: VDD & VDDQ = 2.5V 5% Interface: SSTL_2 I/O Interface Package: 66 Pin TSOP II, 0.65mm pin pitch Lead-free Package is available.
EM6A9160
(Rev. 1.4 May/2006)
8M x 16 DDR Synchronous DRAM (SDRAM)
Pin Assignment (Top View)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BS0 BS1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
* * * * * * * * *
Ordering Information
Part Number EM6A9160TS-3.3/3.3G* EM6A9160TS-3.6/3.6G EM6A9160TS-4/4G EM6A9160TS-5/5G Clock Frequency 300MHz 275MHz 250MHz 200MHz Data Rate 600Mbps/pin 550Mbps/pin 500Mbps/pin 400Mbps/pin Package TSOP II TSOP II TSOP II TSOP II
Note : "G" indicates Pb-free package
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
Overview
EM6A9160
The EM6A9160 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits. It is internally configured as a quad 2M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and /CK. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM6A9160 provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, EM6A9160 features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications.
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Block Diagram
8Mx16 DDR SDRAM
EM6A9160
Column Decoder
Row Decoder Row Decoder Row Decoder Row Decoder
CK /CK CK /CS /RA /CA /WE
DLL CLOCK BUFFER
CONTROL SIGNAL GENERATOR
2Mx16 CELL ARRAY (BANK #0) Sense Amplifier
COMMAND DECODER
MODE REGISTER
Column Decoder 2Mx16 CELL ARRAY (BANK #1) Sense Amplifier
A10 or AP
COLUMN COUNTER
A0 to A11 BS0 BS1
ADDRESS BUFFER
Column Decoder 2Mx16 CELL ARRAY (BANK #2) Sense Amplifier
REFRESH COUNTER
LDQS UDQS
DATA STROBE BUFFER
DQ BUFFER
Column Decoder 2Mx16 CELL ARRAY (BANK #3) Sense Amplifier
DQ0 to DQ15 LDM UDM
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Pin Descriptions
Symbol CK, /CK Type Input
8Mx16 DDR SDRAM
EM6A9160
Table 1. Pin Details of EM6A9160 Description Differential Clock: CK, /CK are driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. Both CK and /CK increment the internal burst counter and controls the output registers. Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CK signal. If CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge). Chip Select: /CS enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when /CS is sampled HIGH. /CS provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The /RAS signal defines the operation commands in conjunction with the /CAS and /WE signals and is latched at the positive edges of CK. When /RAS and /CS are asserted "LOW" and /CAS is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the /WE signal. When the /WE is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the /WE is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Column Address Strobe: The /CAS signal defines the operation commands in conjunction with the /RAS and /WE signals and is latched at the positive edges of CK. When /RAS is held "HIGH" and /CS is asserted "LOW," the column access is started by asserting /CAS "LOW." Then, the Read or Write command is selected by asserting /WE "HIGH " or LOW"." Write Enable: The /WE signal defines the operation commands in conjunction with the /RAS and /CAS signals and is latched at the positive edges of CK. The /WE input is used to select the BankActivate or Precharge command and Read or Write command. Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. Data I/O: The DQ0-DQ15 input and output data are synchronized with the positive edges of CK and /CK. The I/Os are byte-maskable during Writes.
CKE
Input
BS0, BS1 A0-A11
Input Input
/CS
Input
/RAS
Input
/CAS
Input
/WE
Input
LDQS, UDQS LDM, UDM DQ0 - DQ15
Input / Output Input Input / Output
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VDD VSS VDDQ VSSQ VREF NC Supply Supply Supply Supply Supply Ground
8Mx16 DDR SDRAM
EM6A9160
Power Supply: +2.5V 5% DQ Power: +2.5V 5%. Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Reference Voltage for Inputs: +0.5*VDDQ No Connect: These pins should be left unconnected.
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Operation Mode
8Mx16 DDR SDRAM
EM6A9160
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command
BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set Extended MRS No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit
State Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Idle Idle Any Active(4) Any Idle Idle Idle
(SelfRefresh)
CKEn-1 CKEn UDM UDM BS0,1 A10 A0-9,11 /CS /RAS /CAS /WE H H H H H H H H H H H H H H L H L H L H X X X X X X X X X X X X H L H L H L H X X X X X X X X X X X X X X X X X X X X L X X X X X X X X X X X X X X X X X X X L X X X X X X X X X X X V V X V V V V Row address L H L H L H X X
Column address (A0 ~ A8) Column address (A0 ~ A8)
L L L L L L L L L
L L L H H H H L L H H X L L X H X H X H X V X H X X
H H H L L L L L L H H X L L X H X H X H X V X H X X
H L L L L H H L L H L X H H X H X H X H X V X H X X
OP code OP code X X X X X X X X X X X X X X X X X X X X X X
L L H L L H L H L H L H L H L X
Precharge Power Down Mode Entry Precharge Power Down Mode Exit Active Power Down Mode Entry Active Power Down Mode Exit
Idle Any
(PowerDown)
Active Any
(PowerDown)
Data Input Mask Disable Data Input Mask Enable(5)
Active
Active H X H H X X X X Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. LDM and UDM can be enable respectively.
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Mode Register Set (MRS)
8Mx16 DDR SDRAM
EM6A9160
The mode register is divided into various fields depending on functionality. Burst Length Field (A2~A0) * This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8. A2 0 0 0 0 1 1 1 1 * A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length Reserved 2 4 8 Reserved Reserved Reserved Reserved
Addressing Mode Select Field (A3) The Addressing Mode can be one of two modes, both Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode support burst length of 2,4 and 8. A3 0 1 Addressing Mode Sequential Interleave
--- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device. The internal column address is varied by the Burst Length as shown in the following table. Data n Column Address 0
n
1
n+1
2
n+2
3
n+3
4
n+4
5
n+5
6
n+6
7
n+7
2 words Burst Length 4 words 8 words Full Page (Even starting address) --- Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. Data n Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A7 A7 A7 A7 A7 A7 A7 A7 A6 A6 A6 A6 A6 A6 A6 A6 A5 A5 A5 A5 A5 A5 A5 A5 Column Address A4 A4 A4 A4 A4 A4 A4 A4 A3 A3 A3 A3 A3 A3 A3 A3 A2 A2 A2 A2 A1 A1 A0 A0# 4 words 8 words Burst Length
A1# A0 A1# A0# A0 A0#
A2# A1 A2# A1
A2# A1# A0 A2# A1# A0#
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*
8Mx16 DDR SDRAM
EM6A9160
CAS Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) CAS Latency X tCK A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved Reserved 3 clocks 4 clocks Reserved Reserved Reserved
*
Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. A8 0 1 X A7 0 0 1 BS0 0 1 Test Mode Normal mode DLL Reset Test mode An ~ A0 MRS Cycle Extended Functions (EMRS)
*
( BS0, BS1) BS1 RFU RFU
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8Mx16 DDR SDRAM
EM6A9160
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation. The extended mode register is written by asserting low on CS#, RAS#, CAS#, and WE#. The state of A0, A2 ~ A5, A7 ~ A11and BS1 is written in the mode register in the same cycle as CS#, RAS#, CAS#, and WE# going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BS0 is used for EMRS. Refer to the table for specific codes.
Extended Mode Resistor Bitmap
BS1 0 BS0 1 A11 A10 A9 A8 RFU must be set to "0" A7 A6 DS1 A5 A4 A3 A2 RFU must be set to "0" A1 DS0 A0 DLL
BS0 Mode 0 MRS 1 EMRS
A6 0 0 1 1
A1 Drive Strength Strength Comment 0 Full 100% 1 SSTL-2 weak 60% 0 RFU RFU Reserved For Future 1 Matched impedance 30% Output driver matches impedance
A0 DLL 0 Enable 1 Disable
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Absolute Maximum Rating
Symbol VIN, VOUT VDD, VDDQ TOPR TSTG TSOLDER PD IOUT Item
8Mx16 DDR SDRAM
EM6A9160
Rating
-3.3/3.6/4/5 -3.3G/3.6G/4G/5G
Unit V V C C 260 C W mA
Note 1 1 1 1 1 1 1
Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature Power Dissipation Short Circuit Output Current
- 0.3~ VDD + 0.3 - 0.3~3.6 0~70 - 55~150 245 1 50
Recommended D.C. Operating Conditions (Ta = 0 ~ 70 C)
Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input Reference Voltage Termination Voltage Input High Voltage (DC) Input Low Voltage (DC) Input Voltage Level, CLK and CLK# inputs Input leakage current Output leakage current Output High Voltage Output Low Voltage Symbol VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) II IOZ VOH VOL Min. 2.375 2.375 0.49* VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 -5 -5 VTT + 0.76 Max. 2.625 2.625 0.51* VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 5 5 VTT - 0.76 Unit V V V V V V V A A V V IOH = -15.2 mA IOL = +15.2 mA Note
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Symbol CIN CI/O Parameter Input Capacitance (CK pin) DQ, DQS, DM Capacitance
8Mx16 DDR SDRAM
EM6A9160
Unit pF pF pF
Capacitance (VDD = 2.5V, f = 1MHz, Ta = 25 C)
Min. 2.5 2.5 4 Max. 4 4 6.5 Input Capacitance (except for CK pin)
Note: These parameters are periodically sampled and are not 100% tested.
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Parameter & Test Condition
8Mx16 DDR SDRAM
EM6A9160
5
Recommended D.C. Operating Conditions (VDD = 2.5V 5%, Ta = 0~70 C)
Symbol 3.3 3.6 4 Max Unit Notes
OPERATING CURRENT : One bank; Active-Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles. OPERATING CURRENT : One bank; Active-ReadPrecharge; BL=4; CL=4; tRCDRD=4*tCK; tRC=tRC(min); tCK=tCK(min); lout=0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; tCK=tCK(min); CKE=LOW IDLE STANDLY CURRENT : CKE = HIGH; CS#=HIGH(DESELECT); All banks idle; tCK=tCK(min); Address and control inputs changing once per clock cycle; VIN=VREF for DQ, DQS and DM ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; power-down mode; CKE=LOW; tCK=tCK(min) ACTIVE STANDBY CURRENT : CS#=HIGH;CKE=HIGH; one bank active ; tRC=tRC(max);tCK=tCK(min);Address and control inputs changing once per clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle OPERATING CURRENT BURST READ : BL=2; READS; Continuous burst; one bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); lout=0mA;50% of data changing on every transfer OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous Burst ;one bank active; address and control inputs changing once per clock cycle; tCK=tCK(min); DQ,DQS,and DM changing twice per clock cycle; 50% of data changing on every transfer AUTO REFRESH CURRENT : tRC=tRFC(min); tCK=tCK(min) SELF REFRESH CURRENT: Sell Refresh Mode ; CKE<=0.2V;tCK=tCK(min) BURST OPERATING CURRENT 4 bank operation: Four bank interleaving READs; BL=4;with Auto Precharge; tRC=tRC(min); tCK=tCK(min); Address and control inputschang only during Active, READ , or WRITE command
IDD0
200 180 160 140 mA
IDD1
220 200 180 160 mA
IDD2P
50
45
40
35 mA
IDD2N 110 100
90
80 mA
IDD3P
50
45
40
35 mA
IDD3N 120 110 100
90 mA
IDD4R 340 310 280 250 mA
IDD4W 280 260 240 220 mA
IDD5 IDD6
270 250 230 210 mA 2 2 2 2 mA
IDD7
440 400 360 330 mA
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Symbol Parameter Clock cycle time Clock high level width Clock low level width DQS-out access time from CK,CK# Output access time from CK,CK# DQS-DQ Skew Read preamble Read postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS write postamble DQS in high level pulse width DQS in low level pulse width Address and Control input setup time Address and Control input hold time DQ & DM setup time to DQS DQ & DM hold time to DQS Clock half period Output DQS valid window Row cycle time Refresh row cycle time Row active time RAS# to CAS# Delay in Read RAS# to CAS# Delay in Write Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. Address to Col. Address delay Mode register set cycle time Auto precharge write recovery + Precharge Self refresh exit to read command delay Power down exit time Refresh interval time CL = 3 CL = 4 Min 3.3 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.35 0.35 tCLMIN or tCHMIN tHP 0.35 15 17 10 5 3 5 3 3 3 1 2 8 200 tCK + tIS -
8Mx16 DDR SDRAM
EM6A9160
5.0
Electrical AC Characteristics (VDD = 2.5 5%, Ta = 0~70 C)
3.3 Max 10 0.55 0.55 0.6 0.6 0.35 1.1 0.6 1.15 0.6 0.6 0.6 100K 7.8 Min 3.6 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLMIN or tCHMIN tHP 0.4 15 17 10 5 3 5 3 3 2 1 2 8 200 tCK + tIS 3.6 Max 10 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 100K 7.8 Min 4 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLMIN or tCHMIN tHP 0.4 13 15 9 4 2 4 3 3 2 1 2 7 200 tCK + tIS 4.0 Max 10 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 100K 7.8 Min 5 0.45 0.45 -0.7 -0.7 0.9 0.4 0.85 0 0.3 0.4 0.4 0.4 1.0 1.0 0.45 0.45 tCLMIN or tCHMIN tHP 0.45 12 14 8 4 2 4 3 3 2 1 2 7 200 tCK + tIS Max 10 0.55 0.55 0.7 0.7 0.45 1.1 0.6 1.15 0.6 0.6 0.6 100K 7.8 Unit
tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQH tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD twR tCDLR tCCD tMRD tDAL tXSA tPDEX tREF
ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns ns tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns us
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Parameter Input High Voltage (DC) Input Low Voltage (DC) Input Different Voltage, CLK and CLK# inputs Input Crossing Point Voltage, CLK and CLK# inputs
8Mx16 DDR SDRAM
EM6A9160
Recommended A.C. Operating Conditions (VDD = 2.5 5%, Ta = 0~70 C)
Symbol VIH (AC) VIL (AC) VID (AC) VIX (AC) 0.7 0.5*VDDQ-0.2 Min. VREF + 0.35 VREF - 0.35 VDDQ + 0.6 0.5*VDDQ+0.2 Max. Unit V V V V Note
Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. Power-up sequence is described in Note 6. 5. A.C. Test Conditions
SSTL_2 Interface
Reference Level of Output Signals (VRFE) Output Load Input Signal Levels Input Signals Slew Rate Reference Level of Input Signals 0.5 * VDDQ Reference to the Under Output Load (A) VREF+0.35 V / VREF-0.35 V 1 V/ns 0.5 * VDDQ
0.5*VDDQ
25
25 Output
30pF
SSTL_2 A.C. Test Load
6.
Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and maintain CKE "LOW". Power applied to VDDQ the same time as VTT and VREF.
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4) Issue EMRS - enable DLL.
8Mx16 DDR SDRAM
EM6A9160
2) After power-up, No-Operation of 200 -seconds minimum is required. 3) Start clock and keep CKE "HIGH" to maintain either No-Operation or Device Deselect at the input. 5) Issue MRS - reset DLL and set device to idle with bit A8 (An additional 200 cycles min of clock are needed for DLL lock) 6) Precharge all banks of the device. 7) Two or more Auto Refresh commands. 8) Issue MRS - Initialize device operation.
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Timing Waveforms
8Mx16 DDR SDRAM
EM6A9160
Figure 1. AC Parameters for Write Timing (Burst Length=4)
CK
/CK
CMD
Write
ADDR
/CS
DQ
D0
D1
D2
D3
tDH tWPRES tDS tDSL tDSH tWPST
tDQSS
DQS
Preamble
Postamble
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8Mx16 DDR SDRAM
EM6A9160
Figure 2. Read Command to Output Data Latency (Burst Length=2)
CK
/CK
CMD CL=2 DQ
Read
DA0
DA1
DQS
Postamble Preamble
CL=2.5 DQ
DA0 DA1
Postamble
DQS
Preamble
CL=3 DQ
DA0 DA1
Postamble
DQS
Preamble
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8Mx16 DDR SDRAM
EM6A9160
Figure 3. Read Followed by Write (Burst Lenth=4, CAS Latency=3)
CK /CK
tRRD tRCDR
Activate
CMD
Read
ACT
Write
ADDR
Row/Bank0 Col/Bank0 Rol/Bank1 Col/Bank0
/CS
DQ
D0
D1
D2
D3
DQS
Preamble Postamble
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8Mx16 DDR SDRAM
EM6A9160
Figure 4. Write followed by Read (Burst Lenth=4, CAS Latency=3)
CK
/CK
tWTR
CMD
Write
Read
ADDR
Col
Col
/CS
DQ
D0
D1
D2
D3
D0
D1
D2 D3
DQS
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8Mx16 DDR SDRAM
EM6A9160
Figure 5. Precharge Termination of a Burst Read (Burst Length=4, CAS Latency=3)
CK
/CK Precharge CMD Read ACT
ADDR
Col
Bank
Bank
/CS
tRP
DQ D0 D1
DQS
Preamble Postamble
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CK /CK
8Mx16 DDR SDRAM
EM6A9160
Figure 6. Precharge Termination of a Burst Write (Burst Length=4)
tRC
Activate Write Precharge Activate
CMD
ADDR
Row/Bank Col/Bank Row/Bank Row/Bank
/CS
tRCD
DQM
tWR tDS
tRP
tQDH tRAS
DQ
D0
D1
masked by DQM
DQS
Preamble Postamble
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8Mx16 DDR SDRAM
EM6A9160
Figure 7. Auto Precharge after Read Burst (CAS Latency=3)
CK /CK
tRP
BL=2 CMD
ReadA Auto Precharge ACT
DQ
D0
D1
tRP
BL=4 CMD
ReadA Auto Precharge ACT
DQ
D0
D1
D2
D3
tRP
BL=8 CMD
ReadA Auto Precharge ACT
DQ
D0
D1
D2
D3 D4 D5
D6
D7
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8Mx16 DDR SDRAM
EM6A9160
Figure 8. Auto Precharge after Write Burst
CK
/CK BL=2 CMD
WriteA
Auto Precharge ACT tWR tRP
DQ
D0 D1
Preamble
DQS
Postamble
BL=4 CMD
WriteA
Auto Precharge ACT tWR tRP
DQ
D0 D1 D2
D3
Preamble
DQS BL=8 CMD
Postamble
WriteA
Auto Precharge ACT tWR tRP
DQ
D0 D1
D2 D3
D4 D5
D6 D7
Preamble
DQS
Postamble
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8Mx16 DDR SDRAM
EM6A9160
Figure 9. Read Terminated By Burst Stop (Burst Length=8)
CK
/CK
CMD
Read
BST
ADDR
Col
/CS
CL=3 DQ
D0 D1 D2 D3
DQS
24
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 10. Read Terminated by Read (Burst Length=4, CAS Latency=3)
CK /CK
tCCD
CMD
Read Read
ADDR
Col A
Col B
/CS
DQ
DA0
DA1
DB0
DB1
DB2
DB3
DQS
25
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 11. Mode Register Set Command
CK
/CK
tRP
CMD
Precharge MRS
1 clk
ACT
ADDR
MRS Data
Row
/CS
26
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 12. Active / Precharge Power Down Mode
CK
/CK
tIS
CKE
tPDEX
CMD Activate / Precharge Note 1,2
Any Command
Note:
1. All banks should be in idle state prior to entering precharge power down mode. 2. One of the banks should be in active state prior to entering active power down mode.
27
Rev. 1.4
May 2006
EtronTech
8Mx16 DDR SDRAM
EM6A9160
Figure 13. Self Refresh Entry and Exit Cycle
CK /CK
Self Refresh Enter CMD
Auto Refresh
NOP
tRC
CKE
tIS
Self Refresh Exit
tRC is required before any command can be applied, and 200 cycles of clk are required before a READ command can be applied.
28
Rev. 1.4
May 2006
EtronTech
22.22 0.13 66
8Mx16 DDR SDRAM
EM6A9160
66 Pin TSOP II Package Outline Drawing Information Units: mm
34
0.085 0.125 + 0.005 -
10.16 0.13
11.76 0.20
1
33
1.00 0.10
1.20 MAX
0.5 0.1 0~8 0.05 MIN 0.71 TYP 0.65 TYP 0.30 0.08 0.10 MAX 0.25 TYP
29
Rev. 1.4
May 2006
0.8 TYP

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