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OXMPCI954 DATA SHEET
FEATURES
*
Integrated High Performance Quad UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.
* * * * * * * * * * * * * * Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR# Arbitrary trigger levels for receiver and transmitter FIFO interrupts and automatic in-band and out-of-band flow control Infra-red (IrDA) receiver and transmitter operation 9-bit data framing, as well as 5,6,7 and 8 bits Detection of bad data in the receiver FIFO Global Interrupt Status and readable FIFO levels to facilitate implementation of efficient device drivers. Local registers to provide status/control of device functions. 12 multi-purpose I/O pins, which can be configured as input interrupt pins or `wake-up'. Auto-detection of a wide range of optional MicrowireTM compatible EEPROMs, to re-configure device parameters. Function access, to pre-configure each function prior to handover to generic device drivers. Operation via IO or memory mapping. 3.3V operation (5v tolerance on selected I/Os) Extended Operating Temp. Range : -40C to 105C 160-pin LQFP or 176-pin VBGA package
* * * * * * * * * * *
Software compatible with OX16PCI954 Four 16C950 High performance UART channels 8-bit Pass-through Local Bus (PCI Bridge) IEEE1284 Compliant SPP/EPP/ECP parallel port (with external transceiver) Efficient 32-bit, 33MHz, Multi-function target-only PCI controller, fully compliant to PCI Local Bus specification 3.0, and PCI Power Management Specification 1.1 PCI and miniPCI Modes (with CLKRUN# and D3cold support in miniPCI modes) UARTs fully software compatible with 16C550-type devices. UART operation up to 60 MHz via external clock source. Up to 20MHz with the crystal oscillator. Baud rates up to 60Mbps in external 1x clock mode and 15Mbps in asynchronous mode. 128-byte deep FIFO per transmitter and receiver Flexible clock prescaler, from 1 to 31.875 Automated in-band flow control using programmable Xon/Xoff in both directions
DESCRIPTION
The OXMPCI954 is a single chip solution for PCI and miniPCI based serial and parallel expansion add-in cards. It is a dual function PCI device, where function 0 offers four ultra-high performance OX16C950 UARTs, and function 1 is configurable either as an 8-bit Local Bus or a bidirectional parallel port. Each UART channel in the OXMPCI954 is the fastest available PC-compatible UART, offering data rates up to 15Mbps and 128-byte deep transmitter and receiver FIFOs. The deep FIFOs reduce CPU overhead and allow utilisation of higher data rates. Each UART channel is software compatible with the widely used industry-standard 16C550 devices (and compatibles), as well as the OX16C95x family of high performance UARTs. In addition to increased performance and FIFO size, the UARTs also provide the full set of OX16C95x enhanced features including automated in-band flow control, readable FIFO levels etc. To enhance device driver efficiency and reduce interrupt latency, internal UARTs have multi-port features such as shadowed FIFO fill levels, a global interrupt source register and Good-Data Status, readable in four adjacent DWORD registers visible to logical functions in I/O space and memory space. Expansion of serial cards beyond four channels is possible using the 8-bit pass-through Local Bus function. The addressable space can be increased up to 256 bytes, and divided into four chip-select regions. This flexible expansion scheme caters for cards with up to 20 serial ports using external 16C950, 16C952, 16C954 or compatible devices, or composite applications such as combined serial and parallel port expansion cards. Serial port cards with up to 20 ports (or with 4 serial ports and a parallel port) can be designed without redefining any device or timing parameters. The parallel port is an IEEE 1284 compliant SPP/EPP/ ECP parallel port that fully supports the existing Centronics interface. The parallel port can be enabled in place of the Local Bus. An external bus transceiver is required for 5V parallel port operation. For applications that do not require the local bus, or the parallel port, card designers can assign a Subsystem Vendor ID and a Subsystem ID directly using 32 input pins. For full flexibility, all the default configuration register values can be overwritten using an optional MicrowireTM compatible serial EEPROM. This EEPROM can also be used to provide function access to pre-configure each UART into enhanced modes or pre-configure devices on the local bus/parallel port, prior to any PCI configuration accesses and before control is handed to (generic) device drivers.
Oxford Semiconductor Ltd. External--Free Release 25 Milton Park, Abingdon, Oxon, OX14 4SH, UK Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141
(c) Oxford Semiconductor 2005 OXMPCI954 DataSheet DS-0019 - June 2005
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OXMPCI954
REVISION HISTORY
REV 0.0 0.1 1.0 1.1 Jan 2005 Jun 2005 DATE 17/12/2002 11/02/2003 23/06/2003 07/08/2003 12/1/2005 8/6/2005 REASON FOR CHANGE / SUMMARY OF CHANGE Preliminary DataSheet Revised Pin-out, Chip-naming Specified all device modes and added features supported by the device. Added Extended Operating temperature range of -40C to 105C. Corrected Pin Information Diagram for the SUBVEN ID mode. Revisions for additional 176-pin BGA layout (was 160-pin flat pack) Revision for additional green order code for 160-pin LQFP layout
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TABLE OF CONTENTS
1 2 3 4
4.1 4.2 4.3
PERFORMANCE COMPARISON.......................................................................................................... 6 OXMPCI954 DEVICE MODES............................................................................................................... 8 BLOCK DIAGRAM ................................................................................................................................ 9 PIN INFORMATION--160-PIN LQFP .................................................................................................. 10
MODES (SOFTWARE) BACKWARDS COMPATIBLE WITH THE OX16PCI954. .......................................................... 10 ENHANCED MODES OF OPERATION........................................................................................................................... 11 PIN DESCRIPTIONS......................................................................................................................................................... 12 MODES (SOFTWARE) BACKWARDS COMPATIBLE WITH THE OX16PCI954. .......................................................... 19 ENHANCED MODES OF OPERATION........................................................................................................................... 21 PIN DESCRIPTIONS......................................................................................................................................................... 23
5
5.1 5.2 5.3
PIN INFORMATION--176-PIN VBGA ................................................................................................. 19
6 7
7.1 7.2 7.2.1 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.5 7.6 7.6.1 7.6.2 7.7 7.8 7.9 7.10
CONFIGURATION & OPERATION ..................................................................................................... 30 PCI TARGET CONTROLLER.............................................................................................................. 31
OPERATION ..................................................................................................................................................................... 31 CONFIGURATION SPACE ............................................................................................................................................... 31 PCI CONFIGURATION SPACE REGISTER MAP........................................................................................................ 32 ACCESSING LOGICAL FUNCTIONS .............................................................................................................................. 35 PCI ACCESS TO INTERNAL UARTS........................................................................................................................... 35 PCI ACCESS TO 8-BIT LOCAL BUS............................................................................................................................ 36 PCI ACCESS TO PARALLEL PORT ............................................................................................................................ 37 ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 38 LOCAL CONFIGURATION AND CONTROL REGISTER `LCC' (OFFSET 0X00) ........................................................ 38 MULTI-PURPOSE I/O CONFIGURATION REGISTER `MIC' (OFFSET 0X04) ............................................................ 39 LOCAL BUS TIMING PARAMETER REGISTER 1 `LT1' (OFFSET 0X08): .................................................................. 41 LOCAL BUS TIMING PARAMETER REGISTER 2 `LT2' (OFFSET 0X0C): ................................................................. 42 UART RECEIVER FIFO LEVELS `URL' (OFFSET 0X10)............................................................................................. 44 UART TRANSMITTER FIFO LEVELS `UTL' (OFFSET 0X14)...................................................................................... 44 UART INTERRUPT SOURCE REGISTER `UIS' (OFFSET 0X18)............................................................................... 44 GLOBAL INTERRUPT STATUS AND CONTROL REGISTER `GIS' (OFFSET 0X1C) ................................................ 45 PCI INTERRUPTS............................................................................................................................................................. 47 POWER MANAGEMENT .................................................................................................................................................. 48 POWER MANAGEMENT OF FUNCTION 0 ................................................................................................................. 48 POWER MANAGEMENT OF FUNCTION 1 ................................................................................................................. 49 UNIQUE BAR OPTION - FOR FUNCTION 0 ................................................................................................................... 51 MINIPCI SUPPORT - ENHANCED MODES ONLY ......................................................................................................... 52 STANDALONE MODE ...................................................................................................................................................... 56 DEVICE DRIVERS ............................................................................................................................................................ 59 OPERATION - MODE SELECTION ................................................................................................................................. 60 450 MODE..................................................................................................................................................................... 60 550 MODE..................................................................................................................................................................... 60 EXTENDED 550 MODE ................................................................................................................................................ 60 750 MODE..................................................................................................................................................................... 60 650 MODE..................................................................................................................................................................... 60 950 MODE..................................................................................................................................................................... 61 REGISTER DESCRIPTION TABLES ............................................................................................................................... 62 RESET CONFIGURATION ............................................................................................................................................... 66 HARDWARE RESET .................................................................................................................................................... 66 External--Free Release Page 3
8
8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.2 8.3 8.3.1
INTERNAL OX16C950 UARTS ........................................................................................................... 60
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8.3.2 SOFTWARE RESET ..................................................................................................................................................... 66 8.4 TRANSMITTER & RECEIVER FIFOS .............................................................................................................................. 67 8.4.1 FIFO CONTROL REGISTER `FCR' .............................................................................................................................. 67 8.5 LINE CONTROL & STATUS............................................................................................................................................. 68 8.5.1 FALSE START BIT DETECTION.................................................................................................................................. 68 8.5.2 LINE CONTROL REGISTER `LCR'............................................................................................................................... 68 8.5.3 LINE STATUS REGISTER `LSR' .................................................................................................................................. 69 8.6 INTERRUPTS & SLEEP MODE........................................................................................................................................ 70 8.6.1 INTERRUPT ENABLE REGISTER `IER'....................................................................................................................... 70 8.6.2 INTERRUPT STATUS REGISTER `ISR'....................................................................................................................... 71 8.6.3 INTERRUPT DESCRIPTION ........................................................................................................................................ 71 8.6.4 SLEEP MODE ............................................................................................................................................................... 72 8.7 MODEM INTERFACE ....................................................................................................................................................... 72 8.7.1 MODEM CONTROL REGISTER `MCR'........................................................................................................................ 72 8.7.2 MODEM STATUS REGISTER `MSR' ........................................................................................................................... 73 8.8 OTHER STANDARD REGISTERS ................................................................................................................................... 73 8.8.1 DIVISOR LATCH REGISTERS `DLL & DLM'................................................................................................................ 73 8.8.2 SCRATCH PAD REGISTER `SPR' ............................................................................................................................... 73 8.9 AUTOMATIC FLOW CONTROL....................................................................................................................................... 74 8.9.1 ENHANCED FEATURES REGISTER `EFR'................................................................................................................. 74 8.9.2 SPECIAL CHARACTER DETECTION .......................................................................................................................... 75 8.9.3 AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 75 8.9.4 AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 75 8.10 BAUD RATE GENERATION............................................................................................................................................. 76 8.10.1 GENERAL OPERATION ............................................................................................................................................... 76 8.10.2 CLOCK PRESCALER REGISTER `CPR'...................................................................................................................... 76 8.10.3 TIMES CLOCK REGISTER `TCR'................................................................................................................................. 76 8.10.4 EXTERNAL 1X CLOCK MODE..................................................................................................................................... 78 8.10.5 CRYSTAL OSCILLATOR CIRCUIT .............................................................................................................................. 78 8.11 ADDITIONAL FEATURES ................................................................................................................................................ 78 8.11.1 ADDITIONAL STATUS REGISTER `ASR' .................................................................................................................... 78 8.11.2 FIFO FILL LEVELS `TFL & RFL' ................................................................................................................................... 79 8.11.3 ADDITIONAL CONTROL REGISTER `ACR'................................................................................................................. 79 8.11.4 TRANSMITTER TRIGGER LEVEL `TTL' ...................................................................................................................... 80 8.11.5 RECEIVER INTERRUPT. TRIGGER LEVEL `RTL' ...................................................................................................... 80 8.11.6 FLOW CONTROL LEVELS `FCL' & `FCH' .................................................................................................................... 80 8.11.7 DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 80 8.11.8 CLOCK SELECT REGISTER `CKS'.............................................................................................................................. 81 8.11.9 NINE-BIT MODE REGISTER `NMR' ............................................................................................................................. 81 8.11.10 MODEM DISABLE MASK `MDM' .................................................................................................................................. 82 8.11.11 READABLE FCR `RFC'................................................................................................................................................. 82 8.11.12 GOOD-DATA STATUS REGISTER `GDS'.................................................................................................................... 82 8.11.13 PORT INDEX REGISTER `PIX'..................................................................................................................................... 82 8.11.14 CLOCK ALTERATION REGISTER `CKA' ..................................................................................................................... 83
9
9.1 9.2 9.3
LOCAL BUS ........................................................................................................................................ 84
OVERVIEW ....................................................................................................................................................................... 84 OPERATION ..................................................................................................................................................................... 84 CONFIGURATION & PROGRAMMING............................................................................................................................ 85
10
10.1 OPERATION AND MODE SELECTION ........................................................................................................................... 86 10.1.1 SPP MODE ................................................................................................................................................................... 86 10.1.2 PS2 MODE.................................................................................................................................................................... 86 10.1.3 EPP MODE ................................................................................................................................................................... 86 10.1.4 ECP MODE ................................................................................................................................................................... 86 10.2 PARALLEL PORT INTERRUPT ....................................................................................................................................... 87 DS-0019 Jun 05 External--Free Release Page 4
BIDIRECTIONAL PARALLEL PORT............................................................................................... 86
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10.3 REGISTER DESCRIPTION............................................................................................................................................... 88 10.3.1 PARALLEL PORT DATA REGISTER `PDR' ................................................................................................................. 88 10.3.2 ECP FIFO ADDRESS / RLE ......................................................................................................................................... 88 10.3.3 DEVICE STATUS REGISTER `DSR' ............................................................................................................................ 88 10.3.4 DEVICE CONTROL REGISTER `DCR'......................................................................................................................... 89 10.3.5 EPP ADDRESS REGISTER `EPPA' ............................................................................................................................. 89 10.3.6 EPP DATA REGISTERS `EPPD1-4' ............................................................................................................................. 89 10.3.7 ECP DATA FIFO ........................................................................................................................................................... 89 10.3.8 TEST FIFO .................................................................................................................................................................... 89 10.3.9 CONFIGURATION A REGISTER ................................................................................................................................. 89 10.3.10 CONFIGURATION B REGISTER ................................................................................................................................. 89 10.3.11 EXTENDED CONTROL REGISTER `ECR'................................................................................................................... 90
11
11.1 SPECIFICATION ............................................................................................................................................................... 91 11.1.1 ZONE 0: HEADER ........................................................................................................................................................ 92 11.1.2 ZONE 1: LOCAL CONFIGURATION REGISTERS....................................................................................................... 93 11.1.3 ZONE 2: IDENTIFICATION REGISTERS ..................................................................................................................... 94 11.1.4 ZONE 3: PCI CONFIGURATION REGISTERS ............................................................................................................ 94 11.1.5 ZONE 4 : POWER MANAGEMENT DATA (AND DATA_SCALE ZONE) ............................................................. 95 11.1.6 ZONE 5 : FUNCTION ACCESS .................................................................................................................................... 95
SERIAL EEPROM ............................................................................................................................ 91
12
12.1
OPERATING CONDITIONS ............................................................................................................. 97
DC ELECTRICAL CHARACTERISTICS .......................................................................................................................... 97
13
13.1 13.2 13.3
AC ELECTRICAL CHARACTERISTICS.......................................................................................... 99
PCI BUS ............................................................................................................................................................................ 99 LOCAL BUS...................................................................................................................................................................... 99 SERIAL PORTS .............................................................................................................................................................. 101
14 15
15.1 15.2
TIMING WAVEFORMS................................................................................................................... 102 PACKAGE INFORMATION............................................................................................................ 117
160-PIN LQFP................................................................................................................................................................. 117 176-PIN VBGA ................................................................................................................................................................ 118
16
ORDERING INFORMATION .......................................................................................................... 119
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1
PERFORMANCE COMPARISON
Feature Internal serial channels Integral IEEE 1284 EPP/ECP parallel port Multi-function PCI device Support for PCI Power Management Zero wait-state write operation No. of available Local Bus interrupt pins DWORD access to UART Interrupt Source Registers & FIFO Levels Good-Data status Full Plug and Play with external EEPROM Subsystem Vendor ID & Subsystem ID with no external EEPROM External 1x baud rate clock Max baud rate in normal mode Max baud rate in 1x clock mode FIFO depth Sleep mode Auto Xon/Xoff flow Auto CTS#/RTS# flow Auto DSR#/DTR# flow No. of Rx interrupt thresholds No. of Tx interrupt thresholds No. of flow control thresholds Transmitter empty interrupt Readable status of flow control Readable FIFO levels Clock prescaler options Rx/Tx disable Software reset Device ID 9-bit data frames RS485 buffer enable Infra-red (IrDA)
OXMPCI954
4 yes yes yes yes1 12 yes yes yes yes yes 15 Mbps 60 Mbps 128 yes yes yes yes 128 128 128 yes yes yes 248 yes yes yes yes yes yes
16C554 + PCI Bridge 0 no no no no 2 no no yes no no 115 Kbps n/a 16 no no no no 4 1 n/a no no no n/a no no no no no no
16C654 + PCI Bridge 0 no no no no 2 no no yes no no 1.5 Mbps n/a 64 yes yes yes no 4 4 4 no no no 2 no no no no no yes
Table 1: OXMPCI954 performance compared with PCI Bridge + generic UART combinations
Note 1: Zero wait-state applies only to the internal UARTs (after the assertion of DEVSEL#). Read operation incurs 1 wait state.
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OXMPCI954
Improvements of the OXMPCI954 over discrete solutions
Higher degree of integration: The OXMPCI954 device offers four internal 16C950 highperformance UARTs and an 8-bit Local Bus or a Bi-directional parallel port. Multi-function device: The OXMPCI954 is a multi-function device to enable users to load individual device drivers for the internal serial ports, drivers for the peripheral devices connected to the Local Bus or drivers for the internal parallel port. Quad Internal OX16C950 UARTs The OXMPCI954 device contains four ultra-high performance UARTs, which can increase driver efficiency by using features such as the 128-byte deep transmitter & receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt and flow control trigger levels and readable FIFO levels. Data rates are up to 60Mbps. Improved access timing: Access to the internal UARTs, require zero or one PCI wait states. A PCI read transaction from an internal UART can complete within five PCI clock cycles and a write transaction to an internal UART can complete within four PCI clock cycles. Reduces interrupt latency: The OXMPCI954 device offers shadowed FIFO levels and Interrupt status registers of the internal UARTs, and the MIO pins. This reduces the device driver interrupt latency. Power management: The OXMPCI954 device complies with the PCI Power Management Specification 1.1 and the Microsoft Communications Device-class Power Management Specification 2.0 (2000). Both functions offer the extended capabilities for Power Management. This achieves significant power savings by enabling device drivers to power down the PCI functions. For function 0, this is through switching off the channel clock, in power state D3. Wake-up (PME# generation) can be requested by either functions. For function 0, this is via the RI# inputs of the UARTs in the power-state D3 or any modem line and SIN inputs of the UARTs in power-state D2. For function 1, this is via the MIO[2] input. Optional EEPROM: The OXMPCI954 device can be reconfigured from an external EEPROM, to the end-user's requirements. However, this is not normally required in many applications as the default values are sufficient for typical applications. An overrun detection mechanism built into the eeprom controller prevents the PCI system from `hanging' due to an incorrectly programmed eeprom. Subsystem ID and Subsystem Vendor ID In some cases the Subsystem ID and Subsystem Vendor ID can be set via input pins.
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2
OXMPCI954 DEVICE MODES
The OXMPCI954 supports several modes of operation. 3 modes of the device are (software) backwards compatible with the OX16PCI954 device. There are a further 3 modes that are enhanced modes, which offer additional features over those available in the backwards compatible modes. Then, there is a standalone mode that allows a synchronous local bus access to the internal UARTs, without any form of PCI transactions. These modes are summarized in the following table. Device Mode 000 001 010 011 100 101 110 111 Mode Pin Selection MODE(2:0) = 000 MODE(2:0) = 001 MODE(2:0) = 010 MODE(2:0) = 011 MODE(2:0) = 100 MODE(2:0) = 101 MODE(2:0) = 110 MODE(2:0) = 111 Functionality Function 0 : QUAD Uarts Function 1 : 8-bit Local Bus Function 0 : QUAD Uarts Function 1 : Parallel Port Function 0 : QUAD Uarts Subsys ID/Subsys Vendor ID via Device Pins Function 0 : QUAD Uarts (Unique BARs) Function 1 : 8-bit Local Bus Function 0 : QUAD Uarts Function 1 : 8-bit Local Bus Function 0 : QUAD Uarts Function 1 : Parallel Port TestMode (Reserved). Standalone Mode Backwards Compatible / Enhanced Modes Backwards Compatible* Backwards Compatible* Backwards Compatible* Enhanced Mode Enhanced Mode Enhanced Mode N/A N/A
* The OXMPCI954 is not a direct `drop-in' replacement part for the OX16PCI954 owing to a small pinout change and voltage. The device is only S/W compatible.
In the Enhanced Modes, the following additional features are made available over the underlying functionality of the device.
*
* * *
* * *
Pin 88/M15 (MIO[11]) is re-defined as a PCI/miniPCI Mode Selection Pin. Functionality normally associated with the pin MIO[11] is no longer available. This results in the pins MIO[10:0] serving as Multi-purpose I/O pins. All Function 0 and Function 1 interrupts assert on the INTA# pin (by default). Local Registers provide additional Controls and Status Indication. Function 0 option to allow each UART to be separately addressable via its own Base Address Register (in I/O Space) This option can be exercised by the device pins (MODE 011) or by using the external EEPROM to set a specified field in the local registers. Function 0 and Function 1 Power Management Registers indicate Compatibility to Power Management Specification 1.1 Each function implements Power Management Data/Data Scale fields, returning user defined data. Availability of 2 Additional EEPROM Zones : The Power Management Data Zone and The Function Access Zone. Specifically for MiniPCI Selection (Pin 88/M15 = `1' in Enhanced Modes) * Device pin INTB#' is re-defined as a CLKRUN# pin. Compliant to PCI Mobile Design Guide revision 1.1 For PCI modes (Pin 88/M15 = `0' in Enhanced Modes) INTB# is an unused PCI interrupt line. * Device supports PME# generation from the D3cold state and preserves PME# context. This is compliant to Mini PCI Specification, revision 1.0
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3
BLOCK DIAGRAM
MODE[2:0] FIFOSEL MIO[11]* Config. Interface SOUT{3:0] SIN[3:0]
* MIO[11] is a mode selection pin, in the Enhanced Mode.
Function 0 Quad UARTs
RTS[3:0] DTR{3:0] CTS{3:0] DSR{3:0]
AD[31:0] C/BE[3:0]#
Interface Data / Control Bus
DCD{3:0] RI{3:0]
PCI_CLK FRAME# DEVSEL# IRDY# TRDY# STOP# PAR SERR# PERR# IDSEL RESET# INTA# INTB#/CLKRUN# PME# PCI (miniPCI) Interface
Interrupt Logic
MIO Pins
MIO[11:0]*
PD[7:0]
ACK# PE BUSY Parallel Port SLCT ERR# SLIN# INIT# AFD# XTLI XTLO Clock & Baud Rate Generator STB#
Function 1
UART_Clk_Out Local_Bus Clk
LBA7:0] LBCS[3:0] LBD[7:0] Local Bus LBWR#
EE_DI EEPROM Interface
EE_CS EE_CK EE_DO
LBRD# LBRST
DATA_DIR
OXMPCI954 Block Diagram
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4
4.1
PIN INFORMATION--160-PIN LQFP
Modes (Software) Backwards Compatible with the OX16PCI954. Mode `001': Quad UARTs + Parallel Port
MODE[2:0] = 001
SLCT ERR# VDD GND NC NC NC NC NC NC VDD GND NC SLIN# INIT# AFD# STB# GND PDOUT PD0 PD1 PD2 PD3 VDD GND PD4 PD5 PD6 PD7 MIO8 MIO9 MIO10 MIO11 SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3# 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Mode `000': Quad UARTs + 8-bit Local Bus
MODE[2:0] = 000
LBA2 LBA3 VDD GND LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# VDD GND LBCLK LBA4 LBA5 LBA6 LBA7 GND LBDOUT LBD0 LBD1 LBD2 LBD3 VDD GND LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 MIO11 SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3# 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
LBA1 LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# INTB# RST# GND CLK PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND AD25 AD24 C/BE3# IDSEL AD23 AD22 GND VDD AD21 AD20 AD19 VDD GND AD18
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
OXMPCI954-LQ-A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# VDD UART_Ck_Out GND SIN2 SIN1 RI1# DCD1# VDD XTLO XTLI GND DSR1# CTS1# DTR1# RTS1# VDD GND SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 Mode2 EE_DI EE_CK
BUSY PE ACK# NC MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 NC INTA# INTB# RST# GND CLK PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND AD25 AD24 C/BE3# IDSEL AD23 AD22 GND VDD AD21 AD20 AD19 VDD GND AD18
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
OXMPCI954-LQ-A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# VDD UART_Ck_Out GND SIN2 SIN1 RI1# DCD1# VDD XTLO XTLI GND DSR1# CTS1# DTR1# RTS1# VDD GND SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 TEST EE_DI EE_CK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL # GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 GND VDD AD13 AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO
9 NC. Do not connect these pins: 108,111,112,113,114,115,116,124,132
Mode `010': Quad UARTs + Pin Assignable SubSystem ID / Subsystem Vendor ID
MODE[2:0] = 010
Sub_V_ID2 Sub_V_ID3 VDD GND Sub_ID12 Sub_ID13 Sub_ID14 Sub_ID15 NC NC VDD GND NC Sub_V_ID4 Sub_V_ID5 Sub_V_ID6 Sub_V_ID7 GND NC Sub_V_ID8 Sub_V_ID9 Sub_V_ID10 Sub_V_ID11 VDD GND Sub_V_ID12 Sub_V_ID13 Sub_V_ID154 Sub_V_ID15 Sub_ID8 Sub_ID9 Sub_ID10 Sub_ID11 SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Sub_V_ID1 Sub_V_ID0 NC NC Sub_ID7 Sub_ID6 Sub_ID5 Sub_ID4 Sub_ID3 Sub_ID2 Sub_ID1 Sub_ID0 INTA# INTB# RST# GND CLK PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND AD25 AD24 C/BE3# IDSEL AD23 AD22 GND VDD AD21 AD20 AD19 VDD GND AD18
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
OXMPCI954-LQ-A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# VDD UART_Ck_Out GND SIN2 SIN1 RI1# DCD1# VDD XTLO XTLI GND DSR1# CTS1# DTR1# RTS1# VDD GND SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 TEST EE_DI EE_CK
6 NC. Do not connect these pins: 102,108,111,112,123,124
DS-0019 Jun 05
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 GND VDD AD13 AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
External--Free Release
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 GND VDD AD13 AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Page 10
OXFORD SEMICONDUCTOR LTD.
OXMPCI954
4.2
Enhanced Modes of Operation. Mode `100' QUAD UARTs + 8-BIT Local Bus.
MODE[2:0] = 100
Mode `011': Quad UARTs (Unique BARs) + 8-bit Local Bus
MODE[2:0] = 011
LBA2 LBA3 VDD GND LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# VDD GND LBCLK LBA4 LBA5 LBA6 LBA7 GND LBDOUT LBD0 LBD1 LBD2 LBD3 VDD GND LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 PCI/mini-PCI SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
LBA2 LBA3 VDD GND LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# VDD GND LBCLK LBA4 LBA5 LBA6 LBA7 GND LBDOUT LBD0 LBD1 LBD2 LBD3 VDD GND LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 PCI/mini-PCI SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
LBA1 LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# INTB#/CLKRUN# RST# GND CLK PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND AD25 AD24 C/BE3# IDSEL AD23 AD22 GND VDD AD21 AD20 AD19 VDD GND AD18
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
OXMPCI954-LQ-A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# VDD UART_Ck_Out GND SIN2 SIN1 RI1# DCD1# VDD XTLO XTLI GND DSR1# CTS1# DTR1# RTS1# VDD GND SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 Mode2 EE_DI EE_CK
LBA1 LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# INTB#/CLKRUN# RST# GND CLK PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND AD25 AD24 C/BE3# IDSEL AD23 AD22 GND VDD AD21 AD20 AD19 VDD GND AD18
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
OXMPCI954-LQ-A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# VDD UART_Ck_Out GND SIN2 SIN1 RI1# DCD1# VDD XTLO XTLI GND DSR1# CTS1# DTR1# RTS1# VDD GND SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 Mode2 EE_DI EE_CK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Mode `101' : QUAD UARTs + Parallel Port.
MODE[2:0] = 101
SLCT ERR# VDD GND NC NC NC NC NC NC VDD GND NC SLIN# INIT# AFD# STB# GND PDOUT PD0 PD1 PD2 PD3 VDD GND PD4 PD5 PD6 PD7 MIO8 MIO9 MIO10 PCI/MiniPCI SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL
# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 GND VDD AD13 AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO
Mode `111' : Standalone QUAD UART Mode
MODE[2:0] = 111
UART_addr(2) UART_addr(3) VDD GND UART_addr(4) Write# Read# Chip_Select# NC NC VDD GND NC NC NC NC NC GND NC UART_data(0) UART_data(1) UART_data(2) UART_data(3) VDD GND UART_data(4) UART_data(5) UART_data(6) UART_data(7) 0 0 0 0 SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3# 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL
# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 GND VDD AD13 AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
BUSY PE ACK# NC MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 NC INTA# INTB#/CLKRUN# RST# GND CLK PME# AD31 AD30 AD29 GND AD28 AD27 AD26 GND AD25 AD24 C/BE3# IDSEL AD23 AD22 GND VDD AD21 AD20 AD19 VDD GND AD18
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
OXMPCI954-LQ-A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# VDD UART_Ck_Out GND SIN2 SIN1 RI1# DCD1# VDD XTLO XTLI GND DSR1# CTS1# DTR1# RTS1# VDD GND SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 TEST EE_DI EE_CK
UART_addr(1) UART_addr(0) Read_Data_Control NC 0 0 0 0 0 0 0 0 Uart_Interrupt 0 RST# GND Buffered_CLK 0 0 0 0 GND 0 0 0 GND 0 0 1 0 0 0 GND VDD 0 0 0 VDD GND 0
OXMPCI954-LQ-A
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# VDD NC GND SIN2 SIN1 RI1# DCD1# VDD XTLO XTLI GND DSR1# CTS1# DTR1# RTS1# VDD GND SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 Mode2 1 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# GND STOP# PERR# SERR# PAR C/BE1# AD15 AD14 GND VDD AD13 AD12 AD11 GND VDD AD10 AD9 GND AD8 C/BE0# AD7 AD6 GND VDD AD5 AD4 AD3 GND AD2 AD1 AD0 EE_CS EE_DO
9 NC. Do not connect these pins: 108,111,112,113,114,115,116,124,132
13 NC. Do not connect these pins: 39,40,41,71,102,104,105,106,107,108,111,112,124
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External--Free Release
0 0 1 1 1 0 0 GND 0 0 0 0 1 0 0 GND VDD 0 0 0 GND VDD 0 0 GND 0 1 0 0 GND VDD 0 0 0 GND 0 0 0 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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OXFORD SEMICONDUCTOR LTD.
OXMPCI954
4.3
Pin Descriptions
For the actual pinouts of the OXMPCI954 device (for the various modes), please refer to the sections on "Pin Information". PCI / mini-PCI Interface Mode 000, 001, 010, 011, 100, 101 139, 140, 141, 143, 144, 145, 147, 148, 151, 152, 155, 156, 157, 160, 1, 2, 14, 15, 18, 19, 20, 23, 24, 26, 28, 29, 32, 33, 34, 36, 37, 38 149, 3, 13, 27 137 4 7 5 6 9 12 11 10 150 135 133 133 134 134 138
Dir1 P_I/O
Name AD[31:0]
Description Multiplexed PCI Address/Data bus
P_I P_I P_I P_O P_I P_O P_O P_I/O P_O P_I/O P_I P_I P_OD P_O P_OD P_I/O P_OD
C/BE[3:0]# CLK FRAME# DEVSEL# IRDY# TRDY# STOP# PAR SERR# PERR# IDSEL RST# INTA# Uart Interrupt INTB# CLKRUN# PME#
PCI Command/Byte enable PCI system clock Cycle Frame Device Select Initiator ready Target ready Target Stop request Parity System error Parity error Initialisation device select PCI system reset PCI interrupt (All modes except Standalone Mode) Uart Interrupt (Standalone Mode Only) PCI interrupt (All modes except Mini-PCI Mode) ClockRun# Line (mini-PCI modes Only) Power management event
NOTE : The PCI interface is not utilised in the Standalone Mode. For this mode, all PCI inputs are tied to their inactive states.
Serial port pins All Modes 46
Dir1 I
Name FIFOSEL
80, 79, 55, 54
O(h)
SOUT[3:0] IrDA_Out[3:0]
Description FIFO select. For backward compatibility with 16C550, 16C650 and 16C750 devices the UARTs' FIFO depth is 16 when FIFOSEL is low. The FIFO size is increased to 128 when FIFOSEL is high. The unlatched state of this pin is readable by software. The FIFO size may also be set to 128 by setting FCR[5] when LCR[7] is set, or by putting the device into enhanced mode. UART serial data outputs UART IrDA data output when MCR[6] of the corresponding channel is set in enhanced mode UART serial data inputs UART IrDA data input when IrDA mode is enabled (see above) Active-low modem data-carrier-detect input
87, 69, 68, 47
I(h) I(h)
SIN[3:0] IrDA_In[3:0] DCD[3:0]#
85, 74, 66, 49
I(h)
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OXFORD SEMICONDUCTOR LTD.
OXMPCI954
Serial port pins All Modes 82, 77, 59, 52
Dir1 O(h)
Name DTR[3:0]#
Description Active-low modem data-terminal-ready output. If automated DTR# flow control is enabled, the DTR# pin is asserted and deasserted if the receiver FIFO reaches or falls below the programmed thresholds, respectively. In RS485 half-duplex mode, the DTR# pin may be programmed to reflect the state of the transmitter empty bit to automatically control the direction of the RS485 transceiver buffer (see register ACR[4:3]) Transmitter 1x clock (baud rate generator output). For isochronous applications, the 1x (or Nx) transmitter clock may be asserted on the DTR# pins (see register CKS[5:4]) Active-low modem request-to-send output. If automated RTS# flow control is enabled, the RTS# pin is deasserted and reasserted whenever the receiver FIFO reaches or falls below the programmed thresholds, respectively. Active-low modem clear-to-send input. If automated CTS# flow control is enabled, upon deassertion of the CTS# pin, the transmitter will complete the current character and enter the idle mode until the CTS# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the CTS# pin. Active-low modem data-set-ready input. If automated DSR# flow control is enabled, upon deassertion of the DSR# pin, the transmitter will complete the current character and enter the idle mode until the DSR# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the DSR# pin External receiver clock for isochronous applications. The Rx_Clk_In is selected when CKS[1:0] = `01'. Active-low modem Ring-Indicator input External transmitter clock. This clock can be used by the transmitter (and indirectly by the receiver) when CKS[6]='1'. Crystal oscillator output Crystal oscillator input up to 20MHz. External clock pin up to 60MHz.
O(h)
485_En[3:0]
O(h) 81, 78, 58, 53 O(h)
Tx_Clk_Out[3:0] RTS[3:0]#
83, 76, 60, 51
I(h)
CTS[3:0]#
84, 75, 61, 50
I(h)
DSR[3:0]#
I(h) 86, 73, 67, 48 I(h) I(h) 64 63 O I
Rx_Clk_In[3:0] RI[3:0]# Tx_Clk_In[3:0] XTLO XTLI
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OXFORD SEMICONDUCTOR LTD.
OXMPCI954
8-bit local bus Mode 000, 011, 100 71 123 124 102 108 113, 114, 115, 116 111 112 104, 105, 106, 107 119, 120, 121, 122 92, 93, 94, 95 98, 99, 100, 101 Parallel port Mode 001, 101 123
Dir1 O O(h) O O O O(h) O(h) O O O Z O(h) I/O(h)
Name UART_Clk_Out LBRST LBRST# LBDOUT LBCLK LBCS[3:0]# LBDS[3:0]# LBWR# LBRDWR# LBRD# Hi-Z LBA[7:0] LBD[7:0]
Description Buffered crystal output. This clock can drive external UARTs connected to the local bus. Can be enabled / disabled by software. Local bus active-high reset Local bus active-low reset Local bus data out enable. This pin can be used by external transceivers; it is high when LBD[7:0] are in output mode and low when they are in input mode. Buffered PCI clock. Can be enabled / disabled by software Local bus active-low Chip-Select (Intel mode) Local bus active-low Data-Strobe (Motorola mode) Local Bus active-low write-strobe (Intel mode) Local Bus Read-not-Write control (Motorola mode) Local Bus active-low read-strobe (Intel mode) Permanent high impedance (Motorola mode) Local bus address signals Local bus data signals
Dir1 I(h)
Name ACK#
Description Acknowledge (SPP mode). ACK# is asserted (low) by the peripheral to indicate that a successful data transfer has taken place. Identical function to ACK# (EPP mode). Paper Empty. Activated by printer when it runs out of paper. Busy (SPP mode). BUSY is asserted (high) by the peripheral when it is not ready to accept data Wait (EPP mode). Handshake signal for interlocked IEEE 1284 compliant EPP cycles. Select (SPP mode). Asserted by host to select the peripheral Address strobe (EPP mode) provides address read and write strobe Peripheral selected. Asserted by peripheral when selected. Error. Held low by the peripheral during an error condition. Initialise (SPP mode). Commands the peripheral to initialise. Initialise (EPP mode). Identical function to SPP mode. Auto Feed (SPP mode, open-drain) Data strobe (EPP mode) provides data read and write strobe
122 121
I(h) I(h) I(h) I(h)
INTR# PE BUSY WAIT# SLIN# ADDRSTB# SLCT ERR# INIT# INIT# AFD# DATASTB#
107
OD(h) O(h)
120 119 106 105
I(h) I(h) OD(h) O(h) OD(h) O(h)
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OXFORD SEMICONDUCTOR LTD.
OXMPCI954
Parallel port Mode 001, 101 104 Dir1 OD(h) O(h) 92, 93, 94, 95 98, 99, 100, 101 102 I/O(h) O Name STB# WRITE# PD[7:0] PDOUT Description Strobe (SPP mode). Used by peripheral to latch data currently available on PD[7:0] Write (EPP mode). Indicates a write cycle when low and a read cycle when high Parallel data bus Parallel Port data out enable. This pin should be used by external transceivers for 5V signalling; it is high when PD[7:0] are in output mode and low when they are in input mode.
Subsystem ID & Subsystem Vendor ID pins Mode Dir1 Name 010 I Sub_ID[15:0] I Sub_V_ID[15:0]
Description Subsystem ID. After reset the subsystem ID of Function 0 will default to the value assigned to these pins Subsystem Vendor ID. After reset the subsystem vendor ID of Function 0 will default to the value assigned to these pins.
Standalone Mode Mode 111 137 135 113 115 114 123 116, 119, 120, 121, 122 92, 93, 94, 95 98, 99, 100, 101 133
Dir1 P_I P_I I(h) I(h) I(h) I(h) I(h) I/O(h) P_O
Name Buffered_CLK Reset# Chip Select# Write Strobe# Read Strobe# Read Data Control# UART_Address[4:0] UART Data[7:0} Uart Interrupt
Description Clock pin to drive device. Device Reset. Active Low Chip Select Signal - Active Low Write Signal - Active Low Read Signal - Active Low Controls Bidirectional Buffers for Uart Data (read/writes) Low for data reads, HI for writes. Address[4:3] -> Uart Selection Address[2:0] -> Uart register Selection Uart Write Data/Read Data Interrupt line. Active Hi for UART interrupts.
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OXFORD SEMICONDUCTOR LTD.
OXMPCI954
Multi-purpose & External interrupt pins Mode Dir1 000,011,100 001/101 010 132 I/O(h) 131 131 130 130 132 131 131 130 130 O I/O(h) 0 I/O(h) I I/O(h)
Name MIO0 NC MIO1 NC MIO2 PME_In MIO[10:3]
Description Multi-purpose I/O 0. Can drive high or low, or assert a PCI interrupt Output Driving `0'. Can be left as a No-connect. Multi-purpose I/O 1. Can drive high or low, or assert a PCI interrupt (as long as LCC[6:5] = "00"). Output Driving `0' (when LCC[6:5] `00') Can be left as a No-Connect. Multi-purpose I/O 2. When LCC[7] = 0, this pin can drive high or low, or assert a PCI interrupt. Input power management event. When LCC[7] is set this input pin can assert a function 1 PME#. Multi-purpose I/O pins. Can drive high or low, or assert a PCI interrupt
89, 90, 91 125, 126, 127, 128, 129
Multi-purpose & External interrupt pins Mode Dir1 000,001,010 011/100/101 88 I/O(h) 88 I(h)
Name MIO[11] PCI/miniPCI
Description Multi-purpose I/O pin. Can drive high or low, or assert a PCI interrupt PCI/miniPCI selection. Tied Low for PCI mode. Tied High for miniPCI mode.
NOTE : MIO pins are unused in the Standalone Mode of operation and must be tied lo.
EEPROM pins Mode 41 39 42
Dir1 O O IU(h)
Name EE_CK EE_CS EE_DI
40
O
EE_DO
Description EEPROM clock EEPROM active-high Chip Select EEPROM data in, with internal pull-up. When the serial EEPROM is connected, this pin should be pulled up using a 1-10k resistor. When the EEPROM is not used the internal pull-up is sufficient. Pin to be connected to the external EEPROM's EE_DO pin (if used) EEPROM data out. Pin to be connected to the external EEPROM's EE_DI pin (if used)
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OXFORD SEMICONDUCTOR LTD.
OXMPCI954
Miscellaneous pins Mode 43, 44,45
Dir1 I
Name MODE[2:0]
Description Mode selector Pins 000 : Function 0 : QUAD UART. Function 1 : 8bit Local Bus OX16PCI954 Backwards Compatible Mode. 001 : Function 0 : QUAD UART. Function 1 : Parallel Port OX16PCI954 Backwards Compatible Mode.. 010 : Function 0 : QUAD UART. Function 1 is unusable as the local bus pins are used to assign Subsystem ID and Subsystem Vendor ID to function 0. OX16PCI954 Backwards Compatible Mode.. 011 : Function 0 : QUAD UART (Uarts in Unique BARs) Function 1 : 8bit Local Bus Enhanced Mode. 100 : Function 0 : QUAD UART. Function 1 : 8bit Local Bus Enhanced Mode. 101 : Function 0 : QUAD UART. Function 1 : Parallel Port Enhanced Mode. 110: Reserved 111 : Standalone QUAD UART mode..
Power and ground 17, 22, 31, 57, 65, 72, 97, 110, 118, 154, 158 8, 16, 21, 25, 30, 35, 56, 62, 70, 96, 103, 109, 117, 136, 142, 146, 153, 159
V G
VDD GND
Power Supply (3.3V) Power Supply Ground (0V)
Table 2: Pin Descriptions
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OXFORD SEMICONDUCTOR LTD.
Note 1: I/O Direction key: P_I P_O P_I/O P_OD I I(h) IU(h) I/O(h) O O(h) OD OD(h) NC G V PCI input PCI output / PCITristates PCI bi-directional PCI open drain Input Input Input with internal pull-up Bi-Directional Output Output Open drain Open drain No connect Ground 3.3V power 3.3v Only 3.3v Only 3.3v Only 3.3v Only LVTTL level LVTTL level, 5v tolerant LVTTL level, 5v tolerant LVTTL level, 5v tolerant Standard Output 5v tolerant (High Voltage BI-Direct in output mode) Standard Open-drain Output 5v tolerant (High Voltage BI-Direct in open-drain mode)
OXMPCI954
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OXFORD SEMICONDUCTOR LTD.
OXMPCI954
5
5.1
PIN INFORMATION--176-PIN VBGA
Modes (Software) Backwards Compatible with the OX16PCI954.
Mode `000': Quad UARTs + 8-bit Local Bus
MODE[2:0] = 000
1 A B C D E F G H J K L M N P R GND C/BE2# FRAME# TRDY# STOP# C/BE1# VDD GND AD9 AD7 VDD AD3 AD2 AD1 EE_CK 2 AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 AD8 GND GND AD0 EE_DO NC Mode2 3 AD21 VDD NC AD17 GND PAR GND AD12 GND AD6 AD4 NC NC EE_DI Mode0 4 AD22 AD20 NC NC DEVSEL# SERR# AD14 VDD AD10 C/BE0# AD5 EE_CS Mode1 FIFOSEL RI0# NC SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 GND RTS1# VDD DTR1# CTS1# DSR1# XTLI GND VDD DCD1# XTLO RI1# SIN2 UART_Ck _Out SIN1 VDD RTS2# DCD2# GND 5 C/BE3# VDD GND AD23 6 AD26 IDSEL AD24 AD25 7 NC GND AD27 NC 8 AD30 NC AD28 GND 9 CLK AD29 AD31 PME# 10 INTB# GND RST# INTA# 11 MIO1 MIO0 MIO2 MIO3 12 MIO4 MIO5 MIO6 LBA0 LBCS3# LBCLK LBA7 LBD2 LBD4 MIO9 DTR3# NC NC DTR2# RI2# 13 MIO7 LBRST# LBA1 NC LBCS2# VDD LBA6 LBD0 GND LBD7 SIN3 CTS3# NC SOUT2 DSR2# 14 LBRST NC LBA2 GND VDD LBWR# LBA4 LBDOUT LBD3 LBD6 MIO10 RI3# RTS3# NC CTS2# 15 LBA3 LBCS0# LBCS1# LBRD# GND LBA5 GND LBD1 VDD LBD5 MIO8 MIO11 DCD3# DSR3# SOUT3
16 NC. Do not connect these pins: P2,C3,M3,N3,C4,D4,M5,A7,D7,B8,M12,N12,D13,N13,B14,P14
Mode `001': Quad UARTs + Parallel Port
MODE[2:0] = 001
1 A B C D E F G H J K L M N P R GND C/BE2# FRAME# TRDY# STOP# C/BE1# VDD GND AD9 AD7 VDD AD3 AD2 AD1 EE_CK 2 AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 AD8 GND GND AD0 EE_DO NC Mode2 3 AD21 VDD NC AD17 GND PAR GND AD12 GND AD6 AD4 NC NC EE_DI Mode0 4 AD22 AD20 NC NC DEVSEL# SERR# AD14 VDD AD10 C/BE0# AD5 EE_CS Mode1 FIFOSEL RI0# NC SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 GND RTS1# VDD DTR1# CTS1# DSR1# XTLI GND VDD DCD1# XTLO RI1# SIN2 UART_Ck _Out SIN1 VDD RTS2# DCD2# GND 5 C/BE3# VDD GND AD23 6 AD26 IDSEL AD24 AD25 7 NC GND AD27 NC 8 AD30 NC AD28 GND 9 CLK AD29 AD31 PME# 10 INTB# GND RST# INTA# 11 MIO1 NC MIO2 MIO3 12 MIO4 MIO5 MIO6 PE NC NC STB# PD2 PD4 MIO9 DTR3# NC NC DTR2# RI2# 13 MIO7 NC BUSY NC NC VDD AFD# PD0 GND PD7 SIN3 CTS3# NC SOUT2 DSR2# 14 ACK# NC SLCT GND VDD NC SLIN# PDOUT PD3 PD6 MIO10 RI3# RTS3# NC CTS2# 15 ERR# NC NC NC GND INIT# GND PD1 VDD PD5 MIO8 MIO11 DCD3# DSR3# SOUT3
25 NC. Do not connect these pins: P2,C3,M3,N3,C4,D4,M5,A7,D7,B8,B11,E12,F12,M12,N12,B13,D13,E13,N13,B14,F14,P14,B15,C15,D15 DS-0019 Jun 05 External--Free Release Page 19
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OXMPCI954
Mode `010': Quad UARTs + Pin Assignable SubSystem ID / Subsystem Vendor ID
MODE[2:0] = 010
1 A B C D E F G H J K L M N P R GND C/BE2# FRAME# TRDY# STOP# C/BE1# VDD GND AD9 AD7 VDD AD3 AD2 AD1 EE_CK 2 AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 AD8 GND GND AD0 EE_DO NC Mode2 3 AD21 VDD NC AD17 GND PAR GND AD12 GND AD6 AD4 NC NC EE_DI Mode0 4 AD22 AD20 NC NC DEVSEL# SERR# AD14 VDD AD10 C/BE0# AD5 EE_CS Mode1 FIFOSEL RI0# NC SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 GND RTS1# VDD DTR1# CTS1# DSR1# XTLI GND VDD DCD1# XTLO RI1# SIN2 UART_Ck _Out SIN1 VDD RTS2# DCD2# GND 5 C/BE3# VDD GND AD23 6 AD26 IDSEL AD24 AD25 7 NC GND AD27 NC 8 AD30 NC AD28 GND 9 CLK AD29 AD31 PME# 10 INTB# GND RST# INTA# 11 SUB_ID1 SUB_ID0 SUB_ID2 SUB_ID3 12 SUB_ID4 SUB_ID5 SUB_ID6 SUB_V_ID0 SUB_ID15 NC SUB_V_ID7 13 SUB_ID7 NC 14 NC NC 15 SUB_V_ID3 SUB_ID12 SUB_ID13 NC GND SUB_V_ID5 GND SUB_V_ID9 VDD
SUB_V_ID1 SUB_V_ID2 NC SUB_ID14 VDD SUB_V_ID6 GND VDD NC SUB_V_ID4 NC SUB_V_ID11
SUB_V_ID10 SUB_V_ID8 SUB_V_ID12 SUB_ID9 DTR3# NC NC DTR2# RI2# GND
SUB_V_ID15 SUB_V_ID14 SUB_V_ID13 SIN3 CTS3# NC SOUT2 DSR2# SUB_ID10 RI3# RTS3# NC CTS2# SUB_ID8 SUB_ID11 DCD3# DSR3# SOUT3
22 NC. Do not connect these pins: P2,C3,M3,N3,C4,D4,M5,A7,D7,B8,F12,M12,N12,B13,D13,N13,A14,B14,F14,H14,P14,D15
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OXMPCI954
5.2
Enhanced Modes of Operation. 8-bit Local Bus
Mode `011': Quad UARTs (Unique BARs) +
MODE[2:0] = 011
1 A B C D E F G H J K L M N P R GND C/BE2# FRAME# TRDY# STOP# C/BE1# VDD GND AD9 AD7 VDD AD3 AD2 AD1 EE_CK 2 AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 AD8 GND GND AD0 EE_DO NC Mode2 3 AD21 VDD NC AD17 GND PAR GND AD12 GND AD6 AD4 NC NC EE_DI Mode0 4 AD22 AD20 NC NC DEVSEL# SERR# AD14 VDD AD10 C/BE0# AD5 EE_CS Mode1 FIFOSEL RI0# NC SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 GND RTS1# VDD 5 C/BE3# VDD GND AD23 6 AD26 IDSEL AD24 AD25 7 NC GND AD27 NC
8 AD30 NC AD28 GND
9 CLK AD29 AD31 PME#
10 INTB#/ CLKRUN# GND RST# INTA#
11 MIO1 MIO0 MIO2 MIO3
12 MIO4 MIO5 MIO6 LBA0 LBCS3# LBCLK LBA7 LBD2 LBD4 MIO9 DTR3#
13 MIO7 LBRST# LBA1 NC LBCS2# VDD LBA6 LBD0 GND LBD7 SIN3 CTS3# NC SOUT2 DSR2#
14 LBRST NC LBA2 GND VDD LBWR# LBA4 LBDOUT LBD3 LBD6 MIO10 RI3# RTS3# NC CTS2#
15 LBA3 LBCS0# LBCS1# LBRD# GND LBA5 GND LBD1 VDD LBD5 MIO8 PCI/ miniPCI DCD3# DSR3# SOUT3
DTR1# CTS1# DSR1# XTLI
GND VDD DCD1# XTLO
RI1# SIN2 UART_Ck _Out SIN1
VDD RTS2# DCD2# GND
NC NC DTR2# RI2#
16 NC. Do not connect these pins: P2,C3,M3,N3,C4,D4,M5,A7,D7,B8,M12,N12,D13,N13,B14,P14
Mode `100' QUAD UARTs + 8-BIT Local Bus.
MODE[2:0] = 100
1 A B C D E F G H J K L M N P R GND C/BE2# FRAME# TRDY# STOP# C/BE1# VDD GND AD9 AD7 VDD AD3 AD2 AD1 EE_CK 2 AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 AD8 GND GND AD0 EE_DO NC Mode2 3 AD21 VDD NC AD17 GND PAR GND AD12 GND AD6 AD4 NC NC EE_DI Mode0 4 AD22 AD20 NC NC DEVSEL# SERR# AD14 VDD AD10 C/BE0# AD5 EE_CS Mode1 FIFOSEL RI0# NC SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 GND RTS1# VDD DTR1# CTS1# DSR1# XTLI GND VDD DCD1# XTLO RI1# SIN2 UART_Ck _Out SIN1 VDD RTS2# DCD2# GND 5 C/BE3# VDD GND AD23 6 AD26 IDSEL AD24 AD25 7 NC GND AD27 NC 8 AD30 NC AD28 GND 9 CLK AD29 AD31 PME# 10 INTB#/ CLKRUN# GND RST# INTA# 11 MIO1 MIO0 MIO2 MIO3 12 MIO4 MIO5 MIO6 LBA0 LBCS3# LBCLK LBA7 LBD2 LBD4 MIO9 DTR3# NC NC DTR2# RI2# 13 MIO7 LBRST# LBA1 NC LBCS2# VDD LBA6 LBD0 GND LBD7 SIN3 CTS3# NC SOUT2 DSR2# 14 LBRST NC LBA2 GND VDD LBWR# LBA4 LBDOUT LBD3 LBD6 MIO10 RI3# RTS3# NC CTS2# 15 LBA3 LBCS0# LBCS1# LBRD# GND LBA5 GND LBD1 VDD LBD5 MIO8 PCI/ miniPCI DCD3# DSR3# SOUT3
16 NC. Do not connect these pins: P2,C3,M3,N3,C4,D4,M5,A7,D7,B8,M12,N12,D13,N13,B14,P14
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OXMPCI954
Mode `101' : QUAD UARTs + Parallel Port.
MODE[2:0] = 101
1 A B C D E F G H J K L M N P R GND C/BE2# FRAME# TRDY# STOP# C/BE1# VDD GND AD9 AD7 VDD AD3 AD2 AD1 EE_CK 2 AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 AD8 GND GND AD0 EE_DO NC Mode2 3 AD21 VDD NC AD17 GND PAR GND AD12 GND AD6 AD4 NC NC EE_DI Mode0 4 AD22 AD20 NC NC DEVSEL# SERR# AD14 VDD AD10 C/BE0# AD5 EE_CS Mode1 FIFOSEL RI0# NC SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 GND RTS1# VDD DTR1# CTS1# DSR1# XTLI GND VDD DCD1# XTLO RI1# SIN2 UART_Ck _Out SIN1 VDD RTS2# DCD2# GND 5 C/BE3# VDD GND AD23 6 AD26 IDSEL AD24 AD25 7 NC GND AD27 NC 8 AD30 NC AD28 GND 9 CLK AD29 AD31 PME# 10 INTB#/ CLKRUN# GND RST# INTA# 11 MIO1 NC MIO2 MIO3 12 MIO4 MIO5 MIO6 PE NC NC STB# PD2 PD4 MIO9 DTR3# NC NC DTR2# RI2# 13 MIO7 NC BUSY NC NC VDD AFD# PD0 GND PD7 SIN3 CTS3# NC SOUT2 DSR2# 14 ACK# NC SLCT GND VDD NC SLIN# PDOUT PD3 PD6 MIO10 RI3# RTS3# NC CTS2# 15 ERR# NC NC NC GND INIT# GND PD1 VDD PD5 MIO8 PCI/ miniPCI DCD3# DSR3# SOUT3
25 NC. Do not connect these pins: P2,C3,M3,N3,C4,D4,M5,A7,D7,B8,B11,E12,F12,M12,N12,B13,D13,E13,N13,B14,F14,P14,B15,C15,D15
Mode `111' : Standalone QUAD UART Mode
MODE[2:0] = 111
1 A B C D E F G H J K L M N P R GND 1 1 0 0 1 VDD GND 0 0 VDD 0 0 0 NC 2 0 0 0 1 0 0 0 0 0 GND GND 0 NC NC Mode2 3 0 VDD NC 0 GND 0 GND 0 GND 0 0 NC NC 1 Mode0 4 0 0 NC NC 0 0 0 VDD 0 1 0 NC Mode1 FIFOSEL RI0# NC SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 GND RTS1# VDD DTR1# CTS1# DSR1# XTLI GND VDD DCD1# XTLO RI1# SIN2 NC SIN1 VDD RTS2# DCD2# GND 5 1 VDD GND 0 6 0 0 0 0 7 NC GND 0 NC 8 0 NC 0 GND 9 Buffered _CLK 0 0 0 10 0 GND RST# Uart Interrupt 11 0 0 0 0 12 0 0 0 UART_ addr[0] Chip_ Select# NC NC UART_ data[2] UART_ data[4] 0 DTR3# NC NC DTR2# RI2# 13 0 NC UART_ addr[1] NC Read# VDD NC UART_ data[0] GND UART_ data[7] SIN3 CTS3# NC SOUT2 DSR2# 14 Read_Data _Control NC UART_ addr[2] GND VDD NC NC NC UART_ data[3] UART_ data[6] 0 RI3# RTS3# NC CTS2# 15 UART_ addr[3] UART_ addr[4] Write# NC GND NC GND UART_ data[1] VDD UART_ data[5] 0 0 DCD3# DSR3# SOUT3
29 NC. Do not connect these pins: R1,N2,P2,C3,M3,N3,C4,D4,M4,M5,A7,D7,A8,P10,F12,G12,M12,N12,B13,D13,G13,N13,B14,F14,G14,H14,P14,D15,F15
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OXMPCI954
5.3
Pin Descriptions
For the actual pinouts of the OXMPCI954 device (for the various modes), please refer to the sections on "Pin Information". PCI / mini-PCI Interface Mode 000, 001, 010, 011, 100, 101 C9,A8,B9,C8,C7,A6,D6,C6, D5,A4,A3,B4,A2,B2,D3,C2, F2,G4,G2,H3,H2,J4,J1,J2, K1,K3,L4,L3,M1,N1,P1,M2 A5,B1,F1,K4 A9 C1 E4 D2 D1 E1 F3 F4 E2 B6 C10 D10 A10 D9
Dir1 P_I/O
Name AD[31:0]
Description Multiplexed PCI Address/Data bus
P_I P_I P_I P_O P_I P_O P_O P_I/O P_O P_I/O P_I P_I P_OD P_O P_OD P_I/O P_OD
C/BE[3:0]# CLK FRAME# DEVSEL# IRDY# TRDY# STOP# PAR SERR# PERR# IDSEL RST# INTA# Uart Interrupt INTB# CLKRUN# PME#
PCI Command/Byte enable PCI system clock Cycle Frame Device Select Initiator ready Target ready Target Stop request Parity System error Parity error Initialisation device select PCI system reset PCI interrupt (All modes except Standalone Mode) Uart Interrupt (Standalone Mode Only) PCI interrupt (All modes except Mini-PCI Mode) ClockRun# Line (mini-PCI modes Only) Power management event
NOTE : The PCI interface is not utilised in the Standalone Mode. For this mode, all PCI inputs are tied to their inactive states.
Serial port pins All Modes P4
Dir1 I
Name FIFOSEL
R15,P13,M7,P6
O(h)
SOUT[3:0] IrDA_Out[3:0]
Description FIFO select. For backward compatibility with 16C550, 16C650 and 16C750 devices the UARTs' FIFO depth is 16 when FIFOSEL is low. The FIFO size is increased to 128 when FIFOSEL is high. The unlatched state of this pin is readable by software. The FIFO size may also be set to 128 by setting FCR[5] when LCR[7] is set, or by putting the device into enhanced mode. UART serial data outputs UART IrDA data output when MCR[6] of the corresponding channel is set in enhanced mode UART serial data inputs UART IrDA data input when IrDA mode is enabled (see above) Active-low modem data-carrier-detect input
L13,N10,R10,N5
I(h) I(h)
SIN[3:0] IrDA_In[3:0] DCD[3:0]#
N15,P11,P9,P5
I(h)
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Serial port pins All Modes L12,P12,M8,N6
Dir1 O(h)
Name DTR[3:0]#
Description Active-low modem data-terminal-ready output. If automated DTR# flow control is enabled, the DTR# pin is asserted and deasserted if the receiver FIFO reaches or falls below the programmed thresholds, respectively. In RS485 half-duplex mode, the DTR# pin may be programmed to reflect the state of the transmitter empty bit to automatically control the direction of the RS485 transceiver buffer (see register ACR[4:3]) Transmitter 1x clock (baud rate generator output). For isochronous applications, the 1x (or Nx) transmitter clock may be asserted on the DTR# pins (see register CKS[5:4]) Active-low modem request-to-send output. If automated RTS# flow control is enabled, the RTS# pin is deasserted and reasserted whenever the receiver FIFO reaches or falls below the programmed thresholds, respectively. Active-low modem clear-to-send input. If automated CTS# flow control is enabled, upon deassertion of the CTS# pin, the transmitter will complete the current character and enter the idle mode until the CTS# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the CTS# pin. Active-low modem data-set-ready input. If automated DSR# flow control is enabled, upon deassertion of the DSR# pin, the transmitter will complete the current character and enter the idle mode until the DSR# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the DSR# pin External receiver clock for isochronous applications. The Rx_Clk_In is selected when CKS[1:0] = `01'. Active-low modem Ring-Indicator input External transmitter clock. This clock can be used by the transmitter (and indirectly by the receiver) when CKS[6]='1'. Crystal oscillator output Crystal oscillator input up to 20MHz. External clock pin up to 60MHz.
O(h)
485_En[3:0]
O(h) N14,N11,P7,R6 O(h)
Tx_Clk_Out[3:0] RTS[3:0]#
M13,R14,N8,M6
I(h)
CTS[3:0]#
P15,R13,P8,R5
I(h)
DSR[3:0]#
I(h) M14,R12,M10,R4 I(h) I(h) R9 R8 O I
Rx_Clk_In[3:0] RI[3:0]# Tx_Clk_In[3:0] XTLO XTLI
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8-bit local bus Mode 000, 011, 100 P10 A14 B13 H14 F12 E12,E13,C15,B15 F14 D15 G12,G13,F15,G14,A15,C14,C13, D12 K13,K14,K15,J12,J14,H12,H15, H13 Parallel port Mode 001, 101 A14
Dir1 O O(h) O O O O(h) O(h) O O O Z O(h) I/O(h)
Name UART_Clk_Out LBRST LBRST# LBDOUT LBCLK LBCS[3:0]# LBDS[3:0]# LBWR# LBRDWR# LBRD# Hi-Z LBA[7:0] LBD[7:0]
Description Buffered crystal output. This clock can drive external UARTs connected to the local bus. Can be enabled / disabled by software. Local bus active-high reset Local bus active-low reset Local bus data out enable. This pin can be used by external transceivers; it is high when LBD[7:0] are in output mode and low when they are in input mode. Buffered PCI clock. Can be enabled / disabled by software Local bus active-low Chip-Select (Intel mode) Local bus active-low Data-Strobe (Motorola mode) Local Bus active-low write-strobe (Intel mode) Local Bus Read-not-Write control (Motorola mode) Local Bus active-low read-strobe (Intel mode) Permanent high impedance (Motorola mode) Local bus address signals Local bus data signals
Dir1 I(h)
Name ACK#
Description Acknowledge (SPP mode). ACK# is asserted (low) by the peripheral to indicate that a successful data transfer has taken place. Identical function to ACK# (EPP mode). Paper Empty. Activated by printer when it runs out of paper. Busy (SPP mode). BUSY is asserted (high) by the peripheral when it is not ready to accept data Wait (EPP mode). Handshake signal for interlocked IEEE 1284 compliant EPP cycles. Select (SPP mode). Asserted by host to select the peripheral Address strobe (EPP mode) provides address read and write strobe Peripheral selected. Asserted by peripheral when selected. Error. Held low by the peripheral during an error condition. Initialise (SPP mode). Commands the peripheral to initialise. Initialise (EPP mode). Identical function to SPP mode. Auto Feed (SPP mode, open-drain) Data strobe (EPP mode) provides data read and write strobe
D12 C13
I(h) I(h) I(h) I(h)
INTR# PE BUSY WAIT# SLIN# ADDRSTB# SLCT ERR# INIT# INIT# AFD# DATASTB#
G14
OD(h) O(h)
C14 A15 F15 G13
I(h) I(h) OD(h) O(h) OD(h) O(h)
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Parallel port Mode 001, 101 G12 Dir1 OD(h) O(h) K13,K14,K15,J12,J14,H12,H15, H13 H14 I/O(h) O Name STB# WRITE# PD[7:0] PDOUT Description Strobe (SPP mode). Used by peripheral to latch data currently available on PD[7:0] Write (EPP mode). Indicates a write cycle when low and a read cycle when high Parallel data bus Parallel Port data out enable. This pin should be used by external transceivers for 5V signalling; it is high when PD[7:0] are in output mode and low when they are in input mode.
Subsystem ID & Subsystem Vendor ID pins Mode Dir1 Name 010 E12,E13,C15,B15,M15,L14,K12, I Sub_ID[15:0] L15,A13,C12,B12,A12,D11,C11, A11,B11 K13,K14,K15,J12,J14,H12,H15, I Sub_V_ID[15:0] H13,G12,G13,F15,G14,A15,C14, C13,D12
Description Subsystem ID. After reset the subsystem ID of Function 0 will default to the value assigned to these pins Subsystem Vendor ID. After reset the subsystem vendor ID of Function 0 will default to the value assigned to these pins.
Standalone Mode Mode 111 A9 C10 E12 C15 E13 A14 B15,A15,C14,C13,D12 K13,K14,K15,J12,J14,H12,H15, H13 D10
Dir1 P_I P_I I(h) I(h) I(h) I(h) I(h) I/O(h) P_O
Name Buffered_CLK Reset# Chip Select# Write Strobe# Read Strobe# Read Data Control# UART_Address[4:0] UART Data[7:0} Uart Interrupt
Description Clock pin to drive device. Device Reset. Active Low Chip Select Signal - Active Low Write Signal - Active Low Read Signal - Active Low Controls Bidirectional Buffers for Uart Data (read/writes) Low for data reads, HI for writes. Address[4:3] -> Uart Selection Address[2:0] -> Uart register Selection Uart Write Data/Read Data Interrupt line. Active Hi for UART interrupts.
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Multi-purpose & External interrupt pins Mode Dir1 000,011,100 001/101 010 B11 I/O(h) A11 A11 C11 C11 B11 A11 A11 C11 C11 O I/O(h) 0 I/O(h) I I/O(h)
Name MIO0 NC MIO1 NC MIO2 PME_In MIO[10:3]
Description Multi-purpose I/O 0. Can drive high or low, or assert a PCI interrupt Output Driving `0'. Can be left as a No-connect. Multi-purpose I/O 1. Can drive high or low, or assert a PCI interrupt (as long as LCC[6:5] = "00"). Output Driving `0' (when LCC[6:5] `00') Can be left as a No-Connect. Multi-purpose I/O 2. When LCC[7] = 0, this pin can drive high or low, or assert a PCI interrupt. Input power management event. When LCC[7] is set this input pin can assert a function 1 PME#. Multi-purpose I/O pins. Can drive high or low, or assert a PCI interrupt
L14,K12,L15,A13, C12,B12,A12,D11
Multi-purpose & External interrupt pins Mode Dir1 000,001,010 011/100/101 M15 I/O(h) M15 I(h)
Name MIO[11] PCI/miniPCI
Description Multi-purpose I/O pin. Can drive high or low, or assert a PCI interrupt PCI/miniPCI selection. Tied Low for PCI mode. Tied High for miniPCI mode.
NOTE : MIO pins are unused in the Standalone Mode of operation and must be tied lo.
EEPROM pins Mode R1 M4 P3
Dir1 O O IU(h)
Name EE_CK EE_CS EE_DI
N2
O
EE_DO
Description EEPROM clock EEPROM active-high Chip Select EEPROM data in, with internal pull-up. When the serial EEPROM is connected, this pin should be pulled up using a 1-10k resistor. When the EEPROM is not used the internal pull-up is sufficient. Pin to be connected to the external EEPROM's EE_DO pin (if used) EEPROM data out. Pin to be connected to the external EEPROM's EE_DI pin (if used)
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Miscellaneous pins Mode R2,N4,R3
Dir1 I
Name MODE[2:0]
Description Mode selector Pins 000 : Function 0 : QUAD UART. Function 1 : 8bit Local Bus OX16PCI954 Backwards Compatible Mode. 001 : Function 0 : QUAD UART. Function 1 : Parallel Port OX16PCI954 Backwards Compatible Mode.. 010 : Function 0 : QUAD UART. Function 1 is unusable as the local bus pins are used to assign Subsystem ID and Subsystem Vendor ID to function 0. OX16PCI954 Backwards Compatible Mode.. 011 : Function 0 : QUAD UART (Uarts in Unique BARs) Function 1 : 8bit Local Bus Enhanced Mode. 100 : Function 0 : QUAD UART. Function 1 : 8bit Local Bus Enhanced Mode. 101 : Function 0 : QUAD UART. Function 1 : Parallel Port Enhanced Mode. 110: Reserved 111 : Standalone QUAD UART mode..
Power and ground G1,H4,L1,R7,N9,M11,J15,F13, E14,B5,B3 H1,K2,L2,R11,G15,E15,D14,B10, B7,A1
V G
VDD GND
Power Supply (3.3V) Power Supply Ground (0V)
Table 3: Pin Descriptions
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Note 1: I/O Direction key: P_I P_O P_I/O P_OD I I(h) IU(h) I/O(h) O O(h) OD OD(h) NC G V PCI input PCI output / PCITristates PCI bi-directional PCI open drain Input Input Input with internal pull-up Bi-Directional Output Output Open drain Open drain No connect Ground 3.3v Only 3.3v Only 3.3v Only 3.3v Only LVTTL level LVTTL level, 5v tolerant LVTTL level, 5v tolerant LVTTL level, 5v tolerant Standard Output 5v tolerant (High Voltage BI-Direct in output mode) Standard Open-drain Output 5v tolerant (High Voltage BI-Direct in open-drain mode)
OXMPCI954
3.3V power
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6
CONFIGURATION & OPERATION
drivers can then access the functions at the assigned addresses in the usual fashion, with the improved data throughput provided by PCI. Each function operates as though it was a separate device. However there are a set of Local Configuration Registers that can be used to enable signals and interrupts, configure timings, and improve the efficiency of multi-port drivers. This architecture enables separate drivers to be installed for each function. Generic port drivers can be hooked to use the functions individually, or more efficient multi-port drivers can hook both functions, accessing the Local Configuration Registers from either. All registers default after reset to suitable values for typical applications such a 4/8 port serial, or combo 4-port serial/1port parallel add-in cards. However, all identification, control and timing registers can be redefined using an optional serial EEPROM.
The OXMPCI954 is a multi-function, target-only PCI device, compliant with the PCI Local Bus Specification, Revision 3.0 and PCI Power Management Specification, Revision 1.1. The OXMPCI954 affords maximum configuration flexibility by treating the internal UART's, the Local Bus and the Parallel Port as separate logical functions. Each function has its own configuration space and is therefore recognised and configured by the PCI BIOS separately. The functions used are configured by the Mode Selection Pins (MODE[2:0]) as shown in the section "OXMPCI954 Device Modes". The OXMPCI954 is configured by system start-up software during the bootstrap process that follows bus reset. The system scans the bus and reads the vendor and device identification codes from any devices it finds. It then loads device-driver software according to this information and configures the I/O, memory and interrupt resources. Device
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7
7.1
PCI TARGET CONTROLLER
Operation
access while the OXMPCI954 is reading from the serial EEPROM. The OXMPCI954 performs medium-speed address decoding as defined by the PCI specification. It asserts the DEVSEL# bus signal two clocks after FRAME# is first sampled low on all bus transaction frames which address the chip. The internal UARTs are accessed with zero wait states inserted. Fast back-to-back transactions are supported by the OXMPCI954 as a target, so a bus master can perform faster sequences of write transactions to the UARTs or local bus when an inter-frame turn-around cycle is not required. The device supports any combination of byte-enables to the PCI Configuration Registers and the Local Configuration Registers. If a byte-enable is not asserted, that byte is unaffected by a write operation and undefined data is returned upon a read. The OXMPCI954 performs parity generation and checking on all PCI bus transactions as defined by the standard. Note this is entirely unrelated to serial data parity which is handled within the UART functional modules themselves. If a parity error occurs during the PCI bus address phase, the device will report the error in the standard way by asserting the SERR# bus signal. However if that address/command combination is decoded as a valid access, it will still complete the transaction as though the parity check was correct. The OXMPCI954 does not support any kind of caching or data buffering in addition to that already provided within the UARTs by the transmit and receive data FIFOs. In general, registers in the UARTs and on the local bus can not be prefetched because there may be side-effects on read.
The OXMPCI954 responds to the following PCI transactions:* Configuration access: The OXMPCI954 responds to type 0 configuration reads and writes if the IDSEL signal is asserted and the bus address is selecting the configuration registers for function 0 or 1. The device will respond to the configuration transaction by asserting DEVSEL#. Data transfer then follows. Any other configuration transaction will be ignored by the OXMPCI954. IO reads/writes: The address is compared with the addresses reserved in the I/O Base Address Registers (BARs). If the address falls within one of the assigned ranges, the device will respond to the IO transaction by asserting DEVSEL#. Data transfer follows this address phase. For the UARTs and 8-bit Local Bus controller, only byte accesses are possible. For IO accesses to these regions, the controller compares AD[1:0] with the byte-enable signals as defined in the PCI specification. The access is always completed; however if the correct BE signal is not present the transaction will have no effect. Memory reads/writes: These are treated in the same way as I/O transactions, except that the memory ranges are used. Memory access to single-byte regions is always expanded to DWORDs in the OXMPCI954. In other words, OXMPCI954 reserves a DWORD per byte in single-byte regions. The device allows the user to define the active byte lane using LCC[4:3] so that in Big-Endian systems the hardware can swap the byte lane automatically. For Memory mapped access in single-byte regions, the OXMPCI954 compares the asserted byte-enable with the selected byte-lane in LCC[4:3] and completes the operation if a match occurs, otherwise the access will complete normally on the PCI bus, but it will have no effect on either the internal UARTs or the local bus controller. All other cycles (64-bit, special cycles, reserved encoding etc.) are ignored.
*
*
7.2
Configuration space
*
The OXMPCI954 is a dual-function device, where each logical function has its own configuration space. All required fields in the standard header are implemented, plus the Power Management Extended Capability register set. The format of the configuration space is shown in the following tables. In general, writes to any registers that are not implemented are ignored, and all reads from unimplemented registers return 0.
The OXMPCI954 will complete all transactions as disconnect-with-data, i.e. the device will assert the STOP# signal alongside TRDY#, to ensure that the Bus Master does not continue with a burst access. The exception to this is Retry, which will be signalled in response to any DS-0019 Jun 05
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7.2.1
PCI Configuration Space Register map
Predefined PCI Region
31 16
Configuration Register Description
15
0
Device ID Status BIST
Vendor ID Command
Class Code Revision ID Header Type Reserved Reserved Base Address Register 0 (BAR 0) Base Address Register 1 (BAR 1) Base Address Register 2 (BAR 2) Base Address Register 3 (BAR 3) Base Address Register 4 (BAR 4)* Base Address Register 5 (BAR 5)* Reserved Subsystem ID Subsystem Vendor ID Reserved Reserved Cap_Ptr Reserved Reserved Reserved Interrupt Pin Interrupt Line User Defined Region Power Management Capabilities (PMC) Data* Reserved Next Ptr Cap_ID PMC Control/Status Register (PMCSR)
Offset Address 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch
40h 44h
*Fields not implemented in the Backwards Compatible Modes. Available only in the Enhanced Modes.
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PCI Configuration Space Default Values - Function 0
Register Name Function 0 Reset Value Backwards Compatible Modes Enhanced Modes 000 001 010 011 100 101 QUAD QUAD QUAD QUAD QUAD QUAD UART UART UART UART UART UART (SubSys Unique Bar (Optional (Optional IDs via Unique Bar) Unique Bar) pins) 0x1415 0x9501 0x9504 0x9501 (0x9504) 0x0000 0x0290 0x00 0x070006 0x80 0x00000001 0x00000001 0x00000001 (0x00000001) 0x00000000 0x00000001 0x00000000 (0x00000001) 0x00000001 0x00000001 0x00000001 (0x00000001) 0x00000000 0x00000001 0x00000000 (0x00000001) NULL 0x00000001 NULL (0x00000001) NULL 0x00000000 NULL (0x00000000) 0x1415 0x0000 0x40 0x00 0x01 0x01 0x00 0x6C01 0x0000 0x00 (Not Implemented) 0x00 (Implemented) 0x6C02 (PCI mode) 0xEC02 (MiniPCI mode)
OXMPCI954
Program Read/Write EEPROM PCI
Vendor ID Device ID Command Status Revision ID Class Code Header BAR 0 BAR 1 BAR 2 BAR 3 BAR 4 BAR 5 Subsystem Vendor ID Subsystem ID Cap. Ptr Interrupt Line Interrupt Pin Cap ID Next Ptr PM Capabilities PMC Control/Status Register PM Data Register
W W W(Bit 4) W W W W W W (Data Scale) W
R R R/W R/W R R R R R R R R R R R R R R R R R R/W R
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OXMPCI954
PCI Configuration Space Default Values - Function 1
Register Name Function 1 Reset Value Backwards Compatible Modes Enhanced Modes 000 001 010 011 100 101 8-BIT PARALLEL Disabled 8-BIT 8-BIT PARALLEL LOCAL BUS PORT LOCAL BUS LOCAL BUS PORT 0x1415 0x9511 0x9513 0x9510 0x9511 0x9511 0x9513 0x0000 0x0290 0x00 0x068000 0x070101 0x068000 0x068000 0x068000 0x070101 0x80 0x00000001 0x00000000 0x00000001 0x00000000 0x00000000 0x00000000 0x00000001 0x00000001 0x00000000 NULL NULL 0x1415 0x0000 0x40 0x00 0x02 0x01 0x00 0x6C01 0x0000 0x00 (Not Implemented) 0x00 (Implemented) 0x6C02 (PCI mode) 0xEC02 (MiniPCI mode) 0x01 Program Read/Write EEPROM PCI
Vendor ID Device ID Command Status Revision ID Class Code Header BAR 0 BAR 1 BAR 2 BAR 3 BAR 4 BAR 5 Subsystem Vendor ID Subsystem ID Cap. Ptr Interrupt Line Interrupt Pin Cap ID Next Ptr PM Capabilities PMC Control/Status Register PM Data Register
W W W(Bit 4) W W W W W W (Data Scale) W
R R R/W R/W R R R R R R R R R R R R R R R R R R/W R
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7.3
Accessing logical functions
Access to the UARTs, the Local Bus and the Parallel Port is achieved via standard I/O and Memory mapping, at addresses defined by the Base Address Registers (BARs) in the PCI configuration space. The BARs are configured by the system to allocate blocks of I/O and Memory space to the logical functions, according to the size required by the function. The addresses allocated can then be used to access the functions. The mapping of these BARs, which is dependent upon the mode of the device, is shown by the following tables. BAR 0 1 2 3 4 5 BAR 0 1 2 3 4 5 Function 0 QUAD UARTs in Common I/O Space Internal UARTs (I/O mapped) Internal UARTs (Memory mapped) Local configuration registers (I/O mapped) Local configuration registers (Memory mapped) Unused Unused Function 1 Local bus QUAD UARTs in Unique BAR mode Internal UART0 (I/O Mapped) Internal UART1 (I/O Mapped) Internal UART2 (I/O Mapped) Internal UART3 (I/O Mapped) Local configuration registers (I/O mapped) Internal UARTs/ Local configuration registers (Memory mapped)
Parallel port Local bus (I/O mapped) Parallel port base registers Local bus (Memory mapped) Parallel port extended registers Local configuration registers (I/O mapped) Local configuration registers (Memory mapped) Unused Unused
7.3.1 PCI access to internal UARTs IO and Memory Space
The Base Address Registers for the internal UARTs are dependent upon whether the unique bar option has been utilised for Function 0. See Section 8.7 "Unique BAR Option" for further Details. When this (unique bar) option is not selected, then BAR 0 and BAR 1 of function 0 are used to access the internal UARTs. The function reserves a 32-byte block of I/O space and a 4K byte block of memory space. Once the I/O access and the Memory access enable bits in the Command register (configuration space) are set, the UARTs can be accessed according to the following tables. UART Address (hex) 000 001 002 003 004 005 006 007 PCI Offset from Base Address 0 for Function0 in IO space (hex) UART0 UART1 UART2 UART3 00 08 10 18 01 09 11 19 02 0A 12 1A 03 0B 13 1B 04 0C 14 1C 05 0D 15 1D 06 0E 16 1E 07 0F 17 1F
UART Address 000 001 002 003 004 005 006 007
PCI Offset from Base Address 1 for Function0 in Memory space (hex) 00 20 40 60 04 24 44 64 08 28 48 68 0C 2C 4C 6C 10 30 50 70 14 34 54 74 18 38 58 78 1C 3C 5C 7C
Table 4: PCI address map for internal UARTs (I/O and memory)
Note 1: Since 4K of memory space is reserved and the full bus address is not used for decoding, there are a number of aliases of the UARTs in the allocated memory region
When the unique bar option of the device has been selected then BAR0 to BAR3 are used to address each UART individually in I/O space, and BAR5 is used to address the UARTs in Memory Space. The function reserves 8-byte blocks of I/O space for BAR0 to BAR3 and 4K byte block of memory space for BAR5. Once the I/O access and the Memory access enable bits in the Command register (configuration space) are set, the UARTs can accessed according to the following tables. Page 35
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OXMPCI954
UART Address (hex) 000 001 002 003 004 005 006 007 UART Address 000 001 002 003 004 005 006 007
PCI Offset from UARTs Base Address for Function0 in IO space (hex) UART0 UART1 UART2 UART3 (BAR0) (BAR1) (BAR2) (BAR3) 00 00 00 00 01 01 01 01 02 02 02 02 03 03 03 03 04 04 04 04 05 05 05 05 06 06 06 06 07 07 07 07 PCI Offset from Base Address 5 for Function0 in Memory space (hex) UART0 UART1 UART2 UART3 00 20 40 60 04 24 44 64 08 28 48 68 0C 2C 4C 6C 10 30 50 70 14 34 54 74 18 38 58 78 1C 3C 5C 7C
maximum allowable block size is allocated to the I/O space (i.e. 256 bytes), then as access in I/O space is byte aligned, LBA[7:0] equal PCI AD[7:0] respectively. When the user selects an address range which is less than 256 bytes, the corresponding upper address lines will be set to logic zero. The region can be divided into four chip-select regions when the user selects the second uppermost non-zero address bit for chip-select decoding. For example if 32bytes of I/O space are reserved, the local bus address lines A[4:0] are active and the remaining address lines are set to zero. To generate four chip-selects the user should select A3 as the Lower-Address-CS-Decode. In this case A[4:3] will be used internally to decode chip-selects, asserting LBCS0# when the address offset is 00-07h, LBCS1# when the offset is 08-0Fh, LBCS2# when the offset is 10-17h, and LBCS3# when the offset is 18-1Fh. The region can be divided into two chip-select regions by selecting the uppermost address bit to decode chip selects. In the above example, the user can select A4 as the Lower-Address-CS-Decode, thus using A[5:4] internally to decode chip selects. As in this example LBA5 is always zero, only chip-select lines LBCS0# and LBCS1# will be decoded into, asserting LBCS0# when address offset is 000Fh and LBCS1# when offset is 10-1Fh. The region can be allocated to a single chip-select region by assigning an address bit beyond the selected range to Lower-Address-CS-Decode (but not above A8). In the above example, if the user selects A5 as the LowerAddress-CS-Decode, A[6:5] will be used to internally decode chip-selects. As in this example LBA[7:5] are always zero, only the chip select line LBCS0# may be selected. In this case address offset 00-1Fh asserts LBCS0# and the other chip-select lines remain inactive permanently. With default values, the address map for local bus I/O address accesses is the same as for internal UARTs (when the UARTs are in the common I/O Base Address).
Note that in the unique bar mode of operation, the local registers in memory space occupy the same Base Address Register (BAR5) as the internal UARTs in Memory Space. Bit 7 selects the region to be accessed. Access to addresses 00h to 7Fh will be directed to the internal UARTs, and access to addresses 80h to FF will be directed to the local registers.
7.3.2
PCI access to 8-bit local bus
When the local bus is enabled (Modes 000, 011, 100), access to the bus works in a similar fashion to the internal UARTs. The function reserves a block of I/O space and a block of memory space. The I/O block size is user definable in the range of 4 to 256 bytes, and the memory range is fixed at 4K bytes.
I/O space
In order to minimise the usage of IO space, the block size for BAR0 of Function1 is user definable in the range of 4 to 256 bytes. Having assigned the address range, the user can define two adjacent address bits to decode up to four chip selects internally. This facility allows glueless implementation of the local bus connecting to four external peripheral chips. The address range and the lower address bit for chip-select decoding (Lower-Address-CS-Decode) are defined in the Local Bus Configuration register (see LT2 [26:20] in section 7.4). The 8-bit Local Bus has eight address lines (LBA[7:0]) that correspond to the maximum I/O address space. If the DS-0019 Jun 05
Memory Space:
The memory base address registers have an allocated fixed size of 4K bytes in the address space. Since the Local Bus has 8 address lines and the OXMPCI954 only implements DWORD aligned accesses in memory space, the 256 bytes of addressable space per chip select is expanded to 1K. Unlike an I/O access, for a memory access the upper address lines are always active and the internal chip-select decoding logic ignores the user setting for Lower-Address-CS-Decode (LT2[26:23]) and uses PCI AD[11:10] to decode into 4 chip-select regions. When the Local Bus is accessed in memory space, A[9:2] are asserted on LBA[7:0]. The chip-select regions are defined below. Page 36
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OXMPCI954
7.3.3
Local Bus Chip-Select (Data-Strobe) LBCS0# (LBDS0#) LBCS1# (LBDS1#) LBCS2# (LBDS2#) LBCS3# (LBDS3#) PCI Offset from BAR 1 in Function1 (Memory space) Lower Address Upper Limit 000h 3FCh 400h 7FCh 800h BFCh C00h FFCh
PCI access to parallel port
When the parallel port is enabled (Mode 001, 101), access to the Parallel Port works via BAR definitions as usual, except that there are two I/O BARs corresponding to the two sets of registers defined to operate an IEEE1284 EPP/ECP and bi-directional Parallel Port. The user can change the I/O space block size of BAR0 by over-writing the default values in LT2[25:20] using the serial EEPROM (see section 7.4). For example the user can reduce the allocated space for BAR0 to 4 bytes by setting LT2[22:20] to `001'. The I/O block size allocated to BAR1 is fixed at 8 Bytes. Legacy parallel ports expect the upper register set to be mapped 0x400 above the base block, therefore if the BARs are fixed with this relationship, generic parallel port drivers can be used to operate the device in all modes. Example: BAR0 = 0x00000379 (8 bytes at address 0x378) BAR1 = 0x00000779 (8 bytes at address 0x778) If this relationship is not used, custom drivers will be needed.
Table 5: PCI address map for local bus (memory)
Note: The description given for I/O and memory accesses is for an Inteltype configuration for the Local Bus. For Motorola-type configuration, the chip select pins are redefined as data strobe pins. In this mode the Local Bus offers up to 8 address lines and four data-strobe pins.
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7.4
Accessing Local configuration registers
The local configuration registers are a set of device specific registers which can be accessed from either function. They are mapped to the I/O and Memory Base Addresses typically set up in BAR2 and BAR3 of each function. The exception is when the device operates in the unique bar mode, for which access to the local registers via function 0 will be through BAR4 and BAR5. For I/O transactions, access is limited to byte reads/writes. For Memory Transactions, accesses can be Word or Dword accesses, however on little-endian systems such as Intel 80x86 the byte order will be reversed. The following table lists the definitions of the local registers, with the offsets (from the Base Address Register) defined for each local register.
7.4.1
Local Configuration and Control register `LCC' (Offset 0x00)
This register defines control of ancillary functions such as Power Management, external clock reference signals and the serial EEPROM. The individual bits are described below. Bits 1:0 2 4:3 Description Mode[1:0] Status. These bits return the state of the Mode[1:0] pins. Enable UART clock output. When this bit is set, a buffered version of the UART clock is output on the pin "UART_Clk_Out". When this bit is low, the UART_Clk_Out is permanently low. Endian Byte-Lane Select for memory access to 8-bit peripherals. 00 = Select Data[7:0] 10 = Select Data[23:16] 01 = Select Data[15:8] 11 = Select Data[31:24] Memory access to OXMPCI954 is always DWORD aligned. When accessing 8-bit regions like the internal UARTs, the 8-bit Local Bus and the parallel port, this option selects the active byte lane. As both PCI and PC architectures are little endian, the default value will be used by systems, however, some non-PC architectures may need to select the byte lane. Power-down filter time. These bits define a value of an internal filter time for a power-down interrupt request in power management circuitry in Function0. Once Function0 is ready to go into power down mode, OXMPCI954 will wait for the specified filter time and if Function0 is still in power-down request mode, it can assert a PCI interrupt (see section 7.6). 00 = power-down request disabled 10 = 129 seconds 01 = 4 seconds 11 = 518 seconds Function1 MIO2_PME Enable. A value of `1' enables MIO2 pin to set the PME_Status in PMCSR register, and hence assert the PME# pin if enabled. A value of `0' disables MIO2 from setting the PME_Status bit (see section 7.6). Reserved. These bits are used for test purposes. The device driver must write zeros to these bits. EEPROM Clock. For PCI read or write to the EEPROM, toggle this bit to generate an EEPROM clock (EE_CK pin). EEPROM Chip Select. When 1 the EEPROM chip-select pin EE_CS is activated (high). When 0 EE_CS is de-active (low). EEPROM Data Out. For writes to the EEPROM, this output bit is the input-data for the EEPROM. This bit is output on EE_DO and clocked into the EEPROM by EE_CK. EEPROM Data In. For reads from the EEPROM, this input bit is the output-data of the EEPROM connected to EE_DI pin. EEPROM Valid. A 1 indicates that a valid EEPROM program is present External--Free Release Read/Write
EEPROM
Reset PCI R RW RW XX 0 00
W W
6:5
W
RW
00
7
W
RW
0
23:8 24 25 26 27 28
-
R W W W R R
0000h 0 0 0 X X Page 38
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OXMPCI954
Bits 29 30
Description Reload configuration from EEPROM. Writing a 1 to this bit re-loads the configuration from EEPROM. This bit is self-clearing after EEPROM read EEPROM Overrun Indication (when set). In conjunction with Bit 28 (Valid EEPROM) this bit indicates whether a successful eeprom download had taken place. Successful download will have EEPROM_VALID = 1 and EEPROM OVERRUN = 0. MODE[2] Status. Returns the state of the MODE[2] pin.
Read/Write
EEPROM
Reset PCI W R 0 0
-
31
-
R
X
7.4.2
Multi-purpose I/O Configuration register `MIC' (Offset 0x04)
This register configures the operation of the multi-purpose I/O pins `MIO[11:0], as well as providing Enhanced Mode Features, as follows. Bits 1:0 Description MIO0 Configuration Register (When Device Mode `001'/'101'). 00 -> MIO0 is a non-inverting input pin 01 -> MIO0 is an inverting input pin 10 -> MIO0 is an output pin driving `0' 11 -> MIO0 is an output pin driving `1' When Parallel Port is enabled, (Device Mode = `001'/'101'), MIO[0] pin is unused and will remain in forcing output mode. MIO1 Configuration Register (When LCC[6:5] = `00'). 00 -> MIO1 is a non-inverting input pin 01 -> MIO1 is an inverting input pin 10 -> MIO1 is an output pin driving `0' 11 -> MIO1 is an output pin driving `1' When power-down mode in Function 0 is enabled (LCC[6:5] `00'), MIO1 pin is unused and will remain in forcing output mode. MIO2 Configuration Register (When LCC[7]='0'). 00 -> MIO2 is a non-inverting input pin 01 -> MIO2 is an inverting input pin 10 -> MIO2 is output pin driving `0' 11 -> MIO2 is output pin driving `1' When LCC[7] is set, the MIO2 pin is re-defined to a PME_Input. Its polarity will be controlled by MIC[4]. It sets the sticky PME_Status bit in Function1. MIO3 Configuration Register. 00 -> MIO3 is a non-inverting input pin 01 -> MIO3 is an inverting input pin 10 -> MIO3 is an output pin driving `0' 11 -> MIO3 is an output pin driving `1' MIO4 Configuration Register. 00 -> MIO4 is a non-inverting input pin 01 -> MIO4 is an inverting input pin 10 -> MIO4 is an output pin driving `0' 11 -> MIO4 is an output pin driving `1'
EEPROM
Read/Write PCI W RW
Reset 00
3:2
W
RW
00
5:4
W
RW
00
7:6
W
RW
00
9:8
W
RW
00
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Bits 11:10
Description MIO5 Configuration Register. 00 -> MIO5 is a non-inverting input pin 01 -> MIO5 is an inverting input pin 10 -> MIO5 is an output pin driving `0' 11 -> MIO5 is an output pin driving `1' MIO6 Configuration Register. 00 -> MIO6 is a non-inverting input pin 01 -> MIO6 is an inverting input pin 10 -> MIO6 is an output pin driving `0' 11 -> MIO6 is an output pin driving `1' MIO7 Configuration Register. 00 -> MIO7 is a non-inverting input pin 01 -> MIO7 is an inverting input pin 10 -> MIO7 is an output pin driving `0' 11 -> MIO7 is an output pin driving `1' MIO8 Configuration Register. 00 -> MIO8 is a non-inverting input pin 01 -> MIO8 is an inverting input pin 10 -> MIO8 is an output pin driving `0' 11 -> MIO8 is an output pin driving `1' MIO9 Configuration Register. 00 -> MIO9 is a non-inverting input pin 01 -> MIO9 is an inverting input pin 10 -> MIO9 is an output pin driving `0' 11 -> MIO9 is an output pin driving `1' MIO10 Configuration Register. 00 -> MIO10 is a non-inverting input pin 01 -> MIO10 is an inverting input pin 10 -> MIO10 is an output pin driving `0' 11 -> MIO10 is an output pin driving `1' MIO11 Configuration Register. 00 -> MIO11 is a non-inverting input pin 01 -> MIO11 is an inverting input pin 10 -> MIO11 is an output pin driving `0' 11 -> MIO11 is an output pin driving `1' Reserved. The device driver must write zeros to these bits. UART `Unique BAR' mode via EEPROM When set (1), sets up Function 0 such that each UART can be accessed through its own I/O Base Address Register. This bit is available only in the Enhanced Modes (and is ignored in the pin-defined `unique bar' mode). In the enhanced modes, PCI write transactions must not affect the status of this bit. MiniPCI Mode Status When set, indicates that the device is operating in the miniPCI mode. When clear, device is operating in the PCI mode. This bit is available only in the Enhanced Modes (and returns 0 otherwise). Enhanced Mode Status When set, indicates that the device is operating in the Enhanced mode. When clear, device is operating in the Backwards Compatible Mode. Clock Control Handling via Power Management When set (1), the clock control circuitry handling the CLKRUN# line is controlled by the power management states of function 0 and function 1. This bit is available only in the Enhanced Modes and is only relevant for the miniPCI mode of operation. External--Free Release
EEPROM
Read/Write PCI W RW
Reset 00
13:12
W
RW
00
15:14
W
RW
00
17:16
W
RW
00
19:18
W
RW
00
21:20
W
RW
00
23:22
W
RW
00
Bit 25:24 Bit 26
W W
R/W R/W
0 0
Bit 27
-
R
X
Bit 28 Bit 29
W
R R/W
X 0
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Bits Bit 30
Description Disable Clock Control Circuitry (CLKRUN#) When set (1), the clock control circuitry handling the CLKRUN# line is disabled, allowing the host to stop the PCI_CLK at the next available opportunity. Circuitry Is enabled by default to prevent clock stopping. This bit is available only in the Enhanced Modes and is only relevant for the miniPCI mode of operation. Parallel Port Filter Disable When set (1) disables the noise filters on the parallel port data lines and status lines. Filters are enabled by default. This bit is available only in the Enhanced Modes and is only relevant for the parallel port.
EEPROM
Read/Write PCI W R/W
Reset 0
Bit 31
W
R/W
0
7.4.3
Local Bus Timing Parameter register 1 `LT1' (Offset 0x08):
The Local Bus Timing Parameter registers (LT1 and LT2) define the operation and timing parameters used by the Local Bus. The timing parameters are programmed in 4-bit registers to define the assertion/de-assertion of the Local Bus control signals. The value programmed in these registers defines the number of PCI clock cycles after a Reference Cycle when the events occur, where the reference Cycle is defined as two clock cycles after the master asserts the IRDY# signal. The following arrangement provides a flexible approach for users to define the desired bus timing of their peripheral devices. The timings refer to I/O or Memory mapped access to BAR0 and BAR1 of Function1. Bits 3:0 Description Read Chip-select Assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBCS[3:0]# pins are asserted (low) during a read operation from the Local Bus.1 These bits are unused in Motorola-type interface. Read Chip-select De-assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBCS[3:0]# pins are de-asserted (high) during a read from the Local Bus. 1 These bits are unused in Motorola-type interface. Write Chip-select Assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBCS[3:0]# pins are asserted (low) during a write operation to the Local Bus. 1 These bits are unused in Motorola-type interface. Write Chip-select De-assertion (Intel-type interface). Defines the number of clock cycles after the reference cycle when the LBCS[3:0]# pins are de-asserted (high) during a write operation to the Local Bus. 1 Read-not-Write De-assertion during write cycles (Motorola-type interface). Defines the number of clock cycles after the reference cycle when the LBRDWR# pin is de-asserted (high) during a write to the Local Bus. 1 Read Control Assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBRD# pin is asserted (low) during a read from the Local Bus. 1 Read Data-strobe Assertion (Motorola-type interface). Defines the number of clock cycles after the Reference Cycle when the LBDS[3:0]# pins are asserted (low) during a read from the Local Bus. 1 DS-0019 Jun 05 External--Free Release Page 41 Read/Write
EEPROM
Reset PCI RW 0h
W
7:4
W
RW
3h (2h for parallel port) 0h
11:8
W
RW
15:12
W
RW
2h
19:16
W
RW
0h (1h for parallel port)
OXFORD SEMICONDUCTOR LTD.
OXMPCI954
Bits 23:20
Description Read Control De-assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBRD# pin is deasserted (high) during a read from the Local Bus. 1 Read Data-strobe De-assertion (Motorola-type interface). Defines the number of clock cycles after the Reference Cycle when the LBDS[3:0]# pins are de-asserted (high) during a read from the Local Bus. 1 Write Control Assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBWR# pin is asserted (low) during a write to the Local Bus. 1 Write Data-strobe Assertion (Motorola-type interface). Defines the number of clock cycles after the Reference Cycle when the LBDS[3:0]# pins are asserted (low) during a write to the Local Bus. 1 Write Control De-assertion (Intel-type interface). Defines the number of clock cycles after the Reference Cycle when the LBWR# pin is deasserted (high) during a write to the Local Bus. 1 Write Data-strobe De-assertion (Motorola-type interface). Defines the number of clock cycles after the Reference Cycle when the LBDS[3:0]# pins are de-asserted (high) during a write cycle to the Local Bus. 1
Read/Write
EEPROM
Reset PCI RW 3h (2h for parallel port)
W
27:24
W
RW
0h (1h for parallel port)
31:28
W
RW
2h
Note 1:
Only values in the range of 0h to Ah (0-10 decimal) are valid. Other values are reserved. See notes in the following page.
7.4.4
Bits 3:0 7:4 11:8
Local Bus Timing Parameter register 2 `LT2' (Offset 0x0C):
Description Write Data Bus Assertion. This register defines the number of clock cycles after the Reference Cycle when the LBD pins actively drive the data bus during a write operation to the Local Bus. 1 Write Data Bus De-assertion. This register defines the number of clock cycles after the Reference Cycle when the LBD pins go high-impedance during a write operation to the Local Bus. 1,2 Read Data Bus Assertion. This register defines the number of clock cycles after the Reference Cycle when the LBD pins actively drive the data bus at the end of a read operation from the Local Bus. 1 Read Data Bus De-assertion. This register defines the number of clock cycles after the Reference Cycle when the LBD pins go high-impedance during at the beginning of a read cycle from the Local Bus. 1 Reserved. IO Space Block Size of BAR0 in Function1. 000 = Reserved 100 = 32 Bytes 001 = 4 Bytes 101 = 64 Bytes 010 = 8 Bytes 110 = 128 Bytes 011 = 16 Bytes 111 = 256 Bytes Read/Write
EEPROM
Reset PCI RW RW RW 0h Fh 4h (2h for parallel port) 0h 0h `100' (=`010' for parallel port)
W W W
15:12 19:16 22:20
W W
RW R R
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OXMPCI954
Bits 26:23
Description Local Bus Chip-select Parameter `Lower-Address-CS-Decode'. 2 IO space in 8-bit Local Bus 1000 = Res 0000 = A2 1001 = Res 0001 = A3 1010 = Res 0010 = A4 1011 = Res 0011 = A5 1100 = Res 0100 = A6 1101 = Res 0101 = A7 1110 = Res 0110 = A8 1111 = Res 0111 = A9 Reserved Local Bus Software Reset. When this bit is a 1 the Local Bus reset pin is activated. When this bit is a 0 the Local Bus reset pin is de-activated. 3 Local Bus Clock Enable. When this bit is a 1 the Local Bus clock (LBCK) pin is enabled. When this bit is a 0 LBCK pin is permanently low. The Local Bus Clock is a buffered PCI clock. Bus Interface Type. When low (=0) the Local Bus is configured to Inteltype operation, otherwise it is configured to Motorola-type operation. Note that when Mode[1:0] is `01', this bit is hard wired to 0.
Read/Write
EEPROM
Reset PCI RW `0001' (=`0010' for parallel port)
W
28:27 29 30 31
W W W
R RW RW RW
00 0 0 0
Note 1: Note 2: Note 3:
Only values in the range of 0 to Ah (0-10 decimal) are valid. Other values are reserved as writing higher values causes the PCI interface to retry all accesses to the Local Bus as it is unable to complete the transaction in 16 PCI clock cycles. The Lower-Address-CS-Decode parameter is described in sections 7.3.2 & Section 10. These bits are unused for Memory access to the 8-bit Local Bus which uses a fixed decoding to allocate 1K regions to 4 chip selects. For further information on the Local bus, see section 9. Local Bus, UARTs and the Parallel Port are all reset with PCI reset. In Addition, the user can issue the Software Reset Command.
LT2[15:0] enable the card designer to control the data bus during the idle periods. The default values will configure the Local Bus data pins to remain forcing (LT2[7:4] = Fh). LT[15:8] is programmed to place the bus in highimpedance at the beginning of a read cycle and set it back to forcing at the end of the read cycle. For systems that require the data bus to stay in high-impedance, the card designer should write an appropriate value in the range of 0h to Ah to LT2[7:4]. This will place the data bus in high impedance at the end of the write cycle. Whenever the value programmed in LT2[7:4] does not equal Fh, the Local Bus controller will ignore the setting of LT2[15:8] as the data bus will be high-impedance outside write cycles. In this case the card designer should place external pull-ups on the data bus pins LBD[7:0]. While the configuration data is read from the external EEPROM, the LBD pins remain in the high-impedance state. The timing registers define the Local Bus timing parameters based on signal changes relative to a reference cycle which is defined as two PCI clock cycles after IRDY# is asserted for the first time in a frame. The following parameters are fixed relative to the reference cycle.
The Local Bus address pins LBA[7:0] are asserted during the reference cycle. In a write operation, the Local Bus data is available during the reference cycle, however I/O buffers change direction as programmed in LT2[3:0]. In a Motorola type bus write operation, the Read-not-Write pin (LBRDWR#) is asserted (low) during the reference cycle. In a read cycle this pin remains high throughout the duration of the operation. The default settings in LT1 & LT2 registers provide one PCI clock cycle for address and chip-select to control signal set-up time, one clock cycle for address and chip-select from control signal hold time, two clock cycles of pulse duration for read and write control signals and one clock cycle for data bus hold time. These parameters are acceptable for using external OX16C950, OX16C952 and OX16C954 devices connected to the Local Bus, in Intel mode. Some redefinition will be required if the bus is to be operated in Motorola mode. The user should take great care when programming the Local Bus timing parameters. For example defining a value for chip-select assertion which is larger that the value defined for chip-select de-assertion or defining a chipselect assertion value which is greater than control signal assertion will result in obvious invalid local Bus cycles. Page 43
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OXMPCI954
7.4.5
UART Receiver FIFO Levels `URL' (Offset 0x10)
The receiver FIFO level of all internal UARTs are shadowed in Local configuration registers as follows: Bits 7:0 15:8 23:16 31:24 Description UART0 Receiver FIFO Level (RFL[7:0]) UART1 Receiver FIFO Level (RFL[7:0]) UART2 Receiver FIFO Level (RFL[7:0]) UART3 Receiver FIFO Level (RFL[7:0]) Read/Write
EEPROM
Reset PCI R R R R 0x00h 0x00h 0x00h 0x00h
-
7.4.6
UART Transmitter FIFO Levels `UTL' (Offset 0x14)
The transmitter FIFO level of all internal UARTs are shadowed in Local configuration registers as follows: Bits 7:0 15:8 23:16 31:24 Description UART0 Transmitter FIFO Level (TFL[7:0]) UART1 Transmitter FIFO Level (TFL[7:0]) UART2 Transmitter FIFO Level (TFL[7:0]) UART3 Transmitter FIFO Level (TFL[7:0]) Read/Write
EEPROM
Reset PCI R R R R 0x00h 0x00h 0x00h 0x00h
-
7.4.7
UART Interrupt Source Register `UIS' (Offset 0x18)
The UART Interrupt Source register is described below: Bits 5:0 11:6 17:12 23:18 26:24 27 28 29 30 31 Description UART0 Interrupt Source Register (ISR[5:0]) UART1 Interrupt Source Register (ISR[5:0]) UART2 Interrupt Source Register (ISR[5:0]) UART3 Interrupt Source Register (ISR[5:0]) Reserved UART0 Good-Data Status UART1 Good-Data Status UART2 Good-Data Status UART3 Good-Data Status Global Good-Data Status. This bit is the logical AND of bits 27 to 30, i.e. it is set if Good-Data Status of all internal UARTs is set. Read/Write
EEPROM
Reset PCI R R R R R R R R R R 01h 01h 01h 01h 00h 1 1 1 1 1
-
Good-Data status for a given internal UART is set when all of the following conditions are met: * * * ISR reads a level0 (no-interrupt pending), a level 2a (receiver data available, a level 2b (receiver time-out) or a level 3 (transmitter THR empty) interrupt LSR[7] is clear so there is no parity error, framing error or break in the FIFO LSR[1] is clear so no over-run error has occurred
If the device driver software reads the receiver FIFO levels (URL) followed by this register, then if Good-Data status for a given channel is set, the driver can remove the number of bytes indicated by the FIFO level without the need to read the line status register for that channel. This feature enhances the driver efficiency.
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OXMPCI954
For a given channel, if the Good-Data status bit is not set, then the software driver should examine the corresponding ISR bits. For example if bit 29 is low, then the driver should examine bits 17 down to 12 to obtain the ISR[5:0] for UART2. If the ISR indicates a level 4 or higher interrupt, the interrupt is due to a change in the state of modem lines or detection of flow control characters. The device driver-software should then take appropriate measures as would in any other 550/950 driver. When ISR indicates a level 1 (receiver status) interrupt then the driver can examine the Line Status Register (LSR) of the relevant channel. Since reading the LSR clears LSR[7], the device driver-software should either flush or empty the contents of the receiver FIFO, otherwise the Good-Data status will no longer be valid. The UART Receiver FIFO Level (URL), UART Transmitter FIFO Level (UTL), UART Interrupt Source register (UIS) and Global Interrupt Status register (GIS) are allocated adjacent address offsets (10h to 1Ch) in the Base Address Register. The device driver-software can read all of the above registers in single burst read operation. The location offset of the registers are such that the FIFO levels are usually read before the status registers so that the status of the N characters indicated in the receiver FIFO levels are valid.
7.4.8
Bits 3:0 4
Global Interrupt Status and Control Register `GIS' (Offset 0x1C)
Description UART Interrupt Status. These bits reflect the internal interrupt states of UART3 to UART0, respectively.1 MIO0 Status (When device mode `001'/'101'). This bit reflects the state of the internal MIO[0]. The internal MIO[0] reflects the non-inverted or inverted state of MIO0 pin.2 When device mode = `001/'101', this reflects state of the Parallel Port Interrupt The parallel port interrupt is asserted on INTB# in the backwards compatible modes or INTA# in the enhanced modes, by default. MIO1 Status (LCC[6:5]=`00'). This bit reflects the state of the internal MIO[1]. The internal MIO[1] reflects the non-inverted or inverted state of MIO1 pin.2 Function 0 Power-down Interrupt (LCC[6:5] `00'). In this mode this is a sticky bit. When set, it indicates a power-down request issued by Function 0 and would normally have asserted a PCI interrupt if bit 21 was set (see section 8.6). Reading this bit clears it. MIO[11:2] Status. These bits reflect the state of the internal MIO[11:2]. The internal MIO[11:2] reflect the non-inverted or inverted state of MIO[11:2] pins respectively.2 UART Interrupt Mask. When set (1) these bits enable each internal UART to assert a PCI interrupt respectively. When cleared (=0) they prevent the respective channel from asserting a PCI interrupt.3 MIO[0] Interrupt Mask (When device mode `001'/'101'). When set (=1) this bit enables MIO0 pin to assert a PCI interrupt. When cleared (=0) it prevents MIO0 pin from asserting a PCI interrupt.2 Parallel Port Interrupt Mask (When device mode = `001/'101''). When set (=1) this bit enables the Parallel Port to assert a PCI interrupt. When cleared (=0) it prevents the Parallel Port from asserting a PCI interrupt. MIO[1] Interrupt Mask (LCC[6:5]=`00'). When set (=1) this bit enables MIO1 pin to assert a PCI interrupt. When cleared (=0) it prevents MIO1 pin from asserting a PCI interrupt.2 Function 0 Power-down Interrupt Mask (LCC[6:5] `00'). When set (=1) this bit enables the power-down logic in Function0 to assert a PCI interrupt. When Read/Write
EEPROM
Reset PCI R R 0x0h X
-
-
R R
0 X
5
0 W W R RW RW XXXh Fh 1
15:6 19:16 20
W W
RW RW
1 1
21
W
RW
0
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OXMPCI954
Bits
Description cleared (=0) it prevents the power-down logic in Function 0 from asserting a PCI interrupt. MIO Interrupt Mask. When set (=1) these bits enable each MIO[11:2] pin to assert a PCI interrupt respectively. When cleared (=0) they prevent the respective pins from asserting a PCI interrupt.2
Read/Write
EEPROM
Reset PCI RW 3FFh
31:22
W
Note 1: Note 2:
GIS[3:0] are the inverse of UIS[18], UIS[12], UIS[6] and UIS[0] respectively. Systems that do not require the Local Bus or parallel port need not read this register to identify the source of the interrupt as long as they read the UIS (offset 18h) register. The returned value is either the direct state of the corresponding MIO pin or its inverse as configured by the Multi-purpose I/O Configuration register `MIC' (offset 0x04). As the internal MIO can assert a PCI interrupt, the inversion feature can define each external interrupt to be defined as active-low or active-high, as controlled by the MIC register. When the MIO[0] pin has been set-up as an input or output, this can be made to generate an interrupt when the MIO[0] Interrupt Mask (bit 20) is set (=1). This bit enables MIO[0] pin to assert a PCI interrupt. When the MIO[1] pin has been set-up as an input or output, this can be made to generate an interrupt when the MIO[1] Interrupt Mask (bit 21) is set (=1). This bit enables MIO[1] pin to assert a PCI interrupt.
Note 3:
The UART Interrupt Mask register bits are all set after a hardware reset to enable the interrupt from all internal UARTs. This will cater for generic device-driver software that does not access the Local Configuration Registers. The default setting for UART Interrupt Mask bits can be changed using the serial EEPROM. Note that even though by default the UART interrupts are enabled in this register, since after a reset the IER registers of individual UARTs disables all interrupts, a PCI interrupt will not be asserted after a hardware reset. When Mode[2:0]=`010', the MIO pins are used to define a Subsystem ID value, therefore all interrupts due to MIO pins are disabled regardless of the state of the GIS register. The MIO Interrupts Mask register bits are all set after a hardware reset to enable the interrupt from all MIO pins from boot up. The default setting for MIO Interrupt Mask bits can be changed using the serial EEPROM.
Note 4:
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OXMPCI954
7.5
PCI Interrupts
During the system initialisation process and PCI device configuration, system-specific software reads the interrupt pin field to determine which (if any) interrupt pin is used by each function. It programmes the system interrupt router to logically connect this PCI interrupt pin to a system-specific interrupt vector (IRQ). It then writes this routing information to the Interrupt Line field in the function's PCI configuration space. Device driver software must then hook the interrupt using the information in the Interrupt Line field. Interrupt status for all sixteen sources of interrupt is available using the GIS register in the Local Configuration Register set, which can be accessed using I/O or Memory accessed from both logical functions. This facility enables each function to snoop on interrupts asserted from the other function regardless of the interrupt routing. The interrupt from each UART channel is enabled using the IER register and the MCR register for that UART. If the interrupt is enabled and active, then the device will drive the PCI interrupt pin low. Generic device driver software will use the IER register to enable interrupts. The OXMPCI954 offers additional interrupt masking ability using GIS[19:16] (see section 7.4.8). An internal UART channel may assert a PCI interrupt if the interrupt is enabled by IER and GIS[19:16]. All interrupts can be enabled / disabled individually using the GIS register set in the Local configuration registers. When an MIO pin is enabled, an external device can assert a PCI interrupt by driving that pin. The sense of the MIO external interrupt pins (active-high or active-low) is defined in the MIC register. The parallel port can also assert an interrupt (but this will effectively disable the MIO[0] interrupt).
Interrupts in PCI systems are level-sensitive and can be shared. There are up to sixteen sources of interrupt in the OXMPCI954, one in each UART channel and up to twelve from the Multi-Purpose IO pins (MIO11 to MIO0). The Parallel Port and MIO[0] pin share the same interrupt status bit (GIS[4]). The PCI Power Management powerdown interrupt for internal UARTs (Function0) and the MIO[1] pin share the status bit GIS[5]. The Local Bus uses the MIO pins to pass interrupts to the PCI controller. All interrupts are routed to the PCI interrupt pins, INTA# or INTB#. In the backwards compatible modes, the default values for the Interrupt Pin register results in Function 0 interrupts being asserted on the INTA# line and Function1 interrupts being asserted on the INTB# line. In the enhanced modes, both Function 0 and Function 1 interrupts are set to assert on the INTA# line. These default routings may be modified by writing to the Interrupt Pin field in the configuration registers using the serial EEPROM facility. The Interrupt Pin field is normally considered a hard-wired read-only value in PCI. It indicates to system software which PCI interrupt pin (if any) is used by a function. The interrupt pin may only be modified using the serial EEPROM facility, and card developers must not invoke any combination which violates the PCI specification. If in doubt, the default routings should be used. The Following Table relates the Interrupt Pin field to the device pin used. Interrupt Pin 0 1 2 3 to 255 Device Pin used None INTA# INTB# Reserved
Note that the OXMPCI954 only has two PCI interrupt pins : INTA# and INTB#. In the miniPCI mode, INTB# is not available as an interrupt line as the pin is redefined as a dedicated CLKRUN# line.
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OXMPCI954
7.6
Power Management
7.6.1
Power Management of Function 0
The OXMPCI954 is compliant with PCI Power Management Specification Revision 1.1, in the enhanced modes. This is indicated by both functions by their Power Management Capabilities Register (PMC). In the backwards compatibility modes, compliance to version 1.0 is indicated. Each logical function implements its own set of Power Management registers and supports the power states D0, D2 and D3. In miniPCI modes, PME# generation from D3cold is also indicated which preserves PME# context through the use of 3.3v Auxiliary power. See section 8.8 "miniPCI Support" for further details. Power management is accomplished by handling the power-down and power-up ("power management event") requests, that are asserted on the relevant function's interrupt pin and the PME# pin respectively. Each function can assert the PME# pin independently. Power-down requests are not defined by any of the PCI Power Management specifications. It is a device-specific feature and requires a bespoke device driver implementation. The device driver can either implement the power-down itself or use the special interrupt and powerdown features offered by the device to determine when the function or device is ready for power-down. It is worth noting that the PME# pin can, in certain cases, activate the PME# signal when all power is removed from the device. This will cause the PC to wake up from Lowpower state D3(cold). To ensure full cross-compatibility with system board implementations, the use of an isolator FET is recommended (See Diagram). If Power Management capabilities are not required, the PME# pin can be treated as no-connect.
Provided that the necessary controls have been set in the device's local configuration registers (LCC and GIS), the internal UARTs can be programmed to issue powerdown requests and/or `wakeup' requests (power management events), for function 0. Function 0 can be configured to monitor the activity of the serial channels, and issue a power-down interrupt when all of the UARTs are inactive (no interrupts pending and both transmitters and receivers are idle). When all the serial channels are indicating a powerdown request only then will the internal power management circuitry wait for a period of time as programmed into the Power-Down Filter Time. This time is defined by the local configuration register, LCC[7:5]). If the powerdown requests remain valid for this time (this means that all serial channels are still inactive) then the OXMPCI954 will issue a powerdown interrupt on this function's interrupt pin, if this option is enabled. Alternatively, the device driver can poll function 0's powerdown status field in the local configuration register GIS[5] to determine a powerdown request. The powerdown filter stops the UARTs from issuing too many powerdown interrupts whenever the UARTs activity is intermittent. Upon a power down interrupt, the device driver can change the power-state of the device (function 0) as required. Note that the power-state of function 0 is only changed by the device driver and at no point will the OXMPCI954 change its own power state. The powerdown interrupt merely informs the device driver that this logical function is ready for power down. Before placing the device into the lower power states, the driver must provide the means for the function to generate a `wakeup' (power management) event. Whenever the device driver changes function 0's powerstate to state D2 or D3, the device takes the following actions: * The internal clock to the internal UARTs is shut down. * PCI interrupts are disabled regardless of the values contained in the GIS registers. * Access to I/O or Memory BARs is disabled. However, access to the configuration space is still enabled.
PME#
S G
D
PCI connector PME#
VDD
PME# Isolator Circuitry
The device driver can optionally assert/de-assert any of its selected (design dependent) MIO pins to switch-off VCC, disable other external clocks, or activate shut-down modes.
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The device can only issue a wakeup request (a power management event, PME#) if it is enabled by this function's PME_En bit, bit-8 of the PCI Power Management Register PMCSR. PME# assertion, is immediate and does not use the powerdown filter timer. It operates even if the powerdown filter time is set to disabled. Like powerdown, wakeup requests for function 0 can be generated by any serial channel. The means to generate wakeup events from these sources will have been set up prior to placing this function into the powerdown states D2 or D3 (including setting of the PME_En bit). For each UART, when the device (function 0) is in the powerstate D3, only activity on the serial channel's RI# line (the trailing edge of a pulse) will generate a wakeup event. When the device (function 0) is in the power-state D2, then wake-ups are configurable. In this case, a change in the state of any modem line (which is enabled by a 16C950specific mask bit) or a change in the state of the serial input line (again, if enabled by a 16C950-specific mask bit) can issue a wake up request on the PME# pin. It is worth noting that after a hardware reset all of these mask bits are cleared to enable wake up assertion from all modem lines and the SIN line when in the powerstate D2. As the wake up operation from D2 requires at least one mask bit to be enabled, the device driver can for example disable the masks with the exception of the Ring Indicator, so only a modem ring can wake up the computer. In the case for a wake up request from the serial input line EXT_DATA_IN (from the power state D2) then the clock for that channel is turned on so serial data framing can be maintained. When function 0 issues a wake up request from the serial channels, the PME_Status bit in this function's PCI power management registers (PMCSR[15]) will be set. This is a sticky bit which will only be cleared by writing a `1' to it. While PME_En (PMCSR[8]) remains set, the PME_Status will continue to assert the PME# pin to inform the device driver that a power management wake up event has occurred. After a wake up event is signalled, the device driver is expected to return this function to the D0 powerstate.
OXMPCI954
The state of the MIO pin(s) that issues a powerdown request is controlled by the MIC register. This can be active high or active Low. This state can be the same MIO state that asserts function 1's interrupt pin for normal functionality. The assertion of the MIO pins will result in a function 1 powerdown request being made immediately. There is no powerdown filtering time associated with function 1. The powerdown request can be issued on the function's interrupt pin, if this option is enabled. Upon a power down interrupt, the device driver can change the power-state of the device (function 1) as required. Note that the power-state of function 1 is only changed by the device driver and at no point will the OXMPCI954 change its own power state. The powerdown interrupt merely informs the device driver that this logical function is ready for power down. Before placing the device into the lower power states, the driver must provide the means for the function to generate a `wakeup' (power management) event. Whenever the device driver changes function 1's powerstate to state D2 or D3, the device takes the following actions: * Parallel Port placed in a low power mode. * Local Bus Function placed in a low power mode * PCI interrupts are disabled regardless of the values contained in the GIS registers. * Access to I/O or Memory BARs is disabled. However, access to the configuration space is still enabled. Function 1 can only issue a wakeup request (power management event) if it is enabled by this function's PME_En bit, bit-8 of the PCI Power Management Register PMCSR. Wakeup requests for function 1 can only be generated by the Multi_Purpose I/O pin MIO[2]. The means to generate wakeup events from this source will have been set up prior to placing this function into the powerdown states D2 or D3. The state of the MIO[2] pin that results in wakeup requests is determined by the settings in the local configuration register MIC. As soon as the correct logic is invoked than a power management event (wakeup) is asserted. The PME# event is immediate. When function 1 issues a wake up request, the PME_Status bit in this function's PCI power management registers (PMCSR[15]) will be set. This is a sticky bit which will only be cleared by writing a `1' to it. While PME_En (PMCSR[8]) remains set, the PME_Status will continue to Page 49
7.6.2
Power Management of function 1
Provided that the necessary controls have been set in the device's local configuration registers (MIC and GIS), up to 9 Multi_Purpose pins (MIO[11:3]) can be programmed to issue powerdown requests but only MIO[2] can be set to generate `wakeup' requests (power management events), for function 1. The Parallel Port or the Local Bus function are not capable of issuing powerdown requests or power management events but can be placed in a low power state through power management involving the MIO pins. DS-0019 Jun 05
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assert the PME# pin to inform the device driver that a power management wake up event has occurred. After a
OXMPCI954
wake up event is signalled, the device driver is expected to return this function to the D0 power-state
LCC[6:5] 00 01 10 11 01 10 11
GIS[21] X 0 0 0 1 1 1
Power-down Filter Time N/A 4s 129 s 518 s 4s 129 s 515 s
Operation Function 0 power-down interrupt is disabled. MIO[1] can assert a PCI interrupt if GIS[21] is set. Function 0 power-down interrupt is disabled. GIS[5] reflects the state of the internal power-down mode for polling operation. MIO[1] interrupt is disabled Function 0 power-down is enabled. GIS[5] reflects the state of the internal power-down mode. MIO[1] interrupt is disabled.
Table 6: Function 0 (UARTs) Power down interrupt settings
LCC[7] 0 1 1 1 1
MIC[5:4] XX 00 00 01 01
MIO2 Rising X yes no X X
MIO2 Falling X X X Yes No
Function1 PME_Status Remains unchanged Gets set Remains unchanged Gets set Remains unchanged
Table 7: Function 1 (Local Bus) Wake-up configuration
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7.7
Unique Bar Option - for Function 0
PCI Space Dword No 4 5 6 7 8 9 BAR 0 1 2 3 4 5 Description UART 0 UART 1 UART 2 UART 3 Local Registers QUAD UARTs and Local Registers In Memory Space Bar type I/O (8 bytes) I/O (8 bytes) I/O (8 bytes) I/O (8 bytes) I/O (32 bytes) Memory 4K bytes
In the backwards compatible modes, I/O access to the internal UARTs is through a common Base Address Register (BAR0). The BAR definitions for Function 0, in the backwards compatible modes, is as shown below. PCI Space Dword No 4 5 6 7 8 9 BAR 0 1 2 3 4 5 Description Internal UARTs Internal UARTs Local Registers Local Registers NULL NULL Bar type I/O (32 bytes) Mem (4K bytes) I/O (32 bytes) Memory 4K bytes NULL NULL
Some device drivers would prefer that each UART was accessible via its own I/O Base Address Register. This option is available in any of the enhanced modes, either through the selection of the device's mode pins or by utilising the eeprom controller to set the `unique bar mode via seeprom' field, bit[26] of the MIC local register. The following table lists which device modes support this option. Device Mode 000 001 010 011 100 101 110 111 Backwards Compatible / Enhanced Backwards Compatible Backwards Compatible Backwards Compatible Enhanced Enhanced Enhanced Reserved N/A Availability of unique bar mode No No No Set by Default Available through EEPROM option Available through EEPROM option No No
NOTE that the `Unique Bar Mode' only affects the BAR region of Function0. Function 1 is not affected and maintains the configuration set by the device mode pins.
In this case, BAR0 to BAR3 reserve 8 bytes of I/O space to allow access to the registers of UART 0 to UART 3, respectively. As a result of this change, the I/O Base Address for the local registers is defined by BAR4, and BAR5 becomes the Memory Base Address register for both the internal UARTs and the Local Registers. For the purposes of device drivers recognising this configuration, a Device ID of "9504" is reserved and must be returned for function 0 when the `unique bar' option has been exercised. This Device ID is automatically returned during configuration accesses when the unique bar option is selected by the device pins (MODE = "011"). However, when this option is selected via the EEPROM (in the Enhanced modes) then the EEPROM is also required to change the Device ID of function 0 to "9504" by additionally downloading into the PCI Configuration Zone of function 0. Access to UARTs and Local Registers in Memory Space : In the unique bar mode, BAR 5 serves as the Memory Base Address Register for the internal UARTs and the Local Registers. When accessing BAR5, bit 7 of the address determines access to the UARTs or the Local Registers. With Bit 7 = 0, Fields 6:5 define which UART to access, Fields 4:2 define which UART register to access. With Bit 7 = 1, Fields 6:2 Define the BYTE offset for the local registers. Eg 00000b for the LCC register, 00100h for the MIC register. In both cases, fields 1:0 are not utilised and are to be set to zeros. This is because a DWORD is used to hold a single Byte, in Memory Space.
When the `unique bar mode' option is selected, the Base Address Register Region for Function 0 changes as follows.
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7.8
MiniPCI Support - Enhanced Modes only
In the miniPCI mode, the following changes take place to the device functionality and pin definitions.
The OXMPCI954 device operates in the miniPCI mode when Pin 88/M15 is tied HIGH in any one of the Enhanced Modes. For all other cases, the device operates in the PCI mode. MiniPCI mode is not available in any of the backwards compatible modes. Function/Pin Z_INTA Z_INTB D3cold Support
MiniPCI mode PCI interrupt pin For both function 0 and function 1. Redefined as a CLKRUN# pin No PCI interrupts available on this pin PME# from D3 Cold supported Available and indicated in the PCI Power Management Registers
PCI Mode PCI Interrupt pin. For function 0. For function 1 in the Enhanced Modes. PCI interrupt pin For function 1 in the backwards Compatibility Mode. No PME# D3 cold supported. As indicated in the PCI Power Management Registers.
CLKRUN# The OXMPCI954 device is not tolerant to clock stopping on the PCI_CLK line, for full UART functionality. While the UARTs themselves are not dependent upon the PCI_CLK line, and use the crystal oscillator pin as their main clock source, some parts of the device require that the PCI_CLK be operational (ie not stopped) to allow reliable operation of the internal UARTs. Such parts include writing/reading of the UART registers and interrupt handling. For this reason, the OXMPCI954 device implements CLKRUN# to prevent the host from stopping the PCI_CLK (until such time it is not needed). The circuitry handling the CLKRUN# line is compliant to the CLKRUN# requirements as defined by the PCI Mobile Design Guide, version 1.1. Provided that the Central Resource holds the CLKRUN# line active (low), to indicate that the PCI_CLK is enabled, then there is no intervention by the OXMPCI954 device which keeps it's side of the CLKRUN# driver inactive. The CLKRUN# line is a bi-directional pin. When the Central Resource synchronously de-asserts the CLKRUN# line (by initially driven the line high and then leaving it in the high impedance state) to signal the Central Resource's intention to stop (or slow) the PCI_CLK, then it is prevented from doing so by the target that asserts (drives low) the CLKRUN# line 2 clock cycles following the de-assertion. The CLKRUN# line is only asserted by the target for 2 clock cycles, during which time the Central Resource is expected to drive (and hold) the CLKRUN# line asserted, until the next attempt by the host to stop the clock. In this case, the cycle repeats. DS-0019 Jun 05
By default, the clock control circuitry of the OXMPCI954 (in the miniPCI mode) is always enabled. This means that the Central Resource is prevented from stopping the PCI_CLK at all times, as all requests by the Central Resource to stop this clock (by de-asserting the CLKRUN# line) are met by the target re-asserting the CLKRUN# line 2-clock cycles later. This may be an issue from a power management point of view as this default behaviour may prevent the system from going into a low power state or may result in the system being partially shut-down due to the need to maintain PCI_CLKs to the OXMPCI954 based miniPCI card. The clock control circuitry associated with the CLKRUN# line has been provided with controls to help overcome this. In the miniPCI mode (Enhanced mode), the local registers provide 2 controls associated with the CLKRUN# line. These Read-Write fields are accessible via PCI transactions or can be set up by the external EEPROM by downloading into the MIC register of the Local Register Zone. Control CLKRUN# Circuitry Disable CLKRUN# Control via Power Management MIC Register Bit Bit 30 Bit 29 Default State 0 0
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Bits 30:29 00 01 10 11
CLKRUN Circuitry Status CLKRUN#' Operation Enabled (Never Stop PCI-CLK) CLKRUN# Operation via Power Management Control CLKRUN# Operation Disabled (Allow PCI_CLK to stop) CLKRUN# Operation Disabled (Allow PCI_CLK to stop)
device drivers and the host will be required to determine the most suitable point to disable the clock control circuitry. Disabling the clock control circuitry when the OXMPCI954 device is in the fully operational state (eg D0 state) is not recommended as some hosts have been designed to periodically attempt to stop the PCI_CLK as a normal routine. In these cases, if the clock control circuitry has been disabled then the PCI_CLK will be stopped at the next opportunity. If large file transfers are/will be taking place when this event has occurred then this may lead to corrupted data being transmitted/received. In additon to the Clkrun# Circuitry Disable bit, there is an additional control called Clkrun# Control via Power Management. As the name suggests, this allows the clock control logic associated with the CLKRUN# line to be controlled by the Power Management states of the OXMPCI954 device. This is a hardware assist and does not require software involvement with the exception of enabling this field in the 1st place (although this can also be achived via the external eeprom). When the Clkrun Control via Power Management is selected, the device makes use of the knowledge that any attempts by the host (Central Resource) to place both of the functions into a low power state (states D2 or D3 in power management terminology) is a pre-empt condition to the host stopping the PCI-CLK to the OXMPCI954 device in order to reduce power consumption of the card and thus the system. The host is not expected to stop the PCI-CLK to the OXMPCI954 device when at least 1 of the 2 functions is in the fully operation state (D0 state). A statemachine has been built-in that handles the clock control circuitry according to the D0, D2, D3 states of each function. This is as shown overleaf.
The Clkrun# Circuitry Disable bit, allows the device drivers to disable (and re-enable) the clock control circuitry associated with the CLKRUN# line to meet the overall Power Management of the device and the system. When the CLKRUN# circuitry is disabled, then when the CLKRUN# line is deasserted by the Central Resource at the next available opportunity, no attempt is made by the target to assert the CLKRUN# line thereby allowing the Central Resource to stop the PCI_CLK. Once the PCI_CLK is stopped, it is still possible to re-enable the clock run circuitry by writing to the disable field (with a `0') as the Central Resource is expected to restart the PCI_CLK for a sufficient time to allow the write transaction to take place. Once the transaction has been completed, the clock control circuitry will then prevent the central resource from stopping the PCI_CLK until the clock control circuitry is again disabled. While it is perfectly feasible that the clock control circuitry can be disabled (re-enabled) at leisure, the clock control circuitry should only be disabled prior to the device being placed into the low power states D2/D3 by the host, when no operations other than a wake-up are expected from the UARTs. Some interaction between
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H/W Reset Enable CLKRUN#
CLKRUN# Circuitry Enabled (Either Function in D0 state)
Both Functions Placed in Low Power State Disable CLKRUN#
CLKRUN# Disabled (Both Functions in Low power State) PME# Event (wake-up) Enable CLKRUN# Both functions return to fully operation state (D0) CLKRUN# Circuitry Enabled (both function in Low power State)
When either of the 2 functions are in the D0 PowerManagement state, the CLKRUN# circuitry is enabled to prevent the host from stopping the PCI_CLK, at all times. When the host places both functions into any one of the 2 low power states (D2 or D3) then, and only then, is the CLKRUN# circuitry disabled. This means that the host will be able to stop the PCI_CLK at the next available opportunity, which was the likely purpose of placing both functions into a low power state. Once in the low power state, the OXMPCI954 device is not driven by any PCI_CLKs but controls would have been set up by the device drivers to allow the OXMPCI954 device to generate `wake-up' or PME# events. This PME# generation will be via the Z_CTS and Z_RI pins for function0, and the MIO-2 pin for function 1. When the OXMPCI954 generates a PME# event, this event is sufficient to get the attention of the Central Resource that will kick-start the host to restart the PCI_CLKs to the device. The same PME# event is used internally to re-
enable the CLKRUN# circuitry, so that if the host attempts to stop the PCI_CLK before both functions are placed back into the D0 (fully operational state) then it is prevented from doing so. The CLKRUN# circuitry can only be disabled again (ie the cycle is repeated) once both functions are placed back into the fully operation state DO. The host is expected to do this following a PME# wake-up event. The OXMPCI954 device should only be used with hosts that implement the CLKRUN# line and the CLKRUN# protocol. Some hosts may have the CLKRUN# line but may not necessarily implement the CLKRUN# protocols, instead leaving the CLKRUN# pin permanently held in the active (low) state. This will be taken by the OXMPCI954 device as the PCI_CLK always running. Such hosts may then remove the PCI_CLK from the OXMPCI954 device without notification on the CLKRUN# line when requesting the SUSPEND function. This may lead to corrupted data when file transfers subsequently take place owing to loss of the PCI_CLK.
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PME# Generation from D3 Cold In the miniPCI mode, the OXMPCI954 supports PME# generation from the D3 cold state. This is indicated by bit 15 of both functions' PCI power management register PMC (Power Management Capabilities) that indicates "PME# can be asserted from D3cold". For all PCI applications (whether in the backwards compatible mode or in the Enhanced Modes), the PMC register makes no such indications and all Power Management Status and PME# context will be lost following a PCI Reset. For PME# generation in the D3cold, the OXMPCI954 is required to make use of auxiliary 3.3v power when the main 3.3v power has been removed. See Chapter 5 of the PCI Local Bus Power Management Interface Specification. This changeover to/from the main/auxiliary power needs to be handled by the external circuitry that supplies Vcc to the OXMPCI954, in such a way as to not cause any supply interruptions (dropouts) as far as the OXMPCI954 device is concerned. Otherwise, this will result in the loss of the OXMPCI954's internal states. The circuits must be such that there are no sneak-paths between the main 3.3v power and the Auxiliary 3.3v power as these power planes are to be isolated at all times (miniPCI cards cannot connect 3.3v AUX to 3.3v main, or vice versa). When the OXMPCI954 device has been set up to provide wake-up events (PME#), then the OXMPCI954 device will generate PME# events via the Z_RI lines for function 0 and via the MIO_2 line for function 1 when the device is in the D3 cold state (while auxiliary powered). The OXMPCI954 in the miniPCI mode preserves PME# context when the device is transitioned from the D3 cold to the D0 (uninitialised) transition via the Hardware Reset invoked by the PCI RST# line. PME# Context is also preserved following the soft reset when restoring a function from the D3hot state.
When preserving the PME# context, the OXMPCI954 maintains the status of the following registers Bit 8 of the function's PMCSR register. Status of the PME_Status bit Bit 15 of the function's PMCSR register. As a result, this preserves the Status of the PME# line. Preserving PME# Context has 2 issues that need to be handled by the host. These are listed here for reference purposes only. 1. Since the PCI reset does not affect the status of the fields PME_En and PME_Status, there is a possibility that when power is first supplied to the OXMPCI954 device (in the miniPCI mode of operation) that the state of the PME# line is unknown (PME_status is unknown). The host controller must be able to handle this condition until these 2 fields have been intialised by writing to them with the appropriate values. This has been noted in Section 3.2.4 of the PCI Power Management Specification , revision 1.1, that states "system software is required to explicitly initialize all PME# context, for all functions, during initial operating system load." when PME# generation from D3cold is supported. In the D3cold state, when the OXMPCI954 generates a `wake-up' (PME#) event, then this status (PME# wakeup) persists when the OXMPCI954 is transitioned from the D3cold state to the D0(uninitialised) via a PCI Reset. The host controller must be able to handle this condition until the PME_status and/or PME_En bits have been wriiten to with the appropriate values to disable the PME# wake-up request. Status of the PME_En bit
2.
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7.9
Standalone Mode
The standalone mode of the OXMPCI954 device offers a synchronous local bus access to the internal QUAD Uarts, without the overheads of the PCI Bus and the associated PCI Configuration registers (which are held inactive). While it is perfectly possible that access to the internal QUAD UARTs (in this mode) can be through any device that implements an 8-bit local bus function, as long as all the relevant timings are met, this mode has been specifically designed to be used with the 8-bit local bus function of another OXMPCI954 device in order to expand the number of UARTs on the add-in card. Expansion of UART channels is already possible through the use of devices such as the asynchronous OX16C954 device but the standalone mode offers an additional means of UART expansion. When the OXMPCI954 is utilised in the standalone mode, it must be wholly driven by the 8-bit local bus function of the driving OXMPCI954 device. In particular, the PCI_CLK and the PCI Reset Signals are not permitted to be connected directly to the corresponding pins of the standalone device (for excessive loading considerations). The following diagram indicates the recommended connectivity between the driving OXMPCI954 device and the standalone mode OXMPCI954 devices.
Quad UARTs (m PCI954 in Standalone Mode)
Uart Signals {3:0}
Uart Signals {3:0}
PCI_CLK PCI RESET#
Buffered_CLK, Local Bus Reset# Local Trans En
Quad UARTs (m PCI954 in Standalone Mode)
Uart Signals {3:0}
Uart Data
PCI Bus
m PCI954 QUAD Uart w ith 8-bit local bus (Backwards com patible or Enhanced Modes)
Quad UARTs (m PCI954 in Standalone Mode)
Uart Signals {3:0}
Individual Chip Selects
Microwire Eeprom
Quad UARTs (m PCI954 in Standalone Mode)
Uart Signals {3:0}
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The following table lists the recommended connections when interfacing one or more standalone devices, to a driving OXMPCI954. Standalone Mode Signal Pin Buffered_Clk RST# Uart Interrupt OXMPCI954 (Driver) Signal Pin Buffered_CLK Z_Local_Reset MIO(x) Comments CLK signal to standalone device(s) Reset# Signal to standalone device(s) Uart Interrupt line of the standalone device can be connected to any unused MIO pin of the driving OXMPCI954 device, to pass over the uart interrupt as a function1 interrupt (on the driving device's PCI Z_INTA/Z_INTB lines). For multiple standalone devices, each uart interrupt pin must be connected to a separate MIO pin of the driving OXMPCI954. Uart Data I/O Buffer Control Address[4:3] Selects UART Address[2:0] Selects UART register Each Standalone Device must have its chip select signal driven by each z_local_cs(x) of the driving mPCI954 device. Eg Chip Select (Standalone0) = Z-local_cs(0) Chip Select (Standalone1) = Z-local_cs(1) Chip Select (Standalone2) = Z-local_cs(2) Chip Select (Standalone3) = Z-local_cs(3) Write signal to standalone devices(s) Read signal to standalone devices(s) Bidirectional UART read/write Data
Read Data Control Uart Addr [4:0] Chip Select
Local_Trans_En Local Address [4:0] Z_Local_CS(x)
Write# Read# Uart data [7:0]
IOW# IOR# Local_Data[7:0]
Since the PCI Bus interface is not used in the standalone mode of the OXMPCI954 device, then all PCI inputs must be tied to their inactive states.
In order to support the standalone devices, the default LT1/LT2 values associated with the 8-bit local bus function of the driving device need to be changed. The standalone mode devices require several clock cycles for read/write transactions on the local bus as compared to the asynchronous counterpart, the OX16C954. This means that access to the UARTS in the standalone devices is inherently slower than accessing the UARTs in the OX16C954 devices. There are no UART performance penalties. In addition, the I/O bar size of BAR0 (of function 1) for the driving device is required to match the I/O address range of all the standalone UARTs and the lower-CS decode needs to be set so that the relevant z_local_cs line is activated to chip select the standalone devices. The changes to LT1/LT2 are as shown in the following table. (all other local register values to take the default values). Description Read Chip-Select De-assertion Write Chip-Select De-assertion Read Control De-assertion Write Control De-assertion Write Data Bus Assertion Write Data Bus De-assertion Read Data Bus Assertion Read Data Bus De-assertion DS-0019 Jun 05 New Value (Reset Value) 4 (3) 4 (2) 4 (3) 2 (2) 0 (0) F (F) 4 (4) 0 (0) Local Register Field LT1[7:4] LT1[15:12] LT1[23:20] LT1[31:28] LT2[3:0] LT2[7:4] LT2[11:8] LT2[15:12] Page 57
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Description Interfacing to Single Standalone Device IO Space of BAR0 in Function 1 Lower Address CS decode Interfacing to 4 Standalone Devices IO Space of BAR0 in Function 1 Lower Address CS decode Local Bus Clock Enable (Buffered_Clk) The above table assumes two cases.
New Value (Old Value) 4 (4). 5 (1). 6 (4). 5 (1). 1 (0)
Local Register Field LT2[22:20] LT2[26:23] LT2[22:20] LT2[26:23] LT2[30]
Comments I/O space 32 bytes Z_local_cs0 always activated I/O space 128 bytes. Z_local_cs0..3 activated
1. Single Standalone Device, chip selected by the LBCS0# line of the driving OXMPCI954 device. In this case, the 8-bit local bus must address a single standalone device, with 4 UARTs, with each UART containing 8 registers. This requires 32 bytes of I/O space such that Local Address[4:3] Local Address[2:0] Selects the Standalone Mode UART channel Selects the UART registers
All transactions to the 32 bytes of I/O space, must activate the LBCS0# line. So the `lower_cs_decode' value has been set to decode A5. As this is always `0' for all 32 byte I/O accesses, the LBCS0# will be activated for all transactions thus selecting the single standalone device. 2. Quad standalone devices, chip selected by LBCS0#, LBCS1#, etc lines of the driving OXMPCI954 device. In this case, the 8-bit local bus must address 4 standalone devices, each containing 4 UARTs, with each UART containing 8 registers. This requires 128 bytes of I/O space such that Local Address[6:5] Local Address[4:3] Local Address[2:0] Selects Standalone Mode Device Selects the UART channel Selects the UART registers
The LBCS# lines must be activated depending upon the settings of local_address[6:5}. So the `lower_cs_decode' value has been set to decode A5. This will activate the correct LBCS# line to chip select the relevant standalone device for read/write accesses.
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7.10 Device Drivers
This section has been provided for external device driver development. The use of DEVICE IDs alone, will not allow device drivers to determine if the OXMPCI954 device is operating in the backwards-compatible mode or the enhanced mode. Nor will it indicate if the device is operating in the PCI or miniPCI modes. This is because the same DEVICE ID's are returned for functions operating in the backwards compatibility mode and in the enhanced mode. For example, mode 000 (QUAD-UART, 8-bit Local Bus, backwards compatible mode) and mode 100 (QUADUART, 8-bit Local Bus, Enhanced mode) both return Device IDs of 9501/9511 for the 2 functions, respectively. Device Drivers are required to know the exact modes for the purposes of fine-tuning the drivers to match the feature content of the OXMPCI954 device. For example, device drivers will need to know if the device operates in the miniPCI mode for controlling the miniPCI-related features. In order for device drivers to distinguish between the different modes of operation, some reserved fields of the existing local registers LCC and MIC have been defined to indicate the mode of operation. These are as follows Local Register LCC Register (DWORD offset 00h) Bits 1:0 Status of the MODE1, MODE0 pins (Read only) Bit 31 Status of the MODE2 pin (Read Only) Local Register MIC Register (DWORD offset 04h) Bit 25 Reserved. Bit 26 Status of unique bar mode via EEPROM (Read only) Bit 27 MiniPCI Status (Read Only) Bit 28 Enhanced Mode Status (Read Only) Bit 29 CLKRUN control via Power Management -
(R/W field for miniPCI application)
Bit 30 Bit 31
Disable CLKRUN control (R/W field for MiniPCI) Disable Parallel Port Filter (R/W field for Parallel Port)
It is expected that device drivers will inspect (at least) bits 27 and 28 of the MIC register to determine if the device is operating in the backwards compatibility mode or enhanced mode, and if in the enhanced mode whether the device is operating in the PCI or miniPCI environment. This information is required in order to make use of controls for the miniPCI applications and for the parallel port filters. The only exception to this will be where the Device ID of "9504" is present (unique bar mode). In this case, the device will already be operating in the enhanced mode but the device driver will still need to determine if the device is operating in the PCI or miniPCI environment. For all backwards compatibility modes, these register fields have been designed such that they return 0's and all fields are read only. This is as per the existing OX16PCI954 device. For function 1, the local registers will always exist in the same Base Address Registers irrespective of whether function 1 is an 8-bit local bus or a parallel port. For access via function 0, however, access to the local registers is dependent upon whether the UARTs are in common I/O space or in the unique bar I/O space as this will relocate the local registers onto a different base address register (BAR). For the purposes where a single device driver has been developed that caters not only for the OXMPCI954 device but also the existing OX16PCI954 device, then it is possible to distinguish between the OXMPCI954 operating in the backwards compatibility mode and the original OX16PCI954 device by reading the UART Rev ID's of the UARTs. The OXMPCI954 will return a different version for the UARTs. This distinction cannot be made by reading the above local register fields as both devices will return 0's. This has been mentioned for information purposes only.
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8
INTERNAL OX16C950 UARTS
Each of the four UART channels in the OXMPCI954 operates individually as an OX16C950 high-performance serial port. Each channel has its own full set of registers, but all share a common clock and FIFOSEL pin. After a device reset, a common configuration state is loaded into all four channels, but after this time each can be operated individually through its own 8 byte block of addressable space.
8.1
Operation - mode selection
Each channel is backward compatible with the 16C450, 16C550, 16C654 and 16C750 UARTs. The operation of the ports depends on a number of mode settings, which are referred to throughout this section. The modes, conditions and corresponding FIFO depth are tabulated below: UART Mode 450 550 Extended 550 650 750 9501 FIFO size 1 16 128 128 128 128 FCR[0] 0 1 1 1 1 1 Enhanced mode (EFR[4]=1) X 0 0 1 0 1 FCR[5] (guarded with LCR[7] = 1) X 0 X X 1 X FIFOSEL pin X 0 1 X 0 X
Note 1: 950 mode configuration is identical to a 650 configuration
Table 8: UART Mode Configuration increased to 128 by writing a 1 to FCR[5]. Note that access to FCR[5] is protected by LCR[7]. i.e., to set FCR[5], software should first set LCR[7] to temporarily remove the guard. Once FCR[5] is set, the software should clear LCR[7] for normal operation. The 16C750 additional features are available as long as the UART is not put into Enhanced mode; i.e. ensure EFR[4] = `0'. These features are: * * * Deeper FIFOs Automatic RTS/CTS out-of-band flow control Sleep mode
8.1.1
450 Mode
After a hardware reset, bit 0 of the FIFO Control Register (`FCR') is cleared, hence the UARTs are compatible with the 16C450. The transmitter and receiver FIFOs (referred to as the `Transmit Holding Register' and `Receiver Holding Register' respectively) have a depth of one. This is referred to as `Byte mode'. When FCR[0] is cleared, all other mode selection parameters are ignored.
8.1.2
550 Mode
Connect FIFOSEL to GND. After a hardware reset, writing a 1 to FCR[0] will increase the FIFO size to 16, providing compatibility with 16C550 devices.
8.1.5
650 Mode
8.1.3
Extended 550 Mode
Connect FIFOSEL to VDD. Writing a 1 to FCR[0] will now increase the FIFO size to 128, thus providing a 550 device with 128 deep FIFOs.
8.1.4
750 Mode
For compatibility with 16C750, connect FIFOSEL to GND. Writing a 1 to FCR[0] will increase the FIFO size to 16. In a similar fashion to 16C750, the FIFO size can be further
The 950 UART is compatible with the 16C650 when EFR[4] is set, i.e. the device is in Enhanced mode. As 650 software drivers usually put the device in Enhanced mode, running 650 drivers on the one of the UART channels will result in 650 compatibility with 128 deep FIFOs, as long as FCR[0] is set. This is regardless of the state of the FIFOSEL pin. Note that the 650 emulation mode of the OXMPCI954 provides 128-deep FIFOs rather than the 32 provided by a legacy 16C654.
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In enhanced (650) mode the device has the following features available over those provided by a generic 550. (Note: some of these are similar to those provided in 750 mode, but are enabled using different registers). * * * * * * * Deeper FIFOs Sleep mode Automatic in-band flow control Special character detection Infra-red "IrDA-format" transmit and receive mode Transmit trigger levels Optional clock prescaler
OXMPCI954
The 950 trigger levels are enabled when ACR[5] is set where bits 4 to 7 of FCR are ignored. Then arbitrary trigger levels can be defined in RTL, TTL, FCL and FCH registers (see section 8.11). The Additional Status Register (`ASR') offers flow control status for the local and remote transmitters. FIFO levels are readable using RFL and TFL registers. The UART has a flexible prescaler capable of dividing the system clock by any value between 1 and 31.875 in steps of 0.125. It divides the system clock by an arbitrary value in "M+N/8" format, where M and N are 5- and 3-bit binary numbers programmed in CPR[7:3] and CPR[2:0] respectively. This arrangement offers a great deal of flexibility when choosing an input clock frequency to synthesise arbitrary baud rates. The default division value is 4 to provide backward compatibility with 16C650 devices. The user may apply an external 1x (or Nx) clock for the transmitter and receiver to the RI# and DSR# pin respectively. The transmitter clock may instead be asserted on the DTR# pin. The external clock options are selected through the CKS register (offset 0x02 of ICR). It is also possible to define the over-sampling rate used by the transmitter and receiver clocks. The 16C450/16C550 and compatible devices employ 16 times over-sampling, where there are 16 clock cycles per bit. However the 95x UART channels can employ any over-sampling rate from 4 to 16 by programming the TCR register. This allows the data rates to be increased to 460.8 Kbps using a 1.8432MHz clock, or 15 Mbps using a 60 MHz clock. The default value after a reset for this register is 0x00, which corresponds to a 16 cycle sampling clock. Writing 0x01, 0x02 or 0x03 will also result in a 16 cycle sampling clock. To program the value to any value from 4 to 15 it is necessary to write this value into the TCR i.e. to set the device to a 13 cycle sampling clock it would be necessary to write 0x0D to TCR. For further information see section 8.10.3 The UARTs also offer 9-bit data frames for multi-drop industrial applications.
8.1.6
950 Mode
The additional features offered in 950 mode generally only apply when the UART is in Enhanced mode (EFR[4]='1'). Provided FCR[0] is set, in Enhanced mode the FIFO size is 128 regardless of the state of FIFOSEL. Note that 950 mode configuration is identical to that of 650 mode, however additional 950 specific features are enabled using the Additional Control Register `ACR' (see section 8.11.3). In addition to larger FIFOs and higher baud rates, the enhancements of the 950 mode over 650 emulation mode are: * * * * * * * * * * * * * * Selectable arbitrary trigger levels for the receiver and transmitter FIFO interrupts Improved automatic flow control using selectable arbitrary thresholds DSR#/DTR# automatic flow control Transmitter and receiver can be optionally disabled Software reset of device Readable FIFO fill levels Optional generation of an RS-485 buffer enable signal Four-byte device identification (0x16C9500A) Readable status for automatic in-band and out-ofband flow control External 1x clock modes (see section 8.10.4) Flexible "M+N/8" clock prescaler (see section 8.10.2) Programmable sample clock to allow data rates up to 15 Mbps (see section 8.10.3). 9-bit data mode Readable FCR register
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8.2
Register description tables
Each UART is accessed through an 8-byte block of I/O space (or through memory space). Since there are more than 8 registers, the mapping is also dependent on the state of the Line Control Register `LCR' and Additional Control Register `ACR': 1. LCR[7]=1 enables the divider latch registers DLL and DLM. 2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection. 3. ACR[7]=1 enables read access to the 950 specific status registers. 4. ACR[6]=1 enables read access to the Indexed Control Register set (ICR) registers as described on page 64.
Register Name THR 1 RHR 1 IER 1,2 650/950 Mode 550/750 Mode FCR 3 650 mode 750 mode 950 mode ISR 3 LCR 4 MCR 3,4 550/750 Mode 650/950 Mode LSR 3,5 Normal 9-bit data mode MSR 3 101 R 010 011 R R/W 010 W Address 000 000 R/W W R CTS interrupt mask RTS interrupt mask Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data to be transmitted Data received Special Char. Sleep Detect mode Alternate Unused sleep mode RHR Trigger THR Trigger Level Level RHR Trigger FIFO Unused Level Size Unused FIFOs enabled Divisor latch access Tx break Interrupt priority (Enhanced mode) Force parity CTS & RTS Flow Control XON-Any THR Empty Odd / even parity Enable Internal Loop Back Rx Break Parity enable Modem interrupt mask Rx Stat interrupt mask THRE interrupt mask RxRDY interrupt mask
001
R/W
Tx Trigger Enable
Flush THR
Flush RHR
Enable FIFO
Interrupt priority (All modes) Number of stop bits
Interrupt pending Data length
Unused 100 R/W Baud prescale Data Error IrDA mode Tx Empty
OUT2 (Int En)
OUT1
RTS
DTR
Framing Error
Parity Error
Overrun Error
RxRDY
110
R
DCD
RI
SPR 3 Normal 111 R/W 9-bit data 9th Tx Unused mode data bit Additional Standard Registers - These registers require divisor latch access bit (LCR[7]) to be set to 1. DLL DLM 000 001 R/W R/W Divisor latch bits [7:0] (Least significant byte) Divisor latch bits [15:8] (Most significant byte)
9th Rx data bit Delta Trailing DSR CTS DCD RI edge Temporary data storage register and Indexed control register offset value bits
Delta DSR
Delta CTS
Table 9: Standard 550 Compatible Registers
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Register Name EFR XON1 9-bit mode XON2 9-bit mode XOFF1 9-bit mode XOFF2 9-bit mode
Address
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
010 100 101 110 111
R/W R/W R/W R/W R/W
To access these registers LCR must be set to 0xBF CTS RTS Special Enhance In-band flow control mode flow Flow char mode control control detect XON Character 1 Special character 1 XON Character 2 Special Character 2 XOFF Character 1 Special character 3 XOFF Character 2 Special character 4
Table 10: 650 Compatible Registers
Register Name ASR 1,6,7 RFL 6 TFL 3,6 ICR 3,8,9
Address 001 011 100 101
R/W R/W 7 R R R/W
Bit 7 Tx Idle
Bit 6 FIFO size
Bit 5 FIFOSEL
Bit 4
Bit 3
Bit 2
Bit 1 Remote Tx Disabled
Bit 0 Tx Disabled
Special DTR RTS Char Detect Number of characters in the receiver FIFO
Number of characters in the transmitter FIFO Data read/written depends on the value written to the SPR prior to the access of this register (see Table 12)
Table 11: 950 Specific Registers
Register access notes:
Note 1: Requires LCR[7] = 0 Note 2: Requires ACR[7] = 0 Note 3: Requires that last value written to LCR was not 0xBF Note 4: To read this register ACR[7] must be = 0 Note 5: To read this register ACR[6] must be = 0 Note 6: Requires ACR[7] = 1 Note 7: Only bits 0 and 1 of this register can be written Note 8: To read this register ACR[6] must be = 1 Note 9: This register acts as a window through which to read and write registers in the Indexed Control Register set
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Register Name ACR
SPR Offset 10 0x00
R/W R/W
Bit 7 Additiona l Status Enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indexed Control Register Set ICR 950 DTR definition and Read Trigger control Enable Level Enable
CPR TCR CKS TTL RTL FCL FCH ID1 ID2 ID3 REV CSR NMR MDM RFC GDS PIDX CKA
0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0X0F 0X10 0x12 0x13
R/W R/W R/W R/W R/W R/W R/W R R R R W R/W R/W R R R R/W 0 FCR[7] 0 Tx 1x Mode Unused Unused Unused Unused
Auto Tx Rx DSR Disable Disable Flow Control Enable 5 Bit "integer" part of 3 Bit "fractional" part of clock prescaler clock prescaler Unused 4 Bit N-times clock selection bits [3:0] Tx CLK BDOUT DTR 1x Rx 1x 0 Receiver Select on DTR Tx CLK Mode Clock Sel[1:0] Transmitter Interrupt Trigger Level (0-127) Receiver Interrupt Trigger Level (1-127) Automatic Flow Control Lower Trigger Level (0-127) Automatic Flow Control Higher Trigger level (1-127) Hardwired ID byte 1 (0x16) Hardwired ID byte 1 (0xC9) Hardwired ID byte 1 (0x50) Hardwired revision byte (0x0A) Writing 0x00 to this register will reset the UART (Except the CKS register) 9th Bit 9th Bit 9th Bit 9th Bit SChar 4 SChar 3 SChar 2 SChar 1 SIN Modem Trailing DCD wakeup Wakeup RI edge Wakeup disable Disable disable disable FCR[5] FCR[4] FCR[3] FCR[2] 0 0 0 0
Unused 0 FCR[6] 0
9th-bit Int. En. DSR Wakeup disable FCR[1] 0
9 Bit Enable CTS Wakeup disable FCR[0] Good data status Invert internal rx clock
Hardwired Port Index ( 0x00, 0x01, 0x02, 0x03 according to which UART ) Res. Res. Invert Invert Unused Write `0' Write `0' DTR internal signal tx clock
Table 12: Indexed Control Register Set
Note 10: The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the Indexed Control Registers via ICR. Offset values not listed in the table are reserved for future use and must not be used.
To read or write to any of the Indexed Controlled Registers use the following procedure: Writing to ICR registers: Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value). Write the desired offset to SPR (address 111b). Write the desired value to ICR (address 101b). Reading from ICR registers: Ensure that the last value written to LCR was not 0xBF (see above). Write 0x00 offset to SPR to select ACR. Set bit 6 of ACR (ICR read enable) by writing x1xxxxxxb to address 101b. Ensure that other bits in ACR are not changed.
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(Software drivers should keep a copy of the contents of the ACR elsewhere since reading ICR involves overwriting ACR!) Write the desired offset to SPR (address 111b). Read the desired value from ICR (address 101b). Write 0x00 offset to SPR to select ACR. Clear bit 6 of ACR bye writing x0xxxxxxb to ICR, thus enabling access to standard registers again.
OXMPCI954
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8.3
8.3.1
Reset Configuration
Hardware Reset 8.3.2 Software Reset
After a hardware reset, all writable registers are reset to 0x00, with the following exceptions: DLL, which is reset to 0x01. CPR, which is reset to 0x20. The state of read-only registers following a hardware reset is as follows: Indeterminate 00000002 00000002 0x60 signifying that both the transmitter and the transmitter FIFO are empty MSR[3:0]: 00002 MSR[7:4]: Dependent on modem input lines DCD, RI, DSR and CTS respectively ISR[7:0]: 0x01, i.e. no interrupts are pending ASR[7:0]: 1xx000002 The reset state of output signals are tabulated below: Signal SOUT RTS# DTR# Reset state Inactive High Inactive High Inactive High RHR[7:0]: RFL[6:0]: TFL[6:0]: LSR[7:0]:
An additional feature available in the OX16C950 UART is software resetting of the serial channel. This command has the same effect on a single channel as a hardware reset except it does not reset the clock source selections (i.e. CKS register). To reset the UART write 0x00 to the Channel Software Reset register `CSR'.
Table 13: Output Signal Reset State
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8.4
Transmitter & Receiver FIFOs
Byte mode and a FIFO mode. This bit will return to zero after clearing the FIFOs. FCR[2]: Flush THR logic 0 No change. logic 1 Flushes the contents of the THR, in the same manner as FCR[1] does for the RHR.
Both the transmitter and receiver have associated holding registers (FIFOs), referred to as the transmitter holding register (THR) and receiver holding register (RHR) respectively. In normal operation, when the transmitter finishes transmitting a byte it will remove the next data from the top of the THR and proceed to transmit it. If the THR is empty, it will wait until data is written into it. If THR is empty and the last character being transmitted has been completed (i.e. the transmitter shift register is empty) the transmitter is said to be idle. Similarly, when the receiver finishes receiving a byte, it will transfer it to the bottom of the RHR. If the RHR is full, an overrun condition will occur (see section 8.5.3). Data is written into the bottom of the THR queue and read from the top of the RHR queue completely asynchronously to the operation of the transmitter and receiver. The size of the FIFOs is dependent on the setting of the FCR register. When in Byte mode, these FIFOs only accept one byte at a time before indicating that they are full; this is compatible with the 16C450. When in a FIFO mode, the size of the FIFOs is either 16 (compatible with the 16C550) or 128. Data written to the THR when it is full is lost. Data read from the RHR when it is empty is invalid. The empty or full status of the FIFOs is indicated in the Line Status Register `LSR' (see section 8.5.3). Interrupts are generated when the UART is ready for data transfer to/from the FIFOs. The number of items in each FIFO may also be read back from the transmitter FIFO level (TFL) and receiver FIFO level (RFL) registers (see section 8.11.2).
THR Trigger levels:
FCR[3]: Tx trigger level enable logic 0 Transmit trigger levels enabled logic 1 Transmit trigger levels disabled When FCR[3]=0, the transmitter trigger level is always set to 1, thus ignoring FCR[5:4]. Alternatively, 950-mode trigger levels can be set using ACR[5]. FCR[5:4]: Compatible trigger levels 450, 550 and extended 550 modes: The transmitter interrupt trigger levels are set to 1 and FCR[5:4] are ignored. 650 mode: In 650 mode the transmitter interrupt trigger levels can be set to the following values: FCR[5:4] 00 01 10 11 Transmit Interrupt Trigger level 16 32 64 112
Table 14: Transmit Interrupt Trigger Levels These levels only apply when in Enhanced mode and when FCR[3] is set, otherwise the trigger level is set to 1. A transmitter empty interrupt will be generated (if enabled) if the TFL falls below the trigger level. 750 Mode: In 750 compatible mode, transmitter trigger level is set to 1, FCR[4] is unused and FCR[5] defines the FIFO depth as follows: FCR[5]=0: FIFO size is 16 bytes. FCR[5]=1: FIFO size is 128 bytes. In non-Enhanced mode and when FIFOSEL pin is low, FCR[5] is writable only when LCR[7] is set. Note that in Enhanced mode, the FIFO size is increased to 128 bytes when FCR[0] is set. Page 67
8.4.1 FIFO Control Register `FCR' FIFO setup:
FCR[0]: Enable FIFO mode logic 0 Byte mode. logic 1 FIFO mode. This bit should be enabled before setting the FIFO trigger levels. FCR[1]: Flush RHR logic 0 No change. logic 1 Flushes the contents of the RHR This is only operative when already in a FIFO mode. The RHR is automatically flushed whenever changing between DS-0019 Jun 05
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950 mode: Setting ACR[5]=1 enables 950-mode trigger levels set using the TTL register (see section 8.11.4), FCR[5:4] are ignored.
OXMPCI954
950 mode: In similar fashion to for transmitter trigger levels, setting ACR[5]=1 enables 950-mode receiver trigger levels. FCR[7:6] are ignored. FCR [7:6] 00 01 10 11 L1 1 4 8 14 550 Mode Ext. 550 / 750
FIFO Size 128
RHR trigger levels
FCR[7:6]: Compatible Trigger levels 450, 550, extended 550, 650 and 750 modes: The receiver FIFO trigger levels are defined using FCR[7:6]. The interrupt trigger level and upper flow control trigger level where appropriate are defined by L1 in the table below. L2 defines the lower flow control trigger level. Separate upper and lower flow control trigger levels introduce a hysteresis element in in-band and out-of-band flow control (see section 8.9). In Byte mode (450-mode) the trigger levels are all set to 1.
FIFO Size 16
FIFO Size 128
650
L2 n/a n/a n/a n/a
L1 1 32 64 112
L2 1 1 1 1
L1 16 32 112 120
L2 1 16 32 112
Table 15: Compatible Receiver Trigger Levels A receiver data interrupt will be generated (if enabled) if the Receiver FIFO Level (`RFL') reaches the upper trigger level.
8.5
8.5.1
Line Control & Status
False Start Bit Detection
affected. Write the desired LCR value to exit from this selection. LCR[1:0]: Data length LCR[1:0] Determines the data length of serial characters. Note however, that these values are ignored in 9-bit data framing mode, i.e. when NMR[0] is set. LCR[1:0] 00 01 10 11 Data length 5 bits 6 bits 7 bits 8 bits
On the falling edge of a start bit, the receiver will wait for 1/2 bit and re-synchronise the receiver's sampling clock onto the centre of the start bit. The start bit is valid if the SIN line is still low at this mid-bit sample and the receiver will proceed to read in a data character. Verifying the start bit prevents noise generating spurious character generation. Once the first stop bit has been sampled, the received data is transferred to the RHR and the receiver will then wait for a low transition on SIN (signifying the next start bit). The receiver will continue receiving data even if the RHR is full or the receiver has been disabled (see section 8.11.3) in order to maintain framing synchronisation. The only difference is that the received data does not get transferred to the RHR.
Table 16: LCR Data Length Configuration LCR[2]: Number of stop bits LCR[2] defines the number of stop bits per serial character. LCR[2] 0 1 1 Data length 5,6,7,8 5 6,7,8 No. stop bits 1 1.5 2
8.5.2
Line Control Register `LCR'
The LCR specifies the data format that is common to both transmitter and receiver. Writing 0xBF to LCR enables access to the EFR, XON1, XOFF1, XON2 and XOFF2, DLL and DLM registers. This value (0xBF) corresponds to an unused data format. Writing the value 0xBF to LCR will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not
Table 17: LCR Stop Bit Number Configuration
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LCR[5:3]: Parity type The selected parity type will be generated during transmission and checked by the receiver, which may produce a parity error as a result. In 9-bit mode parity is disabled and LCR[5:3] is ignored. LCR[5:3] xx0 001 011 101 111 Parity type No parity bit Odd parity bit Even parity bit Parity bit forced to 1 Parity bit forced to 0
OXMPCI954
The Parity error flag will be set when the data item in error is at the top of the RHR and cleared following a read of the LSR. In 9-bit mode LSR[2] is no longer a flag and corresponds to the 9th bit of the received data in RHR. LSR[3]: Received data framing error logic 0 No framing error. logic 1 Data has been received with an invalid stop bit. This status bit is set and cleared in the same manner as LSR[2]. When a framing error occurs, the UART will try to re-synchronise by assuming that the error was due to sampling the start bit of the next data item. LSR[4]: Received break error logic 0 No receiver break error. logic 1 The receiver received a break. A break condition occurs when the SIN line goes low (normally signifying a start bit) and stays low throughout the start, data, parity and first stop bit. (Note that the SIN line is sampled at the bit rate). One zero character with associated break flag set will be transferred to the RHR and the receiver will then wait until the SIN line returns high. The LSR[4] break flag will be set when this data item gets to the top of the RHR and it is cleared following a read of the LSR. LSR[5]: THR empty logic 0 Transmitter FIFO (THR) is not empty. logic 1 Transmitter FIFO (THR) is empty. LSR[6]: Transmitter and THR empty logic 0 The transmitter is not idle logic 1 THR is empty and the transmitter has completed the character in shift register and is in idle mode. (I.e. set whenever the transmitter shift register and the THR are both empty.) LSR[7]: Receiver data error logic 0 Either there are no receiver data errors in the FIFO or it was cleared by a read of LSR. logic 1 At least one parity error, framing error or break indication in the FIFO. In 450 mode LSR[7] is permanently cleared, otherwise this bit will be set when an erroneous character is transferred from the receiver to the RHR. It is cleared when the LSR is read. Note that in 16C550 this bit is only cleared when all of the erroneous data are removed from the FIFO. In 9-bit data framing mode parity is permanently disabled, so this bit is not affected by LSR[2].
Table 18: LCR Parity Configuration LCR[6]: Transmission break logic 0 Break transmission disabled. logic 1 Forces the transmitter data output SOUT low to alert the communication terminal, or send zeros in IrDA mode. It is the responsibility of the software driver to ensure that the break duration is longer than the character period for it to be recognised remotely as a break rather than data. LCR[7]: Divisor latch enable logic 0 Access to DLL and DLM registers disabled. logic 1 Access to DLL and DLM registers enabled.
8.5.3
Line Status Register `LSR'
This register provides the status of data transfer to CPU. LSR[0]: RHR data available logic 0 RHR is empty: no data available logic 1 RHR is not empty: data is available to be read. LSR[1]: RHR overrun error logic 0 No overrun error. logic 1 Data was received when the RHR was full. An overrun error has occurred. The error is flagged when the data would normally have been transferred to the RHR. LSR[2]: Received data parity error logic 0 No parity error in normal mode or 9th bit of received data is `0' in 9-bit mode. logic 1 Data has been received that did not have correct parity in normal mode or 9th bit of received data is `1' in 9-bit mode.
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8.6
Interrupts & Sleep Mode
In 9-bit data mode, The receiver can detect up to four special characters programmed in the Special Character Registers (see map on page 63). When IER[5] is set, a level 5 interrupt is asserted when the receiver character matches one of the values programmed. 650/950 modes (non-9-bit data framing): logic 0 Disable the special character receive interrupt. logic 1 Enable the special character receive interrupt. In 16C650 compatible mode when the device is in Enhanced mode (EFR[4]=1), this bit enables the detection of special characters. It enables both the detection of XOFF characters (when in-band flow control is enabled via EFR[3:0]) and the detection of the XOFF2 special character (when enabled via EFR[5]). 750 mode (non-9-bit data framing): logic 0 Disable alternate sleep mode. logic 1 Enable alternate sleep mode whereby the internal clock of the channel is switched off. In 16C750 compatible mode (i.e. non-Enhanced mode), this bit is used an alternate sleep mode and has the same effect as IER[4]. IER[6]: RTS interrupt mask logic 0 Disable the RTS interrupt. logic 1 Enable the RTS interrupt. This enable is only operative in Enhanced mode (EFR[4]=1). In non-Enhanced mode, RTS interrupt is permanently enabled IER[7]: CTS interrupt mask logic 0 Disable the CTS interrupt. logic 1 Enable the CTS interrupt. This enable is only operative in Enhanced mode (EFR[4]=1). In non-Enhanced mode, CTS interrupt is permanently enabled.
The serial channel interrupts are asserted on the PCI INTA# pin. The interrupts can be enabled or disabled using the GIS register interrupt mask (see section 7.4.8) and the IER register. Unlike generic 16C550 devices, the interrupt can not be disabled using the implementation-specific MCR[3].
8.6.1
Interrupt Enable Register `IER'
Serial channel interrupts are enabled using the Interrupt Enable Register (`IER'). IER[0]: Receiver data available interrupt mask logic 0 Disable the receiver ready interrupt. logic 1 Enable the receiver ready interrupt. IER[1]: Transmitter empty interrupt mask logic 0 Disable the transmitter empty interrupt. logic 1 Enable the transmitter empty interrupt. IER[2]: Receiver status interrupt Normal mode: logic 0 Disable the receiver status interrupt. logic 1 Enable the receiver status interrupt. 9-bit data mode: logic 0 Disable receiver status and address bit interrupt. logic 1 Enable receiver status and address bit interrupt. In 9-bit mode (i.e. when NMR[0] is set), reception of a character with the address-bit (i.e. 9th bit) set can generate a level 1 interrupt if IER[2] is set. IER[3]: Modem status interrupt mask logic 0 Disable the modem status interrupt. logic 1 Enable the modem status interrupt. IER[4]: Sleep mode logic 0 Disable sleep mode. logic 1 Enable sleep mode whereby the internal clock of the channel is switched off. Sleep mode is described in section 8.6.4. IER[5]: Special character interrupt mask or alternate sleep mode 9-bit data framing mode: logic 0 Disable the received special character interrupt. logic 1 Enable the received special character interrupt.
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Level 2a: 8.6.2 Interrupt Status Register `ISR'
The source of the highest priority interrupt pending is indicated by the contents of the Interrupt Status Register `ISR'. There are nine sources of interrupt at six levels of priority (1 is the highest) as shown in Table 19. Level 1 2a 2b 3 4 52 Interrupt source No interrupt pending 1 Receiver status error or Address-bit detected in 9-bit mode Receiver data available Receiver time-out Transmitter THR empty Modem status change In-band flow control XOFF or Special character (XOFF2) or Special character 1, 2, 3 or 4 or bit 9 set in 9-bit mode CTS or RTS change of state ISR[5:0]
see note 3
Receiver data available interrupt (ISR[5:0]='000100'): This interrupt is active whenever the receiver FIFO level is above the interrupt trigger level.
Level 2b:
Receiver time-out interrupt (ISR[5:0]='001100'): A receiver time-out event, which may cause an interrupt, will occur when all of the following conditions are true: * The UART is in a FIFO mode * There is data in the RHR. * There has been no read of the RHR for a period of time greater than the time-out period. * There has been no new data written into the RHR for a period of time greater than the time-out period. The time-out period is four times the character period (including start and stop bits) measured from the centre of the first stop bit of the last data item received. Reading the first data item in RHR clears this interrupt.
000001 000110 000100 001100 000010 000000 010000
62
100000
Level 3:
Transmitter empty interrupt (ISR[5:0]='000010'): This interrupt is set when the transmit FIFO level falls below the trigger level. It is cleared on an ISR read of a level 3 interrupt or by writing more data to the THR so that the trigger level is exceeded. Note that when 16C950 mode trigger levels are enabled (ACR[5]=1) and the transmitter trigger level of zero is selected (TTL=0x00), a transmitter empty interrupt will only be asserted when both the transmitter FIFO and transmitter shift register are empty and the SOUT line has returned to idle marking state.
Table 19: Interrupt Status Identification Codes
Note1: Note2: Note3: ISR[0] indicates whether any interrupts are pending. Interrupts of priority levels 5 and 6 cannot occur unless the UART is in Enhanced mode. ISR[5] is only used in 650 & 950 modes. In 750 mode, it is `0' when FIFO size is 16 and `1' when FIFO size is 128. In all other modes it is permanently set to 0
ISR[6] and ISR[7] indicated whether the FIFO's are enabled. When you enable FIFOs both bits are set when either 16 or 128, note they also mirror fcr[0].
Level 4:
Modem change interrupt (ISR[5:0]='000000'): This interrupt is set by a modem change flag (MSR[0], MSR[1], MSR[2] or MSR[3]) becoming active due to changes in the input modem lines. This interrupt is cleared following a read of the MSR.
8.6.3 Level 1:
Interrupt Description
Receiver status error interrupt (ISR[5:0]='000110'): Normal (non-9-bit) mode: This interrupt is active whenever any of LSR[1], LSR[2], LSR[3] or LSR[4] are set. These flags are cleared following a read of the LSR. This interrupt is masked with IER[2]. 9-bit mode: This interrupt is active whenever any of LSR[1], LSR[2], LSR[3] or LSR[4] are set. The receiver error interrupt due to LSR[1], LSR[3] and LSR[4] is masked with IER[3]. The `address-bit' received interrupt is masked with NMR[1]. The software driver can differentiate between receiver status error and received address-bit (9th data bit) interrupt by examining LSR[1] and LSR[7]. In 9-bit mode LSR[7] is only set when LSR[3] or LSR[4] is set and it is not affected by LSR[2] (i.e. 9th data bit).
Level 5:
Receiver in-band flow control (XOFF) detect interrupt, Receiver special character (XOFF2) detect interrupt, Receiver special character 1, 2, 3 or 4 interrupt or 9th Bit set interrupt in 9-bit mode (ISR[5:0]='010000'): A level 5 interrupt can only occur in Enhanced-mode when any of the following conditions are met: * A valid XOFF character is received while in-band flow control is enabled. * A received character matches XOFF2 while special character detection is enabled, i.e. EFR[5]=1. * A received character matches special character 1, 2, 3 or 4 in 9-bit mode (see section 8.11.9). It is cleared on an ISR read of a level 5 interrupt.
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Level 6:
CTS or RTS changed interrupt (ISR[5:0]='100000'): This interrupt is set whenever any of the CTS# or RTS# pins changes state from low to high. It is cleared on an ISR read of a level 6 interrupt.
* * *
The UART is not in loopback mode (MCR[4]=0). Changes on modem input lines have been acknowledged (i.e. MSR[3:0]=0000). No interrupts are pending.
8.6.4
Sleep Mode
For a channel to go into sleep mode, all of the following conditions must be met: * * * * * Sleep mode enabled (IER[4]=1 in 650/950 modes, or IER[5]=1 in 750 mode): The transmitter is idle, i.e. the transmitter shift register and FIFO are both empty. SIN is high. The receiver is idle. The receiver FIFO is empty (LSR[0]=0).
A read of IER[4] (or IER[5] if a 1 was written to that bit instead) shows whether the power-down request was successful. The UART will retain its programmed state whilst in power-down mode. The channel will automatically exit power-down mode when any of the conditions 1 to 7 becomes false. It may be woken manually by clearing IER[4] (or IER[5] if the alternate sleep mode is enabled). Sleep mode operation is not available in IrDA mode.
8.7
8.7.1
Modem Interface
Modem Control Register `MCR'
OUT2#) are set in-active (high), and the receiver inputs SIN, CTS#, DSR#, DCD#, and RI# are all disabled. Internally the transmitter output is connected to the receiver input and DTR#, RTS#, OUT1# and OUT2# are connected to modem status inputs DSR#, CTS#, RI# and DCD# respectively. In this mode, the receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the interrupt sources are now the lower four bits of the Modem Control Register instead of the four modem status inputs. The interrupts are still controlled by the IER. MCR[5]: Enable XON-Any in Enhanced mode or enable out-of-band flow control in non-Enhanced mode 650/950 (enhanced) modes: logic 0 XON-Any is disabled. logic 1 XON-Any is enabled. In enhanced mode (EFR[4]=1), this bit enables the XonAny operation. When Xon-Any is enabled, any received data will be accepted as a valid XON (see in-band flow control, section 8.9.3).
MCR[0]: DTR logic 0 Force DTR# output to inactive (high). logic 1 Force DTR# output to active (low). Note that DTR# can be used for automatic out-of-band flow control when enabled using ACR[4:3] (see section 8.11.3). MCR[1]: RTS logic 0 Force RTS# output to inactive (high). logic 1 Force RTS# output to active (low). Note that RTS# can be used for automatic out-of-band flow control when enabled using EFR[6] (see section 8.9.4). MCR[2]: OUT1 Note OUT1# is not bonded out on the OXMPCI954. logic 0 Force OUT1# output low when loopback mode is disabled. logic 1 Force OUT1# output high. MCR[3]: OUT2/Internal interrupt enable Note OUT2# is not bonded out on the OXMPCI954. logic 0 Force OUT2# output low when loopback mode is disabled. logic 1 Force OUT2# output high. MCR[4]: Loopback mode logic 0 Normal operating mode. logic 1 Enable local loop-back mode (diagnostics). In local loop-back mode, the transmitter output (SOUT) and the four modem outputs (DTR#, RTS#, OUT1# and DS-0019 Jun 05
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750 (normal) mode: logic 0 CTS/RTS flow control disabled. logic 1 CTS/RTS flow control enabled. In non-enhanced mode, this bit enables the CTS/RTS outof-band flow control. MCR[6]: IrDA mode logic 0 Standard serial receiver and transmitter data format. logic 1 Data will be transmitted and received in IrDA format. This function is only available in Enhanced mode. It requires a 16x clock to function correctly. MCR[7]: Baud rate prescaler select logic 0 Normal (divide by 1) baud rate generator prescaler selected. logic 1 Divide-by-"M+N/8" baud rate generator prescaler selected. where M & N are programmed in CPR (ICR offset 0x01). After a hardware reset, CPR defaults to 0x20 (divide-by-4) and MCR[7] is reset. User writes to this flag will only take effect in Enhanced mode. See section 8.9.1.
OXMPCI954
8.7.2
Modem Status Register `MSR'
MSR[0]: Delta CTS# Indicates that the CTS# input has changed since the last time the MSR was read. MSR[1]: Delta DSR# Indicates that the DSR# input has changed since the last time the MSR was read. MSR[2]: Trailing edge RI# Indicates that the RI# input has changed from low to high since the last time the MSR was read. MSR[3]: Delta DCD# Indicates that the DCD# input has changed since the last time the MSR was read. MSR[4]: CTS This bit is the complement of the CTS# input. It is equivalent to RTS (MCR[1]) in internal loop-back mode. MSR[5]: DSR This bit is the complement of the DSR# input. It is equivalent to DTR (MCR[0]) in internal loop-back mode. MSR[6]: RI This bit is the complement of the RI# input. In internal loopback mode it is equivalent to the internal OUT1. MSR[7]: DCD This bit is the complement of the DCD# input. In internal loop-back mode it is equivalent to the internal OUT2.
8.8
8.8.1
Other Standard Registers
Divisor Latch Registers `DLL & DLM'
Where divisor is given by DLL + (256 x DLM). More flexible baud rate generation options are also available. See section 8.10 for full details.
The divisor latch registers are used to program the baud rate divisor. This is a value between 1 and 65535 by which the input clock is divided by in order to generate serial baud rates. After a hardware reset, the baud rate used by the transmitter and receiver is given by:
8.8.2
Scratch Pad Register `SPR'
Baudrate =
InputClock 16 * Divisor
The scratch pad register does not affect operation of the rest of the UART in any way and can be used for temporary data storage. The register may also be used to define an offset value to access the registers in the Indexed Control Register set. For more information on Indexed Control registers see sections 8.2 and 8.11.
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8.9
Automatic Flow Control
EFR[3:2]: In-band transmit flow control mode When in-band transmit flow control is enabled, XON/XOFF character(s) are inserted into the data stream whenever the RFL passes the upper trigger level and falls below the lower trigger level respectively. For automatic in-band flow control, bit 4 of EFR must be set. The combinations of software transmit flow control can then be selected by programming EFR[3:2] as follows: logic [00] In-band transmit flow control is disabled. logic [01] Single character in-band transmit flow control enabled, using XON2 as the XON character and XOFF2 as the XOFF character. logic [10] Single character in-band transmit flow control enabled, using XON1 as the XON character and XOFF1 as the XOFF character. logic[11] The value EFR[3:2] = "11" is reserved for future use and should not be used EFR[4]: Enhanced mode logic 0 Non-Enhanced mode. Disables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7 and inband flow control. Whenever this bit is cleared, the settings of other bits of EFR are ignored. logic 1 Enhanced mode. Enables the Enhanced Mode functions. These functions include enabling IER bits 4-7, FCR bits 4-5, MCR bits 5-7. For in-band flow control the software driver must set this bit first. If this bit is set, out-of-band flow control is configured with EFR bits 6-7; otherwise out-of-band flow control is compatible with 16C750. EFR[5]: Enable special character detection logic 0 Special character detection is disabled. logic 1 While in Enhanced mode (EFR[4]=1), the UART compares the incoming receiver data with the XOFF2 value. Upon a correct match, the received data will be transferred to the RHR and a level 5 interrupt (XOFF or special character) will be asserted if level 5 interrupts are enabled (IER[5] set to 1). EFR[6]: Enable automatic RTS flow control. logic 0 RTS flow control is disabled (default). logic 1 RTS flow control is enabled in Enhanced mode (i.e. EFR[4] = 1), where the RTS# pin will be forced inactive high if the RFL reaches the upper flow control threshold. This will be released when the RFL drops below the lower threshold. 650 and 950-mode drivers should use this bit to enable RTS flow control. Page 74
Automatic in-band flow control, automatic out-of-band flow control and special character detection features can be used when in Enhanced mode (flow control is software compatible with the 16C654). Alternatively, 750-compatible automatic out-of-band flow control can be enabled when in non-Enhanced mode. In 950 mode, in-band and out-ofband flow controls are compatible with 16C654 with the addition of fully programmable flow control thresholds.
8.9.1
Enhanced Features Register `EFR'
Writing 0xBF to LCR enables access to the EFR and other Enhanced mode registers. This value corresponds to an unused data format. Writing 0xBF to LCR will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection. Note: In-band transmit and receive flow control is disabled in 9-bit mode. EFR[1:0]: In-band receive flow control mode When in-band receive flow control is enabled, the UART compares the received data with the programmed XOFF character(s). When this occurs, the UART will disable transmission as soon as any current character transmission is complete. The UART then compares the received data with the programmed XON character(s). When a match occurs, the UART will re-enable transmission (see section 8.11.6). For automatic in-band flow control, bit 4 of EFR must be set. The combinations of software receive flow control can be selected by programming EFR[1:0] as follows: logic [00] In-band receive flow control is disabled. logic [01] Single character in-band receive flow control enabled, recognising XON2 as the XON character and XOFF2 as the XOFF character. logic [10] Single character in-band receive flow control enabled, recognising XON1 as the XON character and XOFF1 and the XOFF character. logic [11] The behaviour of the receive flow control is dependent on the configuration of EFR[3:2]. Single character in-band receive flow control is enabled, accepting XON1 or XON2 as valid XON characters and XOFF1 or XOFF2 as valid XOFF characters when EFR[3:2] = "01" or "10". EFR[1:0] should not be set to "11" when EFR[3:2] is `00'.
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EFR[7]: Enable automatic CTS flow control. logic 0 CTS flow control is disabled (default). logic 1 CTS flow control is enabled in Enhanced mode (i.e. EFR[4] = 1), where the data transmission is prevented whenever the CTS# pin is held inactive high. 650 and 950-mode drivers should use this bit to enable CTS flow control. A 750-mode driver should set MCR[5] to enable RTS/CTS flow control.
OXMPCI954
transmitter will be re-enabled. The received data will be transferred to the RHR. When in-band transmit flow control is enabled, the RFL will be sampled whenever the transmitter is idle (briefly, between characters, or when the THR is empty) and an XON/XOFF character will be inserted into the data stream if needed. Initially, remote transmissions are enabled and hence ASR[1] is clear. If ASR[1] is clear and the RFL has passed the upper trigger level (i.e. is above the trigger level), XOFF will be sent and ASR[1] will be set. If ASR[1] is set and the RFL falls below the lower trigger level, XON will be sent and ASR[1] will be cleared. If transmit flow control is disabled after an XOFF has been sent, an XON will be sent automatically.
8.9.2
Special Character Detection
In Enhanced mode (EFR[4]=1), when special character detection is enabled (EFR[5]=1) and the receiver matches received data with XOFF2, the 'received special character' flag ASR[4] will be set and a level 5 interrupt is asserted, if enabled by IER[5]. This flag will be cleared following a read of ASR. The received status (i.e. parity and framing) of special characters does not have to be valid for these characters to be accepted as valid matches.
8.9.4
Automatic Out-of-band Flow Control
8.9.3
Automatic In-band Flow Control
When in-band receive flow control is enabled, the UART will compare the received data with XOFF1 or XOFF2 characters to detect an XOFF condition. When this occurs, the UART will disable transmission as soon as any current character transmission is complete. Status bits ISR[4] and ASR[0] will be set. A level 5 interrupt will occur (if enabled by IER[5]). The UART will then compare all received data with XON1 or XON2 characters to detect an XON condition. When this occurs, the UART will re-enable transmission and status bits ISR[4] and ASR[0] will be cleared. Any valid XON/XOFF characters will not be written into the RHR. An exception to this rule occurs if special character detection is enabled and an XOFF2 character is received that is a valid XOFF. In this instance, the character will be written into the RHR. The received status (i.e. parity and framing) of XON/XOFF characters does not have to be valid for these characters to be accepted as valid matches. When the 'XON Any' flag (MCR[5]) is set, any received character is accepted as a valid XON condition and the
Automatic RTS/CTS flow control is selected by different means, depending on whether the UART is in Enhanced or non-Enhanced mode. When in non-Enhanced mode, MCR[5] enables both RTS and CTS flow control. When in Enhanced mode, EFR[6] enables automatic RTS flow control and EFR[7] enables automatic CTS flow control. This allows software compatibility with both 16C650 and 16C750 drivers. When automatic CTS flow control is enabled and the CTS# input becomes active, the UART will disable transmission as soon as any current character transmission is complete. Transmission is resumed whenever the CTS# input becomes inactive. When automatic RTS flow control is enabled, the RTS# pin will be forced inactive when the RFL reaches the upper trigger level and will return to active when the RFL falls below the lower trigger level. The automatic RTS# flow control is ANDed with MCR[1] and hence is only operational when MCR[1]=1. This allows the software driver to override the automatic flow control and disable the remote transmitter regardless by setting MCR[1]=0 at any time. Automatic DTR/DSR flow control behaves in the same manner as RTS/CTS flow control but is enabled by ACR[3:2], regardless of whether or not the UART is in Enhanced mode.
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8.10 Baud Rate Generation
8.10.1 General Operation
The UART contains a programmable baud rate generator that is capable of taking any clock input from 1.8432MHz to 60MHz and dividing it by any 16-bit divisor number from 1 to 65535 written into the DLM (MSB) and DLL (LSB) registers. In addition to this, a clock prescaler register is provided which can further divide the clock by values in the range 1.0 to 31.875 in steps of 0.125. Also, a further feature is the Times Clock Register `TCR' which allows the sampling clock to be set to any value between 4 and 16. These clock options allow for highly flexible baud rate generation capabilities from almost any input clock frequency (up to 60MHz). The actual transmitter and receiver baud rate is calculated as follows:
8.10.2 Clock Prescaler Register `CPR'
The CPR register is located at offset 0x01 of the ICR The prescaler divides the system clock by any value in the range of 1 to "31 7/8" in steps of 1/8. The divisor takes the form "M+N/8", where M is the 5 bit value defined in CPR[7:3] and N is the 3 bit value defined in CPR[2:0]. The prescaler is by-passed and a prescaler value of `1' is selected by default when MCR[7] = 0. Note that since access to MCR[7] is restricted to Enhanced mode only, EFR[4] should first be set and then MCR[7] set or cleared as required. For higher baud rates use a higher frequency clock, e.g. 14.7456MHz, 18.432MHz, 32MHz, 40MHz or 60.0MHz. The flexible prescaler allows system designers to use clocks that are not integer multiples of popular baud rates; when using a non-standard clock frequency, compatibility with existing 16C550 software drivers may be maintained with a minor software patch to program the on-board prescaler to divide the high frequency clock down to 1.8432MHz. Table 22 on the following page gives the prescaler values required to operate the UARTs at compatible baud rates with various different crystal frequencies. Also given is the maximum available baud rates in TCR = 16 and TCR = 4 modes with CPR = 1.
InputClock BaudRate = SC * Divisor * prescaler
Where: SC = Sample clock values defined in TCR[3:0] Divisor = DLL + ( 256 x DLM ) Prescaler = 1 when MCR[7] = `0' else: = M + ( N / 8 ) where: M = CPR[7:3] (Integer part - 1 to 31) N = CPR[2:0] (Fractional part - 0.000 to 0.875 ) After a hardware reset, the precaler is bypassed (set to 1) and TCR is set to 0x00 (i.e. SC = 16). Assuming this default configuration, the following table gives the divisors required to be programmed into the DLL and DLM registers in order to obtain various standard baud rates: DLM:DLL Divisor Word 0x0900 0x0300 0x0180 0x00C0 0x0060 0x0030 0x0018 0x000C 0x0006 0x0004 0x0003 0x0002 0x0001 Baud Rate (bits per second) 50 110 300 600 1,200 2,400 4,800 9,600 19,200 28,800 38,400 57,600 115,200
8.10.3 Times Clock Register `TCR'
The TCR register is located at offset 0x02 of the ICR The 16C550 and other compatible devices such as 16C650 and 16C750 use a 16 times (16x) over-sampling channel clock. The 16x over-sampling clock means that the channel clock runs at 16 times the selected serial bit rate. It limits the highest baud rate to 1/16 of the system clock when using a divisor latch value of unity. However, the 16C950 UART is designed in a manner to enable it to accept other multiplications of the bit rate clock. It can use values from 4x to 16x clock as programmed in the TCR as long as the clock (oscillator) frequency error, stability and jitter are within reasonable parameters. Upon hardware reset the TCR is reset to 0x00 which means that a 16x clock will be used, for compatibility with the 16C550 and compatibles. The maximum baud-rates available for various system clock frequencies at all of the allowable values of TCR are indicated in Table 23 on the following page. These are the
Table 20: Standard PC COM Port Baud Rate Divisors (assuming a 1.8432MHz crystal) DS-0019 Jun 05
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values in bits-per-second (bps) that are obtained if the divisor latch = 0x01 and the Prescaler is set to 1. The OXMPCI954 has the facility to operate at baud-rates up to 15 Mbps in normal mode. Table 26 indicates how the value in the register corresponds to the number of clock cycles per bit. TCR[3:0] is used to program the clock. TCR[7:4] are unused and will return "0000" if read. TCR[3:0] 0000 to 0011 0100 to 1111 Clock cycles per bit 16 4-15
OXMPCI954
Use of the TCR does not require the device to be in 650 or 950 mode although only drivers that have been written to take advantage of the 950 mode features will be able to access this register. Writing 0x01 to the TCR will not switch the device into 1x isochronous mode this is explained in the following section. (TCR has no effect in isochronous mode). If 0x01, 0x10 or 0x11 is written to TCR the device will operate in 16x mode. Reading TCR will always return the last value that was written to it irrespective of mode of operation.
Table 21: TCR Sample Clock Configuration Clock Frequency (MHz) 1.8432 7.3728 14.7456 18.432 32.000 33.000 40.000 50.000 60.000 CPR value 0x08 (1) 0x20 (4) 0x40 (8) 0x50 (10) 0x8B (17.375) 0x8F (17.875) 0xAE (21.75) 0xD9 (27.125) 0xFF (31.875) Effective crystal frequency 1.8432 1.8432 1.8432 1.8432 1.8417 1.8462 1.8391 1.8433 1.8824 Error from 1.8432MHz (%) 0.00 0.00 0.00 0.00 0.08 0.16 0.22 0.01 2.13 Max. Baud rate with CPR = 1, TCR = 16 115,200 460,800 921,600 1,152,000 2,000,000 2,062,500 2,500,000 3,125,000 3,750,000 Max. Baud rate with CPR = 1, TCR = 4 460,800 1,843,200 3,686,400 4,608,000 8,000,000 8,250,000 10,000,000 12,500,000 15,000,000
Table 22: Example clock options and their associated maximum baud rates
Sampling TCR Clock Value System Clock (MHz) 1.8432 7.372 14.7456 18.432 32 40 50 60
16 15 14 13 12 11 10 9 8 7 6 5 4
0x00 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04
115,200 122,880 131,657 141,785 153,600 167,564 184,320 204,800 230,400 263,314 307,200 368,640 460,800
460,750 491,467 526,571 567,077 614,333 670,182 737,200 819,111 921,500 1,053,143 1,228,667 1,474,400 1,843,000
921,600 983,040 1,053,257 1,134,277 1,228,800 1,340,509 1,474,560 1,638,400 1,843,200 2,106,514 2,457,600 2,949,120 3,686,400
1.152M 1,228,800 1,316,571 1,417,846 1,536,000 1,675,636 1,843,200 2,048,000 2,304,000 2,633,143 3,072,000 3,686,400 4,608,000
2.00M 2,133,333 2,285,714 2,461,538 2,666,667 2,909,091 3.20M 3,555,556 4.00M 4,571,429 5,333,333 6.40M 8.00M
2.50M 2,666,667 2,857,143 3,076,923 3,333,333 3,636,364 4.00M 4,444,444 5.00M 5,714,286 6,666,667 8.00M 10.00M
3.125M 3,333,333 3,571,429 3,846,154 4,166,667 4,545,455 5.00M 5,555,556 6.25M 7,142,857 8,333,333 10.00M 12.50M
3.75M 4.00M 4,285,714 4,615,384 5.00M 5,454545 6.00M 6,666,667 7.50M 8,571428 10.00M 12.00M 15.00M
Table 23: Maximum Baud Rates Available at all `TCR' Sampling Clock Values
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8.10.4 External 1x Clock Mode
The transmitter and receiver can accept an external clock applied to the RI# and DSR# pins respectively. The clock options are selected using the CKS register (see section 8.11.8). The transmitter and receiver may be configured to operate in 1x (i.e. Isochronous mode) by setting CKS[7] and CKS[3], respectively. In Isochronous mode, transmitter or receiver will use the 1x clock (usually, but not necessarily, an external source) where asynchronous framing is maintained using start-, parity- and stop-bits. However serial transmission and reception is synchronised to the 1x clock. In this mode asynchronous data may be transmitted at baud rates up to 60Mbps. The local 1x clock source can be asserted on the DTR# pin. Note that line drivers need to be capable of transmission at data rates twice the system clock used (as one cycle of the system clock corresponds to 1 bit of serial data). Also note that enabling modem interrupts is illegal in isochronous mode, as the clock signal will cause a continuous change to the modem status (unless masked in MDM register, see section 8.11.10).
to the XTLI pin. The circuit required to use the internal oscillator is shown in Figure 1.
XTLO R2 R1 C1
XTLI C2
Figure 1: Crystal Oscillator Circuit Frequency Range (MHz) 1.8432 - 20 C1 (pF) 68 C2 (pF) 22
R1 () 220k
R2 () 470R
Table 24: Component values Note: For better stability use a smaller value of R1. Increase R1 to reduce power consumption. The total capacitive load (C1 in series with C2) should be that specified by the crystal manufacturer (nominally 16pF). Note that for frequency operation above 20MHz, an external clock source is required.
8.10.5 Crystal Oscillator Circuit
The UARTs reference clock may be provided by its own crystal oscillator or directly from a clock source connected
8.11 Additional Features
8.11.1 Additional Status Register `ASR'
ASR[0]: Transmitter disabled logic 0 The transmitter is not disabled by in-band flow control. logic 1 The receiver has detected an XOFF, and has disabled the transmitter. This bit is cleared after a hardware reset or channel software reset. The software driver may write a 0 to this bit to re-enable the transmitter if it was disabled by in-band flow control. Writing a 1 to this bit has no effect. ASR[1]: Remote transmitter disabled logic 0 The remote transmitter is not disabled by inband flow control. logic 1 The transmitter has sent an XOFF character, to disable the remote transmitter (cleared when subsequent XON is sent). This bit is cleared after a hardware reset or channel software reset. The software driver may write a 0 to this bit DS-0019 Jun 05 to re-enable the remote transmitter (an XON is transmitted). Note: writing a 1 to this bit has no effect. ASR[2]: RTS This is the complement of the actual state of the RTS# pin when the device is not in loopback mode. The driver software can determine if the remote transmitter is disabled by RTS# out-of-band flow control by reading this bit. In loopback mode this bit reflects the flow control status rather than the pin's actual state. ASR[3]: DTR This is the complement of the actual state of the DTR# pin when the device is not in loopback mode. The driver software can determine if the remote transmitter is disabled by DTR# out-of-band flow control by reading this bit. In loopback mode this bit reflects the flow control status rather than the pin's actual state. ASR[4]: Special character detected logic 0 No special character has been detected. logic 1 A special character has been received and is stored in the RHR. Page 78
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This can be used to determine whether a level 5 interrupt was caused by receiving a special character rather than an XOFF. The flag is cleared following the read of the ASR. ASR[5]: FIFOSEL This bit reflects the unlatched state of the FIFOSEL pin. ASR[6]: FIFO size logic 0 FIFOs are 16 deep if FCR[0] = 1. logic 1 FIFOs are 128 deep if FCR[0] = 1. ASR[7]: Transmitter Idle logic 0 Transmitter is transmitting. logic 1 Transmitter is idle. This bit reflects the state of the internal transmitter. It is set when both the transmitter FIFO and shift register are empty.
ACR[2]: Enable automatic DSR flow control logic 0 Normal. The state of the DSR# line does not affect the flow control. logic 1 Data transmission is prevented whenever the DSR# pin is held inactive high. This bit provides another automatic out-of-band flow control facility using the DSR# line. ACR[4:3]: DTR# line configuration When bits 4 or 5 of CKS (offset 0x03 of ICR) are set, the transmitter 1x clock or the output of the baud rate generator (Nx clock) are asserted on the DTR# pin, otherwise the DTR# pin is defined as follows: logic [00] DTR# is compatible with 16C450, 16C550, 16C650 and 16C750 (i.e. normal). logic [01] DTR# pin is used for out-of-band flow control. It will be forced inactive high if the Receiver FIFO Level (`RFL') reaches the upper flow control threshold. DTR# line will be reactivated (=0) when the RFL drops below the lower threshold (see FCL & FCH). logic [10] DTR# pin is configured to drive the active-low enable pin of an external RS485 buffer. In this configuration the DTR# pin will be forced low whenever the transmitter is not empty (LSR[6]=0), otherwise DTR# pin is high. logic [11] DTR# pin is configured to drive the activehigh enable pin of an external RS485 buffer. In this configuration, the DTR# pin will be forced high whenever the transmitter is not empty (LSR[6]=0), otherwise DTR# pin is low. If the user sets ACR[4], then the DTR# line is controlled by the status of the transmitter empty bit of LCR. When ACR[4] is set, ACR[3] is used to select active high or active low enable signals. In half-duplex systems using RS485 protocol, this facility enables the DTR# line to directly control the enable signal of external 3-state line driver buffers. When the transmitter is empty the DTR# would go inactive once the SOUT line returns to its idle marking state. ACR[5]: 950 mode trigger levels enable logic 0 Interrupts and flow control trigger levels are as described in FCR register and are compatible with 16C650/16C750 modes. logic 1 16C950 specific enhanced interrupt and flow control trigger levels defined by RTL, TTL, FCL and FCH are enabled.
8.11.2 FIFO Fill levels `TFL & RFL'
The number of characters stored in the THR and RHR can be determined by reading the TFL and RFL registers respectively. When data transfer is in constant operation, the values should be interpreted as follows: 1. The number of characters in the THR is no greater than the value read back from TFL. 2. The number of characters in the RHR is no less than the value read back from RFL.
8.11.3 Additional Control Register `ACR'
The ACR register is located at offset 0x00 of the ICR ACR[0]: Receiver disable logic 0 The receiver is enabled, receiving data and storing it in the RHR. logic 1 The receiver is disabled. The receiver continues to operate as normal to maintain the framing synchronisation with the receive data stream but received data is not stored into the RHR. In-band flow control characters continue to be detected and acted upon. Special characters will not be detected. Changes to this bit will only be recognised following the completion of any data reception pending. ACR[1]: Transmitter disable logic 0 The transmitter is enabled, transmitting any data in the THR. logic 1 The transmitter is disabled. Any data in the THR is not transmitted but is held. However, inband flow control characters may still be transmitted. Changes to this bit will only be recognised following the completion of any data transmission pending. DS-0019 Jun 05
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ACR[6]: ICR read enable logic 0 The Line Status Register is readable. logic 1 The Indexed Control Registers are readable. Setting this bit will map the ICR set to the LSR location for reads. During normal operation this bit should be cleared. ACR[7]: Additional status enable logic 0 Access to the ASR, TFL and RFL registers is disabled. logic 1 Access to the ASR, TFL and RFL registers is enabled. When ACR[7] is set, the MCR, LCR and IER registers are no longer readable but remain writable, and the registers ASR, TFL and RFL replace them in the register map for read operations. The software driver may leave this bit set during normal operation, since MCR, LCR and IER do not generally need to be read.
OXMPCI954
8.11.6 Flow Control Levels `FCL' & `FCH'
The FCL and FCH registers are located at offsets 0x06 and 0x07 of the ICR respectively Enhanced software flow control using XON/XOFF and hardware flow control using RTS#/CTS# and DTR#/DSR# are available when 950 mode trigger levels are enabled (ACR[5]=1). Improved flow control threshold levels are offered using Flow Control Lower trigger level (`FCL') and Flow Control Higher trigger level (`FCH') registers to provide a greater degree of flexibility when optimising the flow control performance. Generally, these facilities are only available in Enhanced mode. In 650 mode, in-band flow control is enabled using the EFR register. An XOFF character may be transmitted when the receiver FIFO exceeds the upper trigger level defined by FCR[7:6] as described in section 8.4.1. An XON is then sent when the FIFO is read down the lower fill level. The flow control is enabled and the appropriate mode is selected using EFR[3:0]. In 950 mode, the flow control thresholds defined by FCR[7:6] are ignored. In this mode, threshold levels are programmed using FCL and FCH. When flow control is enabled by EFR[3:0] and the receiver FIFO level (`RFL') reaches the value programmed in the FCH register, an XOFF will be transmitted to stop the flow of serial data as defined by EFR[3:0]. When the receiver FIFO level falls below the value programmed in FCL the flow is resumed by sending an XON character (as defined in EFR[3:0]). The FCL value of 0x00 is illegal. CTS/RTS and DSR/DTR out-of-band flow control use the same trigger levels as in-band flow control. When out-ofband flow control is enabled, RTS# (or DTR#) line is deasserted when the receiver FIFO level reaches the upper limit defined in the FCH and is re-asserted when the receiver FIFO is drained below a lower limit defined in FCL. When 950 trigger levels are enabled (ACR[5]=1), the CTS# flow control functions as in 650 mode and is configured by EFR[7]. However, RTS# is automatically de-asserted and re-asserted when EFR[6] is set and RFL reaches FCH and drops below FCL. DSR# flow control is configured with ACR[2]. DTR# flow control is configured with ACR[4:3].
8.11.4 Transmitter Trigger Level `TTL'
The TTL register is located at offset 0x04 of the ICR Whenever 950 trigger levels are enabled (ACR[5]=1), bits 4 and 5 of FCR are ignored and an alternative arbitrary transmitter interrupt trigger level can be defined in the TTL register. This 7-bit value provides a fully programmable transmitter interrupt trigger facility. In 950 mode, a priority level 3 interrupt occurs indicating that the transmitter buffer requires more characters when the interrupt is not masked (IER[1]=1) and the transmitter FIFO level falls below the value stored in the TTL register. The value 0 (0x00) has a special meaning. In 950 mode when the user writes 0x00 to the TTL register, a level 3 interrupt only occurs when the FIFO and the transmitter shift register are both empty and the SOUT line is in the idle marking state. This feature is particularly useful to report back the empty state of the transmitter after its FIFO has been flushed away.
8.11.5 Receiver Interrupt. Trigger Level `RTL'
The RTL register is located at offset 0x05 of the ICR Whenever 950 trigger levels are enabled (ACR[5]=1), bits 6 and 7 of FCR are ignored and an alternative arbitrary receiver interrupt trigger level can be defined in the RTL register. This 7-bit value provides a fully programmable receiver interrupt trigger facility as opposed to the limited trigger levels available in 16C650 and 16C750 devices. It enables the system designer to optimise the interrupt performance hence minimising the interrupt overhead. In 950 mode, a priority level 2 interrupt occurs indicating that the receiver data is available when the interrupt is not masked (IER[0]=1) and the receiver FIFO level reaches the value stored in this register. DS-0019 Jun 05
8.11.7 Device Identification Registers
The identification registers is located at offsets 0x08 to 0x0B of the ICR The UARTs offer four bytes of device identification. The device ID registers may be read using offset values 0x08 to 0x0B of the Indexed Control Register. Registers ID1, ID2 and ID3 identify the device as an OX16C950 and return 0x16, 0xC9 and 0x50 respectively. The REV register Page 80
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resides at offset 0x0B of ICR and identifies the revision of OX16C950. This register returns 0x0A for the OXMPCI954.
OXMPCI954
8.11.9 Nine-bit Mode Register `NMR'
The NMR register is located at offset 0x0D of the ICR The UART offers 9-bit data framing for industrial multi-drop applications. The 9-bit mode is enabled by setting bit 0 of the Nine-bit Mode Register (NMR). In 9-bit mode the data length setting in LCR[1:0] is ignored. Furthermore as parity is permanently disabled, the setting of LCR[5:3] is also ignored. The receiver stores the 9th bit of the received data in LSR[2] (where parity error is stored in normal mode). Note that the UART provides a 128-deep FIFO for LSR[3:0]. The transmitter FIFO is 9 bits wide and 128 deep. The user should write the 9th (MSB) data bit in SPR[0] first and then write the other 8 bits to THR. As parity mode is disabled, LSR[7] is set whenever there is an overrun, framing error or received break condition. It is unaffected by the contents of LSR[2] (Now the received 9th data bit). In 9-bit mode, in-band flow control is disabled regardless of the setting of EFR[3:0] and the XON1/XON2/XOFF1 and XOFF2 registers are used for special character detection.
8.11.8 Clock Select Register `CKS'
The CKS register is located at offset 0x03 of the ICR This register is cleared to 0x00 after a hardware reset to maintain compatibility with 16C550, but is unaffected by software reset. This allows the user to select a clock source and then reset the channel to work-around any timing glitches. CKS[1:0]: Receiver Clock Source Selector logic [x0] The output of baud rate generator (internal BDOUT#) is selected for the receiver clock. logic [01] The DSR# pin is selected for the receiver clock. logic [11] The transmitter clock is selected for the receiver. This allows RI# to be used for both transmitter and receiver. CKS[2]: Reserved CKS[3]: Receiver 1x clock mode selector logic 0 The receiver is in Nx clock mode as defined in the TCR register. After a hardware reset the receiver operates in 16x clock mode, i.e. 16C550 compatibility. logic 1 The receiver is in isochronous 1x clock mode. CKS[5:4]: Transmitter 1x clock or baud rate generator output (BDOUT) on DTR# pin logic [00] The function of the DTR# pin is defined by the setting of ACR[4:3]. logic [01] The transmitter 1x clock (bit rate clock) is asserted on the DTR# pin and the setting of ACR[4:3] is ignored. logic [10] The output of baud rate generator (Nx clock) is asserted on the DTR# pin and the setting of ACR[4:3] is ignored. logic [11] Reserved. CKS[6]: Transmitter clock source selector logic 0 The transmitter clock source is the output of the baud rate generator (550 compatibility). logic 1 The transmitter uses an external clock applied to the RI# pin. CKS[7]: Transmitter 1x clock mode selector logic 0 The transmitter is in Nx clock mode as defined in the TCR register. After a hardware reset the transmitter operates in 16x clock mode, i.e. 16C550 compatibility. logic 1 The transmitter is in isochronous 1x clock mode. DS-0019 Jun 05
Interrupts in 9-Bit Mode:
While IER[2] is set, upon receiving a character with status error, a level 1 interrupt is asserted when the character and the associated status are transferred to the FIFO. The UART can assert an optional interrupt if a received character has its 9th bit set. As multi-drop systems often use the 9th bit as an address bit, the receiver is able to generate an interrupt upon receiving an address character. This feature is enabled by setting NMR[2]. This will result in a level 1 interrupt being asserted when the address character is transferred to the receiver FIFO. In this case, as long as there are no errors pending, i.e. LSR[1], LSR[3], and LSR[4] are clear, '0' can be read back from LSR[7] and LSR[1], thus differentiating between an `address' interrupt and receiver error or overrun interrupt in 9-bit mode. Note however that should an overrun or error interrupt actually occur, an address character may also reside in the FIFO. In this case, the software driver should examine the contents of the receiver FIFO as well as process the error. The above facility produces an interrupt for recognizing any `address' characters. Alternatively, the user can configure the UART to compare the receiver data stream with up to four programmable 9-bit characters and assert a level 5 interrupt after detecting a match. The interrupt occurs when the character is transferred to the FIFO (See below).
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NMR[0]: 9-bit mode enable logic 0 9-bit mode is disabled. logic 1 9-bit mode is enabled. NMR[1]: Enable interrupt when 9th bit is set logic 0 Receiver interrupt for detection of an `address' character (i.e. 9th bit set) is disabled. logic 1 Receiver interrupt for detection of an `address' character (i.e. 9th bit set) is enabled and a level 1 interrupt is asserted.
OXMPCI954
logic 0 Trailing edge RI is enabled. It can generate a level 4 interrupt when enabled by IER[3]. In power-state D2, trailing edge RI can assert the PME# line. Trailing edge RI can wake up the UART when it is asleep under auto-sleep operation. logic 1 Trailing edge RI is disabled. In can not generate an interrupt, assert a PME# or wake up the UART. MDM[3]: Disable delta DCD logic 0 Delta DCD is enabled. It can generate a level 4 interrupt when enabled by IER[3]. In powerstate D2, delta DCD can assert the PME# line. Delta DCD can wake up the UART when it is asleep under auto-sleep operation. logic 1 Delta DCD is disabled. In can not generate an interrupt, assert a PME# or wake up the UART. MDM[4]: Modem Wakeup Disable logic 1 Prevents modem status interrupts from taking the UART out of sleep-mode. For low power this may be useful. logic 0 Allows the modem status interrupts to take the UART out of sleep-mode. MDM[5]: Disable SIN wake up logic 0 When the device is in power-down state D2, a change in the state of the serial input line (i.e. start bit) can assert the PME# line logic 1 When the device is in power-down state D2, a change in the state of the serial input line cannot assert the PME# line. MDM[7:6]: Reserved
Special Character Detection
While the UART is in both 9-bit mode and Enhanced mode, setting IER[5] will enable detection of up to four `address' characters. The least significant eight bits of these four programmable characters are stored in special characters 1 to 4 (XON1, XON2, XOFF1 and XOFF2 in 650 mode) registers and the 9th bit of these characters are programmed in NMR[5] to NMR[2] respectively. NMR[2]: NMR[3]: NMR[4]: NMR[5]: Bit 9 of Special Character 1 Bit 9 of Special Character 2 Bit 9 of Special Character 3 Bit 9 of Special Character 4
NMR[7:6]: Reserved Bits 6 and 7 of NMR are always cleared and reserved for future use.
8.11.10 Modem Disable Mask `MDM'
The MDM register is located at offset 0x0E of the ICR This register is cleared after a hardware reset to maintain compatibility with 16C550. It allows the user to mask interrupts, sleep operation and power management events due to individual modem lines or the serial input line. MDM[0]: Disable delta CTS logic 0 Delta CTS is enabled. It can generate a level 4 interrupt when enabled by IER[3]. In powerstate D2, delta CTS can assert the PME# line. Delta CTS can wake up the UART when it is asleep under auto-sleep operation. logic 1 Delta CTS is disabled. In can not generate an interrupt, assert a PME# or wake up the UART. MDM[1]: Disable delta DSR logic 0 Delta DSR is enabled. It can generate a level 4 interrupt when enabled by IER[3]. In powerstate D2, delta DSR can assert the PME# line. Delta DSR can wake up the UART when it is asleep under auto-sleep operation. logic 1 Delta DSR is disabled. In can not generate an interrupt, assert a PME# or wake up the UART. MDM[2]: Disable Trailing edge RI
8.11.11 Readable FCR `RFC'
The RFC register is located at offset 0x0F of the ICR This read-only register returns the current state of the FCR register (Note that FCR is write-only). This register is included for diagnostic purposes.
8.11.12 Good-data status register `GDS'
The GDS register is located at offset 0x10 of the ICR For the definition of Good-data status, refer to section 0. GDS[0]: Good Data Status GDS[7:1]: Reserved
8.11.13 Port Index Register `PIX'
The PIX register is located at offset 0x12 of the ICR. This read-only register gives the UART index. For the OXMPCI954 this will read 0,1,2 or 3 depending on the UART being accessed. Page 82
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8.11.14 Clock Alteration Register `CKA'
The CKA register is located at offset 0x13 of the ICR. This register adds additional clock control mainly for isochronous and embedded applications. The register is effectively an enhancement to the CKS register. This register is cleared to 0x00 after a hardware reset to maintain compatibility with 16C550, but is unaffected by software reset. This allows the user to select a clock mode and then reset the channel to work-around any timing glitches. CKA[0]: Invert internal RX Clock This allows the sense of the receiver clock to be inverted. The main use for this would be to invert an isochronous input clock so the falling edge were used for sampling rather than the rising edge. CKA[1]: Invert internal TX clock This allows the sense of the transmitter clock to be inverted. The main use for this would be to invert an isochronous input clock so the rising edge were used for data output rather than the falling edge. CKA[2]: Invert DTR This allows the DTR output signal to be inverted, which is most likely to be useful when DTR is selected as being the transmitter clock for isochronous applications input clock so the falling edge were used for sampling rather than the rising edge.
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9
9.1
LOCAL BUS
Overview
control signal (LBRDWR#) and the chip-select signals (LBCS[3:0]#) are re-defined to data-strobe (LBDS[3:0]#). A reference cycle is defined, as two PCI clock cycles after the master asserts the IRDY# signal for the first time within a frame. In general, all the local bus control signals change state in the first cycle after the reference cycle, with offsets to provide suitable setup and hold times for common peripheral devices. However, all the timings can be increased / decreased independently in multiples of PCI clock cycles. This feature enables the card designer to override the length of read or write operations, the address and chip-select set-up and hold timing, and the data bus hold timing so that add-in cards can be configured to suit different speed peripheral devices connected to the Local Bus. The designer can also program the data bus to remain in the high impedance state or actively drive the bus during idle periods. The local bus will always return to an idle state, where no chip-select (data-strobe in Motorola mode) signal is active, between adjacent accesses. During read cycles the local bus interface latches data from the bus on the rising edge of the clock where LBRD# (LBDS[3:0]# in Motorola mode) goes high. Card designers should ensure that their peripherals provide the OXMPCI954 with the specified data set-up and hold times with respect to this clock edge. The local bus cannot accept burst transfers from the PCI bus. If a burst transfer is attempted the PCI interface will signal 'disconnect with data' on the first data phase. The local bus does accept 'fast back-to-back' transactions from PCI. A PCI target must complete the transaction within 16 PCI clock cycles from assertion of the FRAME# signal otherwise it should signal a retry. During a read operation from the Local Bus, the OXMPCI954 waits for the masterready signal (IRDY#) and computes the number of remaining cycles to the de-assertion of the read control signal. If the total number of PCI clock cycles for that frame is greater than 16 clock cycles, OXMPCI954 will post a retry. The master would normally return immediately and complete the operation in the following frame.
The OXMPCI954 incorporates a bridge from PCI to the Local Bus. It allows card developers to expand the capabilities of their products by adding peripherals to this bus. When the device mode is `000', `011', `100', the Local Bus is comprised of a bi-directional 8-bit data bus, an 8-bit address bus, up to four chip selects, and a number of control signals that allow for easy interfacing to standard peripherals. It also provides twelve active-high or activelow interrupt inputs (eleven interrupt pins in the enhanced modes). The local bus is configured by LT1 and LT2 (see sections 7.4.3 & 7.4.4) in the Local Configuration Register space. By programming these registers the card developer can alter the characteristics of the local bus to suit the characteristics of the peripheral devices being used.
9.2
Operation
The local bus can be accessed via I/O and memory space, in similar fashion to the internal UARTs. The mapping to the devices will vary with the application, but the bus is fully configurable to facilitate simple development. The operation of the local bus is synchronised to the PCI bus clock. The clock signal is output on pin LBCLK if it has been enabled by setting LT2[30]. The eight bit bi-directional pins LBD[7:0] drive the output data onto the bus during local bus write cycles. For reads, the device latches the data read from these pins at the end of the cycle. The local bus address is placed on pins LBA[7:0] at the start of each local bus cycle and will remain latched until the start of the subsequent cycle. If the maximum allowable block size (256 bytes) is allocated to the local bus in I/O space, then as access in I/O space is byte aligned, AD[7:0] are asserted on LBA[7:0]. If a smaller address range is selected, the corresponding upper address lines will be set to logic zero. The control bus is comprised of up to four chip-select signals LBCS[3:0]#, a read strobe LBRD# and a write strobe LBWR#, in Intel-type interfaces. For Motorola-type interfaces, LBWR# is re-defined to perform read/write DS-0019 Jun 05
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9.3
Configuration & Programming
The configuration registers for the local bus controller are described in sections 7.4.3 & 7.4.4. The values of these registers after reset allow the host system to identify the function and configure its base address registers. Alternatively many of the default values can be reprogrammed during device initialisation through use of the optional serial EEPROM (see section 11). The I/O space block can be varied in size from 4 bytes to 256 bytes (32 bytes is the default) by setting LT2[22:20] accordingly. Varying the block size means the I/O space can be allocated efficiently by the system, whatever the application. The I/O block can then be divided into one, two or four chip-select regions, depending on the setting in LT2[26:23]. To divide the area into a four chip-select region, the user should select the second uppermost non-zero address bit as the Lower-Address-CS-decode. To divide into two regions, the user should select the uppermost address bit. If an address bit beyond the selected range is selected, the
entire I/O space is allocated to CS0#. For example, if 32 bytes of I/O space are reserved, the active address lines are A[4:0]. To divide this into four regions, the Lower Address CS Decode parameter should be set to A3, by programming the value `0001' into LT2[26:23]. To select two regions, choose A4, and to maintain one region, select any value greater than A4. The memory space block is always 4K bytes, and always divided into four chip-select regions of 1K byte each. A soft reset facility is provided so software can independently reset the peripherals on the local bus. The local bus reset signals, LBRST and LBRST#, are always active during a PCI bus reset and also when the configuration register bit LT2[29] is set to 1. The clock enable bit, when set, enables a copy of the PCI bus clock output on the local bus pin LBCLK. A buffered UART clock can also be asserted on the UART_Clk_Out pin. This means that a single oscillator can be used to drive serial ports on the local bus as well as the internal UARTs.
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10 BIDIRECTIONAL PARALLEL PORT
10.1 Operation and Mode selection
The OXMPCI954 offers a compact, low power, IEEE-1284 compliant host-interface parallel port, designed to interface to many peripherals such as printers, scanners and external drives. It supports compatibility modes, SPP, NIBBLE, PS2, EPP and ECP modes. The register set is compatible with the Microsoft(R) register definition. To enable the parallel port function, the device mode must be set to `001' or `101'. The system can access the parallel port via two 8-byte blocks of I/O space; BAR0 contains the address of the basic parallel port registers, BAR1 contains the address of the upper registers. These are referred to as the `lower block' and `upper block' in this section. If the upper block is located at an address 0x400 above the lower block, generic PC device drivers can be used to configure the port, as the addressable registers of legacy parallel ports always have this relationship. If not, a custom driver will be needed. INIT#, AFD# and SLIN# pins change from open-drain outputs to active push-pull (totem pole) drivers (as required by IEEE 1284) and the pins ACK#, AFD#, BUSY, SLIN# and STB# are redefined as INTR#, DATASTB#, WAIT#, ADDRSTB# and WRITE# respectively. An EPP port access begins with the host reading or writing to one of the EPP port registers. The device automatically buffers the data between the I/O registers and the parallel port depending on whether it is a read or a write cycle. When the peripheral is ready to complete the transfer it takes the WAIT# status line high. This allows the host to complete the EPP cycle. If a faulty or disconnected peripheral failed to respond to an EPP cycle the host would never see a rising edge on WAIT#, and subsequently lock up. A built-in time-out facility is provided in order to prevent this from happening. It uses an internal timer which aborts the EPP cycle and sets a flag in the DSR register to indicate the condition. When the parallel port is not in EPP mode the timer is switched off to reduce current consumption. The host time-out period is 10s as specified with the IEEE-1284 specification. The register set is compatible with the Microsoft(R) register definition. Assuming that the upper block is located 400h above the lower block, the registers are found at offset 000-007h and 400-402h. The OXMPCI954 supports version 1.7 of the EPP protocol.
10.1.1 SPP mode
SPP (output-only) is the standard implementation of a simple parallel port. In this mode, the PD lines always drive the value in the PDR register. All transfers are done under software control. Input must be performed in nibble mode. Generic device driver-software may use the address in I/O space encoded in BAR0 of function 1 to access the parallel port. The default configuration allocates 8 bytes to BAR0 in I/O space.
10.1.2 PS2 mode
This mode is also referred to as bi-directional or compatible parallel port. To use the PS2 mode, the mode field of the Extended Control Register (ECR[7:5]) must be set to `001', using the negotiation steps as defined by the IEEE1284 specification. PS2 operation is similar to SPP mode but, in this mode, directional control of the parallel port data lines (PD[7:0]) is possible by setting & clearing DCR[5], the data direction bit.
10.1.4 ECP mode
To use the Extended Capabilities Port (`ECP') mode, the mode field of the Extended Control Register (ECR[7:5]) must be set to `011' using the negotiation steps as defined by the IEEE1284 specification. ECP mode is compatible with the Microsoft(R) register definition for ECP, and the IEEE-1284 bus protocol and timing. The ECP mode supports the decompression of Run-length encoded (RLE) data, in hardware. The RLE received data is expanded automatically by the correct number, into the ECP receiver FIFO. Run-length encoding on data to be transmitted is not available in hardware. This needs to be handled in software, if this feature is required. Assuming that the upper block is located 400h above the lower block, the ECP registers are found at offset 000-007h and 400-402h.
10.1.3 EPP mode
To use the Enhanced Parallel Port `EPP' the mode bits (ECR[7:5]) must be set to `100' 100' using the negotiation steps as defined by the IEEE1284 specification. The EPP address and data port registers are compatible with the IEEE 1284 definition. A write or read to one of the EPP port registers is passed through the parallel port to access the external peripheral. In EPP mode, the STB#, DS-0019 Jun 05
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10.2 Parallel port interrupt
The parallel port interrupt is asserted on the INTA# or INTB# pin, depending upon whether the function is operating in the backwards compatible or enhanced mode. It is enabled by setting DCR[4]. When DCR[4] is set, an interrupt is asserted on the rising edge of the ACK# (INTR#) pin and is held until the status register is read, which resets the INT# status bit as held by the bit DSR[2].
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10.3 Register Description
The parallel port registers are described below. (NB it is assumed that the upper block is placed 400h above the lower block). Register Name PDR DSR Address Offset 000h 001h 001h 002h 003h 004h 005h 006h 007h 400h 400h 400h 401h 402h 403h R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(EPP mode) (Other modes)
R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R R R/W -
SPP (Compatibility Mode) Registers Parallel Port Data Register nBUSY ACK# PE SLCT ERR# INT# nBUSY 0 ACK# 0 PE DIR
1
Timeout
DCR EPPA 1 EPPD1 1 EPPD2 1 EPPD3 1 EPPD4 1 EcpDFifo TFifo CnfgA CnfgB ECR -
0
int Mode[2:0]
SLCT ERR# INT# 1 1 INT_EN nSLIN# INIT# nAFD# nSTB# EPP Address Register EPP Data 1 Register EPP Data 2 Register EPP Data 3 Register EPP Data 4 Register ECP Data FIFO Test FIFO Configuration A Register - always 90h `000000' Reserved - Must write `00001' Reads return FIFO status and Service Interrupt status Reserved
Table 25: Parallel port register set
Note 1 : These registers are only available in EPP mode. Note 2 : Prefix `n' denotes that a signal is inverted at the connector. Suffix `#' denotes active-low signalling
The reset state of PDR, EPPA and EPPD1-4 is not determinable (i.e. 0xXX). The reset value of DSR is `XXXXX111'. DCR and ECR are reset to `0000XXXX' and `00010101' respectively.
10.3.1 Parallel port data register `PDR'
PDR is located at offset 000h in the lower block. It is the standard parallel port data register. Writing to this register in mode 000 (SPP mode) will drive data onto the parallel port data lines. In all other modes the drivers may be tristated by setting the direction bit in the DCR. Reads from this register return the value on the data lines.
DSR[0]: EPP mode: Timeout logic 0 EPP Timer Timeout has not occurred. logic 1 Timeout has occurred (Reading this bit clears it). Other modes: Unused This bit is permanently set to 1. DSR[1]: Unused This bit is permanently set to 1. DSR[2]: INT# logic 0 A parallel port interrupt is pending. logic 1 No parallel port interrupt is pending. This bit is activated (set low) on a rising edge of the ACK# pin. It is de-activated (set high) after reading the DSR. DSR[3]: ERR# logic 0 The ERR# input is low. logic 1 The ERR# input is high. Page 88
10.3.2 ECP FIFO Address / RLE
A data byte written to this address will be interpreted as an address if bit(7) is set, otherwise an RLE count for the next data byte. Count = bit(6:0) + 1.
10.3.3 Device status register `DSR'
DSR is located at offset 001h in the lower block. It is a read only register showing the current state of control signals from the peripheral. Additionally in EPP mode, bit 0 is set to `1' when an operation times out (see section 10.1.3)
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DSR[4]: SLCT logic 0 The SLCT input is low. logic 1 The SLCT input is high. DSR[5]: PE logic 0 The PE input is low. logic 1 The PE input is high. DSR[6]: ACK# logic 0 The ACK# input is low. logic 1 The ACK# input is high. DSR[7]: nBUSY logic 0 The BUSY input is high. logic 1 The BUSY input is low. DCR[4]: ACK Interrupt Enable logic 0 ACK interrupt is disabled. logic 1 ACK interrupt is enabled. DCR[5]: DIR (DIRECTION) * logic 0 PD port is output. logic 1 PD port is input.
OXMPCI954
This bit is overridden during an EPP address or data cycle, when the direction of the port is controlled by the bus access (read/write)
*Note : Microsoft's ECP Specification states that all direction changes related to ECP mode must first be made in the PS/2 mode, for reliable operation.
10.3.4 Device control register `DCR'
DCR is located at offset 002h in the lower block. It is a read-write register which controls the state of the peripheral inputs and enables the peripheral interrupt. When reading this register, bits 0 to 3 reflect the actual state of STB#, AFD#, INIT# and SLIN# pins respectively. When in EPP mode, the WRITE#, DATASTB# AND ADDRSTB# pins are driven by the EPP controller, although writes to this register will override the state of the respective lines. The bits in the DCR register must result in these lines to be in the inactive state, allowing the EPP controller to control these lines. This is also applicable for the ECP mode, to allow the ECP controller to control the parallel port pins. DCR[0]: nSTB# logic 0 Set STB# output to high (inactive). logic 1 Set STB# output to low (active). During an EPP address or data cycle the WRITE# pin is driven by the EPP controller, otherwise it is inactive. DCR[1]: nAFD# logic 0 Set AFD# output to high (inactive). logic 1 Set AFD# output to low (active). During an EPP address or data cycle the DATASTB# pin is driven by the EPP controller, otherwise it is inactive. DCR[2]: INIT# logic 0 Set INIT# output to low (active). logic 1 Set INIT# output to high (inactive). DCR[3]: nSLIN# logic 0 Set SLIN# output to high (inactive). logic 1 Set SLIN# output to low (active). During an EPP address or data cycle the ADDRSTB# pin is driven by the EPP controller, otherwise it is inactive. DS-0019 Jun 05
DCR[7:6]: Reserved These bits are reserved and always set to "00".
10.3.5 EPP address register `EPPA'
EPPA is located at offset 003h in lower block, and is only used in EPP mode. A byte written to this register will be transferred to the peripheral as an EPP address by the hardware. A read from this register will transfer an address from the peripheral under hardware control.
10.3.6 EPP data registers `EPPD1-4'
The EPPD registers are located at offset 004h-007h of the lower block, and are only used in EPP mode. Data written or read from these registers is transferred to/from the peripheral under hardware control.
10.3.7 ECP Data FIFO
Hardware transfers data from this 16-bytes deep FIFO to the peripheral when DCR(5) = `0'. When DCR(5) = `1' hardware transfers data from the peripheral to this FIFO.
10.3.8 Test FIFO
Used by the software in conjunction with the full and empty flags to determine the depth of the FIFO and interrupt levels.
10.3.9 Configuration A register
ECR[7:5] must be set to `111' to access this register. Interrupts generated will always be level, and the ECP port only supports an impID of `001'.
10.3.10 Configuration B register
ECR[7:5] must be set to `111' to access this register. Read only, all bits will be set to 0, except for bit[6] which will reflect the state of the interrupt.
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10.3.11 Extended control register `ECR'
The Extended control register is located at offset 002h in upper block. It is used to configure the operation of the parallel port. ECR[4:0]: Reserved -write These bits are reserved and must always be set to "00001". ECR[0]: Empty - read When DCR[5} = `0' logic 0 FIFO contains at least one byte logic 1 FIFO completely empty When DCR[5} = `1' logic 0 FIFO contains at least one byte logic 1 FIFO contains less than one byte ECR[1]: Full - read When DCR[5} = `0' logic 0 FIFO has at least one free byte FIFO completely full When DCR[5} = `1' logic 0 FIFO has at least one free byte logic 1 FIFO full ECR[2]: serviceIntr - read When DCR[5} = `0' logic 1 writeIntrThreshold (8) free bytes or more in FIFO When DCR[5} = `1' logic 1 readIntrThreshold (8) bytes or more in FIFO ECR[7:5]: Mode These bits define the operational mode of the parallel port. logic `000' SPP logic `001' PS2 logic `010' Reserved logic `011' ECR logic `100' EPP logic `101' Reserved logic `110' Test logic `111' Config
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11 SERIAL EEPROM
11.1 Specification
The OXMPCI954 can be configured using an optional serial electrically-erasable programmable read only memory (EEPROM). If the EEPROM is not present, the device will remain in its default configuration after reset. Although this may be adequate for some applications, many will benefit from the degree of programmability afforded by this feature. The EEPROM interface is based on the proprietary serial interface known as MicrowireTM. The interface has four pins which supply the memory device with a clock, a chip-select and serial data input and output lines. In order to read from such a device, a controller has to output serially a read command and an address, and then input serially the data. The EEPROM interface auto-detects a variety of Microwire compatible EEPROM devices attached to its interface, where the data has been organised as a 16-bit data word format. Devices supported include the NM93C46, C56, C66, C76, and C86. The OXMPCI954 reads data from the serial EEPROM and writes data into the configuration register space immediately after a PCI bus reset. This sequence ends either when the controller finds no EEPROM is present or when it reaches the end of the EEPROM data. Following device configuration, driver software can access the serial EEPROM through four bits in the device-specific Local Configuration Register LCC[27:24]. Software can use this register to manipulate the device pins in order to read and modify the EEPROM contents. In order to prevent an incorrectly coded EEPROM from `hanging' the PCI system (since all PCI accesses will be met with a retry while the external EEPROM device is being accessed), the OXMPCI954 device incorporates an EEPROM overrun detection mechanism that terminates the EEPROM download if any attempts are made to read beyond the size of the detect EEPROM. In this case, the overrun flag is set in the local registers (LCC reg, bit 30). The overrun condition does not reset the device to eliminate the effects of any downloaded (corrupt) values so any overrun indications must be handled by reprogramming the device with the correct eeprom data, as the state of the OXMPCI954 may be unknown. A Windows(R) based utility is available to help generate correct data for the EEPROM. For further details please contact Oxford Semiconductor (see back cover). MicrowireTM is a trade mark of National Semiconductor. For a description of MicrowireTM, please refer to National Semiconductor data manuals.
EEPROM Data Organisation
The serial EEPROM data is divided in four zones or six zones, depending upon whether the device is operating in the backwards compatible or enhanced modes. The size of each zone is an exact multiple of 16-bit WORDs. Zone0 is allocated to the header. A valid EEPROM program must contain a header. The EEPROM can be programmed from the PCI bus. Once the programming is complete, the device driver should either reset the PCI bus or set LCC[29] to reload the OXMPCI954 registers from the serial EEPROM. The general EEPROM data structure is shown in EEPROM Zones : Backwards Compatible Modes DATA Zone 0 1 2 3 Size (Words) One One or more One to four Two or more Description Header Local Configuration Registers Identification Registers PCI Configuration Registers
EEPROM Zones : Enhanced Modes DATA Zone 0 1 2 3 4 5 Size (Words) One One or more One to four Two or more One or more Two or more Description Header Local Configuration Registers Identification Registers PCI Configuration Registers Power Management Data Function Access
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11.1.1 Zone 0: Header
The header identifies the EEPROM program as valid. Different EEPROM headers are expected when the device operates in the backwards compatible or Enhanced Modes.
Bits 15:4
3 2 1 0
Description These bits should return 0x950 to identify a valid program. Once the OXMPCI954 reads 0x950 from these bits, it sets LCC[28] to indicate that a valid EEPROM program is present. Reserved. Write `0' to this bit. 1 = Zone1 (Local Configuration) exists 0 = Zone1 does not exist 1 = Zone2 (Identification) exists 0 = Zone2 does not exist 1 = Zone3 (PCI Configuration) exists 0 = Zone3 does not exist
Bits 15:8
7 6 5 4 3 2
EEPROM Header : Backwards Compatible Mode
1 0
Description These bits should return 0x96 to identify a valid program. Once the OXMPCI954 reads 0x96 from these bits, it sets LCC[28] to indicate that a valid EEPROM program is present. Reserved. Write `0' to this bit. Reserved. Write `0' to this bit. Reserved. Write `0' to this bit. 1 = Zone1 (Local Configuration) exists 0 = Zone1 does not exist 1 = Zone2 (Identification) exists 0 = Zone2 does not exist 1 = Zone3 (PCI Configuration) exists 0 = Zone3 does not exist 1 = Zone4 (Power Management Zone) exists 0 = Zone4 does not exist 1 = Zone5 (Function Access Zone) exists 0 = Zone5 does not exist EEPROM Header: Enhanced Modes
The programming data for each zone follows the proceeding zone if it exists. For example a Header value of 0x9507 (backwards compatible mode header) indicates that all zones exist and they follow one another in sequence, while 0x9505 (backwards compatible mode header) indicates that only Zones 1 and 3 exist where the header data is followed by Zone1 WORDs, and since Zone2 is missing, Zone1 WORDs are followed by Zone3 WORDs.
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11.1.2 Zone 1: Local Configuration Registers
The Zone1 region of EEPROM contains the program value of the vendor-specific Local Configuration Registers using one or more configuration WORDs. Registers are selected using a 7-bit byte-offset field. This offset value is the offset from Base Address Registers in I/O or memory space (see section 7.4). The format of the EEPROM words for this zone, is as shown. Note that not all of the registers in the Local Configuration Register set are writable by EEPROM. Bits 15 Description `0' = There are no more Configuration WORDs to follow in Zone1. Move to the next available zone or end EEPROM program if no more zones are enabled in the Header. `1' = There is another Configuration WORD to follow for the Local Configuration Registers. These seven bits define the byte-offset of the Local configuration register to be programmed. For example the byte-offset for LT2[23:16] is 0x0E. 8-bit value of the register to be programmed
14:8
7:0
The following table shows which Local Configuration registers are writable from the EEPROM. Note that an attempt by the EEPROM to write to any other offset locations can result in unpredictable behaviour. Offset 0x00 0x00 0x00 0x00 0x00 0x04 0x05 0x06 0x07 0x07 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0E 0x0E 0x0F 0x0F 0x0F 0x0F 0x0F 0x1E 0x1E 0x1E 0x1F Bits 1:0 2 4:3 6:5 7 7:0 7:0 7:0 31:29 26 7:0 7:0 7:0 7:0 7:0 3:0 6:4 7 2:0 4:3 5 6 7 3:0 4 7:5 7:0 Description Must be `00'. Enable UART clock-out. Endian byte-lane select. Power-down filter. MIO2_PME enable. Multi-purpose IO configuration. Multi-purpose IO configuration. Multi-purpose IO configuration. Multi-purpose IO configuration. Multi-purpose IO configuration. Local Bus timing parameters Local Bus timing parameters Local Bus timing parameters Local Bus timing parameters Local Bus timing parameters Must be `0000'. IO Space Block size. Lower-Address-CS-Decode. Lower-Address-CS-Decode. Must be `00' Must be `0'. Local Bus clock enable. Bus interface type. UART Interrupt Mask MIO0/Parallel Port interrupt mask Multi-purpose IO interrupt mask. Multi-purpose IO interrupt mask. Reference LCC[2] LCC[4:3] LCC[6:5] LCC[7] MIC[7:0] MIC[15:8] MIC[23:16] MIC[31:29] (Enhanced Modes Only) MIC[26] (Enhanced Modes Only) LT1[15:8] LT1[23:16] LT1[31:24] LT2[7:0] LT2[15:8] LT2[22:20] LT2[23] LT2[26:24] LT2[28:27] LT2[30] LT2[31] GIS[19:16] GIS[20] GIS[23:21] GIS[31:24]
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11.1.3 Zone 2: Identification Registers
The Zone2 region of the EEPROM contains the program value for Vendor ID and Subsystem Vendor ID. The format of Device Identification configuration WORDs are described in the following table. Bits 15 Description `0' = There are no more Zone2 (Identification) bytes to program. Move to the next available zone or end EEPROM program if no more zones are enabled in the Header. `1' = There is another Zone2 (Identification) byte to follow. 0x00 = Vendor ID bits [7:0]. 0x01 = Vendor ID bits [15:8]. 0x02 = Subsystem Vendor ID [7:0]. 0x03 = Subsystem Vendor ID [15:8]. 0x03 to 0x7F = Reserved. 8-bit value of the register to be programmed
The subsequent WORDs for each function contain the address offset and a byte of programming data for the PCI Configuration Space belonging to the function number selected by the proceeding Function-Header. The format of configuration WORDs for the PCI Configuration Registers are described below. Bits 15 Description `0' = This is the last configuration WORD in for the selected function in the Function-Header. `1' = There is another WORD to follow for this function. These seven bits define the byte-offset of the PCI configuration register to be programmed. For example the byte-offset of the Interrupt Pin register is 0x3D. Offset values are tabulated in section 7.2. 8-bit value of the register to be programmed
14:8
14:8
7:0
7:0
The following table shows which PCI Configuration registers are writable from the EEPROM for each function. Offset 0x02 0x03 0x06 0x06 0x06 0x09 0x0A 0x0B 0x2E 0x2F 0x3D 0x42 0x43 Bits 7:0 7:0 3:0 4 7:5 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 Description Device ID bits 7 to 0. Device ID bits 15 to 8. Must be `0000'. Extended Capabilities. Must be `000'. Class Code bits 7 to 0. Class Code bits 15 to 8. Class Code bits 23 to 16. Subsystem ID bits 7 to 0. Subsystem ID bits 15 to 8. Interrupt pin. Power Management Capabilities bits 7 to 0. Power Management Capabilities bits 15 to 8.
11.1.4 Zone 3: PCI Configuration Registers
The Zone3 region of the EEPROM contains any changes required to the PCI Configuration registers (with the exception of the Vendor ID and Subsystem Vendor ID which are programmed through Zone2). This zone is divided into two groups, each of which consists of a function header WORD and one or more configuration WORDs for that function. The function header is described in Table Below. Bits 15 14:3 2:0 Description `0' = End of Zone 3. `1' = Define this function header. Reserved. Write zeros. Function number for the following configuration WORD(s). `000' = Function0 (Internal UARTs) `001' = Function1 (Local Bus / Parallel Port) Other values = Reserved.
EEPROM-writable PCI configuration registers
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11.1.5 Zone 4 : Power Management DATA (and DATA_SCALE zone)
This Zone exists for the Enhanced Modes only. Zone 4 of the EEPROM provides each function's Power Management Registers with user-defined values for the DATA and DATA_SCALE fields, that will be provided to the system software during the initial configuration when requests are made through the DATA_SELECT field. Since there are 16 possible values for the DATA_SELECT fields, the system can request up to 16 sets of DATA and DATA_SCALE values. The organisation of the EEPROM data for this zone is shown in the following table. Each DATA and DATA_SCALE value being programmed is relevant to a particular value of the DATA_SELECT parameter. Bits 15 Description `0' = There are no more Configuration WORDs to follow in Zone4. Move to the next available zone or end EEPROM program if no more zones are enabled in the Header. `1' = There is another Configuration WORD to follow for the Power Management Data zone. Function Select 0=> Values applicable for Function 0 1=> Values applicable for Function 1 DATA SELECT This indicates for which DATA_SELECT value the DATA and DATA_SCALE values in this particular word are associated with. DATA SELECT : 1 of 16 values (0h to Fh) DATA SCALE Value User Value Corresponding to chosen DATA SELECT DATA Register Value User Value Corresponding to chosen DATA SELECT.
11.1.6 Zone 5 : Function Access
This Zone exists for the Enhanced Modes only. Zone 5 allows each of the internal UARTs, devices on the 8-bit Local Bus, or the Parallel Port of the OXMPCI954 device to be pre-configured, prior to any PCI accesses. This is very useful when these functions need to run with (typically generic) device drivers and these drivers are not capable of utilising the enhanced features/modes of these logical units. For example, the 950 mode of the UARTs offer high performance. Generic UART drivers will be unable to set the 950 mode since this requires setting of registers outside the register definition within the generic device drivers. By using function access, the relevant UART registers can be accessed (setup) via the eeprom to enable/customize these features before control is handed to these device drivers. Each 8-bit function access is equivalent to accessing each function through its assigned I/O BAR (Base Address Register), with the exception that a function read access does not return any data (it is discarded internally). The internal UARTs, 8-bit Local Bus or the parallel port behave as though these function accesses via the eeprom were equivalent to PCI-based I/O read/write accesses. Each entry for the Function Access Zone comprises of 2 16 bit words (word pairs), with the exception that when ending this zone this only requires a single word (all 0's) for `termination'. The format is as shown. Word 1 1 1 1 Bits 15 14:12 11 10:8 Description `1' - Function Access Word Pair available. `0' - End Function Access Zone* (over to next available zone or end eeprom download) BAR number to access Acceptable BARs 000 to 100. Others reserved. `0' : Read access required (data will be discarded) `1' : Write access required Function Number, requiring access. 000 - Function 0 (UARTs) 001 - Function 1 (8-bit local Bus / Parallel Port). Others Reserved. I/O address to access This is the address that needs to be written/read and is the offset address from the specified BAR. E.g to access SPR register of UART, address is 00000111 (7dec).
14 13:1 0
9:8 7:0
1
7:0
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Word 2 2 2
Bits 15 14:8 7:0
Description `1' Reserved - write 0's Data to be written to specified address. Field is unused for function access READS (set to 0's for reads)
3) (Continue). Read IER Register, UART 0. End Function Access Zone 1000000000000001 (Function Access Word Pair) 1000000000000000 0000000000000000 (End function Access zone*) 1st Word: Function Number = 000, BAR No =000 (UART0), Read access, address=00000001 (IER reg) 2nd Word: No data to be written (as read access). Read data is discarded
* When ending Function Access Zone, only a single word is required (not word pairs) and all fields must be zeros. See example 3.
2nd
WORD of FUNCTION ACCESS WORD PAIR
When directing Function Access to each Function, the enduser needs to ensure that the BAR number and I/O Address Range is compatible with the Function's I/O makeup for the given device mode. The OXMPCI954 will reject accesses to BARs which do not hold the I/O Base Address of the function and any addresses outside the workable address range for that I/O BAR. For Example, When the UARTs are not in the `unique BAR mode', BAR0 of function 0 is a 32-byte I/O Base Address Register that provides access to the internal UARTs. In this case, Function access will only accept accesses to BAR0 with an I/0 Address Range 0 to 31. Accesses to other BARs or address ranges will be rejected, for function 0. When the UARTs are in the `unique BAR mode', BAR0 to BAR3 of function 0 are an 8-byte I/O Base Address Registers that provide individual access to the internal UARTs. In this case, Function access will only accept accesses to BAR0 to BAR3, with the I/0 Address Range 0 to 7. Accesses to other BARs or address ranges will be rejected, for function 0. Function Access Examples 1) Enable Internal loopback, of UART 0 (Enable bit 4, of UART 0's MCR register). 1000100000000100 1000000000010000 1st Word: Function Number = 000, BAR No = 000 (UART0), Write Access, Address=00000100 (MCR reg). 2nd Word: Data to be written=00010000 2) (Continue). Enable FIFO of UART 1 (Enable bit 0, of UART 1's FCR register) 1001100000000010 1000000000000001 1st Word: Function Number = 000, BAR No = 001 (UART1), Write access, address=00000010 (FCR reg) 2nd Word: Data to be written=00000001 DS-0019 Jun 05
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12 OPERATING CONDITIONS
12.1 DC Electrical Characteristics
Symbol VDD VIN VIN_5V IIN TSTG Parameter DC supply voltage DC input voltage DC input voltage - 5V tolerant DC input current Storage temperature Table 26: Absolute maximum ratings Min -0.3 -0.3 -0.3 -40 Max 3.8 VDD + 0.3 5.6 +/- 10 125 Units V V V mA C
Symbol VDD TC Symbol
Parameter DC supply voltage Temperature Parameter Operating supply current at power-on Operating supply current in normal mode ** Operating supply current in Power-down mode Condition XTAL = 1.8432 MHz (crystal) XTAL = 14.745 MHz (crystal) XTAL = 60 MHz (osc module) XTAL = 1.8432 MHz (crystal) XTAL = 14.745 MHz (crystal) XTAL = 60 MHz (osc module) XTAL = 1.8432 MHz (crystal) XTAL = 14.745 MHz (crystal) XTAL = 60 MHz (osc module)
Min 3.0 -40 Typical 19* 23* 40* 20* 24* 34* 3* 4.4* 5*
Max 3.6 105 Max 34* 40* 68* 41* 42* 55* 11* 14* 15*
Units V C Units
ICC
mA
Table 27: Recommended operating conditions
*These values do not include any statistical spreads and are suitable for indications only. **Values have been measured from a few samples running under the following conditions: 1) 3.3v PCI Environment. 2) PCI CLK active, SYSTEM CLK line driven by a crystal or clock module. 3) All PCI configuration accesses over. 4) Single UART channel (1 COM port) set to operate at the maximum data-transfer rate, with it's internal loop-back enabled. 5) Values measured during file transfers (at the max rate)
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PCI I/O Buffers (3.3v Signalling) All PCI I/O buffers are compliant to the PCI DC/AC Specifications, as defined in the PCI Local Bus Specification 2.3/3.0. DC Specifications Symbol Parameter VCC Supply voltage VIH Input high voltage VIL Input low voltage VOH Output High voltage VOL Output low voltage
Condition
IOUT = -500uA IOUT = 1500uA
Min 3.0 0.5* VCC -0.5 0.9Vcc
Max 3.6 VCC + 0.5 0.3* VCC 0.1Vcc
Unit V V V V V
Non-PCI I/O Buffers Ibhu Input Buffer High Voltage Tolerant, LVTTL-level (with pullup) Ibt Input Buffer, LVTTL-level Ob2/Ob4/Ob8 Output Buffer (2/4/8mA) Bbt4lh Bi-directional Buffer, High Voltage Tolerant, LVTTL level, (4mA Bbt8lh Bi-directional Buffer, High Voltage Tolerant, LVTTL level, (Ioh=6mA, Iol=8mA) DC Specifications(Vcc : 3.3v +/- 0.3v) Symbol Parameter Condition Vcc Supply Voltage Vih Input High Voltage LVTTL 5v Tolerant Vil Input Low Voltage LVTTL 5v tolerant Voh Output High Voltage Ioh = -2mA Ioh = -4mA Ioh = -8mA Vol Output Low Voltage Iol = 2mA Iol = 4mA Iol = 8mA DC Specifications(Vcc : 3.3v +/- 0.3v) Symbol Parameter Condition Ioz 3-state leak Current Voh = Vss Vol = Vcc
Min 3.0 2.0 2.0 2.4 2.4 2.4
Typ 3.3
Max 3.6 0.8 0.8
Unit V V V V V v V V V
0.4 0.4 0.4
Min -10 -10
Typ
Max 10 10
Unit uA uA
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13 AC ELECTRICAL CHARACTERISTICS
13.1 PCI Bus
The timings for PCI pins comply with PCI Specification for the 3.3 Volt signalling environment. AC Specifications Symbol Parameter Condition Min Max Ioh(AC) Switching Current High 0Vout>=0.6Vcc 16Vcc 0.6Vcc>Vout>0.1Vcc 26.7Vout 0.18Vcc>Vout>0 Equation D Slewr Output Rise Slew Rate 0.2Vcc-0.6Vcc load 1 4 Slewf Output Fall Slew Rate 0.6Vxx-0.2Vcc load 1 4
Unit mA mA mA mA mA mA V/ns V/ns
Note 1 1 1,2 1 1 1,2 3 3
1. This specification does not apply to PCI_CLK and RESET# pins. "Switching Current High" specifications are not relevant to SERR#, PME#, INTA#, INTB#. 2. Equation C Ioh = (98.0/Vcc)*(Vout-Vcc)*(Vout+0.4Vcc) for Vcc>Vout>0.7Vcc Equation D Iol = (256/Vcc)*Vout*(Vcc-Vout) for 0v13.2 Local Bus
By default, the Local bus control signals change state in the cycle immediately following the reference cycle, with offsets to provide setup and hold times for common peripherals in Intel mode. The tables below show the local bus parameters using default values for LT1/LT2 local registers. However each of these can be increased or decreased by a number of PCI clock cycles by adjusting the parameters in registers LT1 and LT2. All timing parameters assume a loading of 100pF on the local bus output pins. Symbol tref tza tard tzrcs1 tzrcs2 tcsrd trdcs tzrd1 tzrd2 tdrd tzd1 tzd2 tsd thd Parameter IRDY# falling to reference LBCLK Reference LBCLK to Address Valid Address Valid to LBRD# falling Reference LBCLK to LBCS# falling Reference LBCLK to LBCS# rising LBCS# falling to LBRD# falling LBRD# rising to LBCS# rising Reference LBCLK to LBRD# falling Reference LBCLK to LBRD# rising Data bus floating to LBRD# falling Reference LBCLK to data bus floating at the start of the read transaction Reference LBCLK to data bus driven by OXMPCI954 at the end of the read transaction Data bus valid to LBRD# rising Data bus valid after LBRD# rising Min Max Nominally 2 PCI clock cycles 3.8 12.0 2.8 9.6 3.2 11.0 3 PCI clks + 6.6 3 PCI clks + 21.6 3.2 10.6 3.0 10.0 6.6 21.6 3 PCI clks + 3.6 3 PCI clks + 11.6 2.6 8.2 4.0 13.4 4 PCI clks + 3.8 11.4 0 4 PCI clks + 13.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Table 28: Read operation from Intel-type Local Bus
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Symbol tref tza tawr tzwcs1 tzwcs2 tcswr twrcs tzwr1 tzwr2 tzdv tzdf twrdi
Parameter IRDY# falling to reference LBCLK Reference LBCLK to Address Valid Address Valid to LBWR# falling Reference LBCLK to LBCS# falling Reference LBCLK to LBCS# rising LBCS# falling to LBWR# falling LBWR# rising to LBCS# rising Reference LBCLK to LBWR# falling Reference LBCLK to LBWR# rising Reference LBCLK to data bus valid Reference LBCLK to data bus high-impedance LBWR# rising to data bus invalid
Min Max Nominally 2 PCI clock cycles 4.2 13.2 2.4 8.0 3.2 11.0 2 PCI clks + 6.6 2 PCI clks + 21.6 3.2 10.2 3.0 10.2 6.6 30.0 2 PCI clks + 3.6 2 PCI clks + 11.6 4.0 12.8 Note1 Note1 Note1 Note1
Units ns ns ns ns ns ns ns ns ns ns ns
Table 29: Write operation to Intel-type Local Bus Symbol tref tza tads tzrds1 tzrds2 vtdrd tzd1 tzd2 tsd thd Parameter IRDY# falling to reference LBCLK Reference LBCLK to Address Valid Address Valid to LBDS# falling Reference LBCLK to LBDS# falling Reference LBCLK to LBDS# rising Data bus floating to LBDS# falling Reference LBCLK to data bus floating at the start of the read transaction Reference LBCLK to data bus driven by OXMPCI954 at the end of the read transaction Data bus valid to LBDS# rising Data bus valid after LBDS# rising Min Max Nominally 2 PCI clock cycles 3.8 12.0 2.4 8.8 6.4 20.6 3 PCI clks + 3.6 3 PCI clks + 11.8 2.2 7.4 4.0 13.4 4 PCI clks + 3.8 10.8 0 4 PCI clks + 13.0 Units ns ns ns ns ns ns ns ns ns
Table 30: Read operation from Motorola-type Local Bus Symbol tref tza tads tzw1 tzw2 twds tdsw tzwds1 tzwds2 tzdv tzdf tdsdi Parameter IRDY# falling to reference LBCLK Reference LBCLK to Address Valid Address Valid to LBDS# falling Reference LBCLK to LBRDWR# falling Reference LBCLK to LBRDWR# rising LBRDWR# falling to LBDS# falling LBDS# rising to LBRDWR# rising Reference LBCLK to LBDS# falling Reference LBCLK to LBDS# rising Reference LBCLK to data bus valid Reference LBCLK to data bus high-impedance LBDS# rising to data bus invalid Min Max Nominally 2 PCI clock cycles 4.2 13.2 2.2 7.6 3.6 11.6 2 PCI clks + 6.6 2 PCI clks + 21.2 2.6 9.2 3.0 9.6 6.4 20.8 2 PCI clks + 3.6 2 PCI clks + 12.0 4.0 13.0 Note1 Note1 Note1 Note1 Units ns ns ns ns ns ns ns ns ns ns ns
Table 31: Write operation to Motorola-type Local Bus Note1 : For local bus writes, values on the data bus persist until the next read/write local bus transaction.
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13.3 Serial ports
Isochronous (x1 Clock) Timing: Symbol tirs tirh tits Parameter SIN set-up time to Isochronous input clock `Rx_Clk_In rising 1 SIN hold time after Isochronous input clock `Rx_Clk_In' rising 1 SOUT valid after Isochronous output clock `Tx_Clk_Out' falling 1 Table 32: Isochronous mode timing
Note 1: In Isochronous mode, transmitter data is available after the falling edge of the x1 clock and the receiver data is sampled using the rising edge of the x1 clock. The system designer is should ensure that mark-to-space ratio of the x1 clock is such that the required set-up and hold timing constraint are met. One way of achieving this is to choose a crystal frequency which is twice the required data rate and then divide the clock by two using the on-board prescaler. In this case the mark-to-space ratio is 50/50 for the purpose of set-up and hold calculations.
Min TBD TBD TBD
Max TBD TBD TBD
Units ns ns ns
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14 TIMING WAVEFORMS
CLK
1 2 3 4 5
FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP#
Wait
Address Bus CMD Byte enable#
Data
Figure 2: PCI Read Transaction from internal UARTs
CLK
1 2 3 4
FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# Address Bus CMD Data Byte enable#
Figure 3: PCI Write Transaction to internal UARTs
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Data transfer
Data transfer
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TIMING WAVEFORMS
CLK
1 2 3 4
FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# Address Bus CMD Data Byte enable#
Figure 4: PCI Read transaction from Local Configuration registers
CLK
1 2 3 4
FRAME# AD[31:0] C/BE[3:0]# IRDY# TRDY# DEVSEL# STOP# Address Bus CMD Data Byte enable#
Figure 5: PCI Write transaction to Local Configuration Registers
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Data transfer
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TIMING WAVEFORMS
CLK
1 2 3 4 5 n+5 n+6 Where: n = 0, 1, .., 9 n+7
FRAME# AD[31:0] C/BE[3:0]# IRDY#
Wait Wait Wait
Address Bus CMD
Data Byte enable#
Data
TRDY# DEVSEL# STOP# LBCLK LBA
Local Bus Reference Cycle
t ref
t za
t ard Valid Local Bus Address t zrcs2 trdcs
Data sampled
LBCS# LBRD# LBD LBD
1
t zrcs1 t csrd tzrd1 t t zd1 drd
tzrd2 t zd2
Valid Data t sd Valid Data
2
t hd
Figure 6: PCI Read Transaction from Intel-type Local Bus
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Data transfer
Wait
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TIMING WAVEFORMS
CLK
1 2 3 4 5 n+5 n+6 Where: n = 0, 1, .., 9 n+7
FRAME# AD[31:0] C/BE[3:0]# IRDY#
Wait Wait Wait
Address Bus CMD
Data Byte enable#
TRDY# DEVSEL# STOP# LBCLK LBA
Local Bus Reference Cycle
t ref
t za
t awr Valid Local Bus Address tzwcs2 twrcs tzwr2
LBCS# LBWR# LBD LBD
1
tzwcs1 tcswr tzwr1
Valid Local Bus Data t zdv Valid Local Bus Data twrdi t zdf
2
Figure 7: PCI Write Transaction to Intel-type Local Bus
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Data transfer
Wait
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TIMING WAVEFORMS
CLK
1 2 3 4 5 n+5 n+6 Where: n = 0, 1, .., 9 n+7
FRAME# AD[31:0] C/BE[3:0]# IRDY#
Wait Wait Wait
Address Bus CMD
Data Byte enable#
Data
TRDY# DEVSEL# STOP# LBCLK LBA LBRDWR# LBDS# LBD LBD
1 Local Bus Reference Cycle
t ref
t za
t ads Valid Local Bus Address
t zd1
Data sampled
tzrds1
tzrds2
Data transfer
Wait
tdrd
t zd2
Valid Data t sd Valid Data
2
t hd
Figure 8: PCI Read Transaction from Motorola-type Local Bus
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TIMING WAVEFORMS
CLK
1 2 3 4 5 n+5 n+6 Where: n = 0, 1, .., 9 n+7
FRAME# AD[31:0] C/BE[3:0]# IRDY#
Wait Wait Wait
Address Bus CMD
Data Byte enable#
TRDY# DEVSEL# STOP# LBCLK LBA
Local Bus Reference Cycle
t ref
t za
t ads Valid Local Bus Address t zw2 t dsw
t
zw1
LBRDWR# LBDS# LBD LBD
1
t wds t zwds1 t zwds2
Valid Local Bus Data t zdv Valid Local Bus Data tdsdi t zdf
2
Figure 9: PCI Write Transaction to Motorola-type Local Bus
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Data transfer
Wait
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TIMING WAVEFORMS
SIN t irs t irh Rx_Clk_In SOUT t its Tx_Clk_Out
Figure 10: Isochronous (x1 clock) timing waveform
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Tpd (PCI CLK to Valid Parallel Port Data ) : 22 ns max*
* These values are applicable to a pin loading of100pF.
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Tpc : PCI CLK to Valid Parallel Port Control lines. Tpc (Slin_N) Tpc (Stb_N) Tpc (Init_N) Tpc (Afd_N) : 22.0 ns max* : 22.0 ns max* : 22.0 ns max* : 22.0 ns max*
* These values are applicable to a pin loading of100pF.
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Write to EPP Data Register (EPP Write Data cycle)
PCI CLK no (1st Transaction) 1 - Start of PCI write to EPP Data register 5 - Start of EPP data write cycle on parallel port side. 8 - PCI transaction completes with a `retry' (without affecting ongoing EPP write data cycle) as EPP cycle cannot complete within 16 PCI CLK cycles 7-8 - Peripheral Asserts BUSY 11 - Host responds to BUSY by de-asserting AFD_N (3 clock cycles after sampling BUSY) 13-14 - Peripheral Deasserts BUSY 16 - Host responds to BUSY by asserting STB_N and the parallel port data lines (2 clock cycles after sampling BUSY). - EPP cycle completed. PCI CLK no (Retry Transaction) 1 - Start of Retry transaction, to the original write to EPP data register 5 - Retry transaction completes with "Data Transfer", without initiating another EPP write Data cycle. Tafd (PCI clk to valid AFD_N) - 22ns max* Tstb (PCI clk to valid STB_N) - 22ns max* Tpd (PCI clk to valid Parallel Data) - 22ns max*
EPP Write Data Cycle duration is dependant upon the timing response of the peripheral's BUSY line and the parallel port filters. Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral's BUSY line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
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Read from EPP Data Register (EPP Read Data cycle)
PCI CLK no (1st Transaction) 1 - Start of PCI Read from EPP Data register 4 - Start of EPP data read cycle on parallel port side. 8 - PCI transaction completes with a `retry' (without affecting ongoing EPP read data cycle) as EPP cycle cannot complete within 16 PCI CLK cycles 7-8 - Peripheral Asserts BUSY in response to the host driving AFD_N low. 11 - Host responds to BUSY by de-asserting AFD_N (3 clock cycles after sampling BUSY) 14-15 - Peripheral Deasserts BUSY - EPP cycle completed. PCI CLK no (Retry Transaction) 1 - Start of Retry transaction, to the original read from EPP data register 5 - Retry transaction completes with "Data Transfer", without initiating another EPP read Data cycle. Tafd (PCI clk to valid AFD_N) - 22ns max* Tstb (PCI clk to valid STB_N) - 22ns max* Tpd (PCI clk to valid Parallel Data) - 22ns max*
EPP Read Data Cycle duration is dependant upon the timing response of the peripheral's BUSY line and the parallel port filters. Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral's BUSY line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
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Write to EPP Address Register (EPP Write Address cycle)
PCI CLK no (1st Transaction) 1 - Start of PCI write to EPP Address register 5 - Start of EPP address write cycle on parallel port side. 8 - PCI transaction completes with a `retry' (without affecting current EPP write address cycle) as EPP cycle cannot complete within 16 PCI CLK cycles 7-8 - Peripheral Asserts BUSY 11 - Host responds to BUSY by de-asserting SLIN_N (4 clock cycles after sampling BUSY) 14-15 - Peripheral Deasserts BUSY 17 - Host responds to BUSY by asserting SLIN_N and the parallel port data lines (2 clock cycles after sampling BUSY). - EPP cycle completed. PCI CLK no (Retry Transaction) 1 - Start of Retry transaction, to the original write to EPP address register 5 - Retry transaction completes with "Data Transfer", without initiating another EPP write address cycle. Tslin (PCI clk to valid SLIN_N) Tstb (PCI clk to valid STB_N) Tpd (PCI clk to valid port Address) - 22ns max* - 22ns max* - 22ns max*
EPP Write Address Cycle duration is dependant upon the timing response of the peripheral's BUSY line and the parallel port filters. Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral's BUSY line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
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Read from EPP Address Register (EPP Read Address cycle)
PCI CLK no (1st Transaction) 1 - Start of PCI Read from EPP Address register 4 - Start of EPP address read cycle on parallel port side. 8 - PCI transaction completes with a `retry' (without affecting current EPP read address cycle) as EPP cycle cannot complete within 16 PCI CLK cycles 8-9 - Peripheral Asserts BUSY in response to the host driving SLIN_N low. 12 - Host responds to BUSY by de-asserting SLIN_N (3 clock cycles after sampling BUSY) 15-16 - Peripheral Deasserts BUSY - EPP cycle completed. PCI CLK no (Retry Transaction) 1 - Start of Retry transaction, to the original read from EPP address register 5 - Retry transaction completes with "Data Transfer", without initiating another EPP read address cycle. Tslin (PCI clk to valid SLIN_N) - 22ns max* Tpd (PCI clk to valid Port Address) - 22ns max*
EPP Read Address Cycle duration is dependant upon the timing response of the peripheral's BUSY line and the parallel port filters. Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral's BUSY line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
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2 Consecutive Write Transactions to ECP DFIFO
PCI CLK no 1 6 9-10 10 11 14-15 17 18
- Start of 1st PCI write to ECP DFIFO register - Start of 1st ECP forward Transfer Cycle - 1st PCI transaction terminates with a "Data Transfer" - Peripheral Asserts BUSY in response to the host driving STB_N low - Start of 2nd PCI write to ECP DFIFO register. Current ECP forward transfer remains unaffected. - Host responds to BUSY by de-asserting STB_N (2 clock cycles after sampling BUSY) - 1st ECP forward transfer. - Peripheral Deasserts BUSY - End of 1st ECP forward transfer (2 clock cycles after sampling BUSY) Start of 2nd ECP forward Transfer Cycle - 22ns max* - 22ns max*
Tstb (PCI clk to valid STB_N) Tpd (PCI clk to valid port Address)
ECP Forward Transfer Cycle duration is dependant upon the timing response of the peripheral's BUSY line and the parallel port filters. Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral's BUSY line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
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PCI CLK no (Parallel Port already placed in the reverse ECP transfer mode) 2 - Start of 1st ECP reverse transfer by peripheral 2-3 - Peripheral asserts ACK_N low 6 - Host responds by asserting AFD_N (3 clock cycles after sampling ACK_N low) 10-11 - Peripheral deasserts ACK_N 13 - Host responds by de-asserting AFD_N (2 clock cycles after sampling ACK_N low) - End of ECP reverse transfer (data already transferred to ECP DFIFO) 24 26 - Start of PCI read from ECP DFIFO (does not initiate or affect any ECP reverse transfers that may be taking place) - Start of 2nd ECP reverse transfer by peripheral.
Tafd (PCI clk to AFD_N valid) : 22ns max* Tack-afd : 3 clock cycles (see below) + Tafd
ECP Reverse Transfer Cycle duration is dependant upon the timing response of the peripheral's ACK_N line and the parallel port filters.Example waveform has the parallel port filters disabled. An extra 2 PCI CLK cycles will be incurred in the response of the host to the peripheral's ACK_N line when the filters are enabled.
* These values are applicable to a pin loading of100pF.
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15 PACKAGE INFORMATION
15.1 160-Pin LQFP
Figure 11: 160-pin Low Profile Quad Flat Pack (LQFP) package
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15.2 176-Pin VBGA
Figure 12: 176-pin VFBGA package DS-0019 Jun 05 External--Free Release Page 118
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Figure 13: Custom marking on the 176-Pin VBGA package
16 ORDERING INFORMATION
OXMPCI954-LQ-A
Revision Package Type - 160 LQFP
OXMPCI954-LQ A G
Green (RoHS compliant) Revision Package Type - 160 LQFP
OXMPCI954-VB A G
Green (RoHS compliant) Revision Package Type - 176 VBGA
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NOTES
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CONTACT DETAILS
Oxford Semiconductor Ltd. 25 Milton Park Abingdon Oxfordshire OX14 4SH United Kingdom Telephone: Fax: Sales e-mail: Tech support e-mail: Web site: +44 (0)1235 824900 +44 (0)1235 821141 sales@oxsemi.com support@oxsemi.com http://www.oxsemi.com
DISCLAIMER
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