View NB4L858MFAG_1108072.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NB4L858M 2.5V/3.3V, 3 GHz Dual Differential Clock/Data 2x2 Crosspoint Switch with CML Output and Internal Termination
Description
http://onsemi.com MARKING DIAGRAM*
The NB4L858M is a high-bandwidth low voltage fully differential dual 2 x 2 crosspoint switch with CML outputs that is suitable for applications such as SDH/SONET DWDM and high speed switching applications. Design technique minimizes jitter accumulation, crosstalk, and signal skew which make this device ideal for loop-through and protection channel switching application. Each 2 x 2 crosspoint switch can fan out and/or multiplex up to 3 Gb/s data and 3 GHz clock signals. Differential inputs incorporate a pair of internal 50 W termination resistors in a center-tapped configuration (VTDx Pins) and can accept LVPECL (Positive ECL) or CML input signal without any external component. This feature provides transmission line termination on-chip, at the receiver end, eliminating external components. Differential 16 mA CML output provides matching internal 50 W terminations, and 400 mV output swings when externally terminated, 50 W to VCC. The SELECT inputs are single-ended and can be driven with either LVCMOS or LVTTL input levels. The device is housed in a low profile 7 x 7 mm 32-pin LQFP package.
Features
LQFP-32 FA SUFFIX CASE 873A
NB4L 858M AWLYYWW 32
A WL, L YY, Y WW, W G
1 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
SELA0 0 DA0 VTDA0 DA0 1 SELA1 0 DA1 VTDA1 DA1 1 SELB0 0 DB0 VTDB0 DB0 1 SELB1 0 DB1 VTDB1 DB1 1 50W 50W QB1 QB1 50W 50W B0 QB0 QB0 50W 50W A1 QA1 QA1 50W 50W A0 QA0 QA0
* * * * * * * * * *
Maximum Input Clock Frequency 3 GHz Maximum Input Data Frequency 3 Gb/s 350 ps Typical Propagation Delay 80 ps Typical Rise and Fall Times 12 ps Channel to Channel Skew 0.5 ps RMS Jitter 5 ps Deterministic Jitter @ 2.5 Gb/s Operating Range: VCC = 2.3V to 3.6 V with GND = 0 V CML Output Level (400 mV Peak-to-Peak Output), Differential Output These are Pb-Free Devices
B1
Figure 1. Functional Block Diagram ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2005
1
December, 2005 - Rev. 9
Publication Order Number: NB4L858M/D
NB4L858M
GND VCC QA0 QA0 VCC QA1 QA1 VCC
24 DA0 VTDA0 DA0 SELA1 DA1 VTDA1 DA1 SELA0 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 13 VCC QB1 QB1 VCC QB0 QB0 VCC GND
LQFP-32
12 11 10 9
2
3
4
5
6
7
8
DB1 VTDB1 DB1 SELB0 DB0 VTDB0 DB0 SELB1
Figure 1. Pin Configuration (Top View)
Table 1. TRUTH TABLE
SELA0/SELB0 L L H H SELA1/SELB1 L H L H QA0/QB0 DA0/DB0 DA0/DB0 DA1/DB1 DA1/DB1 QA1/QB1 DA0/DB0 DA1/DB1 DA0/DB0 DA1/DB1 Function 1:2 Fanout or Redundant Distribution Quad Repeater or Crosspoint Switch Quad Repeater or Crosspoint Switch 1:2 Fanout or Redundant Distribution
http://onsemi.com
2
NB4L858M
Table 2. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9,24 10, 13, 16, 17, 20, 23 11 12 14 15 18 19 21 22 25 26 27 28 29 30 31 32 Name DB1 VTDB1 DB1 SELB0 DB0 VTDB0 DB0 SELB1 GND VCC QB0 QB0 QB1 QB1 QA1 QA1 QA0 QA0 DA0 VTDA0 DA0 SELA1 DA1 VTDA1 DA1 SELA0 I/O LVPECL, CML Input - LVPECL, CML Input LVTTL / LVCMOS LVPECL, CML Input - LVPECL, CML Input LVTTL / LVCMOS - - CML Output CML Output CML Output CML Output CML Output CML Output CML Output CML Output LVPECL, CML Input - LVPECL, CML Input LVTTL LVPECL, CML Input - LVPECL, CML Input LVTTL Channel B1 positive signal input. Internal 100 W center-tapped termination pin for channel B1. Channel B1 negative signal input. Channel B0 Output Select. See Table 1. Channel B0 positive signal input. Internal 100 W center-tapped termination pin for channel B0. Channel B0 negative signal input. Channel B1 output select. See Table 1. Supply ground. All GND pins must be externally connected to power supply to guarantee proper operation. Positive Supply. All VCC pins must be externally connected to power supply to guarantee proper operation. Channel B0 negative signal output. Typically terminated with 50 W resistor to VCC. Channel B0 positive signal output. Typically terminated with 50 W resistor to VCC Channel B1 negative signal output. Typically terminated with 50 W resistor to VCC. Channel B1 positive signal output. Typically terminated with 50 W resistor to VCC. Channel A1 negative signal output. Typically terminated with 50 W resistor to VCC. Channel A1 positive signal output. Typically terminated with 50 W resistor to VCC. Channel A0 negative signal output. Typically terminated with 50 W resistor to VCC. Channel A0 positive signal output. Typically terminated with 50 W resistor to VCC. Channel A0 positive signal input. Internal 100 W center-tapped termination pin for channel A0. Channel A0 negative signal input. Channel A1 output select. See Table 1. Channel A1 positive signal input. Internal 100 W center-tapped termination pin for channel A1. Channel A1 negative signal input. Channel A0 output select. See Table 1. Description
http://onsemi.com
3
NB4L858M
Table 3. Table 3. ATTRIBUTES
Characteristics ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Human Body Model Machine Model 32-LQFP Oxygen Index: 28 to 34 Value > 2000 V >110 V Level 2 UL 94 V-0 @ 0.125 in 380
Table 4. MAXIMUM RATINGS
Symbol VCC VI VINPP IIN IOUT TA Tstg qJA qJC Tsol Parameter Positive Power Supply Positive Input Differential Input Voltage |D - D| Static Surge Continuous Surge LQFP-32 Condition 1 GND = 0 V GND = 0 V GND v VI v VCC Condition 2 Rating 3.8 3.8 3.8 45 80 25 80 -40 to +85 -65 to +150 0 LFPM 500 LFPM 2S2P (Note 2) <3 sec @ 260C 32 LQFP 32 LQFP 32 LQFP 80 55 12 to 17 265 Unit V V V mA mA mA mA C C C/W C/W C/W C
Input Current Through Internal RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 2. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power).
http://onsemi.com
4
NB4L858M
Table 5. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS VCC = 2.3 V to 3.6 V, GND = 0 V TA = -40C to +85C
Symbol ICC Voutdiff VOH VOL RTOUT VIH VIL VID RTIN Power Supply Current CML Differential Output Swing (Note 3) No Load Loaded 50 W to VCC Output HIGH Voltage (No Load) Output LOW Voltage (No Load) Output Source Resistance Qx or Qx Input HIGH Voltage Input LOW Voltage Differential Input Voltage (VIHD - VILD) Input Termination Resistance Dx or Dx to VTDx 640 VCC-40 VCC-1000 40 1600 1500 100 40 50 Characteristic Min Typ 130 800 400 VCC-10 VCC-800 50 Max 190 1000 VCC VCC-650 60 VCC VCC-100 1600 60 Unit mA mV mV mV W mV mV mV W
LVTTL CONTROL INPUT PINS VIH VIL IIH IIL Input HIGH Voltage (LVTTL Inputs) Input LOW Voltage (LVTTL Inputs) Input HIGH Current (LVTTL inputs) Input LOW Current (LVTTL Inputs) -10 -10 2000 800 10 10 mV mV mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. CML outputs require 50 W receiver termination resistors to VCC for proper operation.
http://onsemi.com
5
NB4L858M
Table 6. AC CHARACTERISTICS VCC = 2.3 V to 3.6 V, GND = 0 V; (Note 4)
-40C Symbol VOUTPP Characteristic Output Voltage Amplitude (@ VINPPmin) fin 2 GHz (See Figure 2) fin 3 GHz fin 3.5GHz Maximum Operating Data Rate Propagation Delay to Output Differential D/D to Q/Q SELyx to Valid Qyx Output (Note 9) Within -Device Skew (Note 5) Within -Device Skew (Note 6) Device to Device Skew (Note 9) fin =2 GHz fin =3 GHz Peak-to-Peak Data Dependent Jitter fin =2.5Gb/s (Note 9) fin =3.2Gb/s Crosstalk Induced RMS Jitter (Note 11) Input Voltage Swing/Sensitivity (Differential Configuration) Output Rise/Fall Times @ 0.5 GHz (20% - 80%) Qx, Qx 100 80 RMS Random Clock Jitter (Note 8) Min 280 235 170 3 220 350 0.5 12 25 100 0.5 1.0 2.0 10 0.5 800 120 100 80 450 1.0 Typ 365 310 220 Max Min 280 235 170 3 220 350 0.5 12 25 100 0.5 1.0 5.0 10 0.5 800 120 100 80 450 1.0 25C Typ 365 310 220 Max Min 280 235 170 3 220 350 0.5 12 25 100 0.5 1.0 2.0 10 0.5 800 120 450 1.0 ns ps 85C Typ 365 310 220 Gb/s ps Max Unit mV
fDATA tPLH, tPHL tSWiITCH tSKEW
tJITTER
ps
VINPP tr tf
mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% - 80%). 5. Worst-case difference between QA0 and QA1 from either DA0 or DA1 (or between QB0 and QB1 from either DB0 or DB1 respectively), when both outputs come from the same input. 6. Worst-case difference between QA and QB outputs, when DA or DB inputs are shorted. 7. Additive RMS jitter with 50% duty cycle input clock signal. 8. Additive peak-to-peak data dependent jitter with input NRZ data signal. 9. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 10. LVTTL/LVCMOS input edge rate less than 1.5 ns 11. Data taken on the same device under identical condition. 400 350 85C 300 VOLTAGE (mV) 25C 250 200 150 100 50 0 1 1.5 2 2.5 3 3.5 INPUT CLOCK FREQUENCY (GHz) -40C
Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fin) and Temperature
http://onsemi.com
6
NB4L858M
Dx VINPP = VIH(DX) - VIL(DX) Dx Qx VOUTPP = VOH(QX) - VOL(QX) Qx tPHL tPLH
Figure 3. AC Reference Measurement
VCC
50 W Q Driver Device Q Zo = 50 W Zo = 50 W
50 W D Receiver Device D
Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8057/D)
VCC
VCC
VTDX 50 W 50 W RC RC 50 W 50 W QX DX QX
DX
16 mA
GND Input
GND Output
Figure 5. CML Input and Output Structure
http://onsemi.com
7
NB4L858M
640 mV MIN QX 320 mV MIN QX (QX - QX)
QX
1000 mV MAX 500 mV MAX
QX (QX - QX)
Figure 6. CML Output Levels
ORDERING INFORMATION
Device NB4L858MFAG NB4L858MFAR2G Package LQFP-32 (Pb-Free) LQFP-32 (Pb-Free) Shipping 250 Units / Tray 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
http://onsemi.com
8
NB4L858M
PACKAGE DIMENSIONS
LQFP FA SUFFIX 32-LEAD PLASTIC PACKAGE CASE 873A-02 ISSUE B
A
32 4X 25
A1
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V DETAIL Y
17
AE P AE DETAIL Y
V1
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB- 0.10 (0.004) AC
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
D
8X
M_ R
J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
CE
SECTION AE-AE
X DETAIL AD
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
http://onsemi.com
9
0.20 (0.008)
M
AC T-U Z
-T-, -U-, -Z-
EE EE EE
NB4L858M
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
http://onsemi.com
10
NB4L858M/D

▲Up To Search▲

Price & Availability of NB4L858MFAG

	To Download NB4L858MFAG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .