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T6C84
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
T6C84
COLUMN AND ROW DRIVER LSI FOR A DOT MATRIX GRAPHIC LCD
The T6C84 is a driver for a small-to-medium-sized dot matrix graphic LCD. It includes the functions of the T9841B (column driver) and the T9842B (row driver). It has an 8-bit interface circuit and a serial interface circuit. It generates all the timing signals for the display using an on-chip oscillator. It receives 8-bit data from an MPU, latches the data to an on-chip RAM, and displays the image on the LCD (the data in the display RAM correspond to the dots on the display). The device has 136 column driver outputs and 34 row driver outputs enabling it to drive a 136-dot by 34-dot LCD. In addition, there are resistors to divide the bias voltage, a power supply op-amp, DC-DC converter (doubler, tripler, quadruplexer) and contrast control circuit enabling the LCD to be driven by a single power supply.
Features
l On-chip display RAM capacity: 136 x 34 = 4624 bits l Display RAM data (1) Display data = 1........ LCD turns on. (2) Display data = 0........ LCD turns off. l 1/34 duty cycle l Word length of display data can be switched between 8-bit/word and 6-bit/word according to the character font. l LCD driver outputs: 136 column driver outputs and 34 row driver outputs l 8-bit (68/80-series) parallel ot serial interface l On-chip oscillator with one external resistor l Low power consumption l On-chip resistors to divide bias voltage, on-chip operational amplifier for LCD supply, on-chip DC-DC converter, on-chip contrast control circuit l CMOS process l Operating voltage: 2.7 V to 5.5 V l Operating voltage for LCD drive signal: The following condition must be maintained: VDD - VEE1 16.0 V, VDD - VEE2 16.0 V, VEE1 VEE2 l Package: TCP (Tape Carrier Package)
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Block Diagram
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Pin Assignment
Note: The above diagram shows the pin configuration of the LSI Chip; it does not show the configuration of the tape carrier package.
Pin Functions
Pin Name SEG1 to SEG136 COM1 to COM34 DB0 to DB7 I/O Output Output I/O Column driver output Row driver output Data bus Input for parallel interface / serial interface select signal P / S = H Parallel interface is selected. SI and SCK must be connected to VDD or VSS. P / S = L Serial interface is selected. DB0 to DB7 must be open. / WR and / RD must be connected to VDD or VSS. Functions
P/S
Input
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Pin Name 68 / 80 / CS1, CS2 I/O Input Input Functions Input for 68-Series MPU / 80-Series MPU select signal 68 / 80 = H 68-Series MPU is selected. 68 / 80 = L 80-Series MPU is selected. Input for chip select signal / CS1 = L and CS2 = H Selection state Input for data / instruction select signal D / I = H indicates that the data on DB0 to DB7 or SI is display data. D / I = L Indicates that the data on DB0 to DB7 or SI is instruction data. Input for write enable signal (input for read / write select signal) When 80-Series MPU is selected, data on DB0 to DB7 is latched on the rising edge of / WR. When 68-Series MPU is selected, this pin is used to indicate whether read operation or write operation is performed. Input for read enable signal (input for enable signal) When 80-Series MPU is selected, data appears on DB0 to DB7 while / RD = L. When 68-Series MPU is selected, this pin is used for input enable signal. Input for serial data Input for serial clock Input for reset signal / RST = L Reset state Input for standby signal Usually connected to VDD / STB = L T6C84 is in standby state and cannot accept any commands or data. Column driver signal and row driver signal are at the VDD level. When using the internal clock oscillator, connect a resistor between OSC1 and OSC2. When using an external clock, connect the clock to OSC1 and leave OSC2 open. Inputs for frequency selection FS1 FS1, FS2 Input 0 0 1 1 FS2 0 1 0 1 fOSC (kHz) 28.56 57.12 228.48 456.96 fCOM (Hz) 35 35 35 35
D/I
Input
/ WR (R / W)
Input
/ RD (E) SI SCK / RST
Input Input Input Input
/ STB
Input
OSC1, OSC2
PS H L
68 / 80 L H L/H
Interface Type 80-Series MPU 68-Series MPU Serial interface
/ CS1 / CS1 / CS1 / CS1
CS2 CS2 CS2 CS2
D/I D/I D/I D/I
/ WR / WR R/W L/H
/ RD / RD E L/H
SI L/H L/H SI
SCK L/H L/H SCK
DB0 to DB7 DB0 to DB7 DB0 to DB7 Open
Note:
"H" denotes the VDD level; "L" denotes the VSS level.
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Pin Name R1, R2 C1A, C1B VOUT1 C2A, C2B VOUT2 C3A, C3B VOUT3 VEE1, VEE2 VLC1 to VLC5 VDD, VSS I/O Input Connect with external resistor. Connect using a capacitor for doubler. DC-DC converter output (x2 Level) Connect using a capacitor for tripler. DC-DC converter output (x3 Level) Connect using a capacitor for quadruplexer. DC-DC converter output (x4 Level) Power supply for LCD driver circuit When using on-chip DC-DC converter, connect VEE1 and VEE2 to VOUT. Power supply for LCD driver circuit Power supply for logic circuit. Reference: Ground Functions
Function of Each Block
Interface logic
The T6C84 can be operated with an 80-Series MPU, a 68-Series MPU or a serial interface. Fig. 1 shows an example of the interface.
Fig. 1
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Input register
This register stores 8-bit data from the MPU. The D/I signal distinguishes between command data and display data.
Output register
This register stores 8-bit data from the display RAM. When display data is read, the display data specified by the address in the address counter is stored in this register. After that, the address is automatically incremented or decremented. Therefore, when an address is set, the correct data does not appear as the first data item that is read. The data in the specified address location appears as the second data item that is read.
X-address counter
The X-address counter is a 34-up/down counter. It holds the row address of a location in the display RAM. Writing data to or reading data from the display RAM causes the X-address to be automatically incremented or decremented.
Y- (page) address counter
The Y- (page) address counter is a 17-up/down counter, when the word length is eight bits, or a 23-up/down counter, when the word length is six bits. It holds the column address of a location in the display RAM. Writing data to or reading data from the display RAM causes the Y-address to be automatically incremented or decremented.
Z-address counter
The Z-address counter is a 34-up counter that provides the display RAM data for the LCD drive circuit. The data stored in the Z-address register is sent to the Z-address counter as the Z start address. For instance, when the Z start address is 16, the counter increments like this: 16, 17, 18***, 32, 33, 0, 1, 2***14, 15, 16. Therefore, the display start line is line 16 of the display RAM.
Up / down register
The 1-bit datum stored in this register selects either up or down mode for the X-and Y- (page) address counters.
Counter select register
The 1-bit datum stored in this register selects the X-address counter or Y- (page) address counter.
Display ON/OFF register
This 1-bit register holds the display ON/OFF state. In the OFF state, the output data from the display RAM is cleared. In the ON state, the display RAM data is displayed. The display ON/OFF state does not affect the data in the display RAM.
Z-address register
This 6-bit Hregister holds the data which specifies the display start line.
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Word length register
The 1-bit datum stored in this register selects the word length: eight bits per word or six bits per word.
Word length change circuit
This circuit is controlled by the word length register. When the word length is eight bits, data is transferred eight bits at a time. When the word length is six bits, the data transfer method is as shown in Fig. 2 below.
Fig. 2
Oscillator
The T6C84 includes an on-chip oscillator. When using this oscillator, connect an external resistor between OSC1 and OSC2 as shown in Fig. 3. When using an external clock, connect the clock input to OSC1 and leave OSC2 open.
Fig. 3
Timing generation circuit
This circuit divides the signals from the oscillator and generates the display timing signals and the operating clock signal.
Shift register
The T6C84 has two 17-bit shift register. These two 17-bit shift registers can be combined to form a 34-bit shift register.
Latch circuit
The latch circuit latches data from the display RAM.
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Column driver circuit
The column driver circuit consists of 136 driver circuits. One of the four LCD driving levels is selected by the combination of the internal M signal and the display data transferred from the latch circuit. Details of the column driver circuit are shown in Fig. 4.
Fig. 4
Row driver circuit
The row driver circuit consists of 34 driver circuits. One of the four LCD driving levels is selected by the combination of the internal M signal and the data from the shift register. Details of the row driver circuit are shown in Fig. 5.
Fig. 5
DC-DC converter
The T6C84 has an on-chip DC-DC converter. The DC-DC converter generates a x2, x3 or x4 output level. See Fig. 6. When/STB = L, VOUT1, VOUT2 and VOUT3 = 0 (V). The recommended value for the capacitor is 2.2 F.
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(1) Doubler (x2) mode
Fig. 6-1
(2) Tripler (x3) mode
Fig. 6-2
(3) Quadruplexer (x4) mode
Fig. 6-3
When using an external power supply, input the voltage to VEE1 and VEE2 and do not connect the capacitors.
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Voltage divider resistors, contrast control circuit
The T6C84 has on-chip resistors which include op-amps, that divide the bias voltage, and a contrast control circuit. The voltage bias is modified by the value of the external resistor between R1 and R2. These resistors and the contrast control circuit are shown in Fig. 7 below.
Fig. 7
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Op-amp, op-amp control register
The T6C84 has five operational amplifiers which determine the LCD driving levels. The power supplied by these op-amps is modified by the contents of the op-amp control register to match the LCD panel. The op-amp can also be controlled in such a way that it supplies full current on the rising edge of SEG and a reduced current otherwise. To maintain good LCD contrast, connect a capacitor between the op-amp output and VDD. The value of the capacitor should normally be in the range 0.1 to 1.0 F.
Display RAM
The display RAM consists of 34 rows x 136 columns for a total of 4624 cells. It is directly bit-mapped to the LCD. The relation between the display RAM and LCD is shown in Fig. 8. When the word length is set to eight bits, the display RAM is arranged in 17 pages and each page contains 34 words. When the word length is set to six bits, the display RAM is arranged in 23 pages and each page contains 34 words. See Fig. 9.
Fig. 8
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(1) 8-bits-per-word mode
(2) 6-bits-per-word mode
Fig. 9 Command Definitions
Command Name DPE 86E UDE CHE OPA1 OPA2 SYE SZE SXE SCE STRD DAWR DARD D / I / WR / RD 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 DB7 0 0 0 0 0 0 0 0 1 1 B DB6 0 0 0 0 0 0 0 1 0 1 8/6 DB5 0 0 0 0 0 0 1 DB4 0 0 0 1 1 0 DB3 0 0 0 1 0 1 DB2 0 0 1 * * * DB1 1 0 1/0 * 1/0 1/0 DB0 Function
1 / 0 Display ON (1) / OFF (0) 1 / 0 Word Length: 8 bits (1) / 6 bits (0) 1/0 * Counter Select: DB1 Y (1) / X (0) Mode Select: DB0 UP (1) / DOWN (0) Test Mode Select
1 / 0 Op-Amp Power Control 1 1 / 0 Op-Amp Power Control 2 Y- (Page) Address Set Z-Address Set X-Address Set Contrast Set
Y-Address (0 to 22) Z-Address (0 to 33) X-Address (0 to 33)
CONTRAST CONTROL (0 to 63) D R 0 0
Y / X U / D Status Read Display Data Write Display Data Read
Write Data Read Data
*: INVALID
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Display ON/OFF select (DPE)
D/I 0 0 / WR 0 0 / RD 1 1 DB7 0 0 DB6 0 0 DB5 0 0 DB4 0 0 DB3 0 0 DB2 0 0 DB1 1 1 DB0 1 0 Display ON (03H) Display OFF (02H)
This command turns display ON / OFF. It does not affect the data in the display RAM. When the "Display OFF" command is input, VLC1 to VLC5 are all set to VDD. Note: An L input on / RST turns display OFF.
Word length 8 bits/6 bits select (86E)
D/I 0 0 / WR 0 0 / RD 1 1 DB7 0 0 DB6 0 0 DB5 0 0 DB4 0 0 DB3 0 0 DB2 0 0 DB1 0 0 DB0 1 0 8-bit word mode (01H) 6-bit word mode (00H)
This command sets the word length for display RAM data to either six bits or eight bits Note: An L input on / RST sets the word length to eight bits per word.
X / Y (page) counter, up/down mode select (UDE)
D/I 0 0 0 0 / WR 0 0 0 0 / RD 1 1 1 1 DB7 0 0 0 0 DB6 0 0 0 0 DB5 0 0 0 0 DB4 0 0 0 0 DB3 0 0 0 0 DB2 1 1 1 1 DB1 0 0 1 1 DB0 0 1 0 1 X-Counter / Down Mode (04H) X-Counter / Up Mode (05H)
Y-Counter / Down Mode (06H) Y-Counter / Up Mode (07H)
This command selects the counter and the up/down mode. For instance, when X-counter/up mode is selected, the X-address is incremented in response to every data read and write. However, when X-Counter/up mode is selected, the address in the Y- (page) counter will not change. Hence the Y-address must be set (with the SYE command) before it can be changed. Note: An L input on/RST sets the Y-counter to up mode.
Test mode select (CHE)
D/I 0 / WR 0 / RD 1 DB7 0 DB6 0 DB5 0 DB4 1 DB3 1 DB2 * DB1 * DB0 * *: INVALID
This command selects the test mode. Do not use this command.
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Set Y- (page) address (SYE)
D/I 0 / WR 0 / RD 1 DB7 0 DB6 0 DB5 1 DB4 A DB3 A DB2 A DB1 A DB0 A
Range: 8-bit/Word: 20H to 30H (Page 0 to Page 16) 6-bit/Word: 20H to 36H (Page 0 to Page 22) When operating in 8-bits-per-word mode, this command selects one of the 17 pages in the display RAM. Do not try to select a page outside this range. When operating in 6-bits-per-word mode, this command selects one of the 23 pages in the display RAM. Note: An L input on / RST sets the Y-address to page 0.
Set Z-address (SZE)
D/I 0 / WR 0 / RD 1 DB7 0 DB6 1 DB5 A DB4 A DB3 A DB2 A DB1 A DB0 A
Range: 40H to 61H (ZAD0 to ZAD33) This command sets the top row of the LCD screen, irrespective of the current X-address. For instance, when the Z-address is 16, the top row of the LCD screen is address 16 of the display RAM, and the bottom row of the LCD screen is address 15 of the display RAM. Note: An L input on/RST sets the Z-address to 0.
Set X-address (SXE)
D/I 0 / WR 0 / RD 1 DB7 1 DB6 0 DB5 A DB4 A DB3 A DB2 A DB1 A DB0 A
Range: 80H to A1H (XAD0 to XAD33) This command sets the X-address (in the range 0 to 33). An L input on / RST sets the X-address to 0.
Set Contrast (SCE)
D/I 0 / WR 0 / RD 1 DB7 1 DB6 1 DB5 A DB4 A DB3 A DB2 A DB1 A DB0 A
Range: C0H to FFH This command sets the contrast for the LCD. The LCD contrast can be set in 64 steps. The command C0H selects the brightest level; the command FFH selects the darkest.
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Op-amp control 1 (OPA1)
D/I 0 / WR 0 / RD 1 DB7 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 * DB1 A DB0 A *: INVALID
Range: 10H to 13H (when DB2 = 0) This command sets the power supply strength for the operational amplifier. This command selects one of four levels. The command 10H selects the lowest power supply strength and the command 13H selects the maximum power supply strength. Note: An L input to / RST sets the op-amp power supply strength to the lowest level.
Op-amp control 2 (OPA2)
D/I 0 / WR 0 / RD 1 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 * DB1 A DB0 A *: INVALID
Range: 08H to 0BH (when DB2 = 0) This command enhances the power supply strength of the operational amplifier over a short period from the rising edge of SEG. This command selects one of four levels of strength. Note: An L input to / RST sets t to 0 for the op-amp. It is not possible to select the combination OPA1 = 10H and OPA2 = 08H. After a Reset, set OPA1 and OPA2 according to the application.
Fig. 10
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Status read (STRD)
D/I 0 / WR 1 / RD 0 DB7 B DB6 8/6 DB5 D DB4 R DB3 0 DB2 0 DB1 Y/X DB0 U/D
B (Busy)
: When B = 1 the T6C84 is executing an internal operation and no instruction can be accepted except STRD. When B = 0 the T6C84 can accept an instruction.
8 / 6 (Word Length) : When 8 / 6 = 1 the word length of the display data is eight bits per word. When 8 / 6 = 0 the word length of the display data is six bits per word. D (Display) : When D = 1 display is ON. When D = 0 display is OFF. : When R = 1 the T6C84 is in reset state. When R = 0 the T6C84 is in operating state. : When Y / X = 1 the Y counter is selected. When Y / X = 0 the X counter is selected.
R (Reset)
Y / X (Counter)
U / D (Up / down) : When U / D = 1 the X and Y counters are in up mode. When U / D = 0 the X and Y counters are in down mode.
Write / read display data (DAWR / DARD)
D/I 1 1 / WR 0 1 / RD 1 0 DB7 D D DB6 D D DB5 D D DB4 D D DB3 D D DB2 D D DB1 D D DB0 D D DAWR: Display Data Write DARR: Display Data Read
The command DAWR writes the display data to the display RAM. The command DARD outputs the display data from the display RAM. However, when a data read is executed, the correct data does not appear on the first data reading. Therefore, ensure that the T6C84 performs a dummy data read before reading the actual data.
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Function Description
X-address counter and Y- (page) address counter
Fig. 11 shows a sample operation involving the X-address counter. After Reset is executed, the X-address (XAD) becomes 0, then X-counter/up mode is selected. Next, the X-address is set to 32 using the SXE command. After data has been written or read, the X-address is automatically incremented by 1. After X-counter / down mode has been selected and data has been written or read, the X-address is automatically decremented by 1. When the X-counter is selected, the Y-counter is not incremented or decremented.
Fig. 11
Fig. 12 shows a sample operation involving for the Y-address counter in 8-bit word length mode. After Reset is executed, the Y- (page) address (Page) becomes 0, then Y- (page) counter/up mode and 8-bit word length mode are selected. After data has been written or read, the Y- (page) address counter is automatically incremented by 1. After Y- (page) counter/down mode has been selected and data has been written or read, the Y- (page) address is automatically decremented by 1. When the Y- (page) counter is selected, the X-counter is not incremented or decremented.
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Fig. 12
When operating in 6-bits word length mode, the Y- (page) address counter can count up to 22. If Page = 22 in up mode, after data has been written or read, the Y- (page) address (Page) becomes 0. If Page = 0 in down mode, after data has been written or read, the Y- (page) address (Page) becomes 22.
Data read
When reading data, there are some cases when dummy data must be read. This is because when the data read command is invoked, the data pointed to by the address counter is transferred to the output register; the contents of the output register are then transferred by the next data read command. Therefore when reading data straight after power-on or straight after an address-setting command, such as SYE or SXE, a dummy data read must be performed. See Fig. 13.
Fig. 13
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Reset function
When/RST = L, the reset function is executed and the following settings are made. (1) Display **************************** OFF (2) Word length ********************* 8 bits / word (3) Counter mode ***************** Y-counter / up mode (4) Y- (page) address ************ Page = 0 (5) X-address ************************ XAD = 0 (6) Z-address ************************ ZAD = 0 (7) OPA1 ******************************* min (8) OPA2 ******************************* min
Standby function
When/STB = L, the T6C84 is in standby state. The internal oscillator is stopped, power consumption is reduced, and the power supply level for the LCD (VLC1 to VLC5) becomes VDD.
Busy flag
When the T6C84 is executing an internal operation (other than the STRD command), the busy flag is set to logical H. The state of the busy flag is output in response to the STRD command. While the busy flag is H, no instruction can be accepted (except the STRD command). The busy state period (T) is as follows. 2/fOSC T 4 / fOSC [seconds] fOSC: Frequency of OSC1
Oscillation frequency
The frequency select pins (FS1 and FS2) are used to set the relation between the oscillation frequency (fOSC) and the frequency of the internal M signal (fM), as shown in the table below.
Rf (k) 1100 530 140 70 fOSC (kHz) 28.56 57.12 228.48 456.96 fM (Hz) 35 35 35 35 FS1 0 1 0 1 FS2 0 0 1 1
Note: The resistance values are typical values. The oscillation frequency depends on how the device is mounted. It is necessary to adjust the oscillation frequency to a target value.
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LCD Driver Waveform
Absolute Maximum Ratings (Ta = 25C)
Item Supply Voltage (1) Supply Voltage (2) Input Voltage Operating Temperature Storage Temperature Symbol VDD (Note 1) VLC1, 2, 3, 4, 5 VEE1, VEE2 (Note 3) VIN (Note 1, 2) Topr Tstg Rating -0.3 to 7.0 VDD - 18.0 to VDD + 0.3 -0.3 to VDD + 0.3 -20 to 75 -55 to 125 Unit V V V C C
Note1: Referenced to VSS = 0 V Note2: Applies to all data bus pins and input pins except VEE1, VEE2, VLC1, VLC2, VLC3, VLC4 and VLC5. Note3: Ensure that the following condition is always maintained. VDD VLC1 VLC2 VLC3 VLC4 VLC5 VEE2 VEE1
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Electrical Characteristics DC Characteristics Test Conditions (1)
Item Operating Supply (1) Operating Supply (2) H Level Input Voltage L Level
(Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V 10, VLC5 = 0 V, Ta = -20 to 75C)
Symbol VDD VLC5 VEE1, 2 VIH VIL VOH VOL Rcol Test Circuit Test Condition Min 2.7 VDD - 16.0 0.8 VDD 0 VDD - 0.2 0 Typ. Max 3.3 VDD - 4.0 VDD 0.2VDD VDD 0.2 Unit V V V V VDD VLC5, VEE1, VEE2 DB0 to DB7, D / I, / WR, / RD, / CS1, CS2, / RST, / STB, FS1, FS2, SI, SCK, P / S, 68 / 80 DB0 to DB7 Pin Name
Output Voltage
H Level L Level

IOH =-400 A IOL = 400 A VDD - VLC5 = 11.0 V Load current = 100 A VDD - VLC5 = 11.0 V Load current = 100 A

V V
Column Driver Output Resistance
7.5
k
SEG1 to SEG136
Row Driver Output Resistance
Rrow
1.5
k
COM1 to COM34
Input Leakage
IIL
VIN = VDD to GND
-1
1
A
DB0 to DB7, D / I, / WR, / RD, / CS1, CS2, / RST, / STB, FS1, FS2, SI, SCK, P / S, 68 / 80 OSC1 OSC1 OSC1 OSC1 VDD VDD VDD VOUT2 VOUT3
Operating Freq. External Clock Freq. External Clock Duty External Clock Rise / Fall Time Current Consumption (1) Current Consumption (2) Current Consumption (3) Output Voltage (Tripler Mode) Output Voltage (Quadruplexer Mode)
fOSC fex fduty t r / tf IDD1 IDD2 IDDSTB VO2 VO3
2 3
(Note 1) (Note 2) (Note 3) (Note 4) (Note 5)
20 20 45 -1 -4.50 -6.75
50 300 400 -4.90 -7.50
500 500 55 50 420 530 1
kHz kHz % ns A A A V V
Note 1: VDD = 3.0 10%, VEE1, 2 = VOUT2 (tripler mode), no data access Rf = 62 k, no load, 1/7 bias, FS1, 2 = H, OPA1 = 10H, OPA2 = 09H Note 2: VDD = 3.0 10%, VEE1, 2 = VOUT2 (tripler mode), data access cycle f / CE = 1 MHz, Rf = 62 k, no load, 1/7 bias, FS1, 2 = H, OPA1 = 10H, OPA2 = 09H Note 3: VDD = 3.0 10%, VDD - VEE1, 2 = 16.0 V, / STB = L Note 4: VDD = 3.0 V, ILoad = 500 A, VEE1, 2 = - 6.0 V (external power supply) CnA - CnB = 2.2 F, VDD - VOUT2 = 2.2 F, Rf = 62 k, Ta = 25C Note 5: VDD = 3.0 V, ILoad = 500 A, VEE1, 2 = - 9.0 V (external power supply) CnA - CnB = 2.2 F, VDD - VOUT3 = 2.2 F, Rf = 62 k, Ta = 25C
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Test Conditions (2)
Item Operating Supply (1) Operating Supply (2) H Level Input Voltage L Level H Level Output Voltage L Level Column Driver Output Resistance VOL IOL = 400 A VDD - VLC5 = 11.0 V Load current = 100 A VDD - VLC5 = 11.0 V Load current = 100 A VIL VOH IOH = - 400 A 0 VDD - 0.2 0 0.3VDD VDD 0.2 V V DB0 to DB7 V
(Unless Otherwise Noted, VSS = 0 V, VDD = 5.0 V 10%, VLC5 = 0 V, Ta = -20 to 75C)
Symbol VDD VLC5 VEE1, 2 VIH Test Circuit Test Condition Min 4.7 VDD - 16.0 0.7 VDD Typ. Max 5.5 VDD - 4.0 VDD Unit V V V VDD VLC5, VEE1, VEE2 DB0 to DB7, D / I, / WR, / RD, / CS1, CS2, / RST, / STB, FS1, FS2, SI, SCK, P / S, 68 / 80 Pin Name
Rcol
7.5
k
SEG1 to SEG136
Row Driver Output Resistance
Rrow
1.5
k
COM1 to COM34
Input Leakage
IIL
VIN = VDD to GND
-1
1
A
DB0 to DB7, D / I, / WR, / RD, / CS1, CS2, / RST, / STB, FS1, FS2, SI, SCK, P / S, 68 / 80 OSC1 OSC1 OSC1 OSC1 VDD VDD VDD VOUT1 VOUT2
Operating Freq. External Clock Freq. External Clock Duty External Clock Rise / Fall Time Current Consumption (1) Current Consumption (2) Current Consumption (3) Output Voltage (Doubler Mode) Output Voltage (Tripler Mode)
fOSC fex fduty t r / tf IDD1 IDD2 IDDSTB VO1 VO2
1 2
(Note 1) (Note 2) (Note 3) (Note 4) (Note 5)
20 20 45 -1 -4.25 -8.50
50 510 620 -4.50 -9.00
500 500 55 50 640 830 1
kHz kHz % ns A A A V V
Note 1: VDD = 5.0 10%, VEE1, 2 = VOUT1 (doubler mode), no data access Rf = 62 k, no Load, 1/7 bias, FS1, 2 = H, OPA1 = 10H, OPA2 = 09H Note 2: VDD = 5.0 10%, VEE1, 2 = VOUT2 (doubler mode), data access cycle f / CE = 1 MHz, Rf = 62 k, no load, 1/7 bias, FS1, 2 = H, OPA1 = 10H, OPA2 = 09H Note 3: VDD = 5.0 10%, VDD - VEE1, 2 = 16 V, / STB = L Note 4: VDD = 5.0 V, ILoad = 500 A, VEE1, 2 = - 5.0 V (external power supply) CnA - CnB = 2.2 F, VDD - VOUT1 = 2.2 F, Rf = 62 k, Ta = 25C Note 5: VDD = 5.0 V, ILoad = 500 A, VEE1, 2 = - 10.0 V (external power supply) CnA - CnB = 2.2 F, VDD - VOUT2 = 2.2 F, Rf = 62 k, Ta = 25C
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T6C84
Test Circuit
1. Doubler mode
2. Tripler mode
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T6C84
3. Quadruplexer mode
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T6C84
AC Characteristics
80-Series MPU 8-bit interface
Test Conditions (1) (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V 10%, VLC5 = 0 V,
Ta = -20 to 75C)
Item Enable Cycle Time Enable Pulse Width Enable Rise / Fall Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Data Delay Time Data Hold Time Symbol tcycE PWEL tEr, tEf tAS tAH tDS tDHW tDD (Note) tDHR (Note) Min 1000 450 100 0 280 20 20 Max 25 350 Unit ns ns ns ns ns ns ns ns ns
Load Circuit
Test Conditions (2) (Unless Otherwise Noted, VSS = 0 V, VDD = 5.0 V 10%, VLC5 = 0 V,
Ta = -20 to 75C)
Item Enable Cycle Time Enable Pulse Width Enable Rise / Fall Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Data Delay Time Data Hold Time Symbol tcycE PWEL tEr, tEf tAS tAH tDS tDHW tDD (Note) tDHR (Note) Min 500 220 60 0 60 10 20 Max 20 160 Unit ns ns ns ns ns ns ns ns ns
Note: With load circuit connected
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T6C84
68-Series MPU 8-bit interface
Test Conditions (1) (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V 10%, VLC5 = 0 V,
Ta = -20 to 75C)
Item Enable Cycle Time Enable Pulse Width Enable Rise / Fall Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Data Delay Time Data Hold Time Symbol tcycE PWEL tEr, tEf tAS tAH tDS tDHW tDD (Note) tDHR (Note) Min 1000 450 100 0 280 20 20 Max 25 350 Unit ns ns ns ns ns ns ns ns ns
Load Circuit
Test Conditions (2) (Unless Otherwise Noted, VSS = 0 V, VDD = 5.0 V 10%, VLC5 = 0 V,
Ta = -20 to 75C)
Item Enable Cycle Time Enable Pulse Width Enable Rise / Fall Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Data Delay Time Data Hold Time Symbol tcycE PWEL tEr, tEf tAS tAH tDS tDHW tDD (Note) tDHR (Note) Min 500 220 60 0 60 10 20 Max 20 160 Unit ns ns ns ns ns ns ns ns ns
Note: With load circuit connected
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T6C84
Serial interface
Test Conditions (1) (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V 10%, VLC5 = 0 V,
Ta = -20 to 75C)
Item Clock Cycle Time Clock Pulse Width Clock Rise / Fall Time CS Set-up Time CS Hold Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Symbol tcycC PWCL, PWCH tCr, tCf tCSS tCSH tAS tAH tDS tDH Min 1000 450 120 800 250 400 250 100 Max 25 Unit ns ns ns ns ns ns ns ns ns
Test Conditions (2) (Unless Otherwise Noted, VSS = 0 V, VDD = 5.0 V 10%, VLC5 = 0 V,
Ta = -20 to 75C)
Item Clock Cycle Time Clock Pulse Width Clock Rise / Fall Time CS Set-up Time CS Hold Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Symbol tcycC PWCL, PWCH tCr, tCf tCSS tCSH tAS tAH tDS tDH Min 500 220 60 400 120 200 120 50 Max 20 Unit ns ns ns ns ns ns ns ns ns
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T6C84
Application Circuit
Oscillation frequency is at a minimum. LCD drive bias is 1/7. DC-DC converter (in doubler mode) is used. 80-Series MPU is used.
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T6C84
RESTRICTIONS ON PRODUCT USE
000707EBE
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. * Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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