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Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
FEATURES
* 'Trench' technology * Low on-state resistance * Fast switching * Logic level compatible
g
PHP21N06LT, PHB21N06LT PHD21N06LT
QUICK REFERENCE DATA
d
SYMBOL
VDSS = 55 V ID = 19 A RDS(ON) 75 m (VGS = 5 V) RDS(ON) 70 m (VGS = 10 V)
s
GENERAL DESCRIPTION
N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using 'trench' technology. Applications:* d.c. to d.c. converters * switched mode power supplies The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB21N06LT is supplied in the SOT404 (D2PAK) surface mounting package. The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package.
PINNING
PIN 1 2 3 tab DESCRIPTION gate drain 1 source
SOT78 (TO220AB)
tab
SOT404 (D2PAK)
tab
SOT428 (DPAK)
tab
2
1 23
2
1
3
1
3
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tj 150C Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 15 20 19 13 76 56 175 UNIT V V V V A A A W C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages. August 1999 1 Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
AVALANCHE ENERGY LIMITING VALUES
PHP21N06LT, PHB21N06LT PHD21N06LT
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Peak non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 9.7 A; tp = 100 s; Tj prior to avalanche = 25C; VDD 25 V; RGS = 50 ; VGS = 5 V; refer to fig:15 MIN. MAX. 34 UNIT mJ
IAS
-
19
A
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. SOT78 package, in free air SOT428 and SOT404 package, pcb mounted, minimum footprint 60 50 MAX. 2.7 UNIT K/W K/W K/W
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VGS = 10 V; ID = 10 A VGS = 5 V; ID = 10 A Tj = 175C Forward transconductance VDS = 25 V; ID = 10 A Gate source leakage current VGS = 5 V; VDS = 0 V Zero gate voltage drain VDS = 55 V; VGS = 0 V; current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 20 A; VDD = 44 V; VGS = 5 V MIN. 55 50 1.0 0.5 5 TYP. MAX. UNIT 1.5 55 60 13 10 0.05 9.4 2.2 5.4 7 88 25 25 3.5 4.5 7.5 466 95 71 2.0 2.3 70 75 158 100 10 500 15 120 40 45 650 135 85 V V V V V m m m S nA A A nC nC nC ns ns ns ns nH nH nH pF pF pF
Tj = 175C
VDD = 30 V; RD = 1.2 ; RG = 10 ; VGS = 5 V Resistive load Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
August 1999
2
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
PHP21N06LT, PHB21N06LT PHD21N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 20 A; VGS = 0 V IF = 20 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 30 V TYP. MAX. UNIT 1.2 43 94 19 76 1.5 A A V ns nC
Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
100
Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID tp = 10 us
10 100 us 1 ms 10 ms 100 ms
D.C. 1
0.1 1 10 Drain-Source Voltage, VDS (V) 100
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Transient thermal impedance, Zth j-mb (K/W)
Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
10
D = 0.5 1 0.2 0.1 0.05 0.1 0.02 single pulse T 0.01 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 P D tp D = tp/T
Pulse width, tp (s)
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
August 1999
3
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
PHP21N06LT, PHB21N06LT PHD21N06LT
35 30 25 20 15 10 5 0 0
Drain Current, ID (A) Tj = 25 C VGS = 10V 5V
3.4 V 3.2 V 3V 2.8 V 2.6 V 2.4 V 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Transconductance, gfs (S) VDS > ID X RDS(ON) Tj = 25 C
175 C
0
2
4
6
8 10 12 14 Drain current, ID (A)
16
18
20
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS)
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID)
Normalised On-state Resistance
0.3 0.25
Drain-Source On Resistance, RDS(on) (Ohms) 2.6 V 2.4 V 2.8V Tj = 25 C
0.2 0.15 0.1 0.05
3V 3.2 V 3.4 V 5V
VGS = 10V 0 0 5 10 15 20 Drain Current, ID (A) 25 30 35
2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C)
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID)
Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj)
Threshold Voltage, VGS(TO) (V) maximum
Drain current, ID (A) 20 18 16 14 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Gate-source voltage, VGS (V) 175 C Tj = 25 C VDS > ID X RDS(ON)
2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0
typical minimum
-60
-40 -20
0
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics. ID = f(VGS)
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
August 1999
4
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
PHP21N06LT, PHB21N06LT PHD21N06LT
1.0E-01
Drain current, ID (A)
30
Source-Drain Diode Current, IF (A) VGS = 0 V
1.0E-02
25 20
1.0E-03
minimum typical
15
1.0E-04
175 C Tj = 25 C
maximum
10 5 0
1.0E-05
1.0E-06 0 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Maximum Avalanche Current, IAS (A) 10000 Capacitances, Ciss, Coss, Crss (pF) 100
10 1000 Ciss
25 C
100
Coss
1
Tj prior to avalanche = 150 C
Crss 10 0.1 1 10 Drain-Source Voltage, VDS (V) 100 0.1 0.001
0.01
0.1 Avalanche time, tAV (ms)
1
10
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
Gate-source voltage, VGS (V) ID = 20A Tj = 25 C VDD = 11 V
Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDD = 44 V
0
2
4
6
8 10 12 14 Gate charge, QG (nC)
16
18
20
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG)
August 1999
5
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
PHP21N06LT, PHB21N06LT PHD21N06LT
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
SOT78
E P
A A1 q
D1
D
L2(1)
L1 Q
L
b1
1
2
3
b c
e
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.5 4.1 A1 1.39 1.27 b 0.9 0.7 b1 1.3 1.0 c 0.7 0.4 D 15.8 15.2 D1 6.4 5.9 E 10.3 9.7 e 2.54 L 15.0 13.5 L1 3.30 2.79 L2 max. 3.0
(1)
P 3.8 3.6
q 3.0 2.7
Q 2.6 2.2
Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11
Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8".
August 1999
6
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
PHP21N06LT, PHB21N06LT PHD21N06LT
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped)
SOT404
A E A1 mounting base
D1
D
HD
2
Lp
1
3
b c Q
e
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.40 14.80 Q 2.60 2.20
OUTLINE VERSION SOT404
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 98-12-14 99-06-25
Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8".
August 1999
7
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
PHP21N06LT, PHB21N06LT PHD21N06LT
9.0
17.5 2.0
3.8
5.08
Fig.18. SOT404 : soldering pattern for surface mounting.
August 1999
8
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
MECHANICAL DATA
PHP21N06LT, PHB21N06LT PHD21N06LT
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped)
SOT428
seating plane y A E b2 A A1 mounting base A2 D1
E1 D HE L2
2
L L1
1
b1 e e1 b
3
wM A c
0
10 scale
20 mm
DIMENSIONS (mm are the original dimensions) A UNIT max. mm 2.38 2.22 A1(1) 0.65 0.45 A2 0.89 0.71 b 0.89 0.71 b1 max. 1.1 0.9 b2 5.36 5.26 c 0.4 0.2 D1 E D max. max. max. 6.22 5.98 4.81 4.45 6.73 6.47 E1 min. 4.0 e e1 HE max. 10.4 9.6 L 2.95 2.55 L1 min. 0.5 L2 0.7 0.5 w 0.2 y max. 0.2
2.285 4.57
Note 1. Measured from heatsink back to lead. OUTLINE VERSION SOT428 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-04-07
Fig.19. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8".
MOUNTING INSTRUCTIONS
August 1999
9
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
PHP21N06LT, PHB21N06LT PHD21N06LT
Dimensions in mm
7.0
7.0
2.15 2.5
1.5
4.57
Fig.20. SOT428 : soldering pattern for surface mounting.
August 1999
10
Rev 1.500
Philips Semiconductors
Product specification
N-channel TrenchMOSTM transistor Logic level FET
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values
PHP21N06LT, PHB21N06LT PHD21N06LT
This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1999
11
Rev 1.500

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