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PS10 - Active High PS11 - Active Low
PS10/PS11
Initial Release
Quad Power Sequencing Controller
Features
Sequencing of Four or More* Supplies, ICs, or Subsystems Independently Programmable Delays Between Open Drain PWRGD Flags (5ms to 200ms) 10V to 90V Operation Tracking in Combination with Schottky Diodes Input Supervisors Including: o UV/OV Lock Out/Enable o Power-On-Reset (POR) Low Power Consumption, 0.4mA Supply Current Small SO-14 Package
*By Daisy-Chaining PS10/11's
Description
Many of today's high performance FPGA's, Microprocessors, DSP and industrial/embedded subsystems require sequencing of the input power. Historically this has been accomplished: i) discretely using comparators, references & RC circuits; ii) using expensive programmable controllers; or iii) with low voltage sequencers requiring resistor drop downs and several high voltage optocoupler or level shift components. The PS10/11 saves board space, improves accuracy, eliminates optocouplers or level shifts and reduces overall component count by combining four timers, programmable input UV/OV supervisors, a programmable POR and four 90V open drain outputs. A high reliability, high voltage, junction isolated process allows the PS10/11 to be connected directly across the high voltage input rails. The power-on-reset interval (POR) may be programmed by a capacitor on Cramp. To sequence additional systems, PS10/11 may be daisy chained together. If at any time the input supply falls outside the UV/OV detector range the PWRGD outputs will immediately become INACTIVE. Down sequencing may be accomplished with additional components (see page 11). The PS10/PS11 is available in a space saving SO-14 package.
Applications
Power Supply Sequencing -48V Telecom and Networking Distributed Systems -24V Cellular and Fixed Wireless Systems -24V PBX Systems +48V Storage Systems FPGA, Microprocessor Tracking Industrial/Embedded System Timing/Sequencing High Voltage MEMs Driver's Supply Sequencing High Voltage Display Driver's Supply Sequencing
Typical Application Circuit
GND or +48V 487K 6 UV 14 VIN PWRGD-D / PWRGD-D PWRGD-C / PWRGD-C 6.81K 5 7 OV VEE PWRGD-B / PWRGD-B 1 2 3 4 /EN
DC/DC CONVERTER
Waveform
(49.9k pull-up on PS11 PWRGD pins)
/EN
DC/DC CONVERTER
+12V COM
+5V COM
PS10/PS11
TB 11 TC 12 TD 13
PWRGD-A / PWRGD-A
9.76K
Ramp 10
/EN
DC/DC CONVERTER
+3.3V COM
RTB
RTC
RTD
10nF /EN +2.5V COM
-48V or GND
DC/DC CONVERTER
Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V.
Relative to Negative Rail
A051204
Supertex, Inc.
* 1235 Bordeaux Drive, Sunnyvale, CA 94089 * Tel: (408) 222-8888 * FAX: (408) 222-4895 * www.supertex.com
1
PS10/PS11
Absolute Maximum Ratings*
VEE referenced to VIN pin VPWRGD referenced to VEE voltage VUV and VOV referenced to VEE Voltage Operating Ambient Temperature Operating Junction Temperature Storage Temperature Range Power Dissipation @ 25C, 14-Pin SOIC +0.3V to -100V -0.3V to +100V -0.3V to 12V -40C to +85C -40C to +125C -65 to +150C 750mW
Ordering Information
Active State of Power Good Flags High Low Package Options 14 Pin SOIC PS10NG PS11NG
*Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Electrical Characteristics (-10V V
Symbol Parameter
IN
-90V, TA = 25C unless otherwise specified) Min Typ Max Units Conditions
Supply (Referenced to VIN pin)
VEE IEE Supply Voltage Supply Current -90 400 -10 450 V A VEE = -48V
OV and UV Control (Referenced to VEE pin)
VUVH VUVL VUVHY IUV VOVH VOVL VOVHY IOV
#
UV High Threshold# UV Low Threshold UV Hysteresis
# #
1.16 1.06
1.22 1.12 100
1.28 1.18
V V mV
Low to High Transition High to Low Transition
UV Input Current OV High Threshold OV Low Threshold OV Hysteresis
# #
1.0 1.16 1.06 1.22 1.12 100 1.0 1.28 1.18
#
nA V V mV nA
VUV = VEE + 1.9V Low to High Transition High to Low Transition
OV Input Current
VUV = VEE + 1.9V
Specifications apply over 0C TA 70C
Power Good Timing (Test Conditions: CRAMP = 10nF, VUV = VEE + 1.9V, VOV = VEE + 0.5V)
IRAMP tPWRGD-A tPWRGD-B tPWRGD-B tPWRGD-C tPWRGD-C tPWRGD-D tPWRGD-D Ramp Pin Output Current Time from UV High to PWRGD-A Maximum time from PWRGD-A to PWRGD-B Minimum time from PWRGD-A to PWRGD-B Maximum time from PWRGD-B to PWRGD-C Minimum time from PWRGD-B to PWRGD-C Maximum time from PWRGD-C to PWRGD-D Minimum time from PWRGD-C to PWRGD-D 150 3.0 150 3.0 150 3.0 10 8.8 200* 5.0* 200* 5.0* 200* 5.0* 250 8.0 250 8.0 250 8.0 A ms ms ms ms ms ms ms VEE = -48V, CRAMP = 10nF, see Typical Application Circuit RTB = 120k RTB = 3k RTC = 120k RTC = 3k RTD = 120k RTD = 3k
*Note: Variations will track. For example if tPWRGD-A is 250ms then so will be tPWRGD-B/C/D. Contact factory for tighter tolerance version.
Power Good Outputs (Test Conditions: VUV = VEE + 1.9V, VOV = VEE + 0.5V)
VPWRGD-x(hi) VPWRGD-x(lo) IPWRGD-x(lk) Power Good Pin Breakdown Voltage Power Good Pin Output Low Voltage Maximum Leakage Current 2 90 0.4 <1.0 0.5 10 V V A
PWRGD-x = HI Z
IPWRGD = 1mA, PWRGD-x = LOW
VPWRGD = 90V, PWRGD-x = HI Z
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PS10/PS11
PWRGD Logic
Model PS10 PS11 Condition
INACTIVE (not ready) ACTIVE (Ready) INACTIVE (not ready) ACTIVE (Ready)
PWRGD-A/B/C/D
0 1 1 0 VEE HI Z HI Z VEE
Pinout
PWRGD-D (PS10) PWRGD-D (PS11) PWRGD-C (PS10) PWRGD-C (PS11) PWRGD-B (PS10) PWRGD-B (PS11) PWRGD-A (PS10) PWRGD-A (PS11) OV
1 14
V IN
2
13
TD
3
12
TC
4
11
TB
5
10
RAMP
UV
6
9
NC
V EE
7
8
NC
Top View
Pin Description
PWRGD-D - This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-C goes active. PWRGD-C - This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-B goes active. PWRGD-B - This open drain Power Good Output Pin is held inactive on initial power application and goes active a programmed time delay after PWRGD-A goes active. PWRGD-A - This open drain Power Good Output Pin is held inactive on initial power application and goes active one POR delay after the UV pin goes above its High threshold (provided VIN stays within the UV/OV window during this period). To function as an indicator a pullup resistor must be connected from this pin to a voltage rail no more than 90V from VEE. OV - This Over Voltage (OV) sense pin, when raised above its high threshold will immediately cause the Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin falls below the low threshold limit, initiating a new start-up cycle. UV - This Under Voltage (UV) sense pin, when lowered below its low threshold will immediately cause the Power Good Outputs to be pulled low. These outputs will remain low until the voltage on this pin rises above the low threshold limit, initiating a new start-up cycle.
VEE - This pin is the negative terminal of the power supply input to the circuit. VIN - This pin is the positive terminal of the power supply input to the circuit and can withstand 90V with respect to VEE. TD - The resistor connected from this pin to VEE pin sets the time delay from PWRGD-C going active to PWRGD-D going active. TC - The resistor connected from this pin to VEE pin sets the time delay from PWRGD-B going active to PWRGD-C going active. TB - The resistor connected from this pin to VEE pin sets the time delay from PWRGD-A going active to PWRGD-B going active. RAMP - This pin provides a current output so that a timing ramp is generated when a capacitor is connected. This timing Ramp is used to program POR and the time from satisfaction of the UV/OV supervisors to PWRGD-A. NC- No Connect. This pin can be grounded or left floating.
3
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PS10/PS11
Functional Block Diagram
Band Gap Reference
Vint
UV
+
Regulator & POR
V IN
Vbg
-
Logic
UVLO
PWRGD-A
OV
+
PWRGD-B
VEE
PWRGD-C
Vint
10uA
Programmable Timer
PWRGD-D
+ Vint - 1.2V
-
RAMP
TB
TC
TD
Functional Description
The PS10/PS11 are designed to sequence up to 4 power supply modules, ICs or subsystems when the backplane voltage is within the programmed Under-voltage and Overvoltage limits. The power good open drain outputs are sequentially enabled starting from PWRGD-A to PWRGDD. The time delay between power goods is programmable up to 200ms simply by changing the value(s) of RTB, RTC, and RTD. The initial time between satisfaction of the UV/OV supervisors & PWRGD-A can be programmed with Cramp. Description of Operation During the initial power application, the Power Good pins are held low (rising with VIN) for PS10 and high for the PS11. Once the internal under voltage lock out has been satisfied, the circuit checks the input supply under voltage (UV) and over voltage (OV) sense circuits to ensure that the input voltage is within programmed limits. These limits are determined by the selected values for R1, R2, and R3, which form a voltage divider. At the same time, a 10A current source is enabled, charging the external capacitor connected to the ramp pin. The rise time of the ramp pin is determined by the value of the capacitor (10A/Cramp). When the ramp voltage reaches 8.8V, the PWRGD-A pin will change into an active state. PWRGD-B will change into an active state after a programmed time delay from PWRGD-A inactive to active transition. PWRGD-C will change into an active state after a programmed time delay from PWRGD-B inactive to ac-
tive transition. PWRGD-D will change into an active state after a programmed time delay from PWRGD-C inactive to active transition. The controller continuously monitors the UV and OV pins as long as the internal UVLO and POR circuits are satisfied. At any time during the start up cycle or thereafter, crossing the UV low and OV high limits will cause an immediate discharge on Cramp and reset on the power good pins. When the input voltage returns to a value within the programmed UV and OV limits, a new start up sequence will initiate immediately. Programming the Under and Over Voltage Limits The UV and OV pins are connected to comparators with nominal 1.17V thresholds and 100mV of hysteresis (1.17V 50mV). They are used to detect under voltage and over voltage conditions at the input to the circuit. Whenever the OV pin rises above its high threshold (1.22V) or the UV pin falls below its low threshold (1.12V), the PWRGD outputs immediately deactivate. Calculations can be based on either the desired input voltage operating limits or the input voltage shutdown limits. In the following equations the shutdown limits are assumed. The undervoltage and overvoltage shut down thresholds can be programmed by means of the three resistor divider formed by R1, R2 and R3. Since the input currents on the UV and OV pins are negligible the resistor values may be calculated as follows: 4
A051204
PS10/PS11
UVOFF = VUVL = 1.12 = (VEEUV(off)) x (R2+R3)/(R1+R2+R3) OVOFF = VOVL = 1.22 = (VEEOV(off)) x R3/(R1+R2+R3) Where (VEEUV(off)) and (VEEOV(off)) relative to VEE are Under and Over Voltage Shut Down Threshold points. If we select a divider current of 100 A at a nominal operating input voltage of 50 Volts, then From the calculated resistor values the OV and UV start up threshold voltages can be calculated as follows: UVON = VUVH = 1.22 = (VEEUV(on)) x (R2+R3)/(R1+R2+R3) OVON = VOVL = 1.12 = (VEEOV(on)) x R3/(R1+R2+R3) Where (VEEUV(on)) and (VEEOV(on)) are Under and Over Voltage Start Up Threshold points relative to VEE. Then (VEEUV(on)) = 1.22 x (R1+R2+R3)/(R2+R3) R1+R2+R3 = 50V/100A = 500k (VEEUV(on)) = 1.22 x (487k+6.65k+9.31k)/(6.65k+9.31k ) = 38.45V From the second equation, for an OV shut down threshold of 65V, the value of R3 may be calculated. And (VEEOV(on)) = 1.12 x (R1+R2+R3)/R3 OVOFF = 1.22 = (65xR3)/500k R3 = (1.22x 500k)/65 = 9.38k (VEEOV(on) ) = 1.12 x (487k +6.65k +9.31k)/9.31k = 60.51V Therefore, the circuit will start when the input supply voltage is in the range of 38.45V to 60.51V.
The closest 1% value is 9.31k.
From the first equation, for a UV shut down threshold of 35V, the value of R2 can be calculated.
UVOFF = 1.12 = 35 x (R2+R3)/ 500k R2 = ((1.12 x 500k)/35) - 9.76k = 6.69k
6.65k is a standard 1% value Then R1 = 500k - R2 - R3 = 484.04k. 487k, is a standard 1% value.
5
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PS10/PS11 Undervoltage/Overvoltage Operation
GND UVOFF UVON OVON OVOFF
PWRGD Flags Delay Programming
When the ramp voltage hits Vint - 1.17V, PWRGD-A becomes active indicating that the input supply voltage is within the programmed limits. PWRGD-B goes active after a programmed time delay after PWRGD-A went active. PWRGD-C goes active after a programmed time delay after PWRGD-B went active. PWRGD-D goes active after a programmed time delay after PWRGD-C went active. The resistors connected from TB, TC, and TD to VEE pin determines the delay times between the PWRGD flags.
Vin
PWRGD
SET RESET
The value of the resistors determines the capacitor charging and discharging current of a triangular wave oscillator. The oscillator output is fed into an 8-bit counter to generate the desired time delay. The respective time delay is defined by the following equation: tTX = (255 x 2 x COSC x VPP)/ICD and ICD = Vbg / (4 x RTX) Where tTX = Time delay between respective PWRGD flags COSC = 120pF (internal oscillator capacitor) VPP = 8.2V (peak-to-peak voltage swing of oscillator) ICD = Charge and discharge current of oscillator Vbg = 1.17V (internal band gap reference) RTX = Programming resistor at TB, TC, or TD Combining the two equations and solving for RTX yields: RTX = (Vbg x tTX) / (2040 x COSC x VPP)
6 = 0.585 x 10 x tTX
Start-up Timing (PS11 PWRGD-A Active Low)
tPWRGD-A is the time delay from VEEUV(on) to PWRGD-A going active. It can be approximated by
For a time delay of 200ms RTX = 0.585 x 106 x 0.2 = 117k
tPWRGD-A = CRAMP x (VINT-1.17)/IRAMP where CRAMP = capacitor connected from RAMP pin to VEE pin VINT = internal regulated power supply voltage (10V typ) IRAMP = 10A charge current
For a time delay of 5ms RTX = 0.585 x 106 x 0.005 = 2.925k
6
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PS10/PS11
The following waveforms demonstrate the sequencing of the PWRGD flags:
PWRGD Timing (Maximum Delays)
Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 118k, RTC = 118k, RTD = 118k, RPULL-UP = 47k.
PWRGD Timing (PS11)
Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 118k, RTC = 59k, and RTD = 46.4k.
Relative to Negative Rail Relative to Negative Rail
PS11 Power Down Sequence after UVOFF
Test conditions: CRAMP = 10nF, RTB = 3.24k, RTC = 3.24k, RTD = 3.24k, RPULL-UP = 47k, CPWRGD_B = 0.47F, CPWRGD_C = 0.94F, CPWRGD_D = 1.41F, VUVOFF = 33.4V, the assumed brick turn-off threshold is 2.7V min TTL logic high. See power down sequencing on Page 11.
PWRGD Timing (Minimum Delays)
Test conditions: VIN = 48V, CRAMP = 10nF, RTB = 3.24k, RTC = 3.24k, RTD = 3.24k, RPULL-UP = 47k.
Relative to Negative Rail Relative to Negative Rail
7
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PS10/PS11 PS11 Power Down Sequence after OVOFF
Test conditions: CRAMP = 10nF, RTB = 3.24k, RTC = 3.24k, RTD = 3.24k, RPULL-UP= 47k, CPWRGD_B = 0.47F, CPWRGD_C = 0.94F, CPWRGD_D = 1.41F, VOVOFF = 61.6V, the assumed brick turn-off threshold is 2.7V min TTL logic high. See power down sequencing on Page 11.
Relative to Negative Rail
PWRGD Output Configuration
The PS10 and PS11 open drain power good outputs can be connected directly to the Enable pins of the DC/DC converter. The internal pull-up and clamp of the DC/DC converter sets the logic High Enable/Disable voltage.
GND 487K UV 6.81K OV 9.76K VEE
V IN PWRGD-D PWRGD-C
V+
DC/DC Converter +3.3V
PS10
PWRGD-B PWRGD-A EN
COM TB TC TD Ramp V-
RTB
RTC
RTD
10nF
-48V
Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters.
8
A051204
PS10/PS11
PWRGD Output Configuration, continued
GND 487K UV 6.81K OV 9.76K V EE
V IN PWRGD-D PWRGD-C
V+
DC/DC Converter +3.3V
PS11
PWRGD-B PWRGD-A /EN
COM TB TC TD Ramp V-
RTB
RTC
RTD
10nF
-48V
Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active Low Enabled Converters.
Opto-isolated Enable
Some applications require opto-isolator interface to the Enable pin of the DC/DC converter. Make sure that the current transfer ratio of the opto-coupler selected is at least 100% to ensure proper pull-down current on the Enable pin.
GND 487K UV 6.81K OV 9.76K V EE
VIN
PWRGD-D PWRGD-C
V+ 49.9k
DC/DC Converter +3.3V
PS10
PWRGD-B PWRGD-A
Opto-coupler
EN COM
TB
TC
TD
Ramp
V-
RTB
RTC
RTD
10nF
-48V
Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters.
9
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PS10/PS11
Opto-isolated Enable, continued
GND 487K UV 6.81K OV 9.76K VEE
VIN PWRGD-D PWRGD-C 49.9k
V+
DC/DC Converter
PS11
PWRGD-B PWRGD-A
Opto-coupler
+3.3V /EN COM
TB
TC
TD
Ramp
V-
RTB
RTC
RTD
10nF
-48V
Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active Low Enabled Converters.
Increasing the Under and Over Voltage Hysteresis
If the internal UV hysteresis is insufficient for a particular system application, then it may be increased by using separate resistor dividers for UV and OV and providing a resistor feedback from UV pin to the PWRGD pin.
GND 487k 499k VIN UV PWRGD-D PWRGD-C Ruvhys OV VEE V+ DC/DC Converter +3.3V EN COM TB TC TD Ramp V-
PS10
PWRGD-B PWRGD-A
16.5k
9.76k RTB RTC RTD 10nF
-48V
Ruvhys can be calculated based on higher UV On voltage (say 42V): Ruvhys = (Vuvon - Vdiode - Vpwrgdlow)/((Vin-Vuvon)/487k Vuvon/16.5k) = (1.22-0.65-0.4)/((42-1.22)/487k - 1.22/16.5k) = 17.35k
Note: 1. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters. 2. Over voltage shut down set to 63.6V
10
A051204
PS10/PS11
Increasing the Under and Over Voltage Hysteresis, continued
GND 487k 499k VIN PWRGD-D PWRGD-C UV OV COM Ruvhys VEE TB TC TD Ramp V10k V+ DC/DC Converter
PS11
PWRGD-B PWRGD-A /EN
+3.3V
16.5k
9.76k RTB RTC RTD 10nF
-48V Note: 1. Other power good outputs will have the same configuration as PWGRGD-A for Active Low Enabled Converters. 2. Over voltage shut down set to 63.6V
Ruvhys can be calculated based on higher UV On voltage (say 42V): Ruvhys = (Vuvon - Vdiode - Vce/((Vin-Vuvon)/487k Vuvon/16.5k) = (1.22-0.65-0.1)/((42-1.22)/487k - 1.22/16.5k) = 47.97k
Power Down Sequencing
In some applications, a power down sequence may be required. To accomplish this, a capacitor is connected to the power good pins that need to be sequenced down. The power good turn off delays can be approximated by TPWRGD-B(off) = C1 x VENOFF / IPULLUP , TPWRGD-C(off) = C2 x VENOFF / IPULLUP , TPWRGD-D(off) = C3 x VENOFF / IPULLUP , where: TPWRGD-B(off) TPWRGD-c(off) TPWRGD-D(off) VENOFF IPULLUP -Time delay from PWRGD-A going High to PWRGD-B going high. -Time delay from PWRGD-A going High to PWRGD-C going high. -Time delay from PWRGD-A going High to PWRGD-D going high.
- DC/DC minimum off voltage (2.7V typ) - DC/DC /EN pin pull-up current (1mA typ)
Note: Adding C1, C2, C3 will have a negligible affect on the power good fall time.
GND 487K UV
V
IN
/EN4 PWRGD-D /EN3 PWRGD-C PWRGD-B PWRGD-A /EN2
V+
DC/DC Converter
6.81K OV
PS11
+3.3V /EN COM
9.76K
VEE
TB
TC
TD
Ramp
V-
RTB
RTC
RTD
10nF
C3
C2
C1
-48V
Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Only PWRGD-A to DC/DC converter connection is shown for simplicity.
11
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PS10/PS11
PS10 Power Good Clamp
If the active high enabled dc/dc converter used does not have an internal clamp, an external zener diode may be used to protect the module.
GND 487K UV 6.81K OV 9.76K VEE
VIN
PWRGD-D PWRGD-C
V+ 49.9k
DC/DC Converter +3.3V
PS10
PWRGD-B PWRGD-A EN
COM TB TC TD Ramp V-
RTB
RTC
RTD
10nF
-48V
Notes: 1. Under Voltage Shutdown (UV) set to 37V. 2. Over Voltage Shutdown (OV) to 57.8V. 3. Other power good outputs will have the same configuration as PWGRGD-A for Active High Enabled Converters.
Typical Application Circuit for a 12V Non-Isolated System
Most FPGAs, Processors, ASICs, and DSPs require sequencing and rail voltage limitation during start-up and power down sequence of its rails. A typical requirement is: VDD_CORE must not exceed VDD_IO more than 0.6V and VDD_IO must not exceed VIN at any time. This can be accomplished by sequencing the dc/dc converters by the following manner: Turn On: VDD_CORE first, VDD_IO second, and VIN last. Tun-Off: VIN first, VDD_IO second, and VDD_CORE last. The Schottky diodes will limit the voltage between the rails to around 0.3V @ 3A during the power-up and power-down sequence. Assuming that the /EN pins of the dc/dc converters have no pull-up and have a 1.0V turn-off threshold, the power-down sequence time delays can be approximated by: TPWRGD-C to TPWRGD-B = 1F x 1V / 1mA = 1ms TPWRGD-B to TPWRGD-A = (2F-1F) x 1V / 1mA = 1ms
+12V R1 6 UV 14 VIN PWRGD-D PWRGD-C R2 5 OV R3 7 VEE PWRGD-B 1 2 3 4 /EN
Buck Converter
R9 R8 12k 12k /EN
Buck Converter
+5V 30BQ015
VIN
LOAD
VDD_IO
PS11
TB 11 TC 12 TD 13 Ramp 10
PWRGD-A
+3.3V 30BQ015 /EN
Buck Converter
VDD_CORE
GND
+2.5V
RTB
RTC
RTD
10nF
C1 C2 2uF 1uF
GND
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
2004 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
A051204
Doc. #: DSFP-PS10PS11
12
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 / FAX: (408) 222-4895 www.supertex.com
A051204
Package Outlines 14-LEAD SO PACKAGE (NG) (NARROW BODY)
0.340 0.005 (8.636 0.127)
D
0.017 0.003 (0.4318 0.0762)
B
E
0.156 0.002 (3.9624 0.0508)
H
0.2335 0.0105 (5.9309 0.2667)
0.500 T Y P. (12.700)
0.193 0.012 (4.9022 0.3048) 0.350 T Y P. (8.890) 0.006 0.002 (0.1524 0.0508)
A1 e D1 h
0.020 0.009 (0.508 0.2286)
7 (4 P LC S )
45
L1
A
C
0 - 8
L
0.063 0.005 (1.600 0.127)
0.050 T Y P. (1.270)
0.006 0.004 (0.1524 0.1016)
0.035 0.015 (0.889 0.381)
0.0275 0.0025 (0.6985 0.0635)
Note: C ircle (e.g. B ) indicates J E DE C R eference.
Meas urement Legend =
Dimens ions in Inches (Dimens ions in Millimeters )
Doc. #: DSPD14SONG
A050604
(c)2004 S upertex Inc. All rights res erved. Unauthorized us e or reproduction prohibited.
1235 B ordeaux Drive, S unnyvale, C A 94089 T E L: (408) 222-8888 / F AX : (408) 222-4895 www.s upertex.com

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