View V320DS_1007006.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

V320USC Universal System Controller
* * * * * * PCI System Controller for 32-Bit MIPSTM and SuperHTM System Interface Device Highlights
* Glueless interface between popular MIPSTM and SuperHTM processors and the standard 32-bit PCI bus * Fully compliant with PCI 2.2 specification * Configurable for primary master, bus master, or target operation * SDRAM controller with support for Enhanced SDRAM * Up to 1 KB burst access to (E)SDRAM from PCI, 32 bytes from local processor (MIPS mode) * 640 bytes of on-chip FIFO storage with Dynamic Bandwidth AllocationTM architecture * On-the-fly byte order (endian) conversion * I2O ReadyTM ATU and messaging unit * Programmable chip select / peripheral device strobe generation * Hot Swap Ready (PICMGTM Hot Swap Specification 2.1) * Implementation of PCI Bus Power Management Interface Specification Version 1.0 * 3.3 V operation with 5V tolerant inputs * 208-pin PQFP package * Up to 75 MHz local bus clock with separate asynchronous PCI clock up to 50 MHz * Two 32-bit timers * Initialization through local processor, PCI or serial EEPROM
Introduction
The V320USC Universal System Controller simplifies the design of systems based on MIPS and SuperH microprocessors by replacing many lower integration support components with a single, highintegration device. This saves design time, board area, and manufacturing cost. The I2O Ready V320USC from V3 Semiconductor is a high performance PCI bridge with integrated SDRAM controller for MIPS processors operating at up to 75 MHz bus speed. It features address translation capabilities and large on-chip buffers. A separate peripheral bus provides low latency access to SDRAM. The peripheral controller on the V320USC also performs address decoding and chip-select strobes generation for SRAM, PROM and other slow peripherals. The integrated SDRAM Controller connects the processor as well as the PCI bus through on-chip FIFOs to SDRAM arrays of up to 1 GB in size. The fully programmable SDRAM controller also supports the use of Enhanced SDRAM to achieve even greater performance. Burst accesses of up to 1 KB from PCI and 32 bytes from the MIPS processor are supported. The two general purpose 32-bit timers can be individually configured as a pulse width modulator, or used in other modes such as retriggerable or oneshot. The bus watch timer (MIPS mode) prevents system hangs during accesses to undecoded regions. Interrupts for a real time OS can be easily generated by the system heartbeat timer. A watchdog timer is also provided for graceful recovery from catastrophic program failures. Interrupt requests for all on-chip peripherals are managed by the Interrupt Control Unit. Additionally, off-chip interrupts can be routed to the Interrupt Control Unit.
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
* * * *
1
V320USC Universal System Controller Rev. G
The V320USC is packaged in a low-cost 208-pin EIJA Plastic Quad Flat Pack (PQFP), and is available in 75 MHz speed grade (MIPS mode), 66 MHz (SH mode). This document contains the product codes, pinout, package mechanical information, DC characteristics, and AC characteristics for the V320USC. Detailed functional information is contained in the User's Manual.
Product Code
Table 1 describes the product codes available.
Table 1: Product Code Product Code V320USC-75LP REV B1 V320USC-75LPN REV B1 Processors MIPS (32-bit bus), SH3, SH4 (32-bit bus) MIPS (32-bit bus), SH3, SH4 (32-bit bus) Package 208-pin EIAJ PQFP PB-Free 208-pin EIAJ PQFP Frequency 75MHz (66 MHz SH) 75MHz (66 MHz SH)
Pin Description
Table 2 lists the pin types found on the V320USC.
Table 2: Pin Types Pin Type PCI I PCI O PCI I/O PCI I/OD I/O2, I/O8, I/O12 I O2, O8, O12 PCI input only pin. PCI output only pin. PCI tri-state I/O pin. PCI input with open drain output. TTL I/O pins with 2/8/12 mA drive TTL input only pin. TTL output pins with 2/8/12 mA drive Description
2 * www.quicklogic.com *
* * *
*
(c) 2005 QuickLogic Corporation
V320USC Universal System Controller Rev. G
Signal Description
Table 3 through Table 8 describe the function of each pin on the V320USC.
Table 3: Signal Description--PCI Bus Interface Signal AD[31:0] C/BE[3:0] PAR FRAME IRDY TRDY STOP Type PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O R
a
Description Address and data, multiplexed on the same pins. Bus Command and Byte Enables, multiplexed on the same pins. Parity represents even parity across AD[31:0] and C/BE[3:0]. Cycle Frame indicates the beginning and burst length of an access. Initiator Ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. Stop indicates the current target is requesting the master to stop the current transaction (retry or disconnect). Device Select, when actively driven by a target, indicates the driving device has decoded its address as the target of the current access. As an input to the initiator, DEVSEL indicates whether any device on the bus has been selected. Initialization Device Select is used as a chip select during configuration read and write transactions. It must be driven high in order to access the chip's internal configuration space.
Z Z Z Z Z Z Z
DEVSEL
PCI I/O
Z
IDSEL
PCI I
PERR SERR REQ GNT PCLK
PCI I/O PCI I/OD PCI O PCI I PCI I
Z Z Z
Parity Error is used to report data parity errors during all PCI transactions except a Special Cycle. System Error is used to report address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Request indicates to the arbiter that this agent requests use of the bus. Grant indicates to the agent that access to the bus has been granted. PCLK provides timing for all transactions on the PCI bus.
a. R indicates state during reset.
Table 4: Signal Description--Local Bus Interface, MIPSTM Mode Signal SYSAD[31:0] SYSCMD[8:0] VALIDIN VALIDOUT RELEASE WRRDY LCLK Type I/O I/O O8 I I O8 I Z R Z Z Z System Address / Data (multiplexed) System Command / data identifier. When MODE0 = `0', SYSCMD[8:5] should be pulled high. Valid command or data from external agent. This signal should have an external pull-up resistor. Valid command or data from MIPSTM Release the system interface to slave state Write Ready: this signal should have an external pull-up resistor. Local clock Description
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
* * * *
3
V320USC Universal System Controller Rev. G
Table 5: Signal Description--Local Bus Interface, SH3/4 Mode Signal A[31:26]/CS [5:0] A[25:0] D[31:0] RD/WR BS WAIT/RDY RBE_ENa RBE[3:0]b Type I/O8 I I/O8 I/O8 I/O8 I O8 I Z Z Z Z Lower System Address Data Bus Read/not Write. This is also referred to as MWE for SDRAM Bus Cycle Start Bus Wait Enable Read Byte Enables: When active (`0'), PCI byte lane enables are derived from RBE[3:0] for a local-to-PCI read access. Read Byte Enables: provides the byte enable pattern for local-to-PCI read access when RBE_EN is active. Byte enables for writes are derived from the DQM[3:0] signals. Z Bus Request Output: indicates that the V320USC wants to perform a bus cycle on the local bus Bus Acknowledge: asserted to allow the V320USC to take ownership of the local bus. Bus Request Input: assertion of this input will cause the V320USC to give up ownership of the local bus at the end of the current burst/single cycle so that a higher priority master can take ownership. Typically connected to IRQ_OUT. Local clock. This would be connected to either CKIO on the processor or a clock driver which provides a clock with the same phase relationship as CKIO. See V3 Reference Designs for further details. R Z Upper System Address Description
I
BREQ BACK BREQ_INc
O8 I I
LCLK
I
a. Not available in revision B0 silicon b. Not available in revision B0 silicon c. Not available in revision B0 silicon
Table 6: Signal Description--DRAM and Peripheral Bus Interface Signal MA[14:0] DCS[3:0] DQM[3:0] MBE[3:0] RAS CAS MWE MAD[31:0] SDA I/O8 O12 O12 O12 I/O8 I/OD2 Z Z Z Z Z Z Type O12 O8 R Z Z Description SDRAM Memory Address (also, A[16:2] for peripheral access). MA[14:13] are typically used for BA[1:0] SDRAM Chip Select. This should be connected to the CS inputs of SDRAM chips or DIMM devices. SDRAM Data Mask for SDRAM access, Byte enables (MBE[3:0]) and A[1:0] for peripheral access, and write enables for SH3/4 mode access. SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Memory Write Enable SDRAM and peripheral bus data. MAD[31:0] is known as D[31:0] when in SH3/4 mode. Serial EEPROM Data
4 * www.quicklogic.com *
* * *
*
(c) 2005 QuickLogic Corporation
V320USC Universal System Controller Rev. G Table 6: Signal Description--DRAM and Peripheral Bus Interface (Continued) Signal SCL IOC[11:0] INT[3:0] Type O2 I/O8 PCI I/OD R Z Z Z Serial EEPROM Clock Multi-purpose I/O that can be configured for many functions General purpose interrupt inputs/outputs: may be used for either PCI or local processor interrupts Description
Table 7: Signal Description--Mode and Reset Signal RSTIN RSTOUT I O8 0 Type R Description Reset Input: Active low reset input used to initialize all internal functions of the chip. Reset Output: Driven active when the input reset is driven active. Driven inactive when the RSTOUT bit in the system register is set. The RSTOUT signal is synchronous to the rising edge of LCLK. PCI Precharge Bias: This signal is driven low to activate the on-chip precharge bias for use in PICMG Hot Swap applications. Non-Hot Swap applications should pull this signal high. MODE Input: selects the CPU mode:
2 Pin 55 SYSCMD7 `H' `H' `L' MODE 1 Pin 54 SYSCMD8 `H' `L' `L' others 0 Pin 202 `H' `L' `L' `L' Description MIPS with 9 bit SYSCMD MIPS with 5 bit SYSCMD SH3 SH4 reserved
CH
I
MODE2:1 MODE0
I/O8 I
Z
`H' - Tie High with a weak pull up of 4.7-10K `L' - Tie Low with a weak pull down of 4.7-10K
Table 8: Signal Description--Power and Ground Signals Signal VCC GND NC 'H' Type R Description POWER leads for external connection to a 3.3V VCC board plane. GROUND leads for external connection to a GND board plane. No connect. Tie High with a weak pull up of 4.7K-10K
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
* * * *
5
V320USC Universal System Controller Rev. G
DC Specifications
The DC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.2 Section 4.2.1.1. For more information on the PCI DC specifications, see the PCI Specification.
Table 9: Absolute Maximum Ratings Symbol VCC VIN TSTG Parameter Supply voltage DC input voltage Storage temperature range Value -0.3 to +3.6 -0.3 to 6.0 -55 to +125 Unit V V C
Table 10: Guaranteed Operating Conditions Symbol VCC Theta Ja TA Parameter Supply voltage Thermal resistance Ambient temperature range Value 3.0 to 3.6 40 to 45 -40 to +85 Unit V C/w C
Table 11: DC Operating Conditions Symbol ICC(max) ICC(typ) Parameter Maximum supply current Typical supply current Max. 110 80 Unit mA mA Condition PCLK=33MHz, LCLK=66MHz, Vcc=3.6V, all buses operating
6 * www.quicklogic.com *
* * *
*
(c) 2005 QuickLogic Corporation
V320USC Universal System Controller Rev. G
PCI Bus DC Specifications
Table 12: PCI Bus Signals DC Operating Specifications Symbol VIH VIL IIH IIL VOH VOL CIN CCLK CIDSEL LPIN Parameter Input high voltage Input low voltage Input high leakage current Input low leakage current Output high voltage Output low voltage
b c a
Condition
Min. 0.5VCC -0.5 0.7VCC
Max. VCC + 0.5 0.3VCC +10
Unit V V A A V V pF pF pF nH
0 < VIN < VCC IOUT = -500A IOUT = 1500A 5 0.9VCC
0.1VCC 10 12 8 20
Input pin capacitance
PCLK pin capacitance IDSEL pin capacitanced Pin inductance
a. Input leakage currents include high impedance output leakage for all bi-directional buffers with tri-state outputs. b. Signals without pull-up resistors have greater than 3mA low output current. Signals requiring pull resistors have greater than 6mA output current. The latter include FRAME, TRDY, IRDY, STOP, SERR, PERR. c. Absolute maximum pin capacitance for a PCI unit is 10pF (except for CLK). d. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx].
Local Bus DC Specifications
Table 13: Local Bus/M Bus Signals DC Operating Specifications (VCC = 3.3V+ 0.3V) Symbol VIH VIL IIH IIL VOH VOL IOZL IOZH CIO Parameter Input high voltage Input low voltage Input high leakage current Input low leakage current Output high voltage Output low voltage Low level float input leakage High level float input leakage Input and output capacitance VIN = VCC VIN=GND IOUT = -2, -8, -12mA IOUT = 2, 8, 12mA VOL = GND VOH = VCC -10 -10 -10 -10 2.4 0.4 10 10 TBA Condition Min. 2.0 0.8 10 10 Max. Unit V V A A V V A A pF
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
* * * *
7
V320USC Universal System Controller Rev. G
AC Specifications
The AC specifications for the PCI bus signals match exactly those given in the PCI Specification, Rev. 2.1, Section 4.2.1.2. For more information on the PCI AC specifications, including the V/I curves for 5V signalling, see section 4.2.1.2 of the PCI Specification, Rev 2.1.
PCI Bus Timings
Table 14: PCI Bus Signals AC Operating Specifications Symbol Parameter Switching current high (Test point) IOL(AC) ICL tR tF Switching current low (Test point) Low clamp current Unloaded output rise time Unloaded output fall time Condition 0V< VOUT 0.3VCC IOH(AC) 0.3VCC VOUT >0.6VCC 0.6VCC > VOUT >0.1VCC VOUT=0.18VCC -3VLocal and M Bus Timings
Table 15: Local and M Bus AC Test Conditions Symbol VCC VIN COUT Parameter Supply voltage 3.3 volt operation Input low and high voltages Capacitive load on output and I/O pins Limits 3.0 to 3.60 0.4 and 2.0 50 Unit V V pF
Table 16: M Bus AC Test Conditions Symbol VCC VIN COUT Parameter Supply voltage 3.3 volt operation Input low and high voltages Capacitive load on output and I/O pins Limits 3.0 to 3.60 0.4 and 2.0 50 Unit V V pF
Table 17: Capacitive Derating for Output and I/O Pins Output Drive Limit 8 mA 12 mA Supply Voltage 3.3 volt 3.3 volt Derating 0.019 ns/pF for loads > 50 pF 0.017 ns/pF for loads > 50 pF
8 * www.quicklogic.com *
* * *
*
(c) 2005 QuickLogic Corporation
V320USC Universal System Controller Rev. G
Timing Parameters
Figure 1: Clock and Synchronous Signals
TC TCH TSU TH TCL
LOCAL CLOCK INPUT SETUP/HOLD OUTPUT VALID OUTPUT DRIVE OUTPUT FLOAT
VALID TCOV
;;;;;;;;;;; ;;;;;;;;;;; Tczo
TCOZ ;;;;;;
VALID
;;;;;;
VALID
Figure 2: ALE Timing
TALE ALE
ADDRESS
MAD
TASU
TAH
:
Table 18: Local Bus/M-Bus Timing Parameters for Vcc =3.3 Volts +/- 5% Number 1 2 3 4 4a 5 6 7 8 9 10 11 Symbol TC TCH TCL TSU TSU TH TCOV TCZO TCOZ TALE TASU TAH LCLK period LCLK high time LCLK low time Synchronous input setup Synchronous input setup for non-pipelined signalsa Synchronous input hold LCLK to output valid delay LCLK to output driving delay LCLK to high impedance delay ALE pulse width Address to ALE setup time Address hold time from ALE TCH-1 TCH TCL-4 Description 75 MHz Min. 13.33 4.5 4.5 2.5 9 1.5 9 9 12 TCH+2 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns
a. Non-pipelined signals include MRDY when the SYNC_RDY bit in the LB_BUS_CFG register is `0', and BGNT when the BREQ_SYNC register is `1'.
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
* * * *
9
V320USC Universal System Controller Rev. G
Table 19: PCI Bus Timing Parameters for Vcc = 3.3 Volts +/- 10% Number 1 2 2a 3 4 4a 5 6 7 Symbol TC TSU TSU TH TCOV TCOV TCZO TCOZ TRST PCLK period Synchronous input setup to PCLK
a
Description
Min. 20 7 10 0 2 2 2 3 16*TC
Max.
Unit ns ns ns ns
Synchronous input setup to PCLK (GNT) Synchronous input hold from PCLK PCLK to output valid delay
b
11 12 11 14
ns ns ns ns
PCLK to output valid delay (REQ) PCLK to output driving delay PCLK to high impedance delay Reset period
a. All PCI signals except GNT. b. All PCI signals except REQ.
Serial EEPROM Port TImings
The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms generated are shown in Figure 3.
Figure 3: Serial EEPROM Waveforms and Timings
512 PCI BUS CLOCKS
START CONDITION
STOP CONDITION
SCL
SDA
256 PCI BUS CLOCKS
256 PCI BUS CLOCKS
10 * www.quicklogic.com *
* * *
*
(c) 2005 QuickLogic Corporation
V320USC Universal System Controller Rev. G
208-pin EIAJ PQFP in MIPS Mode Pinout Diagram
Figure 4: Pinout for 208-pin EIAJ PQFP in MIPS Mode (top view)
GND MWE# SDRAM_CS0# SDRAM_CS1# SDRAM_CS2# SDRAM_CS3# DQM2# DQM3# IOC0 SYSAD16 GND MA14 MAD16 SYSAD17 MAD17 SYSAD18 MAD18 SYSAD19 MAD19 Vcc GND LCLK CH# SYSAD20 MAD20 SYSAD21 MAD21 SYSAD22 MAD22 SYSAD23 MAD23 SYSAD24 GND Vcc MAD24 SYSAD25 MAD25 SYSAD26 MAD26 SYSAD27 MAD27 SYSAD28 GND MAD28 SYSAD29 MAD29 SYSAD30 MAD30 SYSAD31 MAD31 SYSAD0 Vcc 156 157 105 104
Vcc CAS# IOC11 RAS# IOC10 MA13 IOC9 MA12 MA11 GND INT3# MA10 MA9 IOC8 MA8 IOC7 MA6 IOC6 GND Vcc MA7 IOC5 MA5 IOC4 MA4 IOC3 MA2 'H' GND IOC2 MA3 DQM1# MA1 DQM0# MA0 IOC1 GND Vcc INT2# SCL SDA INT1# INT0# RSTOUT# RSTIN# MODE PCLK GNT# REQ# AD31 AD30 GND
V321USC
MIPS Mode
208 1 53 52 Vcc AD29 AD28 AD27 AD26 AD25 AD24 C_BE3# GND IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 GND Vcc AD16 C_BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# GND PERR# SERR# PAR C_BE1# AD15 AD14 AD13 GND Vcc AD12 AD11 AD10 AD9 AD8 C_BE0# AD7 GND AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND
GND MAD0 SYSAD1 MAD1 SYSAD2 MAD2 SYSAD3 MAD3 SYSAD4 Vcc GND MAD4 SYSAD5 MAD5 SYSAD6 MAD6 SYSAD7 MAD7 SYSAD8 GND MAD8 SYSAD9 MAD9 SYSAD10 MAD10 SYSAD11 MAD11 SYSAD12 Vcc GND MAD12 SYSAD13 MAD13 SYSAD14 MAD14 SYSAD15 MAD15 WRRDY# VALIDIN# GND VALIDOUT# RELEASE# SYSCMD0 SYSCMD1 SYSCMD2 SYSCMD3 SYSCMD4 SYSCMD5 SYSCMD6 SYSCMD7 SYSCMD8 Vcc
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
* * * *
11
V320USC Universal System Controller Rev. G
MIPSTM Mode Pinout Table
Table 20: Pin Assignments for MIPSTM Mode
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Signal VCC AD29 AD28 AD27 AD26 AD25 AD24 C/BE3 GND IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 GND Vcc AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP GND PERR SERR PAR C/BE1 AD15 AD14 AD13 GND Vcc AD12 AD11 AD10 AD9 AD8 C/BE0 Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Signal Vcc SYSCMD8 SYSCMD7 SYSCMD6 SYSCMD5 SYSCMD4 SYSCMD3 SYSCMD2 SYSCMD1 SYSCMD0 RELEASE VALIDOUT GND VALIDIN WRRDY MAD15 SYSAD15 MAD14 SYSAD14 MAD13 SYSAD13 MAD12 GND Vcc SYSAD12 MAD11 SYSAD11 MAD10 SYSAD10 MAD9 SYSAD9 MAD8 GND SYSAD8 MAD7 SYSAD7 MAD6 SYSAD6 MAD5 SYSAD5 MAD4 GND Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Signal Vcc SYSAD0 MAD31 SYSAD31 MAD30 SYSAD30 MAD29 SYSAD29 MAD28 GND SYSAD28 MAD27 SYSAD27 MAD26 SYSAD26 MAD25 SYSAD25 MAD24 Vcc GND SYSAD24 MAD23 SYSAD23 MAD22 SYSAD22 MAD21 SYSAD21 MAD20 SYSAD20 CH LCLK GND Vcc MAD19 SYSAD19 MAD18 SYSAD18 MAD17 SYSAD17 MAD16 MA14 GND Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 Signal Vcc CAS IOC11 RAS IOC10 MA13 IOC9 MA12 MA11 GND INT3 MA10 MA9 IOC8 MA8 IOC7 MA6 IOC6 GND Vcc MA7 IOC5 MA5 IOC4 MA4 IOC3 MA2 'H' GND IOC2 MA3 DQM1 MA1 DQM0 MA0 IOC1 GND Vcc INT2 SCL SDA INT1
12 * www.quicklogic.com *
* * *
*
(c) 2005 QuickLogic Corporation
V320USC Universal System Controller Rev. G Table 20: Pin Assignments for MIPSTM Mode (Continued)
Pin 43 44 45 46 47 Signal AD7 GND AD6 AD5 AD4 Pin 95 96 97 98 99 Signal Vcc SYSAD4 MAD3 SYSAD3 MAD2 Pin 147 148 149 150 151 Signal SYSAD16 IOC0 DQM3 DQM2 DCS3 Pin 199 200 201 202 203 Signal INT0 RSTOUT RSTIN MODE0 PCLK
48 49
50 51 52
AD3 AD2
AD1 AD0 GND
100 101
102 103 104
SYSAD2 MAD1
SYSAD1 MAD0 GND
152 153
154 155 156
DCS2 DCS1
DCS0 MWE GND
204 205
206 207 208
GNT REQ
AD31 AD30 GND
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
* * * *
13
V320USC Universal System Controller Rev. G
208-pin EIAJ PQFP in SH3/4 Mode Pinout Diagram
Figure 5: Pinout for 208-pin EIAJ PQFP in SH3/4 Mode (top view)
GND RD/WR# DCS0# DCS1# DCS2# DCS3# DQMUL#/WE2# DQMUU#/WE3# IOC0 NC GND A16 D16 A17 D17 A18 D18 A19 D19 Vcc GND LCLK CH# A20 D20 A21 D21 A22 D22 A23 D23 A24 GND Vcc D24 A25 D25 A26/CS0# D26 A27/CS1# D27 A28/CS2# GND D28 A29/CS3# D29 A30/CS4# D30 CS5# D31 A0 Vcc
156 157 105 104
Vcc CAS# IOC11 RAS# IOC10 A15 IOC9 A14 A13 GND INT3# A12 A11 IOC8 A10 IOC7 A8 IOC6 GND Vcc A9 IOC5 A7 IOC4 A6 IOC3 A4 'H' GND IOC2 A5 DQMLU#/WE1# A3 DQMLL#/WE0# A2 IOC1 GND Vcc INT2# SCL SDA INT1# INT0# RSTOUT# RSTIN# MODE0 PCLK GNT# REQ# AD31 AD30 GND
V321USC
SH3/4 Mode
208 1 53 52
GND D0 A1 D1 NC D2 NC D3 NC Vcc GND D4 NC D5 NC D6 NC D7 NC GND D8 NC D9 NC D10 NC D11 NC Vcc GND D12 NC D13 NC D14 NC D15 BREQ# WAIT#/RDY# GND BS# BACK# RBE0# RBE1# RBE2# RBE3# RBE_EN# BREQ_IN# H MODE2 MODE1 Vcc
14 * www.quicklogic.com *
* * *
*
Vcc AD29 AD28 AD27 AD26 AD25 AD24 C_BE3# GND IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 GND Vcc AD16 C_BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# GND PERR# SERR# PAR C_BE1# AD15 AD14 AD13 GND Vcc AD12 AD11 AD10 AD9 AD8 C_BE0# AD7 GND AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND
(c) 2005 QuickLogic Corporation
V320USC Universal System Controller Rev. G
SH3/4 Mode Pinout Table
Table 21: Pin Assignments for SH3/4 Mode
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Signal Vcc AD29 AD28 AD27 AD26 AD25 AD24 C/BE3 GND IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 GND Vcc AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP GND PERR SERR PAR C/BE1 AD15 AD14 AD13 GND Vcc AD12 AD11 AD10 AD9 AD8 C/BE0 Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Signal Vcc MODE1 MODE2 'H' BREQ_IN RBE_EN RBE3 RBE2 RBE1 RBE0 BACK BS GND WAIT/RDY BREQ D15 NC D14 NC D13 NC D12 GND Vcc NC D11 NC D10 NC D9 NC D8 GND NC D7 NC D6 NC D5 NC D4 GND Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 Signal Vcc A0 D31 A31/CS5 D30 A30/CS4 D29 A29/CS3 D28 GND A28/CS2 D27 A27/CS1 D26 A26/CS0 D25 A25 D24 Vcc GND A24 D23 A23 D22 A22 D21 A21 D20 A20 CH LCLK GND Vcc D19 A19 D18 A18 D17 A17 D16 A16 GND Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 Signal Vcc CAS IOC11 RAS IOC10 A15 IOC9 A14 A13 GND INT3 A12 A11 IOC8 A10 IOC7 A8 IOC6 GND Vcc A9 IOC5 A7 IOC4 A6 IOC3 A4 'H' GND IOC2 A5 DQMLU/WE1 A3 DQMLL/WE0 A2 IOC1 GND Vcc INT2 SCL SDA INT1
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
* * * *
15
V320USC Universal System Controller Rev. G Table 21: Pin Assignments for SH3/4 Mode (Continued)
Pin 43 44 45 46 47 48 49 50 51 52 Signal AD7 GND AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND Pin 95 96 97 98 99 100 101 102 103 104 Signal Vcc NC D3 NC D2 NC D1 A1 D0 GND Pin 147 148 149 150 151 152 153 154 155 156 Signal NC IOC0 DQMUU/WE3 DQMUL/WE2 DCS3 DCS2 DCS1 DCS0 RD/WR GND Pin 199 200 201 202 203 204 205 206 207 208 Signal INT0 RSTOUT RSTIN MODE0 PCLK GNT REQ AD31 AD30 GND
16 * www.quicklogic.com *
* * *
*
(c) 2005 QuickLogic Corporation
V320USC Universal System Controller Rev. G
Packaging Drawing
Figure 6: 208-pin EIAJ PQFP Mechanical Details
4.20MAX
30.60.4SQ 28.0 TYP SQ 156 157 105 104
3.35TYP
DETAIL OF "P"
0MIN (0.8) 1.3TYP
0.15TYP INDEX 208 52 PIN No.1 0.5 TYP 0.20.1 53
"P"
0 - 12
Contact Information
Phone: (408) 990-4000 (US) (416) 497-8884 (Canada) +(44) 1932 57 9011 (Europe - except Germany/Benelux) +(49) 89 930 86 170 (Germany/Benelux) +(86) 21 6867 0273 (Asia - except Japan) +(81) 45 470 5525 (Japan) E-mail: Sales: info@quicklogic.com www.quicklogic.com/sales
Support: www.quicklogic.com/support Internet: www.quicklogic.com
0.50.2
(c) 2005 QuickLogic Corporation
www.quicklogic.com * *
* * * *
17
V320USC Universal System Controller Rev. G
Revision History
Revision 0.8 0.9 1.00 1.01 1.02 F G Date Dec 98 Jan 99 Mar 99 Apr 99 June 99 July 2004 July 2005 Originator and Comments First pre-silicon revision of preliminary data sheet. First pre-silicon release with Super-HTM processor information. Remove "Preliminary" watermark; Update Table 2: Pin Types; Update Table 3: Signal Descriptions; Update Table 9: Local Bus Signals DC Operating Specifications. Update diagrams; update tables, register data; add M bus data. Update diagrams, update tables, and update register data for B1 step. Bernhard Andretzky and Kathleen Murchek Update to QuickLogic format standards. Mehul Kochar and Kathleen Murchek Updated Product Code table to include item V320USC-75LPN REV B1.
Copyright and Trademark Information
Copyright (c) 2005 QuickLogic Corporation. All Rights Reserved. The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, QuickRAM, QuickPCI and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, EclipsePlus, Eclipse II, QuickFC, QuickDSP, QuickDR, QuickSD, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation.
18 * www.quicklogic.com *
* * *
*
(c) 2005 QuickLogic Corporation

▲Up To Search▲

Price & Availability of V320DS

	To Download V320DS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .