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| Features * * * * * * * * * * * * * * * 12.4 SPECint95, 8.4 SPECfp95 at 266 MHz (TSPC750A) with 1 MB L2 at 133 MHz 11.5 SPECint95, 6.9 SPECfp95 at 266 MHz (TSPC740A) 488 MIPS at 266 MHz Selectable Bus Clock (11 CPU Bus Dividers up to 8x) PD Typical 4.2 W at 200 MHz, Full Operating Conditions Nap, Doze and Sleep Modes for Power Savings Superscalar (3 Instructions per Clock Cycle) 4-GByte Direct Addressing Range 64-bit Data and 32-bit Address Bus Interface 32 KB Instruction and Data Cache Six Independent Execution Units and Two Register Files Write-back and Write-through Operations fint max = 266 MHz fbus max = 83.3 MHz Compatible CMOS Input / TTL Output Description The TSPC750A and TSPC740A microprocessor (after named 750A/740A) are lowpower implementations of the PowerPC Reduced Instruction Set Computer (RISC) architecture. The 750A/740A microprocessors' designs are superscalar, capable of issuing three instructions per clock cycle into six independent execution units. The 740A/750A microprocessors use a 2.6/3.3V CMOS process technology and maintain full interface compatibility with TTL devices. The 750A/740A provide four software controllable power-saving modes and a thermal assist unit management. The 750A/740A microprocessors have separate 32K byte, physically-addressed instruction and data caches and differ only in that the 750A features a dedicated L2 cache interface with L2 on-chip tags. Both are software and bus-compatible with the PowerPC 603TM and PowerPC 604TM families, and are fully JTAG compliant. The TSPC740A microprocessor is pin compatible with the TSPC603e family. PowerPC 750A/740A RISC Microprocessor Family PID8t750A/740A Specification TSPC750A/740A G suffix CBGA255 and CBGA360 Ceramic Ball Grid Array GS suffix CI-CBGA255 and CI-CBGA360 Ceramic Ball Grid Array with Solder Column Interposer (SCI) Rev. 2128A-HIREL-01/02 1 Screening This product is manufactured in full compliance with: * * * CBGA upscreenings based upon ATMEL-Grenoble standards Full military temperature range (Tc = -55C,+125C) Industrial temperature range (Tc = -40C, +110C) CI-CGA versions of TSPC740A and TSPC750A (planned) The TSPC750A is targeted for low power systems and supports the following power management features -- doze, nap, sleep, and dynamic power management. The TSPC750A consists of a processor core and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus. Simplified Block Diagram Figure 1. TSPC750A Block Diagram Instruction Fetch Branch Unit Contr l Unit o Completion 32K ICache System Unit Dispatch BHT/BTIC GPRs FXU1 FXU2 Rename Buffers LSU FPRs Rename Buffers FPU 32K DCache L2 Tags L2 Cache BIU 60x BIU 2 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A General Parameters Technology Die Size Transistor Count Logic Design Packages L2 The general parameters of the 750A/740A are the following: 0.29 mm CMOS, five-layer metal 7.56 mm x 8.79 mm (67 mm2) 6.35 million Fully-static 740A: Surface mount 255 ceramic ball grid array (CBGA) and column interposer ceramic grid array CI-CGA without L2interface 750A: Surface mount 360 ceramic ball grid array (CBGA) and column interposer ceramic grid array CI-CGA with L2 interface Core Power Supply I/O Power Supply 2.6V 100 mV 3.3V 5% VDC Except L2 cache interface that is not supported by the PowerPC version, the major features implemented in the PowerPC 750A architecture are as follows: * * * * * Internal L2 cache controller and 4K-entry tags; external data SRAMs 256K, 512K, and 1-Mbyte 2-way set associative L2 cache support Copy-back or write-through data cache (on a page basis, or for all L2) 64-byte (256K/512K) and 128-byte (1-Mbyte) sectored line size Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs Core-to-L2 frequency divisors of /1, /1.5, /2, /2.5, and /3 supported Four instructions fetched per clock One branch processed per cycle (plus resolving 2 speculations) Up to 1 speculative stream in execution, 1 additional speculative stream in fetch 512-entry branch history table (BHT) for dynamic prediction 64-entry, 4-way set associative branch target instruction cache (BTIC) to minimize branch delay slots Full hardware detection of dependencies (resolved in the execution units) Dispatch two instructions to six independent units (system, branch, load/store, fixedpoint unit 1, fixed-point unit 2, or floating-point) Serialization control (predispatch, postdispatch, execution serialization) One cycle load or store cache access (byte, half-word, word, double-word) Effective address generation Hits under misses (one outstanding miss) Single-cycle misaligned access within double word boundary Alignment, zero padding, sign extend for integer register file Floating-point internal format conversion (alignment, normalization) Sequencing for load/store multiples and string operations Store gathering Cache and TLB instructions Features Level 2 (L2) Cache Interface (not implemented on TSPC740A) * Branch Processing Unit * * * * * Dispatch Unit * * * Load/Store Unit * * * * * * * * * 3 2128A-HIREL-01/02 * * Fixed-point Units * * * * * Bus Interface * * * * Big- and little-endian byte addressing supported Misaligned little-endian support in hardware Fixed-point unit 1 (FXU1)-multiply, divide, shift, rotate, arithmetic, logical Fixed-point unit 2 (FXU2)-shift, rotate, arithmetic, logical Single-cycle arithmetic, shift, rotate, logical Multiply and divide support (multi-cycle) Early out multiply Compatible with 60x processor interface 32-bit address bus 64-bit data bus Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x supported Register file access Forwarding control Partial instruction decode Support for IEEE-754 standard single- and double-precision floating-point arithmetic 3 cycle latency, 1 cycle throughput, single-precision multiply-add 3 cycle latency, 1 cycle throughput, double-precision add 4 cycle latency, 2 cycle throughput, double-precision multiply-add Hardware support for divide Hardware support for denormalized numbers Time deterministic non-IEEE mode Executes CR logical instructions and miscellaneous system instructions Special register transfer instructions 32K, 32-byte line, 8-way set associative instruction cache 32K, 32-byte line, 8-way set associative data cache Single-cycle cache access Pseudo-LRU replacement Copy-back or write-through data cache (on a page per page basis) Supports all PowerPC memory coherency modes Non-blocking instruction and data cache (one outstanding miss under hits) No snooping of instruction cache 128 entry, 2-way set associative instruction TLB 128 entry, 2-way set associative data TLB Hardware reload for TLBs 4 instruction BATs and 4 data BATs Virtual memory support for up to 4 hexabytes (252) of virtual memory Real memory support for up to 4 gigabytes (232) of physical memory Decode * * * Floating-point Unit * * * * * * * System Unit * * Cache Structure * * * * * * * * Memory Management Unit * * * * * * 4 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Testability * * Integrated Power Management * * * Integrated Thermal Management Assist Unit Reliability and Serviceability * * * LSSD scan design JTAG interface Low-power 2.6/3.3V design Three static power saving modes: doze, nap, and sleep Automatic dynamic power reduction when internal functional units are idle On-chip thermal sensor and control logic Thermal Management Interrupt for software regulation of junction temperature. Parity checking on 60x and L2 cache buses Pin Assignments TSPC740A Package The pinout of the TSPC740A, 255 CBGA and CI-CGA packages as viewed from the top surface. 5 2128A-HIREL-01/02 Figure 2. Pinout of TSPC740A, CBGA and CI-CGA Packages as Viewed from the Top Surface 12345678 A B C D E F G H J K L M N P R T Not to Scale View Substrate Encapsulant Die CBGA255 9 1 0 11 1 2 1 3 1 4 1516 Not to scale Substrate Assembly Encapsulant View Die CI-CGA255 TSPC750A Package The pinout of the TSPC750A, 360 CBGA and CI-CGA packages as viewed from the top surface. 6 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Figure 3. Pinout of TSPC750A, CBGA and CI-BGA Packages as Viewed from the Top Surface Pin A1 index TSXP750AVGU 12LH GND VDD 0VDD L20VDD A B C D E F G H J K L M N P R T U V W Not to Scale 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 1718 19 0VDD VDD GND S23670W002 L20VDD View Substrate Assembly Encapsulant Die CBGA360 Not to scale Substrate Assembly Encapsulant View Die CI- CGA360 Pinout Listings Table 1. Pinout Listing for the TSPC740A, 255 CBGA and CI-CGA Packages Signal Name A[0-31] AACK ABB AP[0-3] ARTRY Pin Number C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1, F14, J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1 L2 K4 C1, B4, B3, B2 J4 Active High Low Low High Low I/O I/O Input I/O I/O I/O 7 2128A-HIREL-01/02 Table 1. Pinout Listing for the TSPC740A, 255 CBGA and CI-CGA Packages (Continued) Signal Name AVDD BG BR CI CKSTP_IN CKSTP_OUT CLK_OUT DBB DBG DBDIS DBWO DH[0-31] DL[0-31] Pin Number A10 L1 B6 E1 D8 A6 D7 J14 N1 H15 G4 P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9, P8, N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4 M2, L3, N2, L4, R1, P2, M4, R2 G16 F1 C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7, H10, H12, J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12 A7 B15 (1) Active Low Low Low Low Low Low Low Low Low High High I/O Input Output Output Input Output Output I/O Input Input Input I/O I/O DP[0-7] DRTRY GBL GND High Low Low - I/O Input I/O - HRESET INT L1_TSTCLK Low Low High High Low Low High Low Low Low Low Low - Input Input Input Input Input Input Input Input Output Output Input Input Input D11 D12 B10 C13 B7, B8, C3, C6, C8, D5, D6, H4, J16, A4, A5, A2, A3, B1, B5 C7, E5, E7, E10, E12, G3, G5, G12, G14, K3, K5, K12, K14, M5, M7, M10, M12, P7, P10 A8, B9, A9, D9 D3 J3 D1 A16 B14 C9 L2_TSTCLK(1) LSSD_MODE MCP NC (No-Connect) OVDD PLL_CFG[0-3] QACK QREQ RSRV SMI SRESET SYSCLK (1) 8 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Table 1. Pinout Listing for the TSPC740A, 255 CBGA and CI-CGA Packages (Continued) Signal Name TA TBEN TBST TCK TDI TDO TEA TLBISYNC TMS TRST TS TSIZ[0-2] TT[0-4] WT VDD 2 VOLTDET 3 Notes: Pin Number H14 C2 A14 C11 A11 A12 H13 C4 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D2 F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9, L11 F3 Active Low High Low High High High Low Low High Low Low High High Low High I/O Input Input I/O Input Input Output Input Input Input Input I/O Output I/O Output Output 1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. 2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core. 3. Internally tied to GND in the TSPC740A CBGA package to indicate to the power supply that a low-voltage processor is present. This signal is not a power supply input. Table 2. Pinout Listing for the TSPC750A, 360 CBGA and CI-CGA Packages Signal Name A[0-31] AACK ABB AP[0-3] ARTRY AVDD BG BR CKSTP_OUT CI CKSTP_IN CLKOUT DBB Pin Number A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2 N3 L7 C4, C5, C6, C7 L6 A8 H1 E7 D7 C2 B8 E3 K5 Active High Low Low High Low Low Low High Low High Low I/O I/O Input I/O I/O I/O Input Output Output Output Input Output I/O 9 2128A-HIREL-01/02 Table 2. Pinout Listing for the TSPC750A, 360 CBGA and CI-CGA Packages (Continued) Signal Name DBDIS DBG DBWO DH[0-31] DL[0-31] DP[0-7] DRTRY GBL GND Pin Number G1 K1 D1 W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3, U4, R5 M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2, V3, U3, W2 L1, P2, M2, V2, M1, N2, T3, R1 H6 B1 D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16 B6 C11 (1) Active Low Low Low High High High Low Low - I/O Input Input Input I/O I/O I/O Input I/O - HRESET INT L1_TSTCLK Low Low High High Low Low Low High Input Input Input Output Output Output Output I/O F8 L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18, H17, J14, J13, H19, G18 L13 P17 N15 L16 U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18, V18, U18, V19, U19, T18, T17, R19, R18, R17, R15, P19, P18, P13, N14, N13, N19, N17, M17, M13, M18, H13, G19, G16, G15, G14, G13, F19, F18, F13, E19, E18, E17, E15, D19, D18, D17, C18, C17, B19, B18, B17, A18, A17, A16, B16, C16, A14, A15, C15, B14, C14, E13 V14, U16, T19, N18, H14, F17, C19, B15 D15, E14, E16, H16, J15, L15, M16, P15, R14, R16, T15, F15 L14 M14 F7 N16 G17 F9 B11 B3, B4, B5, A19, W19, W1, K9, K11 (4) , K19 (4) L2ADDR[0-16] L2AVDD L2CE L2CLKOUTA L2CLKOUTB L2DATA[0-63] L2DP[0-7] L2OVDD L2SYNC_IN L2SYNC_OUT L2_TSTCLK L2WE L2ZZ LSSD_MODE(1) MCP NC (No-Connect) OVDD (1) High High High High Low High Low Low - I/O Input Output Input Output Output Input Input - D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4, R6, R9, R11, T5, T8, T12 10 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Table 2. Pinout Listing for the TSPC750A, 360 CBGA and CI-CGA Packages (Continued) Signal Name PLL_CFG[0-3] QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TCK TDI TDO TEA TLBISYNC TMS TRST TS TSIZ[0-2] TT[0-4] WT VDD (2) VOLTDET (3) Notes: Pin Number A4, A5, A6, A7 B2 J3 D3 A12 E10 H9 F1 A2 A11 B10 B7 D9 J1 A3 C8 A10 K7 A9, B9, C9 C10, D11, B12, C12, F11 C3 G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12 K13 Active High Low Low Low Low Low Low High Low High High High Low Low High Low Low High High Low High I/O Input Input Output Output Input Input Input Input Input I/O Input Input Output Input Input Input Input I/O Output I/O Output Output 1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. 2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core. 3. Internally tied to L2OVDD in the TSPC750A packages ATMEL-Grenoble to indicate the power present at the L2 cache interface. This signal is not a power supply input. Caution: this is different from the TSPC740A packages. 4. These pins are reserved for potential future use as additional L2 address pins. 11 2128A-HIREL-01/02 Signal Description Figure 4. TSPC750A Microprocessor Signal Groups L2VDD L2AVDD BR ADDRESS ARBITRATION BG ABB TS A[0-31] ADDRESS BUS AP[0-3] Not supported in the TSPC740A 1 1 1 17 64 8 1 1 2 1 1 L2ADDR 160 L2DATA 063 L2DP 07 L2CE L2WE L2CLKOUT AB L2SYNC_OUT L2SYNC_IN L2ZZ INT SMI MCP SRESET HRESET CKSTP_IN CKSTP_OUT RSRV TBEN TLBISYNC QREQ QACK SYSCLK, PLL_CFG 03 CLK_OUT INTERRUPTS RESET L2 CACHE CLOCK/CONTROL L2 CACHE ADDRESS/ DATA ADDRESS START 1 32 4 TT[0-4] TBST TS1Z[0-2] GBL TRANSFER ATTRIBUTE WT CI 5 1 3 1 1 1 1 1 1 1 1 1 1 TSPC750A 1 1 1 AACK ADDRESS TERMINATION ARTRY DBG DATA ARBITRATION DBWO DBB D 063 DP 07 DBDIS 1 1 1 1 1 64 8 1 1 1 1 4 1 PROCESSOR STATUS CONTROL CLOCK CONTROL DATA TRANSFER 5 3 JTAG:COP Factory Test TEST INTERFACE DATA TERMINATION TA DRTRY TEA 1 1 1 VDD VDD(I:O) AVDD 12 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Scope Applicable Documents Requirements General Design and Construction Terminal Connections Depending on the package, the terminal connections shall be is shown in Table 1, Table 2 and Figure 4. The microcircuits are in accordance with the applicable documents and as specified herein. This drawing describes the specific requirements for the microprocessor TSPC750A, in compliance with ATMEL-Grenoble standard screening. 1. MIL-STD-883: Test methods and procedures for electronics. 2. MIL-PRF-38535 appendix A: General specifications for microcircuits. Absolute Maximum Rating Table 3. Absolute Maximum Ratings Characteristic Core Supply Voltage PLL Supply Voltage L2 DLL Supply Voltage 60x Bus Supply Voltage L2 Bus Supply Voltage Input Voltage Storage Temperature Range Notes: Symbol VDD AVDD L2AVDD OVDD L2OVDD VIN TSTG Value -0.3 to 2.75 (4) -0.3 to 2.75 (4) -0.3 to 2.75 (4) -0.3 to 3.6 (3.5) -0.3 to 3.6 (3.5) -0.3 to 3.6 (2) -55 to 150 Unit V V V V V V C 1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: VIN must not exceed OVDD by more than 0.3V at any time including during power-on reset. 3. Caution: OVDD must not exceed VDD/AVDD by more than 1.2V at any time including during power-on reset. 4. Caution: VDD/AVDD must not exceed OVDD by more than 0.4V at any time including during power-on reset. 5. Caution: VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 5. 13 2128A-HIREL-01/02 Figure 5 shows the allowable undershoot and overshoot voltage on the TSPC750A and TSPC 740A. Figure 5. Overshoot/Undershoot Voltage 4V (L2) OVDD + 5% (L2) OVDD VIH VIL Gnd Gnd 0.3V Gnd 1.0V Not to exceed 10% of tSYSCLK Recommended Operating Conditions Table 4. Recommended Operating Conditions Characteristic Core Supply Voltage PLL Supply Voltage L2 DLL Supply Voltage 60x Bus Supply Voltage L2 Bus Supply Voltage Input Voltage Junction Temperature Note: Symbol VDD AVDD L2AVDD OVDD L2OVDD VIN Tj Value 2.5 to 2.7 2.5 to 2.7 2.5 to 2.7 3.135 to 3.465 3.135 to 3.465 GND to OVDD -55 to +125 Unit V V V V V V C 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 14 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Thermal Characteristics Table 5. Package Thermal Characteristics Characteristic CBGA and CI-CGA packages thermal resistance, junction-to-case thermal resistance (typical) CBGA package thermal resistance, die junction-to-lead thermal resistance (typical) CI-CGA package thermal resistance, die junction-to-lead thermal resistance (typical) Symbol JC JB JB Value 0.03 3.8 4 Rating C/W C/W C/W The board designer can choose between several types of heat sinks to place on the TSPC750A. There are several commercially-available heat sinks for the TSPC750A provided by the following vendors: For the exposed-die packaging technology, shown in Table 5, the intrinsic conduction thermal resistance paths are as follows: * * The die junction-to-case (or top-of-die for exposed silicon) thermal resistance The die junction-to-ball thermal resistance Figure 6 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. Figure 6. C4 Package with Heat Sink Mounted to a Printed-Circuit Board External Resistance Radiation Convection Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads Printed Circuit Board External Resistance Radiation Convection (Note the internal versus external package resistance) Thermal Management Assistance The TSPC750A incorporates a thermal management assist unit (TAU) composed of a thermal sensor, digital-to-analog converter, comparator, control logic, and dedicated special-purpose registers (SPRs). Specifications for the thermal sensor portion of the TAU are found in Table 6. More information on the use of this feature is given in the MPC750A RISC Microprocessor User's manual. 15 2128A-HIREL-01/02 Table 6. Thermal Sensor Specifications VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, 0 Tj < +125C Num 1 2 3 Notes: Characteristic Temperature Range Comparator Settling Time Resolution Min 0 20 4 Max 127 Unit C s C Notes 1 2 3 1. The temperature is the junction temperature of the die. The thermal assist unit's raw output does not indicate an absolute temperature, but it must be interpreted by software to derive the absolute junction temperature. For information about the use and calibration of the TAU, see the Motorola application note AN1800/D "programming the thermal Assist Unit in the MPC750A Microprocessor. This specification reflects the temperature span supported by design. 2. The comparator settling time value must be converted into the number of CPU clocks that need to be written into the THRM3 SPR. 3. Guaranteed by design and characterization. Thermal Management Information This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods-adhesive, spring clip to holes in the printed circuit board or package, and mounting clip and screw assembly; see Figure 7. This spring force should not exceed 5.5 pounds of force. Figure 7. Package Exploded Cross-Sectional View with Several Heat Sink Options Heat Sink CBGA Package Heat Sink Clip Adhesive or Thermal Interface Material Printed Circuit Board Option Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 16 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Adhesives and Thermal Interface Materials Figure 8. Thermal Performance of Select Thermal Interface Material 2 Silicone Sheet (0.006 inch) Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease SpecificThermal Resistance (Kin2/W) 1.5 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi) A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 8 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printedcircuit board (see Figure 7). This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. 17 2128A-HIREL-01/02 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ta + Tr + (jc + int + sa) * Pd Where: Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation the die-junction temperatures (Tj) should be maintained less than the value specified in Table 4. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30 to 40C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10C. The thermal resistance of the thermal interface material (int) is typically about 1C/W. Assuming a Ta of 30C, a Tr of 5C, a CBGA package jc = 2.2, and a power consumption (Pd) of 4.5 watts, the following expression for Tj is obtained: Die-junction temperature: Tj = 30C + 5C + (2.2C/W + 1.0C/W + sa) * 4.5 W For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (sa) versus airflow velocity is shown in Figure 9. Figure 9. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity 8 Thermalloy #2328B Pinfin Heat Sink 7 HeatSink Thermal Resistance (C/W) (25 x 28 x 15 mm) 6 5 4 3 2 1 0.5 1 1.5 2 2.5 Approach AirVelocity(m/s) 3 3.5 18 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 7C/W, thus Tj = 30C + 5C + (2.2C/W +1.0C/W + 7C/W) * 4.5 W, resulting in a die-junction temperature of approximately 81C which is well within the maximum operating temperature of the component. Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering, and Aavid Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature-airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. To expedite system-level thermal analysis, several "compact" thermal-package models are available within FLOTHERM(R). These are available upon request. Power Consideration Power Management The TSPC750A provides four power modes, selectable by setting the appropriate control bits in the MSR and HIDO registers. The four power modes are as follows: * Full-power: This is the default power state of the TSPC750A. The TSPC750A is fully powered and the internal functional units are operating at the full processor clock speed. If the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution, or external hardware. Doze: All the functional units of the TSPC750A are disabled except for the time base/decrementer registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or machine check brings the TSPC750A into the full-power state. The TSPC750A in doze mode maintains the PLL in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to the full-power state takes only a few processor clock cycles. Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the PLL in a powered state. The TSPC750A returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or a machine check input (MCP). A return to full-power state from a nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK is negated, the processor is put in doze mode to support snooping. * * 19 2128A-HIREL-01/02 * Sleep: Sleep mode minimizes power consumption by disabling all internal functional units, after which external system logic may disable the PPL and SUSCLK. Returning the TSPC750A to the full-power state requires the enabling of the PPL and SYSCLK, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset, or a machine check input (MCP) signal after the time required to relock the PPL. Power Dissipation Table 7. Power Consumption VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, -55 Tj < 125C Processor (CPU) Frequency 200 MHz Full-On Mode Typical Maximum Doze Mode Maximum Nap Mode Maximum Sleep Mode Maximum Sleep Mode--PLL and DLL Disabled Typical Maximum Notes: 30 60 50 100 50 100 mW mW 1, 3 1, 2 300 300 300 mW 1, 2 250 250 250 mW 1, 2 1.6 1.8 2.1 W 1, 2 4.2 6.0 5.0 7.0 5.7 7.9 W W 1, 3, 4 1, 2, 4 233 MHz 266 MHz Unit Notes 1. These values apply for all valid 60x bus and L2 bus ratios. The values do not include I/O Supply Power (OVDD and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but is typically <10% of VDD power. Worst case power consumption for AVDD = 15 mw and L2AVDD = 15 mW. 2. Maximum power is measured at VDD = 2.7V 3. Typical power is an average value measured at VDD = AVDD = L2AVDD = 2.6V, OVDD = L2OVDD = 3.3V in a system executing typical applications and benchmark sequences. 4. Full-On mode is measured using worst-case instruction sequence. Electrical Characteristics Static Characteristics Table 8. DC Electrical Specifications VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, -55 Tj < 125C Characteristic Input High Voltage (all inputs except SYSCLK) Input Low Voltage (all inputs except SYSCLK) SYSCLK Input High Voltage Symbol VIH VIL CVIH Min 2 GND 2.4 Max 3.465 0.8 3.465 Unit V V V 1 Notes 1,2 20 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Table 8. DC Electrical Specifications VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, -55 Tj < 125C Characteristic SYSCLK Input Low Voltage Input Leakage Current, VIN = OVDD Hi-Z (off-state) Leakage Current, VIN = OVDD Output High Voltage, IOH = -6 mA Output Low Voltage, IOL = 6 mA Capacitance, VIN = 0V, f = 1 MHz Notes: 1. 2. 3. 4. Symbol CVIL Iin ITSI VOH VOL Cin Min GND 2.4 Max 0.4 30 30 0.4 5.0 Unit V A A V V pF 2, 3 1, 2 1, 2,4 Notes For 60x bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals. Capacitance is periodically sampled rather than 100% tested. The leakage is measured for nominal OVDD and VDD, or both OVDD and VDD must vary in the same direction (for example, both OVDD and VDD vary by either +5% or -5%). Dynamic Characteristics After fabrication, parts are sorted by maximum processor core frequency as shown in "Clock AC Specifications" and tested for conformance to the AC specifications for that frequency. These specifications are for 200, 233, and 266 MHz processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0-3] signals. Parts are sold by maximum processor core frequency. Table 9 provides the clock AC timing specifications as defined in Figure 9. Clock AC Specifications Table 9. Clock AC Timing Specifications VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, -55 Tj < 125C 200 MHz Num Characteristic Processor Frequency VCO Frequency SYSCLK Frequency 1 2, 3 4 SYSCLK Cycle Time SYSCLK Rise and Fall Time SYSCLK Duty Cycle Measured at 1.4V SYSCLK Jitter Internal PLL Relock Time Notes: Min 150 300 25 12 40 Max 200 400 83.3 40 2 60 233 MHz Min 150 300 25 12 40 Max 233 466 83.3 40 2 60 266 MHz Min 150 300 25 12 40 Max 266 533 83.3 40 2 60 Unit MHz MHz MHz ns ns % ps s 2 3 4 5 1 Notes 150 100 150 100 150 100 1. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description in "PLL Configuration," for valid PLL_CFG[0-3] settings 2. Rise and fall times for the SYSCLK input are measured from 0.4 to 2.4V. 3. Timing is guaranteed by design and characterization. 4. The total input jitter (short term and long term combined) must be under 150 ps. 5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. 21 2128A-HIREL-01/02 Figure 10 provides the SYSCLK input timing diagram. Figure 10. SYSCLK Input Timing Diagram 1 4 SYSCLK VM VM 4 CVIH VM CVIL VM = Midpoint Voltage (1.4V) 2 3 60x Bus Input AC Specifications Table 10 provides the 60x bus input AC timing specifications for the TSPC750A as defined in Figure 11 and Figure 12. Input timing specifications for the L2 bus are provided in L2 Bus Input AC Specifications. Table 10. 60x Bus Input AC Timing Specifications(1) VDD =AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, -55 Tj < 125C 200, 233, 266 MHz Num 10a 10b 10c 11a 11b 11c Notes: Characteristic Address/Data/Transfer Attribute Inputs Valid to SYSCLK (Input Setup) All Other Inputs Valid to SYSCLK (Input Setup) Mode select input setup to HRESET (DRTRY, TLBISYNC) SYSCLK to Address/Data/Transfer Attribute Inputs Invalid (Input Hold) SYSCLK to All Other Inputs Invalid (Input Hold) HRESET to mode select input hold (DRTRY, TLBISYNC) Min 2.5 3.0 8 1.0 1.0 0 Max Unit ns ns tsysclk ns ns ns Notes 2 3 4, 5, 6, 7 2 3 4, 6, 7 1. All input specifications are measured from the TTL level (0.8 to 2.0V) of the signal in question to the 1.4V of the rising edge of the input SYSCLK. Input and output timings are measured at the pin. 2. Address/Data/Transfer Attribute inputs are composed of the following -- A[0-31], AP[0-3], TT[0-4], TBST, TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[0-7]. 3. All other signal inputs are composed of the following-TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. 4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 12). 5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. Guaranteed by design and characterization. 7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence. 22 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Figure 11 provides the input timing diagram for the TSPC750A. Figure 11. Input Timing Diagram SYSCLK 10a 10b 11a 11b VM ALL INPUTS VM = Midpoint Voltage (1.4V) Figure 12 provides the mode select input timing diagram for the TSPC750A. Figure 12. Mode Select Input Timing Diagram HRESET 10c VIH 11c MODE PINS VIH = 2.0V 60x Bus Output AC Specifications Table 11 provides the 60x bus output AC timing specifications for the TSPC750A as defined in Figure 13. Output timing specifications for the L2 bus are provided in L2 Bus Output AC Specifications. Table 11. 60x Bus Output AC Timing Specifications (1) VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, -55 Tj < 125C, CL = 50 pF(2) 200, 233, 266 MHz Num 12 13 14 15 16 17 18 Characteristic SYSCLK to Output Driven (Output Enable Time) SYSCLK to Output Valid (TS, ABB, ARTRY, DBB) SYSCLK to all other Outputs Valid (all except TS, ABB, ARTRY, DBB) SYSCLK to Output Invalid (Output Hold) SYSCLK to Output High Impedance (all except ABB, ARTRY, DBB) SYSCLK to ABB, DBB High Impedance after precharge SYSCLK to ARTRY High Impedance before precharge Min 0.5 1.0 Max 6.5 6.5 6.0 1.0 5.5 Unit ns ns ns ns ns tsysclk ns 5 5 3 8 4, 6, 8 8 Notes 23 2128A-HIREL-01/02 Table 11. 60x Bus Output AC Timing Specifications (Continued)(1) VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, -55 Tj < 125C, CL = 50 pF(2) 200, 233, 266 MHz Num 19 20 21 Notes: Characteristic SYSCLK to ARTRY Precharge Enable Maximum Delay to ARTRY Precharge SYSCLK to ARTRY High Impedance After Precharge Min 0.2*tsysclk +1.0 Max 1 2 Unit ns tsysclk tsysclk Notes 3, 4, 7 4, 7 4, 7, 8 1. All output specifications are measured from the 1.4V of the rising edge of SYSCLK to TTL level (0.8 V or 2.0 V) of the signal in question. Both input and output timing are measured at the pin. 2. All maximum timing specifications assume CL = 50 pF. 3. This minimum parameter assumes CL = 0 pF. 4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration of the parameter in question. 5. Output signal transitions from GND to 2.0V or OVDD to 0.8V. 6. Nominal precharge width for ABB and DBB is 0.5 tsysclk. 7. Nominal precharge width for ARTRY is 1.0 tsysclk. 8. Guaranteed by design and characterization. Figure 13. Output Timing Diagram SYSCLK VM VM VM 14 12 15 16 ALL OUTPUTS (Except TS, ABB, ARTRY, DBB) 13 13 15 16 TS 17 ABB, DBB 21 20 19 18 ARTRY VM = Midpoint Voltage (1.4V) 24 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A L2 Clock AC Specifications Table 12. L2CLK Output AC Timing Specifications VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC,-55 Tj < 125C Num Characteristic L2CLK Frequency 22 23 L2CLK Cycle Time L2CLK Duty Cycle L2CLK Jitter Internal DLL-relock Time Notes: 640 Min 80 7.5 50 Max 133 12.5 Unit MHz ns % 2 3 4 Notes 1, 5 150 - ps L2CLK 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB and L2SYNC_OUT pins. The L2 cache interface supports higher frequencies when appropriate load conditions have been considered. The L2 I/O drivers have been designed to support a 133 MHz L2 bus loaded with 4 off-the-shelf pipelined synchronous burst SRAMs. Running the L2 bus beyond 133 MHz requires tightly coupled customized SRAMs or a multi-chip module (MCM) implementation. The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. L2CLK_OUTA and L2CLK_OUTB must have equal loading. 2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage. 3. The total input jitter (short term and long term combined) must be under 150 ps. 4. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization. 5. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. 25 2128A-HIREL-01/02 The L2CLK_OUT timing diagram is shown in Figure 14. Figure 14. L2CLK_OUT Output Timing Diagram 22 L2 SingleEnded Clock Mode 23 VM VM VM L2CLK_OUTA VM VM VM L2CLK_OUTB VM VM VM L2SYNC_OUT VM = Midpoint Voltage (L2OVdd/2) L2 Differential Clock Mode L2OVdd L2CLK_OUTB VM 23 22 VM VM L2CLK_OUTA GND VM VM VM L2SYNC_OUT VM = Midpoint Voltage (L2OVdd/2) Table 13 shows the L2 bus input timing diagrams for the TSPC750A. Figure 15. L2 Bus Input Timing Diagrams 29 30 L2SYNC_IN VM 24 25 ALL INPUTS VM = Midpoint Voltage (1.4V) 26 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A L2 Bus Input AC Specifications The L2 bus input interface AC timing specifications are found in Table 13. Table 13. L2 Bus Input Interface AC Timing Specifications, see note (1) VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, -55 Tj < 125C Processor Frequency 200-266 MHz Num 29, 30 24 25 Notes: Characteristic L2SYNC_IN rise and fall time Data and parity input setup to L2SYNC_IN L2SYNC_IN to data and parity input hold Min 2.0 0.5 Max 1.0 _ Unit ns ns ns Notes 2 1. All input specifications are measured from the TTL level (0.8V or 2.0V) of the signal in question to the midpoint voltage of the rising edge of the input L2SYNC_IN. Input timings are measured at the pins (see Figure 15). 2. Rise and fall times for the L2SYNC_IN input are measured from 0.4 to 2.4V. L2 Bus Output AC Specifications Table 14 provides the L2 bus output interface AC timing specifications for the TSPC750A as defined in Figure 16. Table 14. L2 Bus Output Interface AC Timing Specifications see note (1) VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, -55 Tj < 125C, CL = 20 pF see note (3) L2CR[14-15] is equivalent to: 00 Num 26 27 28 Notes: Characteristic L2SYNC_IN to output valid L2SYNC_IN to output hold L2SYNC_IN to high impedance Min 0.5 (2) 01 Min 1.0 Max 5.5 4.5 Min 1,2 - 10 Max 5.7 4.7 Min 1,5 - 11 Max 6 5 Unit ns ns ns 4 Notes Max 5.0 4.0 1. All outputs are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the TTL level (0.8V or 2.0V) of the signal in question. The output timings are measured at the pins. 2. The outputs are valid for both single-ended and differential L2CLK modes. For flow-THRU and pipelined reg-reg synchronous burst RAMs, L2CR[14-15] = 00 is recommended. For pipelined delay-write synchronous burst SRAMs, L2CR[14-15] = 01 is recommended. 3. All maximum timing specifications assume CL = 20 pF. 4. This measurement assumes CL = 5 pF. 5. Reserved for future use. 27 2128A-HIREL-01/02 Figure 16 shows the L2 bus output timing diagrams for the TSPC750A. Figure 16. L2 Bus Output Timing Diagrams VM VM L2SYNC_IN 26 27 ALL OUTPUTS 28 L2DATA BUS VM = Midpoint Voltage(1.4V) IEEE 1149.1 AC Timing Specifications Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 17, Figure 18, Figure 19, and Figure 20. Table 15. JTAG AC Timing Specifications (Independent of SYSCLK) VDD = AVDD = L2AVDD = 2.6 VDC 100 mV, OVDD = L2OVDD = 3.3 5% VDC, GND = 0 VDC, -55 Tj < 125C, CL = 50 pF Num Characteristic TCK Frequency Of Operation 1 2 3 4 5 6 7 8 9 10 11 12 13 Notes: 1. 2. 3. 4. TCK Cycle Time TCK Clock Pulse Width Measured at 1.4V TCK Rise and Fall Times Specification Obsolete, Intentionally Omitted TRST Assert Time Boundary-scan Input Data Setup Time Boundary-scan Input Data Hold Time TCK to Output Data Valid TCK to Output High Impedance TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK to TDO Data Valid TCK to TDO High Impedance 25 4 15 4 3 0 12 4 3 20 19 12 9 ns ns ns ns ns ns ns ns ns 4 1 2 2 3 3, 4 Min 0 30 15 0 Max 33.3 2 Unit MHz ns ns ns Notes TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. Non-JTAG signal input timing with respect to TCK. Non-JTAG signal output timing with respect to TCK. Guaranteed by design and characterization. 28 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Figure 17 provides the JTAG clock input timing diagram. Figure 17. JTAG Clock Input Timing Diagram 1 2 2 TCK 3 3 VM VM VM VM = Midpoint Voltage Figure 18 provides the TRST timing diagram. Figure 18. TRST Timing Diagram TRST 5 Figure 19 provides the boundary-scan timing diagram. Figure 19. Boundary-Scan Timing Diagram TCK 6 7 DATA INPUTS 8 INPUT DATA VALID DATA OUTPUTS 9 OUTPUT DATA VALID DATA OUTPUTS 8 DATA OUTPUTS OUTPUT DATA VALID 29 2128A-HIREL-01/02 Figure 20 provides the test access port timing diagram. Figure 20. Test Access Port Timing Diagram TCK 10 11 TDI, TMS 12 INPUT DATA VALID TDO 13 OUTPUT DATA VALID TDO 12 TDO OUTPUT DATA VALID Preparation for Delivery Packaging Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. Certificate of Compliance ATMEL-Grenoble offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-PRF-883 and guaranteeing the parameters not tested at temperature extremes for the entire temperature range. Handling MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of static buildup. However, the following handling practices are recommended: a) Devices should be handled on benches with conductive and grounded surfaces. b) Ground test equipment, tools and operator. c) Do not handle devices by the leads. d) Store devices in conductive foam or carriers. e) Avoid use of plastic, rubber, or silk in MOS areas. f) Maintain relative humidity above 50 percent if practical. g) For CI-CGA packages, use specific tray to take care of the highest height of the package compared with the regular CBGA. 30 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Clock Relationships Choice The TSPC750A's PLL is configured by the PLL_CFG[0-3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the TSPC750A is shown in Table 16 for nominal frequencies. Table 17 provides sample core-to-L2 frequencies. Sample Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_CFG [0-3] 1000 1110 1010 0111 1011 1001 1101 0101 0010 0001 1100 0011 1111 Notes: Bus-toCore Multiplier 3x 3.5x 4x 4.5x 5x 5.5x 6x 6.5x 7x 7.5x 8x Core-to VCO Multiplier 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 150 (300) 162 (325) 175 (350) 187 (375) 200 (400) 150 (300) 166 (333) 183 (366) 200 (400) 216 (433) 233 (466) 250 (500) 266 (533) 160 (320) 180 (360) 200 (400) 220 (440) 240 (480) 260 (520) Bus 25 MHz Bus 33.3 MHz Bus 40 MHz Bus 50 MHz 150 (300) 175 (350) 200 (400) 225 (450) 250 (500) Bus 66.6 MHz 200 (400) 233 (466) 266 (533) Bus 75 MHz 225 (450) 262 (525) Bus 83.3 MHz 250 (500) Bus 100 MHz Table 16. TSPC750A Microprocessor PLL Configuration PLL off/bypass PLL off PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied PLL off, no core clocking occurs 1. PLL_CFG[0--3] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the TSPC750A; see "Clock AC Specifications," for valid SYSCLK and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In clock-off mode, no clocking occurs inside the TSPC750A regardless of the SYSCLK input. 31 2128A-HIREL-01/02 Table 17. Sample Core-to-L2 Frequencies Core Frequency in MHz 200 208.3 210 220 225 233.3 240 266 Note: /1 200 208 210 220 225 233.3 240 266 /1.5 133.3 138.6 140 146.6 150 155.5 160 177.3 /2 100 104 105 110 112.5 116.6 120 133 /2.5 80 83.3 84 88 90 93.3 96 106.4 /3 80 88.6 1. The core and L2 frequencies are for reference only. Some configurations may select core or L2 frequencies which are not useful, not supported, or not tested for by the TSPC750A; see "L2 Clock AC Specifications," for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. System Design Information PLL Power Supply Filtering The AVDD and L2AVDD power signals are provided on the TSPC750A to provide power to the clock generation phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the power supplied to the AV DD input signal should be filtered using a circuit similar to the one shown in Figure 21. The circuit should be placed as close as possible to the AVDD pin to ensure it filters out as much noise as possible. An identical but separate circuit should be placed as close as possible to the L2AVDD pin. Figure 21. PLL Power Supply Filter Circuit 10 VDD 10 F 0.1 F AVDD (or L2AVDD) GND Decoupling Recommendations Due to the TSPC750A's dynamic power management feature, large address and data buses, and high operating frequencies, the TSPC750A can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the TSPC750A system, and the TSPC750A itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD and OVDD pin (and L2OVDD for the 360 CBGA) of the TSPC750A. It is also recommended that these decoupling capacitors receive their power from separate VDD, OVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. 32 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A These capacitors should vary in value from 220 pF to 10 F to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated V DD or OV DD pins. Suggested values for the V DD pins-220 pF (ceramic), 0.01 F (ceramic), and 0.1 F (ceramic). Suggested values for the OV DD pins -- 0.01 F (ceramic), 0.1 F (ceramic), and 10 F (tantalum). Only SMT (surface mount technology) capacitors should be used to minimize lead inductance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors-100 F (AVX TPS tantalum) or 330 F (AVX TPS tantalum). Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to VDD. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, OVDD, and GND pins of the TSPC750A. External clock routing should ensure that the rising-edge of the L2 clock is coincident at the CLK input of all SRAMs and at the L2SYNC_IN input of the TSPC750A. The L2CLKOUTA network could be used only, or the L2CLKOUTB network could also be used depending on the loading, frequency, and number of SRAMs. Output Buffer DC Impedance The TSPC750A 60x and L2 I/O drivers were characterized over process, voltage, and temperature. To measure Z0, an external resistor is connected to the chip pad, either to OV DD or OGND. Then, the value of such resistor is varied until the pad voltage is OVDD/2; see Figure 22. The output impedance is actually the average of two components, the resistances of the pull-up and pull-down devices. When Data is held low, SW1 is closed (SW2 is open), and RN is trimmed until Pad = OVDD/2. RN then becomes the resistance of the pull-down devices. When Data is held high, SW2 is closed (SW1 is open), and RP is trimmed until Pad = OVDD/2. RP then becomes the resistance of the pull-up devices. With a properly designed driver RP and RN are close to each other in value. Then Z0 = (RP + RN)/2. 33 2128A-HIREL-01/02 Figure 22. Driver Impedance Measurement OVDD RN SW1 Data Pad SW2 RP OGND Table 18 summarizes the signal impedance results. The driver impedance values were derived by simulation at 65C. As the process varies, the output impedance will be reduced by several ohms. Table 18. Impedance Characteristics VDD = 2.6V, OVDD = 3.3V, Tj = 65C Process TYP 60x 43 L2 38 Symbol Z0 Unit Ohms Pull-up Resistor Requirements The TSPC750A requires high-resistive (weak: 10K) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the TSPC750A or other bus masters. These signals are TS, ABB, DBB, and ARTRY. In addition, the TSPC750A has one open-drain style output that requires a pull-up resistors (weak or stronger: 4.7K - 10K) if it is used by the system. This signal is CKSTP_OUT. During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. Since the TSPC750A must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the TSPC750A or by other receivers in the system. It is recommended that these signals be pulled up through weak (10K) pull-up resistors or restored in some manner by the system. The snooped address and transfer attribute inputs are A[0-31], AP[0-3], TT[0-4], TBST, and GBL. 34 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods. The data bus signals are DH[0-31], DL[0-31], DP[0-7]. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. No pull-up resistors are normally required for the L2 interface. Definitions Datasheet status Objective specification Target specification Preliminary specification site Preliminary specification site Product specification Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. This datasheet contains target and goal specification for discussion with customer and application validation. This datasheet contains target or goal specification for product development. This datasheet contains preliminary data. Additional data may be published later; could include simulation result. This datasheet contains also characterization results. This datasheet contains final product specification. Validity Before design phase. Valid during the design phase. Valid before characterization phase. Valid before the industrialization phase. Valid for production purpose. Life Support Applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. ATMEL-Grenoble customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify ATMEL-Grenoble for any damages resulting from such improper use or sale. 35 2128A-HIREL-01/02 Package Mechanical Data Parameters for the TSPC740A The package parameters are as provided in the following list. The package types are 21 x 21 mm, 255-lead CBGA and CI-CGA. Package outline -- 21 x 21 mm Interconnects -- 255 (16 x 16 ball array - 1) Pitch -- 1.27 mm (50 mil) Minimum module height -- 2.45 mm (CBGA), 3,45 mm (CI-CGA) Maximum module height -- 3.00 mm (CBGA), 4.00 mm (CI-CGA Ball or column diameter -- 0.89 mm (35 mil) Mechanical Dimensions of the TSPC740A CBGA Package Figure 23 provides the mechanical dimensions and bottom surface nomenclature of the TSPC740A, 255 CBGA package. 36 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Figure 23. Mechanical Dimensions and Bottom Surface Nomenclature of TSPC740A (CBGA) 2X 0.2 A1 CORNER A E T T B P 2X 0.2 F N NOTES: A. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. B. DIMENSIONS IN MILLIMETERS. C. TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES. BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY. MILLIMETERS DIM M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 T R P N M L K J H G F E D C B A A A1 B A1 H C D C MIN MAX INCHES MIN MAX 21.000 BSC 0.9 1.10 0.827 BSC 0.035 0.043 21.000 BSC 2.45 0.827 BSC 0.118 0.037 K 3.000 0.096 0.820 0.930 0.032 G H 1.270 BSC 0.050 BSC 0.039 0.790 0.990 0.031 G 255X D 0.3 0.15 K K M N P 0.635 BSC 2.00 8.3 9.0 8.5 9.2 0.025 BSC 0.074 0.327 0.354 0.335 0.362 T T E F 37 2128A-HIREL-01/02 Mechanical Dimensions of the TSPC740A CI-CGA Package Figure 24 provides the mechanical dimensions and bottom surface nomenclature of TSPC740A, 255 CI-CGA package. Figure 24. Mechanical Dimensions and Bottom Surface Nomenclature of TSPC740A (CI-CGA) 38 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Parameters for the TSPC750A The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead CBGA and CI-CGA. Package outline -- 25 x 25 mm Interconnects -- 360 (19 x 19 ball array - 1) Pitch -- 1.27 mm (50 mil) Minimum module height -- 2.65 mm (CBGA), 3,65 mm (CI-CGA) Maximum module height -- 3.20 mm (CBGA), 4,20 mm (CI-CGA) Ball or column diameter -- 0.89 mm (35 mil) 39 2128A-HIREL-01/02 Mechanical Dimensions of the TSPC750A CBGA Package Figure 25 provides the mechanical dimensions and bottom surface nomenclature of the TSPC750A, 360 CBGA package. Figure 25. Mechanical Dimensions and Bottom Surface Nomenclature of the TSPC750A 2X 0.2 A1 CORNER A E3 0.2 T E T P2 B P NOTES: A. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. B. DIMENSIONS IN MILLIMETERS. C. TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES. BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY. D. TOP SIDE CAPACITOR ASSEMBLY AREAS ARE CONNECTED TO POWER PLANES BUT NOT USED MILLIMETERS DIM MIN MAX INCHES MIN MAX 2X 0.2 F D3 A 25.000 BSC 1.1 1.3 0.984 BSC 0.043 0.052 N M A1 B C W V U T R P N M L K J H G F E D C B A A1 H C K M N P D3 H D N2 25.000 BSC 2.65 3.2 0.984 BSC 0.104 0.126 0.032 0.037 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 171819 0.820 0.930 G 1.270 BSC 0.790 0.990 0.050 BSC 0.031 0.039 0.635 BSC 2.00 8.3 9.0 2.75 3 12,5 14.3 8.5 9.2 0.025 BSC 0.079 0.327 0.335 0.354 0.362 0.108 0.118 0.492 0.563 K G 360X D 0.3 0.15 K E3 N2 T T E F P2 40 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A Mechanical Dimensions of the TSPC750A CI-CGA Package Figure 26 provides the mechanical dimensions and bottom surface nomenclature of TSPC750A, 360 CI-CGA package Figure 26. Mechanical Dimensions and Bottom Surface Nomenclature of TSPC750A (CI-CGA) 41 2128A-HIREL-01/02 Ordering Information TS (X) PC750A M Prefix Prototype Type Temperature Range: TC M: -55, +125C V: -40 C, +110C Package G: CBGA GS: CI_CGA G U/T 8 L x Revision Level(1) E: Rev. 2.2 obsolete H: Rev 3.1 Bus divider (to be confirmed) L: Any valid PLL configuration Max internal processor speed 8: 200 MHz 10: 233 MHz 12: 266 MHz Screening Level(1) _: Standard B/Q: MIL-STD-883, Class Q B/T: According to MIL-STD-883 U: Upscreening U/T: Upscreening + burn-in Note: 1. For availability of different versions, contact your Atmel sales office. 42 TSPC750A/740A 2128A-HIREL-01/02 TSPC750A/740A 43 2128A-HIREL-01/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 RF/Automotive Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Microcontrollers Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Asia Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom ASIC/ASSP/Smart Cards Japan Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademarks of Atmel. PowerPC (R) is the registered trademark of IBM Company. Other terms and product names may be the trademarks of others. 2128A-HIREL-01/02 0M |
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