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| TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 D Fully Supports Provisions of IEEE 1394b-2002 at S100, S100B, S200, S200B, S400, and S400B Signaling Rates (B Signifies 1394b Signaling) Fully Supports Provisions of IEEE 1394a-2000 and 1394-1995 Standards for High Performance Serial Bus Fully Interoperable With Firewire, SB1394, DishWire, and i.LINK Implementation of IEEE Std 1394 Provides Three Fully Backward Compatible, (1394a-2000 Fully Compliant) Bilingual 1394b Cable Ports at 400 Megabits per Second (Mbits/s) Same Three Fully Backward Compatible Ports Are 1394a-2000 Fully Compliant Cable Ports at 100/200/400 Mbits/s Full 1394a-2000 Support Includes: - Connection Debounce - Arbitrated Short Reset - Multispeed Concatenation - Arbitration Acceleration - Fly-By Concatenation - Port Disable/Suspend/Resume - Extended Resume Signaling for Compatibility With Legacy DV Devices Power-Down Features to Conserve Energy in Battery Powered Applications Low-Power Sleep Mode Automotive Sleep Mode Support Fully Compliant With Open Host Controller Interface (HCI) Requirements Cable Power Presence Monitoring Cable Ports Monitor Line Conditions for Active Connection to Remote Node Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and 1394a-2000 Features Data Interface to Link-Layer Controller Pin Selectable From 1394a-2000 Mode (2/4/8 Parallel Bits at 49.152 MHz) or 1394b Mode (8 Parallel Bits at 98.304 MHz) D Interface to Link-Layer Controller Supports Low Cost TI Bus-Holder Isolation D Interoperable With Link-Layer Controllers D D Using 3.3-V Supplies Interoperable With Other 1394 Physical Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies Low Cost 49.152-MHz Crystal Provides Transmit and Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz and 98.304 MHz Separate Bias (TPBIAS) for Each Port Low Cost, High Performance 80-Pin TQFP (PFP) Thermally Enhanced Package Software Device Reset (SWR) Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB41BA3 Does Not Load the TPBIAS of Any Connected Device and Blocks Any Leakage From the Port Back to Power Plane The TSB41BA3 Has a 1394a-2000 Compliant Common-Mode Noise Filter on the Incoming Bias Detect Circuit to Filter Out Cross-Talk Noise Cable/Transceiver Hardware Speed and Port Mode Are Selectable by Pin States - Supports Connection to CAT5 Cable Transceiver by Allowing Ports to be Forced to Beta-Only 100 Mbits/s only - Supports Connection to S200 Plastic Optical Fiber Transceivers by Allowing Ports to be Forced to1394b Beta-Only 200 Mbits/s and S100 Mbits/s Only - Supports Use of 1394a Connections by Allowing Ports 1 and 2 to Be Forced to 1394a-Only Mode - Optical Signal Detect Input for All Ports in Beta Mode Enables Connection to Optical Transceivers D D D D D D D D D D D D D D D D D D D Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. i.LINK is a trademark of Sony Corporation. FireWire is a trademark of Apple Computer Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 description The TSB41BA3 provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41BA3 is designed to interface with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It may also be connected cable port to cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2. The TSB41BA3 is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal voltage regulator to the PLLVDD-1.8 and DVDD-1.8 terminals. To protect the phase-locked loop (PLL) from noise, the PLLVDD-1.8 terminals must be separately decoupled from the DVDD-1.8 terminals. The PLLVDD-1.8 terminals are decoupled with 1-F and smaller decoupling capacitors, and the DVDD-1.8 terminals are separately decoupled with a 1-F and smaller decoupling capacitors. The separation between DVDD-1.8 and PLLVDD-1.8 must be implemented by separate power supply rails or planes. The TSB41BA3 may be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-1.8 and DVDD-1.8 terminals to the requirements in the recommended operating conditions section of this data sheet. The PLLVDD-1.8 terminals must be separated from the DVDD-1.8 terminals, the PLLVDD-1.8 terminals are decoupled with 1-F and smaller decoupling capacitors, and the DVDD-1.8 terminals separately decoupled with 1-F and smaller decoupling capacitors. The separation between DVDD-1.8 and PLLVDD-1.8 may be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-1.8 and PLLVDD-1.8 are separated by a filter network to keep noise from the PLLVDD-1.8 supply. The TSB41BA3 requires an external 49.152-MHz crystal to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a-2000 standard. A 98.304-MHz clock signal is supplied by the PHY to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE 1394b-2002 standard. The power down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched internally, combined serially, encoded, and transmitted at 98.304, 122.78, 196.608, 245.76, 393.216, or 491.52 Mbits/s (referred to as S100, S100B, S200, S200B, S400, or S400B speed, respectively) as the outbound information stream. The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the 1394b-2002 standard. The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a-2000 compliant device, the cable interface on that port operates in the 1394a-2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b compliant node, the cable interface on that port operates per the 1394b-2002 standard at S100B, S200B, or S400B speed. The TSB41BA3 automatically determines the correct cable interface connection method for the bilingual ports. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 description (continued) NOTE: The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable. When the BMODE terminal is deasserted, the PHY-link interface is placed in 1394a-2000 mode and BOSS arbitration is disabled. When the BMODE terminal is asserted, the PHY-link interface is placed in 1394b-2002 mode and BOSS arbitration is enabled. During packet reception the serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected and active cable ports. Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a-2000 compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted pair bias (TPBIAS) voltage. When connected to a 1394a-2000 compliant node, the TSB41BA3 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 F. The line drivers in the TSB41BA3, are designed to work with external 112- termination resistor networks in order to match the 110- cable impedance. One termination network is required at each end of a twisted-pair cable. Each network is composed of a pair of series-connected ~56- resistors. The midpoint of the pair of resistors that are connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that are directly connected to the TPB terminals is coupled to ground through a parallel RC network with recommended values of 5 k and 270 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. When the power supply of the TSB41BA3 is off while the twisted-pair cables are connected, the TSB41BA3 transmitter and receiver circuitry present a high-impedance signal to the cable that does not load the device at the other end of the cable. When the TSB41BA3 is used without one or more of the ports brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the preferred method is for the port to be forced to the 1394a-only mode (data-strobe-only mode, DS), then the TPB+ and TPB- terminals can be tied together and then pulled to ground; or the TPB+ and TPB- terminals can be connected to the suggested normal termination network. The TPA+ and TPA- terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal may be left unconnected. If the port is left in bilingual (Bi) mode, then the TPB+ and TPB- terminals may be left unconnected or the TPB+ and TPB- terminals can be connected to the suggested normal termination network. The TPA+ and TPA- terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal can be left unconnected. If the port is left in a forced 1394b beta only (B1, B2, or B4) mode, then the TPB+ and TPB- terminals may be left unconnected or the TPB+ and TPB- terminals can be connected to the suggested normal termination network. The TPA+ and TPA- terminals of an unused port can be left unconnected. The TPBIAS#_SD# terminal must be pulled to ground through a 1.2-k or less resistor. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 description (continued) To operate a port as a 1394b bilingual port, the speed/mode selections terminals (S5_LKON_DS2, S4_DS1, S3_DS0, S2_PC0, S1_PC1, and S0_PC2) need to be pulled to VCC or ground through a 1-k resistor. The port must be operated in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b beta-only connector is connected to the port. To operate the port as a 1394a-only port, the speed/mode selection terminals must be configured correctly to force 1394a-2000-only operation on that port. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode is provided to ensure that 1394b signaling is never sent across a 1394a cable. NOTE:A bilingual port can only connect to a 1394b-only port that operates at S400b. It can not establish a connection to a S200b or S100b port. A port that has been forced to S400b (B4) can connect to a 1394b-only port at S400b (B4) or S200b (B2) or S100b (B1). A port that has been forced to S200b can connect to a 1394b-only port at S200b or S100b. A port that has been forced to S100b can only connect to a 1394b-only port at S100b. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal must be connected to VDD through a 1-k resistor. The SE and SM terminals must be tied to ground through a 1-k resistor. Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They may be pulled high through a 1-k resistor or hardwired low as a function of the equipment design. In some speed/mode selections the S2_PC0, S1_PC1, and S0_PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable), please see Table 1. The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB41BA3, this bit may only be set by a write to the PHY register set. If a node desires to be a contender for IRM or BM, then the node software must set this bit in the PHY register set. The LPS (link power status) terminal works with the S5_LKON_DS2 terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 2 and Table 3 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). NOTE:The TSB41BA3 does not have a cable-not-active (CNA) pin. To achieve a similar function, the individual PHY ports may be set-up to issue interrupts whenever the port changes state. If the LPS pin is low, then this generates a link-on (LKON) output clock. Please see register bits PIE, PEI, and WDIE along with the individual interrupt bits. The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB41BA3 detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB41BA3 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB41BA3 issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible). The PHY uses the S5_LKON_DS2 terminal to notify the LLC to power up and become active. When activated, the output S5_LKON_DS2 signal is a square wave. The PHY activates the S5_LKON_DS2 output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the S5_LKON_DS2 output when the LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the S5_LKON_DS2 output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause S5_LKON_DS2 to be active. If the PHY is power cycled and the power class is 0 through 4, then the PHY asserts S5_LKON_DS2 for approximately 167 s or until both the LPS is active and the LCtrl bit is 1. pin assignments PFP PACKAGE (TOP VIEW) TPBIAS2_SD2 TPBIAS1_SD1 TPA1+ TPA1- AVDD AGND TPB1+ TPB1- TPBIAS0_SD0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AGND AGND AVDD DGND DVDD-1.8 S2_PC0 S1_PC1 S0_PC2 DVDD-3.3 DVDD-3.3 DVDD-1.8 DGND VREG_PD BMODE RESETz DGND PD TESTM SLPEN LPS TPA0+ TPA0- AVDD AGND TPB0+ TPB0- 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 TPA2+ TPA2- AVDD TPB2+ TPB2- 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 123 45 6 TSB41BA3 21 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AGND AVDD DGND DVDD-1.8 SM SE CPS S3_DS0 S4_DS1 PLLVDD-3.3 PLLVDD-1.8 PLLVDD-1.8 PLLGND XI XO PLLGND AVDD R0 R1 AGND PINT S5_LKON_DS2 LREQ DGND PCLK DVDD-3.3 LCLK_PMC DVDD-1.8 CTL0 CTL1 D0 D1 D2 DGND D3 D4 D5 DVDD-3.3 D6 D7 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 functional block diagram R0 CPS LPS SLPEN PINT PCLK LCLK_PMC LREQ CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 RESETz S5_LKON_DS2 BMODE PD S2_PC0 S1_PC1 S0_PC2 SE SM S3_DS0 S4_DS1 TESTM Arbitration and Control State Machine Logic TPA1+ TPA1- Cable Port 1 TPB1+ TPB1- TPA2+ TPA2- Cable Port 2 TPB2+ TPB2- Received Data Decoder/Retimer Bias Voltage and Current Generator R1 TPBIAS0_SD0 TPBIAS1_SD1 TPBIAS2_SD2 Link Interface I/O TPA0+ TPA0- Cable Port 0 TPB0+ TPB0- Crystal Oscillator, PLL System, and Transmit Clock Generator Voltage Regulator Transmit Data Encoder XO XI VREG_PD 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 Terminal Functions TERMINAL NAME AGND AVDD TYPE Supply Supply NO. 21, 40, 43, 50, 61, 62 24, 39, 44, 51, 57, 63 I/O - - DESCRIPTION Analog circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10-F filtering capacitors are also recommended. These supply terminals are separated from the PLLVDD-1.8, PLLVDD-3.3, DVDD-1.8, and DVDD-3.3 terminals internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc impedance connection on the circuit board. Beta-mode input. This terminal determines the PHY-link interface connection protocol. When logic high (asserted), the PHY-link interface complies with the 1394b-2002 B PHY-link interface. When logic low (deasserted), the PHY-link interface complies with the legacy 1394a-2000 standard. When using an LLC such as the 1394b-2002 TSB82AA2, this terminal must be pulled high. When using an LLC such as the 1394a-2000 TSB12LV26, this terminal must be tied low. NOTE: The PHY-link interface cannot be changed between the different protocols during operation. Cable power status input. This terminal is normally connected to cable power through a 400-k resistor. This circuit drives an internal comparator that detects the presence of cable power. This transition from cable power sensed to cable power not sensed may be used to generate an interrupt to the LLC. Control I/Os. These bidirectional signals control communication between the TSB41BA3 and the LLC. Bus holders are built into these terminals. Data I/Os. These are bidirectional data signals between the TSB82BA3 and the LLC. Bus holders are built into these terminals. If power management control (PMC) is selected using LCLK_PMC, then some of these terminals may be used for PMC. See the LCLK_PMC terminal description for more information. Digital circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. - Digital 1.8-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. An additional 1-F capacitor is required for voltage regulation. These supply terminals are separated from the DVDD-3.3, PLLVDD-1.8, PLLVDD-3.3, and AVDD terminals internal to the device to provide noise isolation. Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10-F filtering capacitors are also recommended. The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board. These supply terminals are separated from the PLLVDD-1.8, PLLVDD-3.3, DVDD-1.8, and AVDD terminals internal to the device to provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together with a low dc impedance connection on the circuit board. BMODE CMOS 74 I CPS CMOS 34 I CTL0 CTL1 D0-D7 CMOS CMOS 9 10 11, 12, 13, 15, 16, 17, 19, 20 4, 14, 38, 64, 72, 76 8, 37, 65, 71 I/O I/O DGND DVDD-1.8 Supply Supply DVDD-3.3 Supply 6, 18, 69, 70 - POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 Terminal Functions (Continued) TERMINAL NAME LCLK_PMC TYPE CMOS NO. 7 I/O I DESCRIPTION Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to the PHY. On hardware reset this terminal is sampled to determine the power management control (PMC) mode. LPS BMODE Mode LCLK_PMC H L H No LLC (PMC mode) n/c lps L Legacy LLC LCLK_PMC lps H Beta LLC internal pulldown on LCLK_PMC LCLK_PMC from LLC normally low during reset In PMC mode, since no LLC is attached the data lines (D7-D0) are available to indicate power states. In PMC mode the following signals are output: - D0--port 0 cable-power disable (see Note 1) - D1--port 1 cable-power disable (port in sleep or disabled) - D2--port 2 cable-power disable (port in sleep or disabled) - D6--All ports cable-power disable (all ports in sleep/disable) logical AND of bits 0-2 - D3-D5 and D7 are reserved for future use. Note 1: The cable-power disable is asserted when the port is either: - Hard-disabled (both the disabled and hard disabled bits are set) - Sleep-disabled (both the disabled and sleep_enable bits are set) - Disconnected - Asleep - Connected in DS mode, but nonactive (that is, suspended or disabled) Otherwise, the cable-powered disable output is deasserted (that is, cable power enabled) when the port is dc-connected or active. A bus holder is built into this terminal. Link power status input. This terminal monitors the active/power status of the link-layer controller (LLC) and controls the state of the PHY-LLC interface. This terminal must be connected to either the VDD supplying the LLC through an approximately 1-k resistor or to a pulsed output which is active when the LLC is powered. A pulsed signal must be used when an isolation barrier exists between the LLC and PHY (see Figure 8). The LPS input is considered inactive if it is sampled low by the PHY for more than a LPS_RESET time (~2.6 s), and is considered active otherwise (that is, asserted steady high or an oscillating signal with a low time less than 2.6 s). The LPS input must be high for at least 22 ns to be guaranteed to be observed as high by the PHY. When the TSB41BA3 detects that the LPS input is inactive, it places the PHY-LLC interface into a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D (D0 to D7) outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than a LPS_DISABLE time (~26 s), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The PHY-LLC interface is placed into the disabled state upon hardware reset. The LLC state that is communicated in the self-ID packet is considered active only if both the LPS input is active and the LCtrl register bit is set to 1. The LLC state that is communicated in the self-ID packet is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB41BA3 issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible). LLC request input. The LLC uses this input to initiate a service request to the TSB41BA3. A bus holder is built into this terminal. PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK output provides a 49.152-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is in legacy 1394a-2000 (BMODE input deasserted). Power-down input. A high on this terminal turns off all internal circuitry. Asserting the PD input high also activates an internal pulldown on the RESETz terminal to force a reset of the internal control logic. PHY Interrupt. The PHY uses this output to serially transfer status and interrupt information to the link when PHY-link interface is in the 1394b mode. A bus holder is built into this terminal. PLL circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. LPS CMOS 80 I LREQ PCLK CMOS CMOS 3 5 I O PD PINT PLLGND CMOS CMOS Supply 77 1 25, 28 I O - 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 Terminal Functions (Continued) TERMINAL NAME PLLVDD-1.8 TYPE Supply NO. 29, 30 I/O - DESCRIPTION PLL 1.8-V circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. An additional 1-F capacitor is required for voltage regulation. The PLLVDD-1.8 terminals must be separate from the DVDD-1.8 terminals. These supply terminals are separated from the DVDD-1.8, DVDD-3.3, PLLVDD-3.3 and AVDD-3.3 terminals internal to the device to provide noise isolation. PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors near the terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10-F filtering capacitors are also recommended. This supply terminal is separated from the DVDD-1.8, DVDD-3.3, PLLVDD-1.8, and AVDD-3.3 terminals internal to the device to provide noise isolation. The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit board. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc impedance connection. Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to VDD is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the APPLICATIONS INFORMATION section). The RESETz terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and can also be driven by an open-drain type driver. Current setting resistor terminals. These terminals are connected to a precision external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.34 k 1% is required to meet the IEEE Std 1394-1995 output voltage limits. Test control input. This input is used in the manufacturing test of the TSB41BA3. For normal use this terminal must be pulled low either through a 1-k resistor to GND or directly to GND. Automotive sleep mode enable input. This terminal is used to enable the automotive sleep mode. When deasserted, normal 1394.b functionality is maintained. Test control input. This input is used in the manufacturing test of the TSB41BA3. For normal use this terminal must be pulled low either through a 1-k resistor to GND or directly to GND. Port sleep/mode selection terminals 2-0 and power class programming. On hardware reset, this terminal when used with the other 5 selection pins allows the user to select the speed and mode of the ports. See Table 1. Depending on the selection these inputs may set the default value of the power class indicated during self-ID. Programming is done by tying the terminals high through a 1-k or smaller resistor or by tying directly to ground through a 1-k or smaller resistor. Bus holders are built into these terminals. Port sleep/mode selection terminal 3. On hardware reset, this terminal when used with the other 5 selection pins allows the user to select the speed and mode of the ports. See Table 1. Programming is done by tying the terminals high through a 1-k or smaller resistor or by tying directly to ground through a 1-k or smaller resistor. A bus holder is built into this terminal. Port sleep/mode selection terminal 4. On hardware reset, this terminal when used with the other 5 selection pins allows the user to select the speed and mode of the ports. See Table 1. Programming is done by tying the terminals high through a 1-k or smaller resistor or by tying directly to ground through a 1-k or smaller resistor. A bus holder is built into this terminal. PLLVDD-3.3 Supply 31 - RESETz CMOS 75 I R0 R1 SE SLPEN SM S2_PC0 S1_PC1 S0_PC2 Bias 23 22 35 79 36 66 67 68 - CMOS CMOS CMOS CMOS I I I I S3_DS0 CMOS 33 I S4_DS1 CMOS 32 I POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 Terminal Functions (Continued) TERMINAL NAME S5_LKON_DS2 TYPE CMOS NO. 2 I/O I/O DESCRIPTION Port sleep/mode selection terminal 5 and link-on output. This terminal may be connected to the linkon input terminal of the LLC through a 1-k resistor if the link-on input is available on the link layer. On hardware reset, this terminal when used with the other 5 selection pins allows the user to select the speed and mode of the ports. See Table 1. A bus holder is built into this terminal. After hardware reset, this terminal is the link-on output, which notifies the LLC or other power-up logic to power up and become active. The link-on output is a square wave signal with a period of approximately 163 ns (8 PCLK cycles) when active. The link-on output is otherwise driven low, except during hardware reset when it is high impedance. The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit cleared) and when one: a) The PHY receives a link-on PHY packet addressed to this node b) The PEI (port-event interrupt) register bit is 1, or c) Any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt), or d) The PHY is power cycled and the power class is 0 through 4 Once activated, the link-on output is active until the LLC becomes active (both the LPS input active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the link-on output is otherwise active because one of the interrupt bits is set (that is, the link-on output is active due solely to the reception of a link-on PHY packet). In the case of power cycling the PHY, the LKON signal must stop after 167 s if the above conditions have not been met. NOTE: If an interrupt condition exists which otherwise causes the link-on output to be activated if the LLC were inactive, then the link-on output is activated when the LLC subsequently becomes inactive. Test control input. This input is used in the manufacturing test of the TSB41BA3. For normal use this terminal must be pulled high through a 1-k resistor to VDD. Port 0 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Please request the S800 1394b layout recommendations document from your TI representative. Port 1 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Please request the S800 1394b layout recommendations document from your TI representative. Port 2 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector. Please request the S800 1394b layout recommendations document from your TI representative. Twisted-pair bias output and signal detect input. This provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection in 1394a-2000 mode. Each of these terminals, except for an unused port, must be decoupled with a 1.0-F capacitor to ground. For the unused port, this terminal can be left unconnected. When a port is configured as a beta mode port (B1, B2, B4) this terminal becomes an input and must be high when a valid signal is present. For optical transceivers the signal detect of the transceiver must be connected to this terminal. The input is an LVCMOS level input. Voltage regulator powerdown input. When asserted logic high, this pin powers down the internal 3.3-V-to-1.8-V regulator. For single-supply (3.3-V only) operation, this pin must be tied to GND. Crystal oscillator inputs. These terminals connect to a 49.152-MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used (see crystal selection section in the document SLLS418A). XI is a 1.8-V CMOS input. TESTM TPA0- TPA0+ TPB0- TPB0+ TPA1- TPA1+ TPB1- TPB1+ TPA2- TPA2+ TPB2- TPB2+ TPBIAS0_SD0 TPBIAS1_SD1 TPBIAS2_SD2 CMOS Cable 78 45, 46, 41, 42 52 53 48 49 58 59 55 56 47 54 60 I I/O Cable I/O Cable I/O Cable In I/O VREG_PD XI XO CMOS Crystal 73 27 26 I I O 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 Table 1. Port Speed/Mode Selection MODE NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 S5_LINK ON_DS2 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S4_ DS1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 S3_ DS0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 S2_ PC0 PC0 PC0 PC0 0 0 0 0 1 1 1 1 PC0 PC0 PC0 PC0 PC0 PC0 PC0 PC0 PC0 PC0 PC0 PC0 PC0 PC0 PC0 S1_ PC1 PC1 PC1 PC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 S0_ PC2 PC2 PC2 PC2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 PORT 2 Bil DS DS B1 B2 B4 # B2 B1 DS DS B2 B1 B2 B4 B1 Bil Bil Bil B1 DS DS DS B1 B1 B2 B4 T T T S S S S S T T S S S S S T T T S T T T S S S S PORT 1 Bil Bil DS B1 B2 B4 Bil DS DS DS DS Bil Bil Bil Bil Bil Bil Bil Bil Bil Bil Bil DS DS DS DS T T T S S S T T T T T T T T T T T T T T T T T T T T PORT 0 Bil Bil Bil B1 B2 B4 B4 DS B2 B4 B4 B1 B2 B4 B2 B1 B2 B4 B4 B1 B2 B4 B2 B1 B2 B4 T T T S S S S T S S S S S S S S S S S S S S S S S S POWER CLASS PC = (PC0, PC1, PC2) PC = (PC0, PC1, PC2) PC = (PC0, PC1, PC2) PC = 000 PC = 000 PC = 000 PC = 100 PC = 100 PC = 100 PC = 100 PC = 100 PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) PC = PC0,0,0 (100 or 000) SELF-ID 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394a S100 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 1394b 27 1 1 1 PC0 1 1 B1 S DS T B4 S PC = PC0,0,0 (100 or 000) Bil = 1394b-2002 Bilingual (S400b only Beta operating speed and data strobe: S400, S200, and S100 operating speeds) DS = 1394a-2000, data strobe-only, S400, S200, and S100 operating speeds B1 = 1394b-2002 Beta-only, S100b operating speed B2 = 1394b-2002 Beta-only, S200b and S100b operating speeds # B4 = 1394b-2002 Beta-only, S400b, S200b, and S100b operating speeds S = TPBIAS#_SD# pin is in signal detect input mode T = TPBIAS#_SD# pin is in TPBIAS output mode POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 port mode/speed selection example connections 3.3 V 3.3 V Signal Detect S5_DS2 S4_DS1 TPBIAS0_SD0 Port 0 POF S200 TSB41BA3 TPBIAS S3_DS0 PC0 (Don't Care) 3.3 V S1_PC1 S0_PC2 TPBIAS2_SD2 Port 2 TPBIAS S2_PC0 TPBIAS1_SD1 Port 1 1394b 9-Pin Bilingual 1394a 6-Pin DS Mode 21, Port/Speed Mode (1, 1, 0, PC0, 0, 1) 3.3 V 3.3 V S5_DS2 S4_DS1 3.3 V SD High 3.3 V TSB41BA3 Signal Detect TPBIAS0_SD0 Port 0 TSB17BA1 Transformer RJ45 S100 S3_DS0 PC0 (Don't Care) S2_PC0 TPBIAS1_SD1 Port 1 TPBIAS 1394a 6-Pin DS Signal Detect S1_PC1 S0_PC2 TPBIAS2_SD2 Port 2 POF S100 Mode 24, Port/Speed Mode (1, 1, 1, PC0, 0, 0) 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free air temperature, TA TSB41BA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TSB41BA3I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground. DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = 25C 52.5 mW/C PACKAGE PFP PFP TA 25C POWER RATING 5.05 W TA = 70C POWER RATING 2.69 W TA = 85C POWER RATING 1.9 W 3.05 W 31.7 mW/C 1.62 W 1.15 W PFP# 2.01 W 20.3 mW/C 1.1 W 1.1 W This is the inverse of the traditional junction-to-ambient thermal resistance (RJA). 2 oz. trace and copper pad with solder. 2 oz. trace and copper pad without solder. # For more information, refer to TI application note PowerPAD Thermally Enhanced Package, (SLMA002). PowerPAD is a trademark of Texas Instruments. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 recommended operating conditions MIN Source power node Supply voltage, 3.3 VDD Supply voltage, 1.8 VDD LREQ, CTL0, CTL1, D0-D7, LCLK_PMC High-level input voltage, VIH S5_LKON_DS2, S4_DS1, S3_DS0, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE, TPBIAS0_SD0, TPBIAS1_SD1, TPBIAS2_SD2 RESETz LREQ, CTL0, CTL1, D0-D7, LCLK_PMC Low-level input voltage, VIL S5_LKON_DS2, S4_DS1, S3_DS0, S2_PC0, S1_PC1, S0_PC2, SLPEN, PD, BMODE, TPBIAS0_SD0, TPBIAS1_SD1, TPBIAS2_SD2 RESETz Output current, IOL/OH Output current, IO CTL0, CTL1, D0-D7, S5_LKON_DS2, PINT, PCLK TPBIAS outputs TA = 70C RJA = 31.5_C/W, TA = 70C Maximum junction temperature, TJ (see RJA values listed in thermal JA characteristics table) RJA = 49.2_C/W, TA = 70C RJA = 19C/W, TA = 85C RJA = 31.5_C/W, TA = 85C RJA = 49.2_C/W, TA = 85C 1394b Differential input voltage, VID 1394a Differential input voltage, VID 1394a Common-mode input voltage, VIC Power-up reset time, tpu Receive input jitter Cable inputs, during data reception Cable inputs, during data reception Cable inputs, during arbitration TPB cable inputs, source power node TPB cable inputs, nonsource power node RESETz input TPA, TPB cable inputs, S100 operation TPA, TPB cable inputs, S200 operation TPA, TPB cable inputs, S400 operation Between TPA and TPB cable inputs, S100 operation Receive input skew Between TPA and TPB cable inputs, S200 operation Between TPA and TPB cable inputs, S400 operation All typical values are at VDD = 3.3 V and TA = 25C. For a node that does not source power; see Section 4.2.2.2 in IEEE 1394a-2000. Time after valid clock received at PHY XI input terminal. 200 118 168 0.4706 0.4706 2 RJA = 19C/W, -4 -5.6 Nonsource power node 3.0 3.0 1.65 2.6 0.7xVDD 0.6xVDD 1.2 0.2xVDD 0.3xVDD 4 1.3 84.1 93.3 106.4 99.1 108.4 121.5 800 260 265 2.515 2.015 1.08 0.5 0.315 0.8 0.55 0.5 ns ns mV V ms mV C C C C V V TYP 3.3 3.3 1.85 MAX 3.6 3.6 2.00 V V UNIT mA mA 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver PARAMETER VOD VOD IDIFF ISP200 1394a differential output voltage 1394a differential output voltage Driver difference current, TPA+, TPA-, TPB+, TPB- Common-mode speed signaling current, TPB+, TPB- Drivers enabled, speed signaling off S200 speed signaling enabled 56 , TEST CONDITION See Figure 1 MIN 172 400 -1.05 -4.84 -12.4 550 TYP MAX 265 800 1.05 -2.53 -8.10 UNIT mV mV mA mA ISP400 Common-mode speed signaling current, TPB+, TPB- S400 speed signaling enabled mA VOFF Off state differential voltage Drivers disabled, See Figure 1 20 mV Limits defined as algebraic sum of TPA+ and TPA- driver currents. Limits also apply to TPB+ and TPB- algebraic sum of driver currents. Limits defined as absolute limit of each of TPB+ and TPB- driver currents. receiver PARAMETER ZID ZIC VTH-R VTH-CB VTH+ VTH- VTH-SP200 VTH-SP400 Differential impedance Common-mode impedance Receiver input threshold voltage Cable bias detect threshold, TPBx cable inputs Positive arbitration comparator threshold voltage Negative arbitration comparator threshold voltage Speed signal threshold Speed signal threshold TEST CONDITION Drivers disabled 20 Drivers disabled Drivers disabled Drivers disabled Drivers disabled Drivers disabled TPBIAS-TPA common mode voltage, drivers disabled -30 0.6 89 -168 49 314 24 30 1.0 168 -89 131 396 MIN 4 TYP 7 4 MAX UNIT k pF k pF mV V mV mV mV mV device PARAMETER IDD VTH VOH VOL IBH+ IBH- IOZ Supply current 3.3 VDD Power status threshold, CPS input High-level output voltage, CTL0, CTL1, D0-D7, PCLK, S5_LKON_DS2 outputs Low-level output voltage, CTL0, CTL1, D0-D7, PCLK, S5_LKON_DS2 outputs Positive peak bus holder current, D0-D7, CTL0-CTL1, LREQ Negative peak bus holder current, D0-D7, CTL0-CTL1, LREQ Off-state output current, CTL0, CTL1, D0-D7, S5_LKON_DS2 I/Os TEST CONDITION See Note 2 400-k resistor VDD = 3 to 3.6 V, IOH = -4 mA IOL = 4 mA VDD = 3.6 V, VI = 0 V to VDD VDD = 3.6 V, VI = 0 V to VDD VO = VDD or 0 V 0.05 -1.0 4.7 2.8 0.4 1 -0.05 5 MIN TYP 75 7.5 MAX UNIT mA V V V mA mA A IIRST Pullup current, RESETz input VI = 1.5 V or 0 V -90 -20 A VO TPBIAS output voltage At rated IO current 1.665 2.015 V Measured at cable power side of resistor. This parameter applicable only when ISO low. NOTE 2: Repeat Max Packet (1 port receiving maximum size isochronous packet--4096 bytes, sent on every isochronous interval, data value of 0xCCCCCCCCh; 2 ports repeating; all ports with S400 beta-mode connection), VDD3.3 = 3.3 V, internal regulator, TA = 25_C POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued) thermal characteristics PARAMETER RJA RJC RJA RJC RJA RJC Junction-to-free-air thermal resistance Junction-to-case-thermal resistance Junction-to-free-air thermal resistance Junction-to-case-thermal resistance Junction-to-free-air thermal resistance Junction-to-case-thermal resistance TEST CONDITION Board mounted, No air flow, High conductivity TI recommended test board, chip soldered or greased to thermal land with 2 oz. copper Board mounted, No air flow, High conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land with 2 oz. copper Board mounted, No air flow, High conductivity JEDEC test board with 1 oz. copper MIN TYP 19.04 0.17 31.52 0.17 49.17 3.11 MAX UNIT C/W C/W C/W C/W C/W C/W switching characteristics PARAMETER tr tf tsu th tsu th td TP differential rise time, transmit TP differential fall time, transmit Setup time, CTL0, CTL1, D1-D7, LREQ to PCLK Hold time, CTL0, CTL1, D1-D7, LREQ after PCLK Setup time, CTL0, CTL1, D1-D7, LREQ to LCLK_PMC Hold time, CTL0, CTL1, D1-D7, LREQ after LCLK_PMC Delay time, PCLK to CTL0, CTL1, D1-D7, PINT 1394a-2000 1394a-2000 1394b 1394b 1394a-2000 and 1394b TEST CONDITION 10% to 90%, 90% to 10%, 50% to 50%, 50% to 50%, 50% to 50%, 50% to 50%, 50% to 50%, At 1394 connector At 1394 connector See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 3 MIN 0.3 0.3 2.5 0 2.5 0 0.5 7 TYP MAX 0.8 0.8 UNIT ns ns ns ns ns ns ns PARAMETER MEASUREMENT INFORMATION TPAx+ TPBx+ 56 TPAx- TPBx- Figure 1. Test Load Diagram 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PARAMETER MEASUREMENT INFORMATION xCLK tsu D, CTL, LREQ th Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms xCLK td D, CTL Figure 3. Dx and CTLx Output Delay Relative to xCLK Waveforms APPLICATION INFORMATION Please obtain from the TI website or your local TI representative the reference schematics, reference layouts, debug documents, and software recommendations for the TSB41BA3. internal register configuration There are 16 accessible internal registers in the TSB41BA3. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which 1 of 8 pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. Note that while this register set is compatible with 1394a-2000 register sets, some fields have been redefined and this register set contains additional fields. Table 2 shows the configuration of the base registers, and Table 3 gives the corresponding field descriptions. The base register field definitions are unaffected by the selected page number. A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION Table 2. Base Register Configuration BIT POSITION Address 0000 0001 0010 0011 0100 0101 0110 0111 LCtrl WDIE RHB IBR Extended (111b) PHY_Speed (111b) C ISBR Max Legacy SPD Page_Select CTOI SREN Jitter (000b) CPSI BLINK Rsvd STOI Bridge Port_Select PEI 0 1 2 Physical ID Gap_Count Num_Ports (0011b) Delay (0000b) Pwr_Class EAA Rsvd EMC 3 4 5 6 R 7 CPS Table 3. Base Register Field Descriptions FIELD Physical ID SIZE 6 TYPE Rd DESCRIPTION This field contains the physical address ID of this node determined during self-ID. The physical-ID is invalid after a bus reset until the self-ID has completed as indicated by an unsolicited register 0 status transfer from the PHY to the LLC. Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1 during tree-ID if this node becomes root. Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to serial bus cable power through a 400-k resistor. A 0 in this bit indicates that the cable power voltage has dropped below its threshold for ensured reliable operation. Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB bit is reset to 0 by a hardware reset, and is unaffected by a bus reset. If two nodes on a single bus have their root holdoff bit set, then the result is not defined. To prevent two nodes from having their root-holdoff bit set, this bit must only be written using a PHY configuration packet. Initiate bus reset. This bit instructs the PHY to initiate a long (166 s) bus reset at the next opportunity. Any receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The IBR bit is reset to 0 after a hardware reset or a bus reset. Care must be exercised when writing to this bit to not change the other bits in this register. It is recommended that whenever possible a bus reset be initiated using the ISBR bit and not the IBR bit. Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet. The gap count is reset to 3Fh by hardware reset or after two consecutive bus resets without an intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet). It is strongly recommended that this field only be changed using PHY configuration packets. Extended register definition. For the TSB41BA3, this field is 111b, indicating that the extended register set is implemented. Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41BA3 this field is 3. PHY speed capability. This field is no longer used. For the TSB41BA3 PHY this field is 111b. Speeds for 1394b PHYs must be checked on a port-by-port basis. Standby/restore enable. This bit when set to 1 enables the port to go into the standby reduced power state when commanded by a Standby PHY command packet. This enable works for all ports of the local device. Note the 1394b standard only allows leaf (one port connected) nodes to be placed into standby mode. PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY, expressed as 144+(delay x 20) ns. For the TSB41BA3 this field is 0. R CPS 1 1 Rd Rd RHB 1 Rd/Wr IBR 1 Rd/Wr Gap_Count 6 Rd/Wr Extended Num_Ports PHY_Speed SREN 3 4 3 1 Rd Rd Rd Rd/Wr Delay 4 Rd 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION Table 3. Base Register Field Descriptions (Continued) FIELD LCtrl SIZE 1 TYPE Rd/Wr DESCRIPTION Link-active status control. This bit controls the indicated active status of the LLC reported in the self-ID packet. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC bit in the node self-ID packet is set active only if both the LPS input is active and the LCtrl bit is set. The LCtrl bit provides a software controllable means to indicate the LLC self-ID active status in lieu of using the LPS input terminal. The LCtrl bit is set to 1 by hardware reset and is unaffected by bus-reset. NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received packets and status information continue to be presented on the interface, and any requests indicated on the LREQ input are processed, even if the LCtrl bit is cleared to 0. Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to 0 on hardware reset. After hardware reset, this bit may only be set via a software register write. This bit is unaffected by a bus reset. PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater data delay, expressed as (jitter+1) x 20 ns. For the TSB41BA3, this field is 0. Node power class. This field indicates this node power consumption and source characteristics and is replicated in the pwr field (bits 21-23) of the self-ID packet. This field is reset to the state specified by the S5-S0 input terminals upon a hardware reset, and is unaffected by a bus reset. See Table 1 and Table 10. Watchdog interrupt enable. This bit, if set to 1, enables the port event interrupt (PIE) bit to be set whenever resume operations begin on any port, or when any of the CTOI, CPSI, or STOI interrupt bits are set and the link interface is nonoperational. This bit is reset to 0 by hardware reset and is unaffected by bus reset. Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 s) arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset. It is recommended that short bus reset is the only reset type initiated by software. IEC 61883-6 requires that a node initiate short bus resets to minimize any disturbance to an audio stream. NOTE: Legacy IEEE Std 1394-1995 compliant PHYs are not capable of performing short bus resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus reset being performed. Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the CTOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the S5_LKON_DS2 output to notify the LLC to service the interrupt. NOTE: If the network is configured in a loop, then only those nodes which are part of the loop generate a configuration-timeout interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus-reset. This bit is only set when the bus topology includes 1394a nodes; otherwise, 1394b loop healing prevents loops from being formed in the topology. Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating that cable power may be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be cleared by writing a 1 to this register bit. If the CPSI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the S5_LKON_DS2 output to notify the LLC to service the interrupt. State-timeout interrupt. This bit indicates that a state time-out has occurred (which also causes a bus-reset to occur). This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. If the STOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the S5_LKON_DS2 output to notify the LLC to service the interrupt. Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (WDIE) bit is set, then the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. C 1 Rd/Wr Jitter Pwr_Class 3 3 Rd Rd/Wr WDIE 1 Rd/Wr ISBR 1 Rd/Wr CTOI 1 Rd/Wr CPSI 1 Rd/Wr STOI 1 Rd/Wr PEI 1 Rd/Wr POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION Table 3. Base Register Field Descriptions (Continued) FIELD EAA SIZE 1 TYPE Rd/Wr DESCRIPTION Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration enhancements defined in 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus reset. This bit has no effect when the device is operating in 1394b mode. NOTE: The use of accelerated arbitration is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. The EAA bit is set only if the attached LLC is 1394a-2000 compliant. If the LLC is not 1394a-2000 or 1394b-2002 compliant, then the use of the arbitration acceleration enhancements can interfere with isochronous traffic by excessively delaying the transmission of cycle-start packets. Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of differing speeds in accordance with the protocols defined in 1394a-2000. This bit is reset to 0 by hardware reset and is unaffected by bus reset. This bit has no effect when the device is operating in 1394b mode. NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be 1394a-2000 or 1394b-2002 compliant. Maximum legacy-path speed. This field holds the maximum speed capability of any legacy node (1394a-2000 or 1394-1995 compliant) as indicated in the self-ID packets received during bus-initialization. Encoding is the same as for the PHY_SPEED field (but limited to S400 maximum). Beta-mode link. This bit indicates that a beta-mode capable link is attached to the PHY. This bit is set by the BMODE input terminal on the TSB41BA3. This field controls the value of the bridge (brdg) field in self-ID packet. The power reset value is 0. Details for when to set these bits are specified in the IEEE 1394.1 bridging specification. Page_Select. This field selects the register page to use when accessing register addresses 8 through 15. This field is reset to 0 by a hardware reset and is unaffected by bus-reset. Port_Select. This field selects the port when accessing per-port status or control (for example, when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by hardware-reset and is unaffected by bus-reset. EMC 1 Rd/Wr Max Legacy SPD BLINK Bridge Page_Select Port_Select 3 Rd 1 2 3 4 Rd Rd/Wr Rd/Wr Rd/Wr The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 4 shows the configuration of the port status page registers, and Table 5 gives the corresponding field descriptions. If the selected port is unimplemented, then all registers in the port status page are read as 0. Table 4. Page 0 (Port Status) Register Configuration BIT POSITION Address 1000 1001 1010 1011 1100 1101 1110 1111 Reserved 0 Astat Negotiated_speed DC_connected Connection_unreliable Max_port_speed Reserved Sleep_Flag Port_error Sleep_enable Loop_disable In_standby Hard_disable Reserved Reserved 1 2 BStat PIE 3 4 Ch Fault LPP Beta_mode 5 Con Standby_fault 6 RXOK Disscrm Cable_speed Reserved 7 Dis B_Only(0) 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION Table 5. Page 0 (Port Status) Register Field Descriptions FIELD Astat SIZE 2 TYPE Rd DESCRIPTION TPA line state. This field indicates the instantaneous TPA line state of the selected port, encoded as follows: Code Arb Value 11 Z 01 1 10 0 00 invalid TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the AStat field. Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid after a bus-reset until tree-ID has completed. Debounced port connection status. This bit indicates that the selected port is connected. The connection must be stable for the debounce time of approximately 341 ms for the Con bit to be set to 1. The Con bit is reset to 0 by hardware reset and is unaffected by bus-reset. NOTE: The Con bit indicates that the port is physically connected to a peer PHY, but this does not mean that the port is necessarily active. For 1394b-coupled connections, the Con bit is set when a port detects connection tones from the peer PHY and operating speed negotiation is completed. Receive OK. In 1394a-2000 mode this bit indicates the reception of a debounced TPBias signal. In Beta_mode, this bit indicates the reception of a continuous electrically valid signal. Note: RxOK is set to false during the time that only connection tones are detected in beta mode. Port disabled control. If this bit is 1, then the selected port is disabled. The Dis bit is reset to 0 by hardware reset (all ports are enabled for normal operation following hardware reset). The Dis bit is not affected by bus-reset. When this bit is set, the port cannot become active; however, the port still tones, but does not establish an active connection. Indicates the maximum speed negotiated between this PHY port and its immediately connected port. The encoding is as for Max_port_speed. It is set on connection when in Beta_mode, or to a value established during self-ID when in 1394a-2000 mode. Port event interrupt enable. When this bit is 1, a port event on the selected port sets the port event interrupt (PEI) bit and notifies the link. This bit is reset to 0 by a hardware reset, and is unaffected by bus-reset. Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect incoming cable bias from its attached peer. Writing 1 to this bit clears the Fault bit to 0. This bit is reset to 0 by hardware reset and is unaffected by bus-reset. This bit is set to 1 if an error is detected during a standby operation and cleared on exit from the standby state. A write of 1 to this bit or receipt of the appropriate remote command packet clears it to 0. When this bit is cleared, standby errors are cleared. Disable scrambler. If this bit is set to 1, then the data sent during packet transmission is not scrambled. Beta-mode operation only. For the TSB41BA3, this bit is set to 0 for all ports when all ports are programmed as bilingual or a combination of bilingual and data-strobe (1394a) only. If a port has been programmed to be beta-only at a selected speed (for example B1 is beta-only S100), then this bit is set to 1. If this bit is set to 1, the port has detected a dc connection to the peer port by means of a 1394a-style connect detect circuit. Bstat Ch 2 1 Rd Rd Con 1 Rd RxOK 1 Rd Dis 1 Rd/Wr Negotiated_speed 3 Rd PIE 1 Rd/Wr Fault 1 Rd/Wr Standby_fault 1 Rd/Wr Disscrm B_Only 1 1 Rd/Wr Rd DC_connected 1 Rd POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION Table 5. Page 0 (Port Status) Register Field Descriptions (Continued) FIELD Max_port_speed SIZE 3 TYPE Rd/Wr DESCRIPTION Max_port_speed The maximum speed at which a port is allowed to operate in beta mode. The encoding is: 000 = S100 001 = S200 010 = S400 011 = S800 100 = S1600 101 = S3200 110 = reserved 111 = reserved An attempt to write to the register with a value greater than the hardware capability of the port results in the maximum value that the port is capable of being stored in the register. The port uses this register only when a new connection is established in the beta mode when a port is programmed as a beta-only port. When a port is programmed as a bilingual port, it is fixed at S400 for the beta speed and is not updated by a write to this register. The power reset value is the maximum speed capable of the port. Software may modify this value to force a port to train at a lower than maximum (when in a beta-only mode), but no lower than minimum speed. This flag is set permanently to 1. This variable is set to the maximum speed that the port is capable of. The encoding is the same as for Max_port_speed. If this bit is set to 1, then a beta mode speed negotiation has failed or synchronization has failed. A write of 1 to this field resets the value to 0. Operating in beta mode. If this bit is 1, the port is operating in beta mode; it is equal to 0 otherwise (that is, when operating in 1394a-2000 mode, or when disconnected). If Con is 1, RxOK is 1, and Beta_mode is 0, then the port is active and operating in the 1394a-2000 mode. Incremented whenever the port receives an invalid codeword, unless the value is already 255. Cleared when read (including being read by means of a remote access packet). Intended for use by a single bus-wide diagnostic program. This bit is set to 1 if the port is in the sleep state. The transition to the sleep state occurs only if the port has been enabled for the sleep mode. This bit is set to 1 if the port has been enabled for sleep mode. If SLPEN pin is sampled high during reset, then this bit is set high for all ports. If sampled low, then it is 0. Software may individually enable or disasble sleep mode for a port by writing to this bit. Sleep mode operation is described in IDB-1394 specification. In PMC mode when no link is present the sleep state of each port can be monitored on the data lines as described in the Terminal Functions table entry for LCLK_PMC. This bit is set to 1 if the port has been placed in the loop disable state as part of the loop free build process (the PHYs at either end of the connection are active, but if the connection itself were activated, then a loop would exist). Cleared on bus reset and on disconnection. This bit is set to 1 if the port is in standby power-management state. No effect unless the port is disabled. If this bit is set to 1, the port does not maintain connectivity status on an ac connection when disabled. The values of the Con and RxOK bits are forced to 0. This flag can be used to force renegotiation of the speed of a connection. It can also be used to place the device into a lower power state since when hard disabled, a port no longer tones to maintain 1394b ac-connectivity status. LPP (Local_plug_present) Cable_speed Connection_unreliable Beta_mode 1 3 1 1 Rd Rd Rd/Wr Rd Port_error 8 Rd/Wr Sleep_Flag Sleep_enable 1 1 Rd Rd/Wr Loop_disable 1 Rd In_standby Hard_disable 1 1 Rd Rd/Wr 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. Table 6 shows the configuration of the vendor identification page, and Table 7 shows the corresponding field descriptions. Table 6. Page 1 (Vendor ID) Register Configuration BIT POSITION Address 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 Compliance Reserved Vendor_ID[0] Vendor_ID[1] Vendor_ID[2] Product_ID[0] Product_ID[1] Product_ID[2] 4 5 6 7 Table 7. Page 1 (Vendor ID) Register Field Descriptions FIELD Compliance Vendor_ID Product_ID SIZE 8 24 24 TYPE Rd Rd Rd DESCRIPTION Compliance level. For the TSB41BA3 this field is 02h, indicating compliance with the 1394b-2002 specification. Manufacturer's organizationally unique identifier (OUI). For the TSB41BA3 this field is 08_00_28h (Texas Instruments) (the MSB is at register address 1010b). Product identifier. For the TSB41BA3 this field is 83_30_01h (the MSB is at register address 1101b). The vendor-dependent page provides access to the special control features of the TSB41BA3, as well as configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. Table 8 shows the configuration of the vendor-dependent page, and Table 9 shows the corresponding field descriptions. Table 8. Page 7 (Vendor-Dependent) Register Configuration BIT POSITION Address 1000 1001 1010 1011 1100 1101 1110 1111 SWR 0 1 2 Reserved Reserved for test Reserved for test Reserved for test Reserved for test Reserved for test Reserved for test Reserved for test 3 4 5 6 Reserved 7 Table 9. Page 7 (Vendor-Dependent) Register Field Descriptions FIELD SWR SIZE 1 TYPE Rd/Wr DESCRIPTION Software hard reset. Writing a 1 to this bit forces a hard reset of the PHY (same effect as momentarily asserting the RESETz terminal low). This bit is always read as a 0. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION power-class programming The S2_PC0, S1_PC1, and S2_PC2 terminals can be used in some port speed/mode selections to set the default value of the power-class indicated in the pwr field (bits 21-23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 10. The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4. Table 10. Power Class Descriptions PC0-PC2 000 001 010 011 100 101 110 111 DESCRIPTION Node does not need power and does not repeat power. Node is self-powered and provides a minimum of 15 W to the bus. Node is self-powered and provides a minimum of 30 W to the bus. Node is self-powered and provides a minimum of 45 W to the bus. Node may be powered from the bus and is using up to 3 W, no additional power is needed to enable the link. The node may also provide power to the bus. The amount of bus power that it provides can be found in the configuration ROM. Reserved for future standardization. Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link. Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link. 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION power-class programming (continued) Outer Shield Termination TSB41BA3 CPS 400 k VP Cable Power Pair 270 F TPBIAS 56 TPA+ TPA- 56 1 F Cable Pair A 1 M Cable Port TPB+ TPB- 56 0.1 F Cable Pair B 56 VG 270 pF (see Note A) 5 k NOTE A: The IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 270-pF capacitor is recommended. Figure 4. Typical TP Cable Connections Outer Cable Shield 1 M 0.01 F 0.001 F Chassis Ground Figure 5. Typical DC Isolated Outer Shield Termination POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION power-class programming (continued) Outer Cable Shield Chassis Ground Figure 6. Non-DC Isolated Outer Shield Termination 10 k Link Power LPS Square Wave Input 10 k LPS Figure 7. Nonisolated Connection Variations for LPS PHY VDD 18 k Square Wave Signal 0.033 F 13 k LPS PHY GND Figure 8. Isolated Circuit Connection for LPS 26 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION designing with PowerPAD The TSB41BA3 is housed in a high performance, thermally enhanced, 80-terminal PFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches or vias under the package. The recommended option, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the maximum size required for the keepout area for the 80-terminal PFP PowerPAD package is 10 mm x 10 mm. The actual PowerPAD size for the TSB41BA3 is 6 mm x 6 mm. It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land varies in size, depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction. Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report, (SLMA002), available via the TI Web pages at URL: http://www.ti.com. Figure 9. Example of a Thermal Land for the TSB41BA3 PHY For the TSB41BA3, this thermal land must be grounded to the low impedance ground plane of the device. This improves not only thermal performance but also the electrical grounding of the device. It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size ought to be as large as possible without shorting device signal terminals. The thermal land may be soldered to the exposed PowerPAD using standard reflow soldering techniques. While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low impedance ground plane for the device. More information may be obtained from the TI application note PHY Layout, (SLLA020). PowerPAD is a trademark of Texas Instruments. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION using the TSB41BA3 with a 1394-1995 or 1394a-2000 link layer The TSB41BA3 implements the PHY-LLC interface specified in the 1394b Supplement. This interface is based upon the interface described in Section 17 of IEEE 1394b-2002. When using a LLC compliant with this interface, the BMODE input must be tied high. The TSB41BA3 also functions with a LLC that is compliant with the older 1394 standards. This interface is compatible with both the older Annex J interface specified in the IEEE Std 1394-1995 (with the exception of the Annex J isolation interfacing method) and the PHY-LLC interface specified in 1394a-2000. When using a LLC compliant with this interface, the BMODE input must be tied low. When the BMODE input is tied low, the TSB41BA3 implements the PHY-LLC interface specified in the 1394a-2000 Supplement. This interface is based upon the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in the oldest TI PHY devices. The PHY-LLC interface specified in 1394a-2000 is compatible with the older Annex J. However, the TSB41BA3 does not support the Annex J isolation interfacing method. When implementing the 1394a-2000 interface, certain signals are not used: - - The PINT output (terminal 1) may be left open The LCLK_PMC input (terminal 7) must be tied directly to ground or through a pulldown resistor of ~1 k or less, unless the PMC mode is desired (see LCLK_PMC terminal description). All other signals are connected to their counterparts on the 1394a link-layer controller. The PCLK output corresponds to the SCLK input signal on most LLCs. The 1394a-2000 Supplement includes enhancements to the Annex J interface that should be comprehended when using the TSB41BA3 with a 1394-1995 LLC device. D A new LLC service request was added which allows the LLC to temporarily enable and disable asynchronous arbitration accelerations. If the LLC does not implement this new service request, then the arbitration enhancements must not be enabled (see the EAA bit in PHY register 5). D The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not support multispeed concatenation, then multispeed concatenation must not be enabled in the PHY (see the EMC bit in PHY register 5). D In order to accommodate the higher transmission speeds expected in future revisions of the standard, 1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus request from 7 bits to 8 bits. The new speed codes were carefully selected so that new 1394a-2000 PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit speed codes. The TSB41BA3 correctly interprets both 7-bit bus requests (with 2-bit speed code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by another request (for example, a register read or write request), then the TSB41BA3 correctly interprets both requests. Although the TSB41BA3 correctly interprets 8-bit bus requests, a request with a speed code exceeding S400 while in 1394a-2000 PHY-link interface mode results in the TSB41BA3 transmitting a null packet (data-prefix followed by data-end, with no data in the packet). 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION power-up reset To ensure proper operation of the TSB41BA3 the RESETz terminal must be asserted low for a minimum of 2 ms from the time that PHY power reaches the minimum required supply voltage and the input clock to the PHY is valid. When using a passive capacitor on the RESETz terminal to generate a power-on reset signal, the minimum reset time is assured if the value of the capacitor satisfies the following equation (the value must be no smaller than approximately 0.1 F): Cmin = 0.0077 * T + 0.085 + (external_oscillator_start-up_time * 0.05) Where Cmin is the minimum capacitance on the RESETz terminal in F, T is the VDD ramp time, 10%-90%, in ms, external_oscillator_start-up_time is the time from power applied to the external oscillator until the oscillator outputs a valid clock in ms. If a crystal is used rather than an oscillator, then the external_oscillator_start-up_time may be set to 0. For example with a 2-ms power ramp time and a 2-ms oscillator startup time: Cmin = 0.0077 * 2 + 0.085 + (2 * 0.05) = 0.2 F It is appropriate to select the nearest standard value capacitor that exceeds this value, for example 0.22 F. Or with a 2-ms power ramp time and a 49.152-MHz fundamental crystal: Cmin = 0.0077 * 2 + 0.085 + (0 * 0.05) = 0.1 F crystal oscillator selection The TSB41BA3 and other TI PHY devices are designed to use an external 49.152-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates. A variation of less than 100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must be able to compensate for this difference over the maximum packet length. Larger clock variations may cause resynchronization overflows or underflows, resulting in corrupted packet data or even PHY lockup. For the TSB41BA3, the PCLK output may be used to measure the frequency accuracy and stability of the internal oscillator and PLL from which it is derived. When operating the PHY-LLC interface with a non-1394b LLC, the frequency of the PCLK output must be within 100 ppm of the nominal frequency of 49.152 MHz. When operating the PHY-LLC interface with a 1394b LLC, the frequency of the PCLK output must be within 100 ppm of the nominal frequency of 98.304 MHz. The following are some typical specifications for crystals used with the physical layers from TI in order to achieve the required frequency accuracy and stability: D Crystal mode of operation: Fundamental D Frequency tolerance at 25_C: Total frequency variation for the complete circuit is 100 ppm. A crystal with 30 ppm frequency tolerance is recommended for adequate margin. for adequate margin. D Frequency stability (over temperature and age): A crystal with 30 ppm frequency stability is recommended POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 29 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION NOTE: The total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the oscillator alone. Aging also contributes to the frequency variation. D Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation is dependent upon the load capacitance specified for the crystal. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also board layout and circuit. It may be necessary to iteratively select discrete load capacitors until the PCLK output is within specification. It is recommended that load capacitors with a maximum of 5% tolerance be used. As an example, for the OHCI + 41LV03 evaluation module (EVM) which uses a crystal specified for 12 pF loading, load capacitors (C9 and C10 in Figure 10) of 16 pF each were appropriate for the layout of that particular board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals (CPHY), and the loading of the board itself (CBD). The value of CPHY is typically about 1 pF, and CBD is typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is: C L + C9 C10 ) C PHY ) C BD C9 ) C10 C9 X1 X1 49.152 MHz CPHY + CBD IS X0 C10 Figure 10. Load Capacitance for the TSB41BA3 PHY NOTE: The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency, minimizing noise introduced into the PHY's phase lock loop, and minimizing any emissions from the circuit. The crystal and two load capacitors must be considered as a unit during layout. The crystal and load capacitors must be placed as close as possible to one another while minimizing the loop area created by the combination of the three components. Varying the size of the capacitors may help in this. Minimizing the loop area minimizes the effect of the resonant current (IS) that flows in this resonant circuit. This layout unit (crystal and load capacitors) must then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. C9 C10 X1 Figure 11. Recommended Crystal and Capacitor Layout 30 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION It is strongly recommended that part of the verification process for the design be to measure the frequency of the PCLK output of the PHY. This should be done with a frequency counter with an accuracy of 6 digits or better. If the PCLK frequency is more than the crystal's tolerance from 49.152 MHz or 98.304 MHz, then the load capacitance of the crystal may be varied to improve frequency accuracy. If the frequency is too high, add more load capacitance; if the frequency is too low, decrease load capacitance. Typically, changes must be done to both load capacitors (C9 and C10 above) at the same time, and both must be of the same value. Additional design details and requirements may be provided by the crystal vendor. bus reset It is recommended, that whenever the user has a choice, the user should initiate a bus reset by writing to the initiate short bus reset (ISBR) bit (bit 1 PHY register 0101b). Care must be taken to not change the value of any of the other writeable bits in this register when the ISBR bit is written to. In the TSB41BA3, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization sequence, however, it is recommended to use the ISBR bit instead. The IBR bit is located in PHY register 1 along with the root-holdoff (RHB) bit and gap-count register. As required by the 1394b Supplement this configuration maintains compatibility with older TI PHY designs which were based upon either the suggested register set defined in Annex J of IEEE Std 1394-1995 or the 1394a-2000 Supplement. Therefore, whenever the IBR bit is written, the RHB bit and gap-count are also necessarily written. It is recommended that the RHB bit and gap-count only be updated by PHY configuration packets. The TSB41BA3 is 1394a and 1394b compliant, and therefore both the reception and transmission of PHY configuration packets cause the RHB and gap-count to be loaded, unlike older IEEE Std 1394-1995 compliant PHYs which decode only received PHY configuration packets. The gap-count is set to the maximum value of 63 after two consecutive bus resets without an intervening write to the gap-count, either by a write to PHY register 1 or by a PHY configuration packet. This mechanism allows a PHY configuration packet to be transmitted and then a bus reset to be initiated so as to verify that all nodes on the bus have updated their RHB bits and gap-count values, without having the gap-count set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the gap-count of each node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, then all other nodes on the bus have their gap-count values set to 63, while this node's gap-count remains set to the value just loaded by the write to PHY register 1. Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use of the IBR bit, RHB bit, and gap-count in PHY register 1: D Following the transmission of a PHY configuration packet, a bus reset must be initiated in order to verify that all nodes have correctly updated their RHB bits and gap-count values, and to ensure that a subsequent new connection to the bus causes the gap-count to be set to 63 on all nodes in the bus. If this bus reset is initiated by setting the IBR bit to 1, then the RHB bit and gap-count register must also be loaded with the correct values consistent with the just transmitted PHY configuration packet. In the TSB41BA3, the RHB bit and gap-count have been updated to their correct values upon the transmission of the PHY configuration packet, and so these values may first be read from register 1 and then rewritten. D Other than to initiate the bus reset which must follow the transmission of a PHY configuration packet, whenever the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63 so as to be consistent with other nodes on the bus, and the RHB bit must be maintained with its current value. D The PHY register 1 must not be written to except to set the IBR bit. The RHB bit and gap-count must not be written without also setting the IBR bit to 1. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 31 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 APPLICATION INFORMATION bus reset (continued) D To avoid these problems all bus resets initiated by software must be initiated by writing the ISBR bit (bit 1 PHY register 0101b). Care must be taken to not change the value of any of the other writeable bits in this register when the ISBR bit is written to. Also, the only means to change the gap count of any node must be by means of the PHY configuration packet, which changes all nodes to the same gap count. 32 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) The TSB41BA3 is designed to operate with an LLC such as the Texas Instruments TSB12LV21B, TSB12LV26, TSB12LV32, TSB42AA4, or TSB12LV01B when the BMODE terminal is tied low. Details of operation for the Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface. This interface is formally defined in IEEE 1394a-2000, Section 5A. The interface to the LLC consists of the PCLK, CTL0-CTL1, D0-D7, LREQ, LPS, and S5_LKON_DS2 terminals on the TSB41BA3, as shown in Figure 12. TSB41BA3 PCLK (SYSCLK) CTL0-CTL1 Link-Layer Controller D0-D7 LREQ LPS S5_LKON_DS2 Figure 12. PHY-LLC Interface The PCLK terminal provides a 49.152-MHz interface system clock. All control and data signals are synchronized to, and sampled on, the rising edge of PCLK. This terminal serves the same function as the SYSCLK terminal of 1394a-2000 compliant PHY devices. The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data between the TSB41BA3 and LLC. The D0-D7 terminals form a bidirectional data bus, which transfers status information, control information, or packet data between the devices. The TSB41BA3 supports S100, S200, and S400 data transfers over the D0-D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200 operation only the D0-D3 terminals are used; and in S400 operation all D0-D7 terminals are used for data transfer. When the TSB41BA3 is in control of the D0-D7 bus, unused Dn terminals are driven low during S100 and S200 operations. When the LLC is in control of the D0-D7 bus, unused Dn terminals are ignored by the TSB41BA3. The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access to the serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration. The LPS and S5_LKON_DS2 terminals are used for power management of the PHY and LLC. The LPS terminal indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable PCLK. The S5_LKON_DS2 terminal sends a wake-up notification to the LLC or external circuitry and indicates an interrupt to the LLC when either LPS is inactive or the PHY register L bit is 0. The TSB41BA3 normally controls the CTL0-CTL1 and D0-D7 bidirectional buses. The LLC is allowed to drive these buses only after the LLC has been granted permission to do so by the PHY. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 33 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY to gain control of the serial-bus in order to transmit a packet, or to control arbitration acceleration. The PHY may initiate a status transfer either autonomously or in response to a register read request from the LLC. The PHY initiates a receive operation whenever a packet is received from the serial-bus. The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. Table 11 and Table 12 show the encoding of the CTL0-CTL1 bus. Table 11. CTL Encoding When PHY Has Control of the Bus CTL0 0 0 1 1 CTL1 0 1 0 1 NAME Idle Status Receive Grant No activity (this is the default mode) Status information is being sent from the PHY to the LLC. An incoming packet is being sent from the PHY to the LLC. The LLC has been given control of the bus to send an outgoing packet. DESCRIPTION Table 12. CTL Encoding When LLC Has Control of the Bus CTL0 0 0 1 1 CTL1 0 1 0 1 NAME Idle Hold Transmit Reserved DESCRIPTION The LLC releases the bus (transmission has been completed) The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet is to be transmitted (concatenated) without arbitrating An outgoing packet is being sent from the LLC to the PHY None LLC service request To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends a serial bit stream on the LREQ terminal as shown in Figure 13. LR0 LR1 LR2 LR3 LR (n-2) LR (n-1) Each cell represents one clock sample time, and n is the number of bits in the request stream. Figure 13. LREQ Request Stream 34 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) LLC service request (continued) The length of the stream varies depending on the type of request as shown in Table 13. Table 13. Request Stream Bit Length REQUEST TYPE Bus request Read register request Write register request Acceleration control request NUMBER OF BITS 7 or 8 9 17 6 Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. The second through fourth bits of the request stream indicate the type of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low. Table 14 shows the encoding for the request type. Table 14. Request Type Encoding LR1-LR3 000 001 010 011 100 101 110 111 NAME ImmReq IsoReq PriReq FairReq RdReg WrReg AccelCtl Reserved DESCRIPTION Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration. Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap. Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol. Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol. The PHY returns the specified register contents through a status transfer Write to the specified register Enable or disable asynchronous arbitration acceleration Reserved For a bus request, the length of the LREQ bit stream is 7 or 8 bits as shown in Table 15. Table 15. Bus Request BIT(s) 0 1-3 4-6 7 NAME Start bit Request type Request speed Stop bit DESCRIPTION Indicates the beginning of the transfer (always 1) Indicates the type of bus request. See Table 14. Indicates the speed at which the PHY sends the data for this request. See Table 16 for the encoding of this field. Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit may be omitted. Table 16 shows the 3-bit request speed field used in bus requests. Table 16. Bus Request Speed Encoding LR4-LR6 000 010 100 All Others DATA RATE S100 S200 S400 Invalid POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 35 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) LLC service request (continued) NOTE: The TSB41BA3 accepts a bus request with an invalid speed code and processes the bus request normally. However, during packet transmission for such a request, the TSB41BA3 ignores any data presented by the LLC and transmits a null packet. For a read register request the length of the LREQ bit stream is 9 bits as shown in Table 17. Table 17. Read Register Request BIT(s) 0 1-3 4-7 8 NAME Start bit Request type Address Stop bit A 100 indicating this is a read register request Identifies the address of the PHY register to be read Indicates the end of the transfer (always 0) DESCRIPTION Indicates the beginning of the transfer (always 1) For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 18. Table 18. Write Register Request BIT(s) 0 1-3 4-7 8-15 16 NAME Start bit Request type Address Data Stop bit A 101 indicating this is a write register request Identifies the address of the PHY register to be written to Gives the data that is to be written to the specified register address Indicates the end of the transfer (always 0) DESCRIPTION Indicates the beginning of the transfer (always 1) For an acceleration control request, the length of the LREQ data stream is 6 bits as shown in Table 19. Table 19. Acceleration Control Request BIT(s) 0 1-3 4 5 NAME Start bit Request type Control Stop bIt DESCRIPTION Indicates the beginning of the transfer (always 1) A 110 indicating this is an acceleration control request Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0 Indicates the end of the transfer (always 0) For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests if the receive state is asserted while the LLC is sending the request. The LLC may then reissue the request one clock after the next interface idle. The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears an isochronous request only when the serial bus has been won. 36 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) LLC service request (continued) To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to send another type of packet. After the interface is released the LLC may proceed with another request. The LLC may make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are cleared upon a bus reset. For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the PHY continues to attempt the transfer of the requested register until it is successful. A write or read register request may be made at any time, including while a bus request is pending. Once a read register request is made, the PHY ignores further read register requests until the register contents are successfully transferred to the LLC. A bus reset does not clear a pending read register request. The TSB41BA3 includes several arbitration acceleration enhancements, which allow the PHY to improve bus performance and throughput by reducing the number and length of interpacket gaps. These enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set. The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances. The acceleration control request is therefore provided to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the TSB41BA3 during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start message is imminent, and then re-enables the enhancements when it receives a cycle start message. The acceleration control request may be made at any time, however, and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request causes the enhancements to be re-enabled, if the EAA bit is set. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 37 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) status transfer A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting status (01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals. The PHY maintains CTL = Status for the duration of the status transfer. The PHY may prematurely end a status transfer by asserting something other than status on the CTL terminals. This occurs if a packet is received before the status transfer completes. The PHY continues to attempt to complete the transfer until all status information has been successfully transmitted. There is at least one idle cycle between consecutive status transfers. The PHY normally sends just the first 4 bits of status to the LLC. These bits are status flags that are needed by the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register request, or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined condition where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the physical-ID register that contains the new node address. All status transfers are either 4 or 16 bits unless interrupted by a received packet. The status flags are considered to have been successfully transmitted to the LLC immediately upon being sent, even if a received packet subsequently interrupts the status transfer. Register contents are considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status transfer is retried after being interrupted only if any status flags remain to be sent, or if a register transfer has not yet completed. Table 20 shows the definition of the bits in the status transfer and Figure 14 shows the timing. Table 20. Status Bits BIT(s) 0 1 2 3 4-7 8-15 NAME Arbitration reset gap Subaction gap Bus reset Interrupt Address Data DESCRIPTION Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as defined in the IEEE 1394a-2000 standard). This bit is used by the LLC in the busy/retry state machine. Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the IEEE 1394a-2000 standard). This bit is used by the LLC to detect the completion of an isochronous cycle. Indicates that the PHY has entered the bus reset state Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out, a cable-power voltage falling too low, a state time-out, or a port status change. This field holds the address of the PHY register whose contents are being transferred to the LLC This field holds the register contents SYSCLK CTL0, CTL1 00 (a) 01 (b) S[0:1] S[14:15] 00 D0, D1 00 00 Figure 14. Status Transfer Timing 38 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) status transfer (continued) The sequence of events for a status transfer is as follows: (a) Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless interrupted by a receive operation), a status transfer is either 2 or 8 cycles long. A 2-cycle (4-bit) transfer occurs when only status information is to be sent. An 8-cycle (16-bit) transfer occurs when register data is to be sent in addition to any status information. (b) Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines. The PHY may also interrupt a status transfer at any cycle by asserting receive on the CTL lines to begin a receive operation. The PHY asserts at least one idle cycle between consecutive status transfers. receive Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive on the CTL terminals and a logic 1 on each of the D bus terminals (data-on indication). The PHY indicates the start of a packet by placing the speed code (encoded as shown in Table 21) on the D terminals, followed by packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet has been transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included in the calculation of CRC or any other data protection mechanisms. It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D bus terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all cases, in normal operation, the TSB41BA3 sends at least one data-on indication before sending the speed code or terminating the receive operation. The TSB41BA3 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization, to the LLC. This packet it transferred to the LLC just as any other received self-ID packet. SYSCLK CTL0, CTL1 (a) (b) 10 00 (e) (c) D0-D7 XX FF (data-on) SPD (d) d0 dn 00 NOTE A: SPD = Speed code, see Table 21. d0-dn = Packet data Figure 15. Normal Packet Reception Timing POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 39 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) receive (continued) The sequence of events for a normal packet reception is as follows: (a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle. (b) Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more cycles preceding the speed-code. (c) Speed-code. The PHY indicates the speed of the received packet by asserting a speed-code on the D lines for one cycle immediately preceding packet data. The link decodes the speed-code on the first receive cycle for which the D lines are not the data-on code. If the speed-code is invalid or indicates a speed higher that that which the link is capable of handling, then the link must ignore the subsequent data. (d) Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet data on the D lines with receive on the CTL lines for the remainder of the receive operation. (e) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. SYSCLK CTL0, CTL1 (a) D0-D7 XX 10 (b) FF (data-on) 00 (c) 00 Figure 16. Null Packet Reception Timing The sequence of events for a null packet reception is as follows: (a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle. (b) Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles. (c) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. Table 21. Receive Speed Codes D0-D7 00XX XXXX 0100 XXXX 0101 0000 11YY YYYY DATA RATE S100 S200 S400 data-on indication NOTE: X = Output as 0 by PHY, ignored by LLC. Y = Output as 1 by PHY, ignored by LLC. 40 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) transmit When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting the grant state (11b) on the CTL terminals for one PCLK cycle, followed by idle for one clock cycle. The LLC then takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless the LLC is immediately releasing the interface, the LLC may assert the idle state for at most one clock before it must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control of the bus while it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (that is, the LLC need not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this time. When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle, and then asserts idle for one additional cycle before releasing the interface bus and putting the CTL and D terminals in a high-impedance state. The PHY then regains control of the interface bus. The hold state asserted at the end-of-packet transmission indicates to the PHY that the LLC requests to send another packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation request by waiting the required minimum packet separation time and then asserting grant as before. This function may be used to send a unified response after sending an acknowledge, or to send consecutive isochronous packets during a single isochronous period. Unless multispeed concatenation is enabled, all packets transmitted during a single bus ownership must be of the same speed (since the speed of the packet is set before the first packet). If multispeed concatenation is enabled (when the EMSC bit of PHY register 5 is set), then the LLC must specify the speed code of the next concatenated packet on the D terminals when it asserts hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the speed code that precedes received packet data as given in Table 21. After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC, there is an extra clock period allowed so that both sides of the interface can operate on registered versions of the interface signals. SYSCLK (a) CTL0, CTL1 00 11 00 (b) 00 (c) 01 (d) 10 (e)/(f) 00/01 00 (g) 00 D0-D7 00 00 d0, d1, . . . dn 00/SP 00 00 Link Controls CTL and D PHY High-Impedance CTL and D Outputs NOTE A: SPD = Speed code, see Table 21. d0-dn = Packet data Figure 17. Normal Packet Transmission Timing POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 41 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION transmit (continued) The sequence of events for a normal packet transmission is as follows: (a) Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link so that the link may transmit a packet. The PHY releases control of the interface (that is, it places its CTL and D outputs in a high-impedance state) following the idle cycle. (b) Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit. (c) Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These hold cycle(s) are optional; the link is not required to assert hold preceding transmit. (d) Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with the data on the D lines. (e) Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on the CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in order to transmit a concatenated packet. The link asserts idle to indicate that packet transmission is complete and the PHY may release the serial bus. The link then asserts idle for one more cycle following this hold or idle cycle before releasing the interface and returning control to the PHY. (f) Concatenated packet speed-code. If multispeed concatenation is enabled in the PHY, then the link asserts a speed-code on the D lines when it asserts hold to terminate packet transmission. This speed-code indicates the transmission speed for the concatenated packet that is to follow. The encoding for this concatenated packet speed-code is the same as the encoding for the received packet speed-code (see Table 21). The link may not concatenate an S100 packet onto any higher-speed packet. (g) After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status transfer, receive operation, or transmit operation. SYSCLK (a) (b) (c) (d) (e) CTL0, CTL1 00 11 00 00 01 00 00 D0-D7 00 00 00 Link Controls CTL and D PHY High-Impedance CTL and D Outputs Figure 18. Cancelled/Null Packet Transmission 42 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) transmit (continued) The sequence of events for a cancelled/null packet transmission is as follows: (a) Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link. (b) Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle is optional; the link is not required to assert idle preceding hold. (c) Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These hold cycle(s) are optional; the link is not required to assert hold preceding idle. (d) Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle on the CTL lines and then releasing the interface and returning control to the PHY. Note that the link may assert idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does not assert hold. It is recommended that the link assert three cycles of idle to cancel a packet transmission if no hold cycles are asserted. This ensures that either the link or PHY controls the interface in all cycles. (e) After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status transfer, receive operation, or transmit operation. interface reset and disable The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface may be placed into a reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface is not operational (whether reset, disabled, or in the process of initialization), the PHY cancels any outstanding bus request or register read request, and ignores any requests made via the LREQ line. Additionally, any status information generated by the PHY is not queued and does not cause a status transfer upon restoration of the interface to normal operation. The LPS signal may be either a level signal or a pulsed signal, depending upon whether the PHY-LLC interface is a direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY and LLC the LPS signal must be pulsed. In a direct connection, the LPS signal may be either a pulsed or a level signal. Timing parameters for the LPS signal are given in Table 22. Table 22. LPS Timing Parameters PARAMETER TLPSL TLPSH TLPS_RESET TLPS_DISABLE TRESTORE TCLK_ACTIVATE DESCRIPTION LPS low time (when pulsed) (see Note 5) LPS high time (when pulsed) (see Note 5) LPS duty cycle (when pulsed) (see Note 6) Time for PHY to recognize LPS deasserted and reset the interface Time for PHY to recognize LPS deasserted and disable the interface Time to permit optional isolation circuits to restore during an interface reset Time for PCLK to be activated from reassertion of LPS PHY not in low-state MIN 0.09 0.021 20% 2.60 26.03 15 MAX 2.60 2.60 60% 2.68 26.11 23 60 s s s ns UNIT s s PHY in low-power state 5.3 7.3 ms The maximum value for TRESTORE does not apply when the PHY-LLC interface is disabled, in which case an indefinite time may elapse before LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for less than TLPS_DISABLE. NOTES: 3. The specified TLPSL and TLPSH times are worst-case values appropriate for operation with the TSB41BA3. These values are broader than those specified for the same parameters in the 1394a-2000 Supplement (that is, an implementation of LPS that meets the requirements of 1394a-2000 operates correctly with the TSB41BA3). 4. A pulsed LPS signal must have a duty cycle (ratio of TLPSH to cycle period) in the specified range to ensure proper operation when using an isolation barrier on the LPS signal (for example, as shown in Figure 8). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 43 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) interface reset and disable (continued) The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request activity. When the PHY observes that LPS has been deasserted for TLPS_RESET, it resets the interface. When the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity on the LREQ signal. Figure 19 shows the timing for interface reset. (a) PCLK (c) CTL0, CTL1 D0 - D7 (b) LREQ (d) LPS TLPS_RESET TRESTORE Figure 19. Interface Reset The sequence of events for resetting the PHY-LLC interface is as follows: (a) Normal operation. Interface is operating normally, with LPS asserted, PCLK active, status and packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line. In the above diagram, the LPS signal is shown as a nonpulsed level signal. However, it is permissible to use a pulsed signal for LPS in a direct connection between the PHY and LLC; a pulsed signal is required when using an isolation barrier. (b) LPS deasserted. The LLC deasserts the LPS signal and, within 1.0 s, terminates any request or interface bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low. (c) Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state. (d) Interface restored. After the minimum TRESTORE time, the LLC may again assert LPS active. When LPS is asserted, the interface is initialized as described below. If the LLC continues to keep the LPS signal deasserted, it then requests that the interface be disabled. The PHY disables the interface when it observes that LPS has been deasserted for TLPS_DISABLE. When the interface is disabled, the PHY sets its CTL and D outputs as stated above for interface reset, but also stops PCLK activity. The interface is also placed into the disabled condition upon a hardware reset of the PHY. Figure 20 shows the timing for the interface disable. When the interface is disabled, the PHY enters a low-power state if none of its ports are active. 44 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) interface reset and disable (continued) (a) PCLK (c) (d) CTL0, CTL1 D0 - D7 (b) LREQ LPS TLPS_RESET TLPS_DISABLE Figure 20. Interface Disable The sequence of events for disabling the PHY-LLC is as follows: (a) Normal operation. Interface is operating normally, with LPS active, PCLK active, status and packet data reception and transmission via the CTL and D lines, and request activity via the LREQ line. (b) LPS deasserted. The LLC deasserts the LPS signal and, within 1.0 s, terminates any request or interface bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low. (c) Interface reset. After TLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state. (d) Interface disabled. If the LPS signal remains inactive for TLPS_DISABLE time, then the PHY terminates PCLK activity by driving the PCLK output low. The PHY-LLC interface is now in the disabled state. After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal operation when LPS is reasserted by the LLC. Figure 21 shows the timing for interface initialization. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 45 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) interface reset and disable (continued) ISO (high) 7 Cycles SYSCLK (b) CTL0 (d) CTL1 (c) D0 - D7 LREQ (a) LPS TCLK_ACTIVATE Figure 21. Interface Initialization The sequence of events for initialization of the PHY-LLC is as follows: (a) LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by reasserting the LPS signal. (In the above diagram, the interface is shown in the disabled state with PCLK low inactive. However, the interface initialization sequence described here is also executed if the interface is merely reset but not yet disabled.) (b) PCLK activated. If the interface is disabled, then the PHY reactivates its PCLK output when it detects that LPS has been reasserted. If the PHY has entered a low-power state, then it takes between 5.3 to 7.3 ms for PCLK to be restored; if the PHY is not in a low-power state, then the PCLK is restored within 60 ns. The PCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz 100 ppm (period of 20.345 ns). During the first 7 cycles of PCLK, the PHY continues to drive the CTL and D terminals low. The LLC is also required to drive its CTL and D outputs low for 1 of the first 6 cycles of PCLK but to otherwise place its CTL and D outputs in a high-impedance state. The LLC continues to drive its LREQ output low during this time. (c) Receive indicated. Upon the eighth PCLK cycle following reassertion of LPS, the PHY asserts the receive state on the CTL lines and the data-on indication (all 1s) on the D lines for one or more cycles. (d) Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This indicates that the PHY-LLC interface initialization is complete and normal operation may commence. The PHY now accepts requests from the LLC via the LREQ line. 46 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) The TSB41BA3 is designed to operate with a LLC such as the Texas Instruments TSB82AA2 when the BMODE terminal is tied high. Details of operation for the Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface. This interface is formally specified in the IEEE 1394b-2002 standard. The interface to the LLC consists of the PCLK, LCLK_PMC, CTL0-CTL1, D0-D7, LREQ, PINT, LPS, and S5_LKON_DS2 terminals on the TSB41BA3, as shown in Figure 22. TSB41BA3 LCLK_PMC PCLK CTL0-CTL1 Link-Layer Controller D0-D7 LREQ LPS S5_LKON_DS2 PINT Figure 22. PHY-LLC Interface The LCLK_PMC terminal provides a clock signal to the PHY. The LLC derives this clock from the PCLK signal and is phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK_PMC. The PCLK terminal provides a 98.304-MHz interface system clock. All control, data, and PHY interrupt signals are synchronized to the rising edge of PCLK. The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data between the TSB41BA3 and LLC. The D0-D7 terminals form a bidirectional data bus, which transfers status information, control information, or packet data between the devices. The TSB41BA3 supports S400B, S200B, and S100B data transfers over the D0-D7 data bus. In S400B, S200B, and S100B operation all Dn terminals are used. The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access to the serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration. All data on LREQ is synchronous to LCLK_PMC. The LPS and S5_LKON_DS2 terminals are used for power management of the PHY and LLC. The LPS terminal indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable PCLK. The S5_LKON_DS2 terminal sends a wake-up notification to the LLC and indicates an interrupt to the LLC when either LPS is inactive or the PHY register L bit is 0. The PINT terminal is used by the PHY for the serial transfer of status, interrupt, and other information to the LLC. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 47 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) The TSB41BA3 normally controls the CTL0-CTL1 and D0-D7 bidirectional buses. The LLC is allowed to drive these buses only after the LLC has been granted permission to do so by the PHY. There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data transmit, and data receive. The LLC issues a service request to read or write a PHY register or to request the PHY to gain control of the serial-bus in order to transmit a packet. The PHY may initiate a status transfer either autonomously or in response to a register read request from the LLC. The PHY initiates a receive operation whenever a packet is received from the serial-bus. The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. Table 23 and Table 24 show the encoding of the CTL0-CTL1 bus. Table 23. CTL Encoding When PHY Has Control of the Bus CTL0 0 0 1 1 CTL1 0 1 0 1 NAME Idle Status Receive Grant No activity (this is the default mode) Status information is being sent from the PHY to the LLC. An incoming packet is being sent from the PHY to the LLC. The LLC has been given control of the bus to send an outgoing packet. DESCRIPTION Table 24. CTL Encoding When LLC Has Control of the Bus CTL0 0 0 1 1 CTL1 0 1 0 1 NAME Idle Transmit Reserved Hold/More Information DESCRIPTION The LLC releases the bus (transmission has been completed). An outgoing packet is being sent from the LLC to the PHY. Reserved The LLC is holding the bus while data is being prepared for transmission, or the LLC is sending a request to arbitrate for access to the bus, or the LLC is identifying the end of a subaction gap to the PHY. LLC service request To request access to the bus, to read or write a PHY register, or to send a link notification to PHY, the LLC sends a serial bit stream on the LREQ terminal as shown in Figure 23. LR0 LR1 LR2 LR3 LR (n-2) LR (n-1) Each cell represents one clock sample time, and n is the number of bits in the request stream. Figure 23. LREQ Request Stream The length of the stream varies depending on the type of request as shown in Table 25. 48 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) LLC service request (continued) Table 25. Request Stream Bit Length REQUEST TYPE Bus request Read register request Write register request Link notification request PHY-link interface reset request NUMBER OF BITS 11 10 18 6 6 Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. The second through fifth bits of the request stream indicate the type of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low. Table 26 shows the encoding for the request type. Table 26. Request Type Encoding LR1-LR4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 NAME Reserved Immed_Req Next_Even Next_Odd Current Reserved Isoch_Req_Even Isoch_Req_Odd Cyc_Start_Req Reserved Reg_Read Reg_Write Isoch_Phase_Even Reserved Immediate request. Upon detection of idle, the PHY arbitrates for the bus. Next even request. The PHY arbitrates for the bus to send an asynchronous packet in the even fairness interval phase. Next odd request. The PHY arbitrates for the bus to send an asynchronous packet in the odd fairness interval phase. Current request. The PHY arbitrates for the bus to send an asynchronous packet in the current fairness interval. Reserved Isochronous even request. The PHY arbitrates for the bus to send an isochronous packet in the even isochronous period. Isochronous odd request. The PHY arbitrates for the bus to send an isochronous packet in the odd isochronous period. Cycle start request. The PHY arbitrates for the bus to send a cycle start packet. Reserved Register read request. The PHY returns the specified register contents through a status transfer. Register write request. Write to the specified register in the PHY. Isochronous phase even notification. The link reports to the PHY that: 1) A cycle start packet has been received 2) The link has set the isochronous phase to even. Isochronous phase odd notification. The link reports to the PHY that: 1) A cycle start packet has been received 2) The link has set the isochronous phase to odd. Cycle start due notification. The link reports to the PHY that a cycle start packet is due for reception. Reserved DESCRIPTION 1101 Isoch_Phase_Odd 1110 1111 Cycle_Start_Due Reserved For a bus request, the length of the LREQ bit stream is 11 bits as shown in Table 27. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 49 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) LLC service request (continued) Table 27. Bus Request BIT(s) 0 1-4 5 6-9 10 NAME Start bit Request type Request format Request speed Stop bit DESCRIPTION Indicates the beginning of the transfer (always 1) Indicates the type of bus request. See Table 26. Indicates the packet format to be used for packet transmission. See Table 28. Indicates the speed at which the link sends the data to the PHY. See Table 29 for the encoding of this field. Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit may be omitted. Table 28 shows the 1-bit request format field used in bus requests. Table 28. Bus Request Format Encoding LR5 0 1 DATA RATE Link does not request either beta or legacy packet format for bus transmission Link requests beta packet format for bus transmission Table 29 shows the 4-bit request speed field used in bus requests. Table 29. TBus Request Speed Encoding LR6-LR9 0000 0001 0010 0011 0100 0101 0110 All Others DATA RATE S100 Reserved S200 Reserved S400 Reserved S800 Invalid NOTE: The TSB41BA3 accepts a bus request with an invalid speed code and processes the bus request normally. However, during packet transmission for such a request, the TSB41BA3 ignores any data presented by the LLC and transmits a null packet. For a read register request, the length of the LREQ bit stream is 10 bits as shown in Table 30. Table 30. Read Register Request BIT(s) 0 1-4 5-8 9 NAME Start bit Request type Address Stop bit A 1010 indicates this is a read register request Identifies the address of the PHY register to be read Indicates the end of the transfer (always 0) DESCRIPTION Indicates the beginning of the transfer (always 1) For a write register request, the length of the LREQ bit stream is 18 bits as shown in Table 31. 50 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) LLC service request (continued) Table 31. Write Register Request BIT(s) 0 1-4 5-8 9-16 17 NAME Start bit Request type Address Data Stop bit A 1011 indicates this is a write register request Identifies the address of the PHY register to be written Gives the data that is to be written to the specified register address Indicates the end of the transfer (always 0) DESCRIPTION Indicates the beginning of the transfer (always 1) For a link notification request, the length of the LREQ bit stream is 6 bits as shown in Table 32. Table 32. Link Notification Request BIT(s) 0 1-4 5 NAME Start bit Request type Stop bit DESCRIPTION Indicates the beginning of the transfer (always 1) A 1100, 1101, or 1110 indicates this is a link notification request Indicates the end of the transfer (always 0) For fair or priority access, the LLC sends a bus request at least one clock after the PHY-LLC interface becomes idle. The PHY queues all bus requests and can queue one request of each type. If the LLC issues a different request of the same type, then the new request overwrites any nonserviced request of that type. Note, upon the receipt (CTL terminals are asserted to the receive state, 10b) of a packet, queued requests are not cleared by the PHY. The cycle master node uses a cycle start request (Cyc_Start_Req) to send a cycle start message. After receiving or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears an isochronous request only when the serial bus has been won. To send an acknowledge packet, the LLC must issue an immediate bus request (Immed_Req) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet. As soon as the received packet ends, the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to send another type of packet. After the interface is released the LLC may proceed with another request. For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the LLC at the next opportunity through a PHY status transfer. A write or read register request may be made at any time, including while a bus request is pending. Once a read register request is made, the PHY ignores further read register requests until the register contents are successfully transferred to the LLC. A bus reset does not clear a pending read register request. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 51 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) status transfer A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. Two types of status transfers may occur: bus status transfer and PHY status transfer. Bus status transfers send the following status information: bus reset indications, subaction and arbitration reset gap indications, cycle start indications, and PHY interface reset indications. PHY status transfers send the following information: PHY interrupt indications, unsolicited and solicited PHY register data, bus initialization indications, and PHY-link interface error indications. The PHY uses a different mechanism to send the bus status transfer and the PHY status transfer. Bus status transfers use the CTL0-CTL1 and D0-D7 terminals to transfer status information. Bus status transfers can occur during idle periods on the PHY-link interface or during packet reception. When the status transfer occurs, a single PCLK cycle of status information is sent to the LLC. The information is sent such that each individual Dn terminal conveys a different bus status transfer event. During any bus status transfer, only one status bit is set. If the PHY-link interface is inactive, then the status information is not sent. When a bus reset on the serial bus occurs, the PHY sends a bus reset indication (via the CTLn and Dn terminals), cancels all packet transfer requests, sets asynchronous and isochronous phases to even, forwards self-ID packets to the link, and sends an unsolicited PHY register 0 status transfer (via the PINT terminal) to the LLC. In the case of a PHY interface reset operation, the PHY-link interface is reset on the following PCLK cycle. Table 33 shows the definition of the bits during the bus status transfer and Figure 24 shows the timing. Table 33. Status Bits STATUS BIT D0 D1 D2 D3 D4 D5 D6 D7 CTL[0:1] Bus reset Arbitration reset gap--Odd Arbitration reset gap--Even Cycle start--Odd Cycle start--Even Subaction gap PHY interface reset Reserved XX 01 XX DESCRIPTION D[0:7] XX ST XX Status Bits Figure 24. Bus Status Transfer Timing 52 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) status transfer (continued) PHY status transfers use the PINT terminal to serially send status information to the LLC as shown in Figure 25. PHY status transfers (Table 34) can occur at any time during normal operation. The PHY uses the PHY_INTERRUPT PHY status transfer when required to interrupt the LLC due to a configuration timeout, a cable power failure, a port interrupt, or an arbitration timeout. When transferring PHY register contents, the PHY uses either the solicited or the unsolicited register read status transfer. The unsolicited register 0 contents are passed to the LLC only during initialization of the serial bus. After any PHY-link interface initialization, the PHY sends a PHY status transfer indicating whether or not a bus reset occurred during the inactive period of the PHY-link interface. If the PHY receives an illegal request from the LLC, then the PHY issues an INTERFACE_ERROR PHY status transfer. LR0 LR1 LR2 LR3 LR (n-2) LR (n-1) Each cell represents one clock sample time, and n is the number of bits in the request stream. Figure 25. PINT (PHY Interrupt) Stream Table 34. PHY Status Transfer Encoding PI[1:3] 000 001 010 011 100 101 110 111 NOP PHY_INTERRUPT PHY_REGISTER_SOL PHY_REGISTER_UNSOL PH_RESTORE_NO_RESET PH_RESTORE_RESET INTERFACE_ERROR Reserved NAME No status indication Interrupt indication: configuration timeout, cable power failure, port event interrupt, or arbitration state machine timeout Solicited PHY register read Unsolicited PHY register read PHY-link interface initialized; no bus resets occurred PHY-link interface initialized; a bus reset occurred PHY received illegal request Reserved DESCRIPTION NUMBER OF BITS 5 5 17 17 5 5 5 Reserved Most PHY status transfers are 5 bits long. The transfer consists of a start bit (always 1), followed by a request type (see Table 34), and lastly followed by a stop bit (always 0). The only exception is when the transfer of a register contents occurs. Solicited and unsolicited PHY register read transfers are 17 bits long and include the additional information of the register address and the data contents of the register (see Table 35). Table 35. Register Read (Solicited and Unsolicited) PHY Status Transfer Encoding BIT(s) 0 1-3 4-7 8-15 16 Start bit Request type Address Data Stop bit NAME DESCRIPTION Indicates the beginning of the transfer (always 1) A 010 or a 011 indicates a solicited or unsolicited register contents transfer Identifies the address of the PHY register whose contents are being transferred The contents of the register specified in bits 4 through 7 Indicates the end of the transfer (always 0) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 53 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) receive When the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates the start of a packet by placing the speed code (encoded as shown in Table 36) on the D terminals, followed by packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet has been transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included in the calculation of CRC or any other data protection mechanisms. The PHY may optionally send status information to the LLC at anytime during the data-on indication. Only bus status transfer information can be sent during a data-on indication. The PHY holds the CTL terminals in the status state for 1 PCLK cycle and modifies the D terminals to the correct status state. Note that the status transfer during the data-on indication does not need to be preceded or followed by a data-on indication. It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all cases, in normal operation, the TSB41BA3 sends at least one data-on indication before sending the speed code or terminating the receive operation. The TSB41BA3 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization, to the LLC. This packet it transferred to the LLC just as any other received self-ID packet. PCLK CTL0, CTL1 (a) (b) 10 00 (e) (c) D0-D7 XX FF (data-on) SPD (d) d0 dn 00 NOTE A: SPD = Speed code, see Table 36. d0-dn = Packet data Figure 26. Normal Packet Reception Timing 54 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) receive (continued) PCLK CTL0, CTL1 10 (a) (b) 01 10 00 (e) (c) (d) d0 dn 00 D0-D7 XX FF (data-on) STATUS FF (data-on) SPD NOTE A: SPD = Speed code, see Table 36. d0-dn = Packet data. STATUS = status bits, see Table 33. Figure 27. Normal Packet Reception Timing With Optional Bus Status Transfer The sequence of events for a normal packet reception is as follows: (a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle. (b) Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more cycles preceding the speed-code. The PHY may optionally send a bus status transfer during the data-on indication for one PCLK cycle. During this cycle, the PHY asserts status (01b) on the CTL lines while sending status information on the D lines. (c) Speed-code. The PHY indicates the speed of the received packet by asserting a speed-code on the D lines for one cycle immediately preceding packet data. The link decodes the speed-code on the first receive cycle for which the D lines are not the data-on code. If the speed-code is invalid or indicates a speed higher that that which the link is capable of handling, then the link must ignore the subsequent data. (d) Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet data on the D lines with receive on the CTL lines for the remainder of the receive operation. (e) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. PCLK CTL0, CTL1 (a) D0-D7 XX 10 (b) FF (data-on) 00 (c) 00 Figure 28. Null Packet Reception Timing POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 55 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) receive (continued) The sequence of events for a null packet reception is as follows: (a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle. (b) Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles. (c) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines. The PHY asserts at least one idle cycle following a receive operation. Table 36. Receive Speed Codes and Format D0-D7 0000 0000 0000 0001 0000 0100 0000 0101 0000 1000 0000 1001 0000 1101 1111 1111 All Others DATA RATE AND FORMAT S100 legacy S100 beta S200 legacy S200 beta S400 legacy S400 beta S800 beta Data-on indication Reserved NOTE: Y = Output as 1 by PHY, ignored by LLC. X = Output as 0 by PHY, ignored by LLC. transmit When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting the grant state (11b) on the CTL terminals and the grant type on the D terminals for one PCLK cycle, followed by idle for one clock cycle. The LLC then takes control of the bus by asserting either idle (00b), hold (11b) or transmit (01b) on the CTL terminals. If the PHY does not detect a hold or transmit state within eight PCLK cycles, then the PHY takes control of the PHY-link interface. The hold state is used by the LLC to retain control of the bus while it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (that is, the LLC need not assert hold before transmit). During the hold state, the LLC is expected to drive the D lines to 0. The PHY asserts data-prefix on the serial bus during this time. When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle. If the hold is asserted, then the hold is immediately followed by one clock cycle of idle. The link then releases the PHY-link interface by putting the CTL and D terminals in a high-impedance state. The PHY then regains control of the PHY-link interface. 56 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) transmit (continued) PHY CTL[0:1] 00 11 00 ZZ ZZ ZZ ZZ ZZ ZZ PHY D[0:7] 00 GT 00 ZZ ZZ ZZ ZZ ZZ ZZ LLC CTL[0:1] ZZ ZZ ZZ ZZ ZZ 11 11 01 01 LLC D[0:7] ZZ ZZ ZZ ZZ ZZ 00 00 d0 d1 PHY CTL[0:1] ZZ ZZ ZZ ZZ ZZ ZZ 00 00 00 PHY D[0:7] ZZ ZZ ZZ ZZ ZZ ZZ 00 00 00 LLC CTL[0:1] 01 01 11 00 ZZ ZZ ZZ ZZ ZZ LLC D[0:7] dn-1 dn LR 00 ZZ ZZ ZZ ZZ ZZ GT = Grant Type LR = Link Request Type d0-dn = packet data Figure 29. Transmit Packet Timing With Optional Link Request The hold state asserted at the end of packet transmission allows the LLC to make an additional link request for packet transmission and/or to notify the PHY that the packet marks the end of a subaction. The link requests allowed after packet transmission are listed in Table 37 (note that the link request types allowed during this period are a subset of all of the allowed types of link requests--see Table 26). The associated speed codes and packet format are listed in Table 37 and Table 38, respectively. If the LLC requests to send an additional packet, then the PHY does not necessarily have to grant the request. If the LLC is notifying the PHY of the end of a subaction, then the LLC sets D4 during the hold state at the end of packet transmission. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 57 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) transmit (continued) Table 37. Link Request Type Encoding During Packet Transmission D1-D3 000 001 010 011 100 101 110 111 Request Type No request Isoch_Req_Odd Isoch_Req_Even Current Next_Even Next_Odd Cyc_Start_Req Reserved Table 38. Link Request Speed Code Encoding During Packet Transmission D5-D6 00 01 10 11 DATA RATE S100 S200 S400 S800 Table 39. Link Request Format Encoding During Packet Transmission D0 0 1 FORMAT Link does not request either beta or legacy packet format for bus transmission Link requests beta packet format for bus transmission Table 40. Subaction End Notification Encoding During Packet Transmission D4 0 1 DESCRIPTION Transmitted packet does not represent end of a subaction Transmitted packet marks the end of a subaction The PHY indicates to the link during the GRANT cycle which type of grant is being issued. This indication includes the grant type as well as the grant speed. The link uses the bus grant for transmitting the granted packet type. The link transmits a granted packet type only if its request type exactly matches the granted speed and the granted format. Table 41. Format Type During Grant Cycle D0 VALUE DURING GRANT CYCLE 0 1 FORMAT Unspecified Beta format 58 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 PRINCIPLES OF OPERATION (1394B INTERFACE) transmit (continued) Table 42. Grant Type Values During Grant Cycle [D1-D3] VALUE DURING GRANT CYCLE 000 001 010 011 100 101 110 111 REQUEST TYPE Reserved Reserved Isochronous grant Reserved Reserved Asynchronous grant Cycle start grant Immediate grant Table 43. Speed Type Values During Grant Cycle [D5-D6] VALUE DURING GRANT CYCLE 00 01 10 11 SPEED TYPE S100 S200 S400 S800 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 59 TSB41BA3 IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS155 - MAY 2003 MECHANICAL DATA PFP (S-PQFP-G80) 0,27 0,17 41 PowerPAD PLASTIC QUAD FLATPACK 0,50 60 0,08 M 61 40 Thermal Pad (see Note D) 80 21 0,13 NOM 1 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 1,05 0,95 20 Gage Plane 0,25 0,15 0,05 0,75 0,45 Seating Plane 0- 7 1,20 MAX 0,08 4146925/A 01/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. Please see the APPLICATION INFORMATION section, designing with PowerPAD for more information. E. Falls within JEDEC MS-026 PowerPAD is a trademark of Texas Instruments. 60 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated |
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