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TPS2383
SLUS559 - APRIL 2003
OCTAL POWER SOURCING EQUIPMENT POWER MANAGER
FEATURES D Compliant to Power Over Ethernet IEEE D D D D D D D D D D D D D D D D D D D D D
802.3af Standard Octal Power Port Control Operation in DTE PSE or Stand-Alone Mid-Span Modes Two-Point 25-k Resistor Discovery Capacitive Detection for Non-Compliant Legacy Loads Power Classification with Bypass Option Controlled di/dt Ramp Power-Up and Power-Down for EMI Reduction Current Management for Charging Powered Device Bulk Capacitance Electronic Circuit Breaker Fault detection Input Undervoltage Lockout (UVLO) Load Overcurrent and Undercurrent Detection 12-Bit Port Current and Voltage Acquisition Standard Slave I2C Serial Interface 5-Bit Serial Address Selectability Discovery and/or Classification Bypass Modes Selectable Via Register Opto-Coupler Compatible SDA and SCL Lines for System Ground Isolation Dual Color LED Driver for Port Status Hardware FAULT Interrupt Minimal, Per-Port External Parts Count Single +48-V Supply Capable 64-Pin LQFP Package (PM)
DESCRIPTION
The TPS2383 family of products are power sourcing equipment power managers (PSEPM) that are compliant to the power-over-ethernet (PoE) IEEE 802.3af Standard. A PSEPM port can discover, classify and deliver power to a powered device (PD) capable of accepting PoE twisted pair cable. The TPS2383 is fully programmable by the user. This allows for the detection and powering of both fully compliant 802.3 devices as well as custom detection of legacy devices. The TPS2383 PSEPM can individually manage power for up to eight ethernet ports. All operations of the TPS2383 are controlled through register read and write operations over a standard (slave) I2C serial interface. The TPS2383 has dual SDA lines to allow easy application of opto-coupler circuitry to maintain ethernet port isolation when a ground based controller is used. Each TPS2383 has five selection pins making it possible to address up to 32 devices on the I2C bus and allows individual control and monitoring of up to 256 ethernet ports from a single master I2C controller. Per-port write registers initiate and manipulate the flow of the discovery, classification, and power-up states while the read registers contain status information of the enable process, faults, classification value, and real time port operating current and voltage. Per-port status LED drivers are provided which can be manually controlled through the serial I/O. The TPS2383 is available in a full function 64-pin LQFP.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1999 - 2003, Texas Instruments Incorporated
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TPS2383
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DESCRIPTION (continued)
External N-channel MOSFETs switch port power. High-voltage (HV) gate drive ensures that these FETs are fully enhanced, resulting in lower power dissipation and enabling the use of lower costs FETs. The TPS2383 generates its HV gate supply from the 48-V port power, simplifying system power supply design. An external 3.3-V digital supply is also used. This supply can be active when 48-V power is not present which allows the user to access the part through the serial I/O in this case. A 5-V analog supply is used to power port LEDs and internal analog functions. Due to the very low quiescent current, both the 3.3-V and 5-V supply can be generated from the +48-V power bus with minimal external components. An internal power-on-reset (POR) circuit with an ORed external input pin resets all registers positions to a known safe state upon power up.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) TPS2383 V48, 1P, 2P, 3P, 4P, 5P, 6P, 7P, 8P, 1N, 2N, 3N, 4N, 5N, 6N, 7N, 8N 1RS, 2RS, 3RS, 4RS, 5RS, 6RS, 7RS, 8RS, 1G, 2G, 3G, 4G, 5G, 6G, 7G, 8G Input voltage range, VCC I t lt VL V5 SCL_I, SDA_I, SDA_O, INTB, A1, A2, A3, A4, A5, EN, PORB Storage temperature, Tstg Operating temperature, TJ -0.5 to 65 -0.5 to 12 -0.5 to 3.9 -0.5 to 5 -0.5 to 6 -55 to 150 0 to 70 C C V UNIT
Lead temperature, Tsol, 1,6 mm (1/16 inch) from case for 10 seconds 260 (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into and negative out of, the specified terminal.
RECOMMENDED OPERATING CONDITIONS
MIN Input voltage, VV48 Operating junction temperature, TJ 44 0 NOM 48 MAX 57 70 UNIT V C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MAX Human body model CDM Machine model 1.5 1 0.2 kV UNIT
ORDERING INFORMATION
PACKAGED DEVICES(2) TA LQFP-64 (PM)
0C to 70C TPS2383PM (2) The PM package is available taped and reeled. Add R suffix to device type (e.g.TPS2383PMR) to order quantities of 2,500 devices per reel and 90 units per tube.
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TPS2383
SLUS559 - APRIL 2003
ELECTRICAL CHARACTERISTICS
VV48= 48 V, RT = 120 k, 0C to 70C, and TA = TJ (unless otherwise noted) PARAMETER POWER SUPPLIES Off mode (all ports) Quiescent current V48 current, Quiescent current, V5 Quiescent current, VL Internal analog supply, V10 Internal reference(1) Input UVLO Internal POR timeout (I2C) Internal POR timeout (state machine) LED OUTPUTS High-level output voltage, L1 through L8 Low-level output voltage, L1 through L8 Tri-state leakage(1) Input resistance, nP to nN Classification voltage Discovery voltage, high Discovery voltage, low Loop power supply feedthru loop control range C Discovery short-circuit current Port output, undervoltage Port output, overvoltage ClassLimit1 = 0, ClassLimit1 = 1, Classification current limit ClassLimit1 = 0, ClassLimit1 = 1, N-CHANNEL MOSFET GATE CONTROL Gate turn-off MOSFET RDS(on) Maximum gate voltage Gate turn-off delay time from overcurrent fault Gate turn-off timer from UV/OV fault UV/OV spike timer, power quality warning(1) Gate turn-off timer from overload fault After port enabled and ramped up, (1024 CLK periods) (256 CLK periods) (32768 CLK periods) 1024 256 32768 CLK CLKs 8 200 10 12 7.5 V s ClassLimit2 = 0 ClassLimit2 = 0 ClassLimit2 = 1 ClassLimit2 = 1 40 51 42 53 160 80 40 20 mA A/B select = B ISRC = 5 mA ISINK = 5 mA 4 0.75 0.1 240 15.0 7.5 3.5 400 17.5 8.8 4.4 1.5 3 44 55 V 9.5 5.5 mV mA V 640 V A k After all supplies are good (8 CLK periods) After all supplies are good (65536 CLK periods) Powered mode (all ports) Powered mode (all ports), Powered mode (all ports), VV5 = 5 V VVL = 3.3 V 9.75 2.475 28 3 5 10 2 10.50 2.500 37 8 65536 CLKs 5 10 15 4 11.50 2.525 40 V mA TEST CONDITIONS MIN TYP MAX UNIT
ANALOG CIRCUITS - PORT VOLTAGE CONTROL LOOP
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TPS2383
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ELECTRICAL CHARACTERISTICS
VV48= 48 V, RT = 120 k, 0C to 70C, and TA = TJ (unless otherwise noted) PARAMETER LOW-SIDE CURRENT-SENSE Overload threshold voltage Peak current threshold voltage Overload timout Maximum swing, CINT Reset voltage, CINT Maximum swing, CR Input leakage, nRS ANALOG-TO-DIGITAL CONVERTER A/D resistive scaling(1) A/D classificatin scaling(1) A/D load current scaling(1) A/D load voltage scaling(1) A/D load c rrent con ersion current conversion A/D port voltage conversion DIGITAL I/O Logic input threshold voltage, SCL, SDA_I, A1 through A5, EN, PORB Input hysteresis, SCL, SDA_I Input hysteresis, EN, PORB Input pull-down resistance, EN, PORB Pull-up current, A0, A1, A2, A3, A4, A5 Logic high leakage, SDA_O Logic low leakage, SDA_O Logic high leakage, INTB Logic high leakage, INTB DIGITAL I/O TIMING I2C CHARACTERISTICS Clock frequency, SCL SCL high Pulse duration P lse d ration Rise time, SCL, SDA Fall time, SCL, SDA Setup time SDA to SCL Hold time SCL to SDA Bus free time between startup and stop Setup time SCL to start condition Hold time start condition to SCL Setup time, SCL to stop condition 250 0 4.7 4.7 4 4 s s SCL low 0 4 4.7 1000 300 ns 500 kHz s s Drain = 65 V ISINK = 3 mA Drain = 6 V ISINK = 3 mA 1.5 250 150 50 10 10 200 10 200 25 mV k A A mV A mV V ILOAD = 50 mA, ILOAD = 300 mA, VPORT = 5 V VPORT = 45 V RRS = 0.5 RRS = 0.5 RRD = 1 k RRS = 0.5 RRS = 0.5 9 10 4.5 10 72 35 4.72 33.6 236 1416 168 1512 count count/mA count/V 165 175 187 213 50 207 250 100 11 100 6.0 mV ms V mV V A count/k TEST CONDITIONS MIN TYP MAX UNIT
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TPS2383
SLUS559 - APRIL 2003
TERMINAL FUNCTIONS
TERMINAL NAME PIN I/O DESCRIPTION POWER AND GROUND AG1 26 I Analog ground 1. Analog ground of the V5, V10 and V48 power systems. It should be externally tied to the common copper 48-V return plane. This pin should carry the low side of two de-coupling capacitors tied to V48 and V10 Analog ground 2. Analog ground, which ties to the substrate and ESD of the device. It should be externally tied to the common copper 48-V return plane. AG1 and AG2 must be tied together directly for lowest noise operation. Digital ground. It connects to the internal logic ground bus. It should be externally tied to the common copper 48V return plane. In addition a 0.1uF de-coupling capacitor should terminate as close to this node and the VL pin as possible. Reference ground. A precision sense of the external ground plane. It should also be used as the ground guard ring for the integration capacitor (CINT). It should be the closest ground to the low side of the 0.5- current sense resistors, as well as RD, CINT, and RT. It should tie to common copper 48-V return plane. +10V analog supply.Connects to the internal analog power bus. This voltage is generated internally. This pin should not be tied to any external supplies. A 0.1-F de-coupling capacitor should terminate as close to this node and the AG2 pin as possible. This pin can be used for external generation of V5. +48V input to the device. This supply can have a range of 44 V to 57 V. This pin should be de-coupled with a 0.1-F capacitor from V48 to AG2 placed as close to the device as possible. External +5V analog supply.Connects to the internal analog power bus. This supplies the LED output drivers and internal analog circuits. A 0.1-F de-coupling capacitor should terminate as close to this node and the AG1 pin as possible. External +3.3V logic supply. This pin connects to the internal logic power bus. This is the supply voltage for the internal device logic. A 0.1-F de-coupling capacitor should terminate as close to this node and the DG pin as possible. This pin can be powered from V5 by using a 4.22-k resistor from V5 to VL..
AG2
51
I
DG
56
I
RG
29
I
V10
28
O
V48
27
I
V5
25
I
VL
54
I
PORT ANALOG SIGNALS 1P 2P 3P 4P 5P 6P 7P 8P 1N 2N 3N 4N 5N 6N 7N 8N 1 8 9 16 33 40 41 48 2 7 10 15 34 39 42 47 I I I I I I I I I I I I I I I I Port negative. -48V load return sense pin. The low side of the load is switched and protected with the external in. rotected N-channel MOSFET. Port positive. +48V load sense pin. Terminal voltage is monitored and controlled differentially with respect to nN. Optionally if the application warrants it, this high-side path can be protected with the use of a self-resetting poly it high side self resetting Optionally, fuse.
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TPS2383
SLUS559 - APRIL 2003
TERMINAL FUNCTIONS (continued)
TERMINAL NAME 1G 2G 3G 4G 5G 6G 7G 8G 1RS 2RS 3RS 4RS 5RS 6RS 7RS 8RS PIN 3 6 11 14 35 38 43 46 4 5 12 13 36 37 44 45 I/O DESCRIPTION PORT ANALOG SIGNALS (continued) O O O O O O O O I I I I I I I I Ramp capacitor. During load power up and down, this capacitor is used as the di/dt current slew capacitor. A 4-V peak triangular waveform is present on this pin during ramp up/down. Connect a 0.047-F capacitor from this pin to AG2 and a 120-k resistor at RT to meet the 802.3af specification timing levels. Timing capacitor. This capacitor and the resistor on the RT pin set the internal clock frequency of the device. This clock is used for the internal state machine, integrating A/D counters, POR time-out, and fault and delay timers of each port. Use a 47-pF to 220-pF capacitor for CT and a 120-k resistor on RT to set the internal clock in a range of 100 kHz to 500 kHz. This timing can be overridden by driving the CT pin with a 0 V to 5 V square wave with a frequency from 0 kHz to 500 kHz. This capacitor is used for the ramp A/D converter signal integration. Connect a 0.033-F capacitor from this pin to RG. For minimal errors due to dielectric absorption, use a poly or Teflon capacitor type. Ceramic types can be used, but note the increased conversion error. Port resistor sense. This is the kelvin sense path for the high potential end of the load current sense resistor. sense kel in c rrent resistor Parameters controlled by the load current sense resistor include: the average undercurrent/overcurrent and peak-load current thresholds, the peak PD inrush current limit during startup, and the nominal classification g current levels Use a 0 5 load current sense resistor to be compliant to the 802 3 specification levels levels. 0.5- 802.3 levels. Port gate. Connect to the gate of an external N-channel MOSFET. During turn-on, this pin is controlled by a linear current amplifier (LCA) such that the load current ramps up from zero to a maximum sourcing current of 425 mA. This pin is driven to as high as 10 V. During controlled turn-off, this pin is driven such that the load in in current ramps down from a maximum of 425 mA to zero. The capacitor on the CR pin is utilized to generate the ramp control signal voltages During a fault turn off this pin is discharged quickly with a low on resistance voltages. turn-off on-resistance internal switch.
ANALOG SIGNALS CR 50 I
CT
52
I
CINT L1 L2 L3 L4 L5 L6 L7 L8 RD
30 17 18 19 20 21 22 23 24 32
I O O O O O O O O I
LED lamp drivers. Dual or single color LEDs can be connected to each of these pins. Each pin indicates the state of the corresponding port This is a tri state port that is under full control of the host micro controller As port. tri-state micro-controller. such it can also be used as a data port, or general-purpose output driver. ort, general- ur ose out ut
The discovery current-sense resistor is connected in the path from the RD pin to RG ground. The discovery current-sense resistor sets the discovery value to 25-k (nominal) when a 1000- value is used. For best noise performance, de-couple this pin with a 0.82-F, ceramic capacitor to RG ground. Bias set resistor. This resistor sets all precision bias currents within the device. This pin is forced to an internal 1.25-V reference voltage level. The current that flows into this resistor due to the applied 1.25-V bias is replicated and used throughout the device. This resistor also works in conjunction with the capacitors on CR, CT and CINT to set internal timing values. Use a 120-k resistor to be compliant to the requirements of 802.3af.
RT
31
I
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TPS2383
SLUS559 - APRIL 2003
TERMINAL FUNCTIONS (continued)
TERMINAL NAME A1 A2 A3 A4 A5 EN INTB PIN 64 63 62 61 60 53 59 I/O DESCRIPTION DIGITAL SIGNALS I I I I I I O This pin is normally to be held low. It has been reserved for future expansion of the TPS238x device family This is an open drain output that goes low if a fault condition is produced on any of the eight ports. This pin can be used to override the internal POR. When held low, the I2C interface, all the state machines, and registers are held in reset. When all internal and external supplies are within specification, and this pin is set to a logic high level, the POR delay begins. The I2C interface and registers becomes active within eight CLK periods of this event and communications to read or preset registers can begin. The reset delay for the remainder of the device then extinguishes within 65536 CLK periods. Serial clock input pin for the I2C interface. Serial data input pin for the I2C interface. When jumpered with the SDA_O pin, this connection becomes the standard bi-directional serial data line (SDA). Serial data open drain output for the I2C interface. When jumpered with the SDA_I pin, this connection becomes the standard bi-directional serial data line (SDA). This is a high-voltage open drain output that can drive opto-coupler LEDs directly from the +48-V bus with an external, series current limiting resistor. Addresses 1 through 5. This is the I2C address select input. Select the appropriate binary address on these pins by connecting this pin to device ground for a logic low and tying this pin to the VL pin for a logic high. high
PORB
49
I
SCL_I SDA_I
55 58
I I
SDA_O
57
O
PACKAGE DESCRIPTION
PM PACKAGE (TOP VIEW)
A1 A2 A3 A4 A5 INTB SDA_I SDA_O DG SCL_I VL EN CT AG2 1P 1N 1G 1RS 2RS 2G 2N 2P 3P 3N 3G 3RS 4RS 4G 4N 4P
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
CR PORB 8P 8N 8G 8RS 7RS 7G 7N 7P 6P 6N 6G 6RS 5RS 5G 5N 5P
10 11 12 13 14 15
33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32
L1 L2 L3 L4 L5 L6 L7 L8 V5 AG1 V48 V10 RG CINT RT RD
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TPS2383
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FUNCTIONAL DESCRIPTION
The TPS2383 architecture has been designed to work efficiently with simple low-cost controllers such as those in the MSP430 family of devices. Reference design and code examples for complete PSE management are available from TI for the TPS2383/MSP430 chipset solution. The PSEPM discovery method, as defined in the IEEE 802.3af Standard, uniquely identifies a powered device 25-k - resistor. Use of low-level probe signals during discovery prevents damage to non-802.3 devices. The use of a point-to-point slope detection method for the PD 25-k resistor measurement allows accurate detection, even if series steering diodes are present at the PD. For legacy loads, capacitive detection can be enabled. In this mode the TPS2383 A/D is used to measure the loads capacitive value. After a successful discovery of the PD, the TPS2383 has a classification feature to identify the expected PD power level based on a current signature from the PD. The classification current level is measured at a reduced terminal voltage of 17.5 V and classified with 12 bits of resolution. The controller can then use this information to classify per the levels of the IEEE 802.3af standard or use levels custom to the application. Knowledge of the expected load power allows the power sourcing equipment to be built with a smaller and less expensive system power supply. For installations where classification is not needed, and reduced power-up time is desired, classification can be bypassed by setting the appropriate bits in the per-port write register. In classification and powered modes, the PSEPM drives an external low side N-channel MOSFET for control of the 48-V return line. The use of an external N-channel MOSFET enables selection of very low RDS(on) devices to minimize board power dissipation in enclosures that may be controlling 100's of ports. Current sensing is performed with a low value resistor, again minimizing board power dissipation. In discovery mode, due to the very low current used, an internal N-channel MOSFET is utilized in conjunction with an external, high value, current sense resistor. The TPS2383 identifies all fault conditions defined in the PoE IEEE 802.3af Standard. The monitored conditions include input undervolatge lockout (UVLO), output undervoltage (UV) and overvoltage (OV), average and peak overcurrent detection, average undercurrent detection, and run current. If a fault condition is detected during power ramp or at any other time, the PSEPM circuit breaks by disconnecting the 48-V return line and then updates the fault status of the corresponding port register. When the TPS2383 is disabled the PSEPM ramps the current down at a controlled rate and the PSEPM changes states to a lower power sleep mode. To maintain full compliance to Underwriters Laboratory (UL), IEC950 SELV and NEMKO safety standards an optional, low cost self-resetting PTC fuse can be added to the unswitched +48-V line to protect the system supply and wiring infrastructure from secondary building wiring faults. When the PSEPM is enabled and a PD is discovered and optionally classified, power is ramped to the PD at a controlled current ramp rate to reduce EMI. Upon completion of the current ramp up, the port current remains limited at less than 400 mA. Upon startup the port can remain in current limit for a timed value of 50 ms which allows the bulk filter capacitance of the PD to charge. Once a PD is successfully powered and the external N-channel MOSFET is fully on, the average and peak current to the PD is continuously monitored. A disconnected load is detected if the average current falls below 10 mA. An overcurrent is detected if the average current exceeds 375 mA and/or the peak current exceeds 425 mA. If any of these conditions exist, status bits are set in the per-port read register set and the power is removed from the load. For maximum rejection of external wiring and power supply noise sources during the measurement of line current, voltage, resistance or capacitance in discovery, classification and powered modes, a proprietary low noise A/D converter is used. Converted measurements are processed and compared with digital set-points for limit compliance. The 12-bit conversion of this data-acquisition system is available through the read register enabling measurement of the discovery resistance, classification current and powered mode port running current and voltage. This is a valuable feature in ethernet switch management as it allows monitoring of real-time parameters across the system network. The TPS2383 is available in a full function 64 pin LQFP package.
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TPS2383
SLUS559 - APRIL 2003
TPS2383 Evaluation Board
The full performance features of the TPS2383/MSP430 chipset can be demonstrated with the TPS2383EVM-001 evaluation board. The TPS2383EVM-001 is a scaleable system that can be expanded to support 48 ports using a single microcontroller. This evaluation design can be used as a hardware/firmware template for modification to specific customer requirements. Please contact Texas Instruments or refer to the TPS2383EVM-001 Users Guide (SLUUxxx) for complete information.
FUNCTIONAL BLOCK DIAGRAM
TPS2383 Chip Power Supply Management V48 V10 ANALOG SUPPLY WRITE REGISTER PSE Port Section
PSE PORT 8 PSE PORT 7 PSE PORT 6 PSE PORT 5 PSE PORT 4 PSE PORT 3 PSE PORT 2 PSE PORT 1
INPUT UVLO POR
PORB
PORT PORT CONTROLLER MONITOR STATE and FET READ REGISTER MACHINE CONTROL
PORT INTERFACE 4 Pins/Port (32 PINS)
V5 INTERNAL DIGITAL BUS VL CONTROL LOGIC ANALOG
INTERNAL ANALOG BUS
MAIN OSC and CLK
SDA_O SDA_I SCL INTB DEVICE ADDRESS and INTERRUPT FUTURE ENHANCEMENT 2 WIRE SERIAL IO SLAVE I2C CONTROLLER MASTER SEQUENCER STATE MACHINE
A/D STATE MACHINE
RAMP
MUX 12 BIT A/D STATE
VOLTAGE
REFERENCE
CHIP BIAS
MACHINE POWER
RAMP
CONTROL
A1
A2
A3
A4
A5
EN
PORT ADDRESS PINS A1 - A5
CT GNDS (2 ANA PINS, 1 DIG PIN)
RT
RG
CINT
RD
CR UDG-03062
LED DRIVERS
LED DRIVERS L1-L8 (8 PINS)
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TPS2383
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TPS2383 BLOCK DIAGRAM - SHARED PORT ANALOG RESOURCES
Poly PTC Fuse BBR550, 90 V, 0.55 A +48 V TPS2383 Shared Resources TPS2383 Port Resources Power to Ethernet XFMR POSOUT + AG1 RD 1 k CD 0.82 F + + Current Command + P C1 0.47 F N NEGOUT
+ A/D State Machine 4 to 1 MUX Voltage Control 8 to 1 MUX
CINT 0.033F
12-bit A/D
Overload Timer 0.187 V 4 to 1 MUX A/B select
Ramp State Machine Offset Correction 250 A 4 to 1 MUX 25 A 25 A + 1.5 V
Overcurrent 0.213 V + RG
8:1 4V Clamp
8 to 1 MUX
7-s Digital Filter
1 of 8 channels 50 Fast Ramp CR Slow Ramp CR 0.047 F RD 32 26 AG2 51
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+
8 to 1 MUX
UV/OV Filter
Spike Filter
Discovery/ Class
Port State Machine
VOV
VUV
A G
Linear Current B Controller
RS Rs 0.5
+
48 V RTN
UDG-03063
TPS2383
SLUS559 - APRIL 2003
FUNCTIONAL DESCRIPTION SEPM STATE MACHINES
The TPS2383 has circuit resources that are common to each port and circuit resources that are shared by all ports. Five independent state machines are used to control the common and shared PSEPM resources. Port control, UV/OV/OC and overload protection are all features that are common to each port. Data acquisition and power ramping are shared functions for all the ports. The master sequencer state machine is used to index the port presently being serviced and to distribute the shared resources to the currently selected port. The single master sequencer is responsible for incrementally accessing ports 1 through 8 and allowing those ports to process register data when they are accessed. Ports 1 through 8 each have a port sequencer, which controls all the power enabling and fault protection functions of the port per the register commands. The A/D has an A/D Sequencer that triggers, cycles and signals the port and master sequencer upon completion. The ramp sequencer controls the power ramping resource and is triggered by the port and master sequencer and provides a completion signal when power ramping is over. Upon power-up the master sequencer is enabled and running after a POR delay and begins acting on register commands. A shorter POR delay releases the reset on the I2C function and registers before the port reset is removed. This arrangement allows for register setup and polling over the I2C bus quickly upon power up but ensures that power cannot be applied until the power supply is fully energized and stable. The default power-up state for all command registers is a null condition. The state sequence order of the TPS2383 is discovery, classification and power delivery if a POE compliant device is detected on the other end of the data cable. The master sequencer powers-up in a default free-running mode. The TPS2383 also has a JOG mode. By setting the JOG_MODE register bit high, the master sequencer then no longer runs freely, but increments to the next sequential port each time the JOG register bit is set to a logic 1. The JOG bit is self-cleared once the port increments to the next position. Sequencing starts with port 1 and ends with port 8 and then repeats. The port sequencer signals status information to the master sequencer and skips over disabled ports. When the master sequencer detects an enabled port, it pauses at that port until discovery, classification and power-up is complete before proceeding to the next. When the master sequencer reaches a powered port, it pauses and take a reading of the ports run-time current and/or voltage before proceeding to the next port. When a powered PD load is disconnected, the disconnect event can be detected the next time that port is selected by the master sequencer. When the disable bit of a powered port is set in the corresponding register, that operation is completed the next time the master sequencer selects that port. An overcurrent fault event shuts down the offending port independent of any sequencer state.
DUAL COLOR LED DRIVERS
The LED driver pins (L1 through L8) can be used to drive single or dual, color LEDs. These LEDs are intended to provide installation or service personnel with the necessary information to install and troubleshoot the system infrastructure. The Ln pins have internal tri-state drivers. These LEDs can be controlled directly from the I2C registers. The reset state of all the LEDs is tri-state. Cross-conduction logic disables both internal high- and low-side MOSFETS if an attempt is made to enable both transistors on a given port. These are high current (10-mA) drivers that can be used for other applications such as the drive of optocouplers or electromechanical devices, or can just be used as an 8-bit data port.
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TPS2383
SLUS559 - APRIL 2003
FUNCTIONAL DESCRIPTION I2C INTERFACE
The serial interface used in the TPS2383 is a standard two-wire I2C slave architecture core. The standard bi-directional SDA lines of the I2C architecture are broken out into an independent input and output path. This feature simplifies, earth grounded, controller applications that require opto-isolators to keep the 48-V return of the ethernet power system floating. For applications where opto-isolation is not required, the bi-directional property of the SDA line can be restored by connecting SDA_I to SDA_O. The SCL line is a unidirectional input only line as the TPS2383 is always accesses as a slave device and it never controls the bus. Data transfers that require a data-flow reversal on the SDA line are four-byte operations. This occurs during a TPS2383 port read access cycle where a slave address byte is sent, followed by a port/register address byte write. A second slave address byte is sent followed by the data byte read using the port/register setup from the second byte in the sequence. Data write transfers to the TPS2383 do not require a data-flow reversal and as such only a three-byte operation is required. The sequence in this case is to send a slave address byte, followed by a write of the port/register address followed by a write of the data byte for the addressed port. The I2C access cycle consists of the following steps 1 through 7 and is also shown in Figure 4. 1. Start sequence (S) 2. Slave address field 3. Read/write 4. Acknowledge 5. Port/register address or data field 6. Acknowledge/not acknowledge 7. Stop sequence (P) The I2C interface and the port read write registers are held in active reset until input voltage is within specification and the internal POR timer has timed out. Start/Stop The high-to-low transition of SDA while SCL is high defines the start condition. The low-to-high transition of SDA while SCL is high defines the stop condition. The master device initiates all start and stop conditions. A first serial packet enclosed within start and stop bits, consists of a seven-bit address field, read/write bit, and the acknowledge bit. The acknowledge bit is always generated by the device receiving the address or data field. Five of the seven address bits are used by the TPS2383. The sixth and seventh bit is a placeholder for future expansion. During a write operation to the TPS2383 from the master device, the data field is eight bits. During a read operation where the TPS2383 is writing to the master device, the data field is also eight bits.
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Start/Stop Sequence
SCL SDA
Start Condition(S)
Clock 1
Clock 1
Clock 0
Clock 1
Stop Condition (P)
Figure 1. I2C Read/Write Cycles
Write Cycle SDA_I
R/W Bit
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A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 R3 R2 R1 P2 P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
Start Bit SDA_O
Device Address R/W=0
Ack Bit
Register/Port Address
Ack Bit
Data from Master to TPS2383
Ack Stop Bit Bit
Read Cycle SDA_I
R/W Bit
R/W Bit
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 R2 R1 R0 P2 P1 P0
A7 A6 A5 A4 A3 A2 A1 A0
Start Bit SDA_O
Device Address R/W=0
Ack Bit
Register/Port Address
Device Address
Ack Bit
Start Bit
R/W=1
Ack Bit
Data from TPS2383 to Master
Ack Bit
Stop Bit
SLUS559 - APRIL 2003
D7 D6 D5 D4 D3 D2 D1 D0
TPS2383
UDG-03060
TPS2383
SLUS559 - APRIL 2003
FUNCTIONAL DESCRIPTION
Chip Address The address field of the TPS2383 is eight bits and contains five bits of device address select, a read/write bit, and two spare bits per table 1. The leading two bits are not used and are reserved for future port expansion. The five device address select bits follow this. These bits are compared against the hard-wired state of the corresponding, device address select pins (A1 through A5). When the field contents are equivalent to the pin logic states, the device is addressed. These bits are followed by a least significant bit (LSB), which is used to set the read or write condition (1 for read and 0 for write). Following a start condition and an address field, the TPS2383 responds with an acknowledgement by pulling the SDA line low during the ninth clock cycle if the address field is equivalent to the value programmed by the pins. The SDA line remains a stable low while the ninth clock pulse is high. Table 1. Address Selection Field
BIT A7 A6 A5 A4 A3 A2 A1 A0 FUNCTION Future expansion (not used) Future expansion (not used) Device address. Compared with A5 Device address. Compared with A4 Device address. Compared with A3 Device address. Compared with A2 Device address. Compared with A1 Read/write
Port/Register Cycle After the chip address cycle, the TPS2383 accepts eight bits of port/register specific data as defined in Table 2. After receiving the eight-bit data field, the TPS2383 pulls the SDA line high for one clock cycle. A stop condition is then initiated by the transmitting device after the acknowledge pulse. The SDA line transition then latchs the selection of the appropriate internal register for the follow on data read or write operation. Table 2. Register/Port Addressing
BIT D7 D6 D5 D4 D3 D2 FUNCTION Future expansion Future expansion R2, register select MSB R1, register select R0, register select LSB P2, port address MSB 000 = 001 = 010 = 011 = 100 = 101 = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = Control (common Write register) Port Status (per port Read register) ( er ort Port Control (per port Write register) A2D Register low byte (common read register) A2D Register high byte (common read register) Chip identification/revision (common read register) Port 1 Port 2 Port 3 Port 4 Port 5 P t6 Port Port 7 Port 8 STATE
D1
P1, port address
D0
P0, port address LSB
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TPS2383
SLUS559 - APRIL 2003
FUNCTIONAL DESCRIPTION
Port/Register Cycle Table 3. Common Control Write Register, Register Address = 000 (Common Register)
BIT D7 D6 D5 FUNCTION Jog_mode Jog Bypass ramp 0 = Normal mode 1 = Jog mode 0 = Don't jog 1 = Jog. This bit is self-clearing. It does not need to be reset to a 0 for each new jog. 0 = Normal mode 1 = Bypass power-up ramp and powered mode for all ports 0 = Normal mode 1 = Disable the effect of the logic signal from the Disconnect detection circuits. This is an expansion function for future parts. This bit should be set to a logic 1 0 = Normal mode 1 = Bypass discovery mode. 0 = Normal mode 1 = Bypass current sample of all powered ports. 0 = Normal mode 1 = Bypass classification of all ports. 0 = Normal mode 1 = Disable the effect of the logic signal from the Discovery circuits. This is an expansion function for future parts. This bit should be set to a logic 1. STATE PRESET STATE 0 0 0
D4
Disconnect disable
0
D3 D2 D1
Bypass discovery Bypass sample Bypass classification
0 0 0
D0
Discovery fault disable
0
Table 4. Port Status Port 1 Read Register, Register Address = 001, Port Address = 000
BIT D7 D6 D5 D4 D3 D2 FUNCTION Port service Down (port 1 only) Ramp ServiceB Current SampleB A to D ServiceB Fault status (MSB) 0 = Port not selected 1 = Port selected and being serviced 0 = Selected port is not yet ramped up 1 = Selected port has been ramped up 0 = Selected port is using the RAMP module 1 = Selected port is not using the RAMP module 0 = Selected port current is being acquired 1 = Selected port current is not being acquired 0 = A/D data acquisition in process 1 = A/D not performing a conversion 000 = Reset state 001 = UV/OV fault/spike 010 = UV/OV spike 011 = Peak over-current fault 100 = Overload fault 101 = Di Discovery F il Fail 110 = Reserved for future 111 = Reserved for future STATE PRESET STATE 0 0 0
D1
Fault status
D0
Fault status (LSB)
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TPS2383
SLUS559 - APRIL 2003
FUNCTIONAL DESCRIPTION
Table 5. Port Status Read Register, Register Address = 001, Port Address = 001-111 (Port 2 through Port 8)
BIT D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Port service Spare Spare Spare Spare Fault status (MSB) Fault status Fault status (LSB) 000 = Reset state 001 = UV/OV fault/spike 010 = UV/OV spike 011 = Peak over-current fault 100 = Overload fault 101 = Discovery Fail 110 = Load disconnect 111 = Reserved for future 0 = Port not selected 1 = Port selected and being serviced STATE PRESET STATE 0 0 1 1 1
000
Table 6. Port Control Write Register, Register Address = 010, Port Address = 000 (Port 1 Register)
BIT D7 D6 D5 D4 D3 D2 D1 Enable modes D0 FUNCTION Port fault disable POR disable Software RESET LED blink example LED low-side enable LED high-side enable STATE 0 = Normal mode 1 = Disable the port overload and UV/OV timers 0 = Normal POR timing 1 = Force POR to a non-reset state 0 = Normal operation 1 = Reset all circuits and start a POR timing cycle 0 = LED is continuous 1 = Blink the enabled LED at a 0.25 Hz rate 1 = Enable the low-side FET and drive the LED pin low 1 = Enable the high-side FET and drive the LED pin to V5 00 = Port OFF or disable ower 01 = Discovery - classification - power on sequence 10 = Sample powered-mode current 11 = Power-down an active PRESET STATE 0 0 0 0 0 0
0
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TPS2383
SLUS559 - APRIL 2003
FUNCTIONAL DESCRIPTION
Table 7. Port Control Write Register, Register Address = 010, Port Address = 001 (Port 2 Register)
BIT D7 D6 FUNCTION Port fault disable Spare Class Limit2, Class Limit1 0,0 = 160-mA classification current limit 0,1 = 80-mA classification current limit 1,0 = 40-mA classification current limit 1,1 = 20-mA classification current limit 0 = LED is on continuous. 1 = Blink the enabled LED at a fast-blink rate. Note fast-blink rate (in milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be as fast as 65 ms for a 500-kHz, TPS2383 clock. 1 = Enable the low-side FET and drive the LED pin low 1 = Enable the high-side FET and drive the LED pin to V5 00 = Port OFF or disable ower 01 = Discovery - classification - power on sequence 10 = Sample powered-mode current 11 = Power-down an active port STATE 0 = Normal mode 1 = Disable the port overload and UV/OV timers PRESET STATE 0 0
D5
Class Limit 2
0
D4 D3 D2 D1
LED blink enablle LED low-side enable LED high-side enable
0 0 0
Enable modes D0
0
Table 8. Port Control Write Register, Register Address = 010, Port Address = 010 (Port 3 Register)
BIT D7 D6 D5 FUNCTION Port fault disable Spare A/D input select 0 = Normal mode - select port currents 1 = Select port voltage 0 = LED is on continuous. 1 = Blink the enabled LED at a fast-blink rate. Note fast-blink rate (in milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be as fast as 65 ms for a 500-kHz TPS2383 clock. 1 = Enable the low-side FET and drive the LED pin low 1 = Enable the high-side FET and drive the LED pin to V5 00 = Port OFF or disable ower 01 = Discovery - classification - power on sequence 10 = Sample powered-mode current 11 = Power-down an active port STATE 0 = Normal mode 1 = Disable the port overload and UV/OV timers PRESET STATE 0 0 0
D4 D3 D2 D1
LED blink enablle LED low-side enable LED high-side enable
0 0 0
Enable modes D0
0
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TPS2383
SLUS559 - APRIL 2003
FUNCTIONAL DESCRIPTION
Table 9. Port Control Write Register, Register Address = 010, Port Address = 011 (Port 4 Register)
BIT D7 D6 D5 FUNCTION Port fault disable Spare A/D input select 0 = Normal mode - select port currents 1 = Select port voltage 0 = LED is on continuous. 1 = Blink the enabled LED at a "fast blink" rate. Note "fast blink" rate (in milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be as fast as 65ms for a 500 kHz TPS2383 clock. 1 = Enable the low-side FET and drive the LED pin low 1 = Enable the high-side FET and drive the LED pin to V5 00 = Port OFF or disable 01 = Discovery - classification - power on sequence ower 10 = Sample powered-mode current 11 = Power-down an active port STATE 0 = Normal mode 1 = Disable the port overload and UV/OV timers PRESET STATE 0 0 0
D4
LED blink enablle
0
D3 D2 D1
LED low-side enable LED high-side enable
0 0
Enable modes D0
0
Table 10. Port Control Write Register, Register Address = 010, Port Address = 100-111 (Port 4 through Port 8 Register)
BIT D7 D6 D5 FUNCTION Port fault disable Spare Spare 0 = LED is on continuous. 1 = Blink the enabled LED at a "fast blink" rate. Note "fast blink" rate (in milliseconds) equivalent to 0.00013 x TPS2383 clock (CLK). This could be as fast as 65ms for a 500 kHz TPS2383 clock. 1 = Enable the low-side FET and drive the LED pin low 1 = Enable the high-side FET and drive the LED pin to V5 00 = Port OFF or disable 01 = Discovery - classification - power on sequence ower 10 = Sample powered-mode current 11 = Power-down an active port STATE 0 = Normal mode 1 = Disable the port overload and UV/OV timers PRESET STATE 0 0 0
D4
LED blink enablle
0
D3 D2 D1
LED low-side enable LED high-side enable
0 0
Enable modes D0
0
Run Current/Voltage During power delivery, the average value of the port running current or voltage is available from the read register. The slope type converter used produces 12 bits of input offset corrected conversion with a typical integration or averaging period of approximately one line cycle (16 ms). The actual averaging period is set by the CLK frequency and is equivalent to 8192 periods of that frequency. The lower eight bits of this conversion are available at the port register 011. The remaining upper four bits and A/D status bits are available at register 100. The converter span is 4096 bits. The A/D conversion port displays the real time counter output and holds the final static value at the completion of conversion
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TPS2383
SLUS559 - APRIL 2003
FUNCTIONAL DESCRIPTION
Table 11. Common Analog to Digital Conversion Port Read Register, Register Address = 011
BIT D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION A2D bit 7 A2D bit 6 A2D bit 5 A2D bit 4 A2D bit 3 A2D bit 2 A2D bit 1 A2D bit 0 A/D lower bits STATE PRESET STATE
Table 12. Common Analog to Digital Conversion Port Read Register, Register Address = 100
BIT D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION A2D zero cross A2D overflow Reserved for test Reserved for test A2D bit 11 A2D bit 10 A2D bit 9 A2D bit 8 A/D upper bits 0 = CINT is above zero threshold 1 = CINT is below zero threshold 1 = A2D overflow detected STATE PRESET STATE
Table 13. Chip Identification/Revision Read Register, Register Address = 101
BIT D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION Rev ID MSB Rev ID Rev ID LSB Device ID MSB Device ID Device ID Device ID Device ID LSB Function of revision STATE PRESET STATE
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TPS2383
SLUS559 - APRIL 2003
APPLICATION INFORMATION
SWITCH/HUB RJ-45 CT Choke TX 2 CT Choke RX 6 1 w/grn POWERED DTR RJ-45 w/grn 1 CT Choke RX 2 CT Choke TX 6
grn
grn
3
w/org
w/org
3
org
org
4 PPTC Fuse TPS2383 PSE P (1 Port) N V48 G RS 5
blue
blue
4
w/blue
w/blue
5
7
w/brn
w/brn
7 PD Signature 8 PD DC/DC Supply
8 568A
brn
brn
GND
568A Up to 350 feet of category 5 cable
RG
Optically Coupled I2C Serial Bus + 48-V Supply - MSP430 Controller UDG-03061
Figure 2. System Block Diagram
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TPS2383
SLUS559 - APRIL 2003
APPLICATION INFORMATION
V5
SCL BUS I2C BUS SDA BUS INTB BUS CT 0.1 F 120 pF +48V BUS POS NEG V5 4.22 k PORB 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 CR 49 PORB CR 0.047 F
CT
SDA_O
SDA_I
SCL_I
INTB
AG2
DG
A1
A2
A3
A4
A5
VL
EN
Xformer
RJ45-8/
RJ45-1/
Xformer
1 0.47 F 0.5 IRFD110 0.5 2 3 4 5 6 7 8 9
1P 1N 1G 1RS 2RS 2G 2N 2P 3P TPS2383 OCTAL PSE CONTROLLER
8P 8N 8G 8RS 7RS 7G 7N 7P 6P 6N 6G 6RS 5RS 5G 5N 5P V48 V10 RG CINT AG1 RT RD V5 L1 L2 L3 L4 L5 L6 L7 L8
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 0.5 0.5 IRFD110 0.47 F 0.47 F 0.5 0.5 IRFD110 0.47 F 0.47 F
RJ45-2/
Xformer
0.47 F
Xformer
RJ45-7/
10 3N RJ45-3/ Xformer 11 3G 0.47 F 0.5 IRFD110 0.5 RJ45-4/ Xformer 0.47 F 12 3RS 13 4RS 14 4G 15 4N 16 4P
Xformer Xformer
RJ45-6/ RJ45-5/
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V5
CD 0.82 F 0.1 F 0.1 F 0.1 F CINT 0.033 F RD 1 k
RT 120 k
Kelvin RS Sense
100 Green Green Green Green Green Green Green Green 100 Red 100 Red 100 Red 100 Red 100 Red 100 Red 100 Red 100 Red
V5
PORT 1 STATUS
PORT 2 STATUS
PORT 3 STATUS
PORT 4 STATUS
PORT 5 STATUS
PORT 6 STATUS
PORT 7 STATUS
PORT 8 STATUS
* All fuses are Self Resetting BBR550, Raychem
UDG-03064
Figure 3. Typical Eight-Port Application
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TPS2383
SLUS559 - APRIL 2003
APPLICATION INFORMATION
Controller VDD
SCL Bus SDA Bus Controller GND CMOS HEX Inverter CMOS HEX Inverter
220
OP1 PS9701
OP2 PS9701
220
OP3 PS9701
Isolated Ethernet Power System 1 k 330 1 k Floating +5V Floating GND
64
63
62
61
60
59
58 SDA_I
57 SDA_O
56 DG
55 SCL_I
54
53
52
51
50
49
TPS2383
UDG-03065
Figure 4. Using Optoisolators for I2C Bus/System Ground Isolation
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TPS2383
SLUS559 - APRIL 2003
APPLICATION INFORMATION
0.1 F 4.22 k
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50 CR 31 RT
SDA_O
SDA_I
SCL_I
TPS2383 No LED Drive AG1 V48 V10 RG V5 L1 L2 L3 L4 L5 L6 L7 L8
CINT
17
18
19
20
21
22
23
24
25
26
27
28
29
30
+48 V Bus Positive
47
32
RD
PORB
INTB
AG2
A1
A2
A3
A4
VL
A5
DG
EN
CT
49
80 V NMOS
+5 V + 0.1 F 10 F Tantalum 0.1 F
5 V LDO OUT GND IN
+8 V 0.1 F
+48 V Bus Negative
UDG-03066
Figure 5. V5 and VL Generation from Single +48-V Supply
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MECHANICAL DATA
MTQF008A - JANUARY 1995 - REVISED DECEMBER 1996
PM (S-PQFP-G64)
0,27 0,17 48 33
PLASTIC QUAD FLATPACK
0,50
0,08 M
49
32
64
17 0,13 NOM
1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,45 1,35
16 Gage Plane
0,25 0,05 MIN 0- 7
0,75 0,45
Seating Plane 1,60 MAX 0,08 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated

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