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TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor
Data Manual
Literature Number: SPRS200B July 2002 - Revised May 2003
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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Copyright 2003, Texas Instruments Incorporated
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS200A device-specific data sheet to make it an SPRS200B revision. Scope: Applicable updates to the C64x device family, specifically relating to the TMS320DM642 device, have been incorporated. "TBD" areas, where possible, have been resolved since the last document update.
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ADDS/CHANGES/DELETES Title Page: Changed the origination date of the TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor Data Manual from "June 2002" to "July 2002" Revision History: Created a Revision History for the SPRS200B document Description section: Updated the reference document title in the "For more details on the Video Port peripherals ..." paragraph Changed the literature number from "TBD" to "SPRU629" Changed the "The VXCO interpolated control ..." paragraph from "The VXCO interpolated control port (VIC) ..." to "The VXCO interpolated control (VIC) port ..." Changed the "The VXCO interpolated control ..." paragraph "TBD" to "For more details on the VIC port, see the ... (literature number SPRU629)" Changed the "The ethernet media access controller (EMAC) provides ..." paragraph "TBD" to "For more details on the EMAC, see the ... (literature number SPRU628)" reference Added more module functionality clarification to the "The management data input/output (MDIO) module provides TBD ..." paragraph Added the "For more details on the MDIO, see the ... (literature number SPRU628)" reference to the "The management data input/output (MDIO) module provides TBD ..." paragraph Deleted "boot from a serial EEPROM" from the "The I2C0 port on the TMS320DM642 allows the DSP ..." paragraph Table 1-1, Characteristics of the DM642 Processor Added "[DeviceID Register value 0x9065]" to the Hardware Features for the PCI Device Compatibility section: Deleted "The common peripheral set, code-compatibility, and ..." sentence from the "C64x DSP generation of devices has a diverse and powerful ..." paragraph Table 1-10, Ethernet MAC (EMAC) Registers: Deleted "??" from "Processor Test Access ??" for the RXFIFO and TXFIFO Table 1-12, EWRAP Registers: Changed the Reserved row from "01C8 0TBD - 01C8 37FF" to "01C8 300C - 01C8 37FF" Table 1-21, PCI Registers: Deleted the "TBD PID Peripheral device identification register Register value TBD" row [The Register value information now resides in the Characteristics of the DM642 Processor table (Table 1-1) of this document] Table 2-1, PCI_EN, HD5, and MAC_EN Peripheral Selection (HPI, GP0[15:9], PCI, EMAC, MDIO, and VIC) Updated the pin location of the PCI_EN Pin from "[AA4]" to "[E2]" Updated the pin location of the MAC_EN Pin from "[D6]" to "[C5]" Changed the GP0 pins under PERIPHERALS SELECTED from "GP0 - GP0[15:9]" to "GP0[15:9]" Table 2-2, HPI vs. EMAC Peripheral Pin Selection Updated the pin location of the MAC_EN Pin from "[D6]" to "[C5]"
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PAGE(s) NO. 62
ADDS/CHANGES/DELETES Table 2-3, DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI, and HD5): Changed the EMIFA input clock select bits FUNCTIONAL DESCRIPTION for the "11" setting from "AECLKIN" to "Reserved" Peripheral Configuration Lock section: Changed the sentence "Switching between peripherals that share multiplexed pins ..." to "Software muxed pins should not be programmed to switch functionalities during run-time." Table 2-7, Device Status (DEVSTAT) Register Selection Bit Descriptions Changed the EMAC enable bit DESCRIPTION from "1 = IEMAC is enabled." to "1 = EMAC is enabled." Changed the HPI bus width control bit DESCRIPTION from "1 = IHPI operates in 32-bit mode." to "1 = HPI operates in 32-bit mode." Changed the EMIFA input clock select bits DESCRIPTION for the "11" setting from "AECLKIN" to "Reserved" Multiplexed Pins section: Changed the sentence "Those muxed pins that are configured by software can be programmed to switch functionalities at any time." to "Those muxed pins that are configured by software should not be programmed to switch functionalities during run-time. Configuration Examples section: Deleted "TBD" from the Configuration Examples title Changed lead-in paragraph from "TBD" to new figure references Added three new figures depicting DM642 Configuration Examples (Figure 2-6, Figure 2-7, and Figure 2-8) Terminal Functions table, RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS (CONTINUED) section: Added "This pin must remain low during device reset." to the GP0[0] signal description Terminal Functions table, EMIFA (64-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL section: Changed the AECLKIN pin DESCRIPTION "The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the ... pins." from "... BEA[17:16] pins." to "... AEA[20:19] pins." Terminal Functions table, EMIFA (64-BIT) - ADDRESS section, - Boot mode (AEA[22:21]): section: Changed the "00" setting from "No boot" to "No boot (default mode)" Changed the "01" setting from "HPI boot" to "HPI/PCI boot (based on PCI_EN pin)" Changed the "10" setting from "EMIFA 8-bit ROM boot with default timings (default mode)" to "Reserved" Changed the "11" setting from "Reserved" to "EMIFA boot" Terminal Functions table, VCX0 INTERPOLATED CONTROL PORT (VIC) section: Deleted the "TBD" from the VDAC/GP0[8]/PCI66 pin description Terminal Functions table, TIMER 1 section: Changed the IPD/IPU for TOUT1/LENDIAN from "IPD" to "IPU" Terminal Functions table, MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) CONTROL section: Changed the VP0D[19]/AHCLKX0 pin description from "... McBSP0 transmit high-frequency ..." to "... McASP0 transmit highfrequency ..." Terminal Functions table, GROUND PINS section: Added the "F5" pin to the Vss GROUND PINS Figure 2-9, TMS320DM64x DSP Device Nomenclature (Including the TMS320DM642 Device): Changed device nomenclature from a "TMS" example to a "TMX" example due to the current DM642 device stage Documentation Support section: Added new paragraph: "The TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629) describes the functionality of the Video Port and VIC Port peripherals."
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Revision History
PAGE(s) NO. 106
ADDS/CHANGES/DELETES Multichannel Audio Serial Port (McASP0) Peripheral and McASP Block Diagram sections: Added new reference paragraph "For more detailed information on and the functionality of the McASP peripheral, see the TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041)." Deleted the subsections after the 2.12.1 McASP block diagram on modes, error handling/management, and interrupts/EDMA events (now covered in Literature Number SPRU041) IEEE 1149.1 JTAG Compatibility Statement section: Updated/changed/added paragraphs to clarify the TRST and RESET pin functions on the DM642 DSP device Bootmode section: Added new Bootmode section Asynchronous Memory Timing section: Updated/changed Figure 5-1, Asynchronous Memory Read Timing for EMIFA Updated/changed Figure 5-2, Asynchronous Memory Write Timing for EMIFA Table 15-1, Timing Requirements for PCLK: Split the "-500, -600" column into two separate columns "-500 [33 MHz]" and "-600 [66 MHz]" Changed/Updated the -500 [33 MHz] and -600 [66 MHz] parametric values
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Contents
Contents
Section 1 Page 17 18 18 19 21 22 22 24 27 29 48 50 52 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 GDK BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 GNZ BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Device Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 CPU (DSP Core) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9 Peripheral Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10 EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11 Interrupt Sources and Interrupt Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12 Signal Groups Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Device 2.1 2.2 2.3
2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24
Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Peripheral Selection at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Peripheral Selection After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.1 Peripheral Configuration Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.2 Device Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.3 JTAG ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Debugging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Multichannel Audio Serial Port (McASP0) Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.12.1 McASP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 VIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 EMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 2.19.1 Power-Supply Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 IEEE 1149.1 JTAG Compatibility Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 EMIF Device Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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Section 3
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Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Absolute Maximum Ratings Over Operating Case Temperature Range . . . . . . . . . . . . . . . . . . . . . . . 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Signal Transition Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Input and Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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Asynchronous Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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Programmable Synchronous Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Synchronous DRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
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HOLD/HOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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BUSREQ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12 Multichannel Audio Serial Port (McASP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
13 Inter-Integrated Circuits (I2C) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
14 Host-Port Interface (HPI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
15 Peripheral Component Interconnect (PCI) Timing
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16 Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
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Section 17 Video 17.1 17.2 17.3 17.4 17.5
Page Port Timing (VP0, VP1, VP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Data and Control Timing (Video Capture Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCLKIN Timing (Video Display Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx and VPxCLKOUTx (Video Display Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx) . . . . . . . . . . . . . . . . . . . . . . . . 164 164 165 166 166 168
18 Ethernet Media Access Controller (EMAC) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
19 Management Data Input/Output (MDIO) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
20 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
21 General-Purpose Input/Output (GPIO) Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
22 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
23 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 23.1 Ball Grid Array Mechanical Data Drawing (GDK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 23.2 Ball Grid Array Mechanical Data Drawing (GNZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
July 2002 - Revised May 2003
SPRS200B
9
Figures
List of Figures
Figure 1-1 1-2 1-3 1-4 1-5 1-6 Page GDK BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GNZ BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320C64x CPU (DSP Core) Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU and Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 23 26 52 53
2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13
Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 - 0x01B3F003] . . . . . . 63 Peripheral Enable/Disable Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] - Read/Write Accesses . . . . . . . . . . . 66 Device Status Register (DEVSTAT) Description - 0x01B3 F004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 JTAG ID Register Description - TMS320DM642 Register Value - 0x0007 902F . . . . . . . . . . . . . . . . . . . . 68 Configuration Example A (3 20-Bit Video Ports + HPI + EMAC + MDIO + I2C0 + EMIF + 3 Timers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Configuration Example B (2 10-Bit Video Ports + 2 McBSPs + EMAC + MDIO + I2C0 + EMIF) [Possible Video IP Phone Application] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Configuration Example C (2 10-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF) [Possible Set-Top Box Application] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TMS320DM64x DSP Device Nomenclature (Including the TMS320DM642 Device) . . . . . . . . . . . . . . . . 101 External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode . . . . . . . . . . . . . . . . . . . . . . . 104 McASP0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 I2C0 Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Schottky Diode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3-1 3-2 3-3 3-4
Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input and Output Voltage Reference Levels for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . Rise and Fall Transition Time Voltage Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120 120 120 121
4-1 4-2 4-3 4-4 4-5 4-6
CLKIN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKOUT6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ECLKIN Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AECLKOUT1 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AECLKOUT2 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
122 123 123 124 124 125
5-1 5-2
Asynchronous Memory Read Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Asynchronous Memory Write Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
10
SPRS200B
July 2002 - Revised May 2003
Figures
Figure Page 6-1 Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2) . . . . . . . . . . . 130 6-2 Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0) . . . . . . . . . . . 131 6-3 Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) . . . . . . . . . . . 132
7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8
SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM
Read Command (CAS Latency 3) for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACTV Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCAB Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEAC Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REFR Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MRS Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Refresh Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
134 135 136 136 137 137 138 138
8-1
HOLD/HOLDA Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
9-1
BUSREQ Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
10-1
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
11-1
External/NMI Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12-1 12-2
McASP Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 McASP Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
13-1 13-2
I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8
HPI16 Read Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI16 Read Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI16 Write Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI16 Write Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI32 Read Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI32 Read Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI32 Write Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI32 Write Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150 150 151 151 152 152 153 153
15-1 15-2
PCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 PCI Reset (PRST) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
July 2002 - Revised May 2003
SPRS200B
11
Figures
Figure 15-3 15-4 15-5
Page PCI Input Timing (33-/66-MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 PCI Output Timing (33-/66-MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 PCI Serial EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
16-1 16-2 16-3 16-4 16-5 16-6
McBSP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSR Timing When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
159 159 160 161 162 163
17-1 17-2 17-3 17-4 17-5 17-6
Video Port Capture VPxCLKINx TIming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Capture Data and Control Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Display VPxCLKINx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Display Data Output Timing and Control Input/Output Timing With Respect to VPxCLKINx and VPxCLKOUTx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port Dual-Display Sync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
164 164 165 166 167 168
18-1 18-2 18-3 18-4
MRCLK Timing (EMAC - Receive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MTCLK Timing (EMAC - Transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMAC Receive Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMAC Transmit Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
169 169 170 170
19-1 19-2
MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
20-1
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
21-1
GPIO Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
22-1
JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12
SPRS200B
July 2002 - Revised May 2003
Tables
List of Tables
Table 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-17 1-18 1-19 1-20 1-21 1-22 1-23 1-24 1-25 1-26 1-27 1-28 1-29 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 3-1 Page Characteristics of the DM642 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320DM642 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIFA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L2 Cache Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quick DMA (QDMA) and Pseudo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA Parameter RAM (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Selector Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Power-Down Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ethernet MAC (EMAC) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMAC Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EWRAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McBSP 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GP0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VXCO Interpolated Control (VIC) Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McASP0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . McASP0 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TMS320DM642 EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DM642 DSP Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 27 29 29 31 32 32 33 33 33 38 38 38 39 39 40 40 40 40 41 41 41 42 42 44 47 47 48 50
PCI_EN, HD5, and MAC_EN Peripheral Selection (HPI, GP0[15:9], PCI, EMAC, MDIO, and VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 HPI vs. EMAC Peripheral Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI, and HD5) . . . . . 62 Peripheral Configuration (PERCFG) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PCFGLOCK Register Selection Bit Descriptions - Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 PCFGLOCK Register Selection Bit Descriptions - Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Device Status (DEVSTAT) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 JTAG ID Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 DM642 Device Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 TMS320DM642 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time . . . . . 105 Board-Level Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
July 2002 - Revised May 2003
SPRS200B
13
Tables
Table 4-1 4-2 4-3 4-4 4-5 4-6 4-7
Page Timing Requirements for CLKIN for -500 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for CLKIN for -600 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 . . . . . . . . . . . . . . . Timing Requirements for AECLKIN for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 122 123 123 124 124 125
5-1 5-2
Timing Requirements for Asynchronous Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . 126 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6-1 6-2
Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . . . 129 Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . 133 Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Timing Requirements for Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Switching Characteristics Over Recommended Operating Conditions During Reset . . . . . . . . . . . . . . . 141 Timing Requirements for External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
7-1 7-2
8-1 8-2
9-1
10-1 10-2 11-1
12-1 12-2 13-1 13-2 14-1 14-2
Timing Requirements for McASP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Switching Characteristics Over Recommended Operating Conditions for McASP . . . . . . . . . . . . . . . . . 144 Timing Requirements for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Switching Characteristics for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Timing Requirements for Host-Port Interface Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14
SPRS200B
July 2002 - Revised May 2003
Tables
Table 15-1 15-2 15-3 15-4 15-5 15-6
Page Timing Requirements for PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for PCI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for PCI Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for PCI Outputs . . . . . . . . . . . . . Timing Requirements for Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 154 155 155 156 156 157 158 159 160 160 161 161 162 162 163 163 164 164 165 166 166 167 168 169 169 170 170
Timing Requirements for McBSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for McBSP . . . . . . . . . . . . . . . . . Timing Requirements for FSR When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . 16-7 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . 16-9 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . 16-11 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17-2 17-3 17-4 17-5 17-6 17-7 18-1 18-2 18-3 18-4 Timing Requirements for Video Capture Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirments for STCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements in Video Capture Mode for Video Data and Control Inputs . . . . . . . . . . . . . . . . . . Timing Requirements for Video Display Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to VPxCLKINx and VPxCLKOUTx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions in Video Display Mode for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx . . . . . . . . . . . Timing Requirements for Dual-Display Sync Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for MRCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for MTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Requirements for EMAC MII Receive 10/100 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-1 16-2 16-3 16-4 16-5
19-1 19-2 20-1 20-2
Timing Requirements for MDIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Switching Characteristics Over Recommended Operating Conditions for MDIO Output . . . . . . . . . . . . 171 Timing Requirements for Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs . . . . . . . . . . . . 172
July 2002 - Revised May 2003
SPRS200B
15
Tables
Table 21-1 21-2
Page Timing Requirements for GPIO Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs . . . . . . . . . . . . 173
22-1 22-2
Timing Requirements for JTAG Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port . . . . . . . . . . . 174
23-1 23-2
Thermal Resistance Characteristics (S-PBGA Package) [GDK] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Thermal Resistance Characteristics (S-PBGA Package) [GNZ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
16
SPRS200B
July 2002 - Revised May 2003
Features
1
Features
D High-Performance Digital Media Processor
(TMS320DM642) - 2-, 1.67-ns Instruction Cycle Time - 500-, 600-MHz Clock Rate - Eight 32-Bit Instructions/Cycle - 4000, 4800 MIPS - Fully Software-Compatible With C64x VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core - Eight Highly Independent Functional Units With VelociTI.2 Extensions: - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle - Load-Store Architecture With Non-Aligned Support - 64 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Byte-Addressable (8-/16-/32-/64-Bit Data) - 8-Bit Overflow Protection - Bit-Field Extract, Set, Clear - Normalization, Saturation, Bit-Counting - VelociTI.2 Increased Orthogonality L1/L2 Memory Architecture - 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) - 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) - 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) Endianess: Little Endian, Big Endian 64-Bit External Memory Interface (EMIF) - Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) - 1024M-Byte Total Addressable External Memory Space
D Enhanced Direct-Memory-Access (EDMA) D
Controller (64 Independent Channels) 10/100 Mb/s Ethernet MAC (EMAC) - IEEE 802.3 Compliant - Media Independent Interface (MII) - 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels Management Data Input/Output (MDIO) Three Configurable Video Ports - Providing a Glueless I/F to Common Video Decoder and Encoder Devices - Supports Multiple Resolutions and Video Standards - Supports RAW Video I/O - Transport Stream Interface Mode VCXO Interpolated Control Port (VIC) - Supports Audio/Video Synchronization Host-Port Interface (HPI) [32-/16-Bit] 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2 Multichannel Audio Serial Port (McASP) - Eight Serial Data Pins - Wide Variety of I2S and Similar Bit Stream Format - Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats Inter-Integrated Circuit (I2C) Bus Two Multichannel Buffered Serial Ports Three 32-Bit General-Purpose Timers Sixteen General-Purpose I/O (GPIO) Pins Flexible PLL Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 548-Pin Ball Grid Array (BGA) Package (GDK Suffix), 0.8-mm Ball Pitch 548-Pin Ball Grid Array (BGA) Package (GNZ Suffix), 1.0-mm Ball Pitch 0.13-m/6-Level Cu Metal Process (CMOS) 3.3-V I/Os, 1.2-V Internal (-500) 3.3-V I/Os, 1.4-V Internal (-600)
D
D D
D D D D
D
D
D D D D D D D D D D D
D D
C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
July 2002 - Revised May 2003
SPRS200B
17
PRODUCT PREVIEW
Features
1.1
GDK BGA Package (Bottom View)
GDK 548-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW )
AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D
PRODUCT PREVIEW
C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26
Figure 1-1. GDK BGA Package (Bottom View)
1.2
GNZ BGA Package (Bottom View)
GNZ 548-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW )
AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26
Figure 1-2. GNZ BGA Package (Bottom View)
Bottom View
18
SPRS200B
July 2002 - Revised May 2003
Description
1.3
Description
The TMS320C64x DSPs (including the TMS320DM642 device) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000 DSP platform. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-- with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI architecture. The DM642 can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals. The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. All three Video Port peripherals have the capability to operate as a video-capture port, a video-display port, or a transport stream interface (TSI) capture port. The DM642 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M). These three video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels -- A and B with a 5120-byte capture/display buffer that is splittable between the two channels. For capture operation, the video port can operate as two 8/10-bit channels of BT.656 or two 8/10-bit channel of raw video capture; or as a single channel of 8/10-bit BT.656, 8/10-bit raw video, 16/20-bit Y/C video, 16/20-bit raw video, or 8-bit TSI.
TMS320C6000, and C6000 are trademarks of Texas Instruments. July 2002 - Revised May 2003 SPRS200B 19
PRODUCT PREVIEW
Description
For display operation, the video port can operate as a single channel (using only channel A) of 8/10-bit BT.656 display, 8/10-bit raw video display, 16/20-bit Y/C video display, or 16/20-bit raw video display. Also, in the display mode of operation, the video port is capable of operating in a two-channel 8/10-bit raw mode in which two channels are locked to the same timing. For more details on the Video Port peripherals, see the TMS320DM642 Technical Overview (literature number SPRU615) or the TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629). The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.
PRODUCT PREVIEW
McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The VXCO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see the TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629). The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628). The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628). The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The DM642 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
Windows is a registered trademark of the Microsoft Corporation.
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Device Characteristics
1.4
Device Characteristics
Table 1-1 provides an overview of the DM642 DSP. The table shows significant features of the DM642 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.
Table 1-1. Characteristics of the DM642 Processor
HARDWARE FEATURES EMIFA (64-bit bus width) (clock source = AECLKIN) EDMA (64 independent channels) McASP0 (uses Peripheral Clock [AUXCLK]) I2C0 (uses Peripheral Clock) HPI (32- or 16-bit user selectable) DM642 1 1 1 1 1 (HPI16 or HPI32) 1 2 3 1 1 1 3 16 288K 16K-Byte (16KB) L1 Program (L1P) Cache Organization Control Status Register (CSR.[31:16]) JTAGID register (address location: 0x01B3F008) MHz 16KB L1 Data (L1D) Cache 256KB Unified Mapped RAM/Cache (L2) 0x0C01 0x0007902F 500, 600 2 ns (DM642-500) [500 MHz CPU, 100 MHz EMIF, 33 MHz PCI port] 1.67 ns (DM642-600) [600 MHz CPU, 133 MHz EMIF, 66 MHz PCI port] 1.2 V (-500) 1.4 V (-600) 3.3 V Bypass (x1), x6, x12 548-Pin BGA (GDK) 548-Pin BGA (GNZ) 0.13 m PP TMX320DM642GDK, TMX320DM642GNZ
Peripherals Not all peripherals pins are available at the same time (For more detail, see the Device Configuration section).
PCI (32-bit), 66-MHz/33-MHz [DeviceID Register value 0x9065] McBSPs (internal clock source = CPU/4 clock frequency) Configurable Video Ports (VP0, VP1, VP2) 10/100 Ethernet MAC (EMAC) Management Data Input/Output (MDIO) VXCO Interpolated Control Port (VIC) 32-Bit Timers (internal clock source = CPU/8 clock frequency) General-Purpose Input/Output Port (GP0) Size (Bytes)
On-Chip Memory
CPU ID + CPU Rev ID JTAG BSDL_ID Frequency
Cycle Time
ns
Voltage PLL Options BGA Package Process Technology Product Status Device Part Numbers
Core (V) I/O (V) CLKIN frequency multiplier 23 x 23 mm 27 x 27 mm m Product Preview (PP), Advance Information (AI), or Production Data (PD) (For more details on the C6000 DSP part numbering, see Figure 2-9)
On this DM64x device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device speed portion of this data sheet. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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Device Compatibility
1.5
Device Compatibility
The DM642 device is a code-compatible member of the C6000 DSP platform. The C64x DSP generation of devices has a diverse and powerful set of peripherals. For more detailed information on the device compatibility and similarities/differences among the DM642 and other C64x devices, see the TMS320DM642 Technical Overview (literature number SPRU615).
1.6
Functional Block Diagram
Figure 1-3 shows the functional block diagram of the DM642 device.
PRODUCT PREVIEW
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Functional Block Diagram
SDRAM SBSRAM ZBT SRAM FIFO SRAM ROM/FLASH I/O Devices
64
EMIF A Timer 2 Timer 1 Timer 0 VCXO Interpolated Control Port (VIC) Video Port 2 (VP2)
TMS320DM642
L1P Cache Direct-Mapped 16K Bytes Total
C64x DSP Core Instruction Fetch Instruction Dispatch Advanced Instruction Packet Instruction Decode Data Path A A Register File A31-A16 A15-A0 Data Path B B Register File B31-B16 B15-B0 Control Registers Control Logic Test Advanced In-Circuit Emulation
Video Port 0 (VP0) OR 8/10-bit VP0 AND McBSP0 OR McASP0 Control Enhanced DMA Controller (edma) L2 Cache Memory 256kBytes
Video Port 1 (VP1) OR 8/10-bit VP1 AND McBSP1 OR McASP0 Data
L1D Cache 2-Way Set-Associative 16K Bytes Total
See Note A
PLL (x1, x6, x12)
Power-Down Logic
PCI-66 OR HPI32 OR HPI16 AND EMAC MDIO Boot Configuration
16
GP0
16
I2C0
McBSPs: Framing Chips - H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs NOTE A: The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins. The Video Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins. The PCI peripheral is muxed with the HPI(32/16), EMAC, and MDIO peripherals. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet.
Figure 1-3. Functional Block Diagram
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.L1
.S1
.M1 .D1
.D2 .M2 .S2
.L2
Interrupt Control
CPU (DSP Core) Description
1.7
CPU (DSP Core) Description
The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP VelociTI architecture. These enhancements include:
* *
Register file enhancements Data path extensions Quad 8-bit and dual 16-bit extensions with data flow enhancements Additional functional unit hardware Increased orthogonality of the instruction set Additional instructions that reduce code size and increase register flexibility
PRODUCT PREVIEW
* * * *
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the C64x register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1-4]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a "data cross path"--a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. This is a key factor for video and imaging applications.
TMS320C62x is a trademark of Texas Instruments. 24 SPRS200B July 2002 - Revised May 2003
CPU (DSP Core) Description
Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically "true"). The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16 x 16-bit multiplies or four 8 x 8-bit multiplies per clock cycle. The .M unit can also perform 16 x 32-bit multiply operations, dual 16 x 16-bit multiplies with add/subtract operations, and quad 8 x 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable. For more details on the C64x CPU functional units enhancements, see the following documents:
* *
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) TMS320C64x Technical Overview (literature number SPRU395)
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CPU (DSP Core) Description
src1 .L1 src2 8 8
dst long dst long src ST1b (Store Data) ST1a (Store Data) 32 MSBs 32 LSBs long src long dst dst .S1 src1 Data Path A src2 long dst dst .M1 src1 src2 LD1b (Load Data) LD1a (Load Data) 32 MSBs 32 LSBs .D1 dst src1 src2
8 8 Register File A (A0-A31)
See Note A See Note A
PRODUCT PREVIEW
DA1 (Address)
2X 1X
src2 DA2 (Address) LD2a (Load Data) LD2b (Load Data) 32 LSBs 32 MSBs src2 .M2 src1 dst long dst src2 Data Path B .S2 src1 dst long dst long src See Note A See Note A Register File B (B0- B31) 8 8 .D2 src1 dst
ST2a (Store Data) ST2b (Store Data)
32 MSBs 32 LSBs long src long dst dst .L2 src2 src1 Control Register File 8 8
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 1-4. TMS320C64x CPU (DSP Core) Data Paths
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Memory Map Summary
1.8
Memory Map Summary
Table 1-2 shows the memory map address ranges of the DM642 device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address ranges in the DM642 device begin at the hex address location 0x8000 0000 for EMIFA.
Table 1-2. TMS320DM642 Memory Map Summary
MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) 256K 768K 23M 256K 256K 256K 256K 256K 256K 256K 256K 256K 512K 256K 256K - 4K 4K 16K 32K 16K 192K 256K 256K 256K 16K 16K 16K 16K 192K 4K 8K 2K 2K 3.5M 52 928M - 52 HEX ADDRESS RANGE
Internal RAM (L2) Reserved Reserved External Memory Interface A (EMIFA) Registers L2 Registers HPI Registers McBSP 0 Registers McBSP 1 Registers Timer 0 Registers Timer 1 Registers Interrupt Selector Registers EDMA RAM and EDMA Registers Reserved Timer 2 Registers GP0 Registers Device Configuration Registers I2C0 Data and Control Registers Reserved McASP0 Control Registers Reserved Reserved Emulation PCI Registers VP0 Control VP1 Control VP2 Control VIC Control Reserved EMAC Control EMAC Wrapper EWRAP Registers MDIO Control Registers Reserved QDMA Registers Reserved
0000 0000 - 0003 FFFF 0004 0000 - 000F FFFF 0010 0000 - 017F FFFF 0180 0000 - 0183 FFFF 0184 0000 - 0187 FFFF 0188 0000 - 018B FFFF 018C 0000 - 018F FFFF 0190 0000 - 0193 FFFF 0194 0000 - 0197 FFFF 0198 0000 - 019B FFFF 019C 0000 - 019F FFFF 01A0 0000 - 01A3 FFFF 01A4 0000 - 01AB FFFF 01AC 0000 - 01AF FFFF 01B0 0000 - 01B3 EFFF 01B3 F000 - 01B3 FFFF 01B4 0000 - 01B4 3FFF 01B4 4000 - 01B4 BFFF 01B4 C000 - 01B4 FFFF 01B5 0000 - 01B7 FFFF 01B8 0000 - 01BB FFFF 01BC 0000 - 01BF FFFF 01C0 0000 - 01C3 FFFF 01C4 0000 - 01C4 3FFF 01C4 4000 - 01C4 7FFF 01C4 8000 - 01C4 BFFF 01C4 C000 - 01C4 FFFF 01C5 0000 - 01C7 FFFF 01C8 0000 - 01C8 0FFF 01C8 1000 - 01C8 2FFF 01C8 3000 - 01C8 37FF 01C8 3800 - 01C8 3FFF 01C8 4000 - 01FF FFFF 0200 0000 - 0200 0033 0200 0034 - 2FFF FFFF
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Memory Map Summary
Table 1-2. TMS320DM642 Memory Map Summary (Continued)
MEMORY BLOCK DESCRIPTION McBSP 0 Data McBSP 1 Data Reserved McASP0 Data Reserved Reserved VP0 Channel A Data VP0 Channel B Data VP1 Channel A Data VP1 Channel B Data VP2 Channel A Data VP2 Channel B Data BLOCK SIZE (BYTES) 64M 64M 64M 1M 64M - 1M 832M 32M 32M 32M 32M 32M 32M 256M 256M 256M 256M 1G HEX ADDRESS RANGE
3000 0000 - 33FF FFFF 3400 0000 - 37FF FFFF 3800 0000 - 3BFF FFFF 3C00 0000 - 3C0F FFFF 3C10 0000 - 3FFF FFFF 4000 0000 - 73FF FFFF 7400 0000 - 75FF FFFF 7600 0000 - 77FF FFFF 7800 0000 - 79FF FFFF 7A00 0000 - 7BFF FFFF 7C00 0000 - 7DFF FFFF 7E00 0000 - 7FFF FFFF 8000 0000 - 8FFF FFFF 9000 0000 - 9FFF FFFF A000 0000 - AFFF FFFF B000 0000 - BFFF FFFF C000 0000 - FFFF FFFF
PRODUCT PREVIEW
EMIFA CE0 EMIFA CE1 EMIFA CE2 EMIFA CE3 Reserved
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Peripheral Register Descriptions
1.9
Peripheral Register Descriptions
Table 1-3 through Table 1-27 identify the peripheral registers for the DM642 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
Table 1-3. EMIFA Registers
HEX ADDRESS RANGE 0180 0000 0180 0004 0180 0008 0180 000C 0180 0010 0180 0014 0180 0018 0180 001C 0180 0020 0180 0024 - 0180 0040 0180 0044 0180 0048 0180 004C 0180 0050 0180 0054 0180 0058 - 0183 FFFF
ACRONYM GBLCTL CECTL1 CECTL0 - CECTL2 CECTL3 SDCTL SDTIM SDEXT - CESEC1 CESEC0 - CESEC2 CESEC3 -
REGISTER NAME EMIFA global control EMIFA CE1 space control EMIFA CE0 space control Reserved EMIFA CE2 space control EMIFA CE3 space control EMIFA SDRAM control EMIFA SDRAM refresh control Reserved EMIFA CE1 space secondary control EMIFA CE0 space secondary control Reserved EMIFA CE2 space secondary control EMIFA CE3 space secondary control Reserved EMIFA SDRAM extension
COMMENTS
Table 1-4. L2 Cache Registers (C64x)
HEX ADDRESS RANGE 0184 0000 0184 2000 0184 2004 0184 2008 0184 200C 0184 4000 0184 4004 0184 4010 0184 4014 0184 4020 0184 4024 0184 4030 0184 4034 0184 5000 0184 5004 ACRONYM CCFG - L2ALLOC0 L2ALLOC1 L2ALLOC2 L2ALLOC3 - L2FBAR L2FWC L2CBAR L2CWC L1PFBAR L1PFWC L1DFBAR L1DFWC - L2FLUSH L2CLEAN Reserved L2 allocation register 0 L2 allocation register 1 L2 allocation register 2 L2 allocation register 3 Reserved L2 flush base address register L2 flush word count register L2 clean base address register L2 clean word count register L1P flush base address register L1P flush word count register L1D flush base address register L1D flush word count register Reserved L2 flush register L2 clean register REGISTER NAME Cache configuration register COMMENTS
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Peripheral Register Descriptions
Table 1-4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE ACRONYM - 0184 8000 -0184 81FC 0184 8200 0184 8204 0184 8208 0184 820C 0184 8210 0184 8214 0184 8218 0184 821C 0184 8220 MAR0 to MAR127 MAR128 MAR129 MAR130 MAR131 MAR132 MAR133 MAR134 MAR135 MAR136 MAR137 MAR138 MAR139 MAR140 MAR141 MAR142 MAR143 MAR144 MAR145 MAR146 MAR147 MAR148 MAR149 MAR150 MAR151 MAR152 MAR153 MAR154 MAR155 MAR156 MAR157 MAR158 MAR159 MAR160 MAR161 MAR162 MAR163 MAR164 MAR165 MAR166 Reserved Reserved Controls EMIFA CE0 range 8000 0000 - 80FF FFFF Controls EMIFA CE0 range 8100 0000 - 81FF FFFF Controls EMIFA CE0 range 8200 0000 - 82FF FFFF Controls EMIFA CE0 range 8300 0000 - 83FF FFFF Controls EMIFA CE0 range 8400 0000 - 84FF FFFF Controls EMIFA CE0 range 8500 0000 - 85FF FFFF Controls EMIFA CE0 range 8600 0000 - 86FF FFFF Controls EMIFA CE0 range 8700 0000 - 87FF FFFF Controls EMIFA CE0 range 8800 0000 - 88FF FFFF Controls EMIFA CE0 range 8900 0000 - 89FF FFFF Controls EMIFA CE0 range 8A00 0000 - 8AFF FFFF Controls EMIFA CE0 range 8B00 0000 - 8BFF FFFF Controls EMIFA CE0 range 8C00 0000 - 8CFF FFFF Controls EMIFA CE0 range 8D00 0000 - 8DFF FFFF Controls EMIFA CE0 range 8E00 0000 - 8EFF FFFF Controls EMIFA CE0 range 8F00 0000 - 8FFF FFFF Controls EMIFA CE1 range 9000 0000 - 90FF FFFF Controls EMIFA CE1 range 9100 0000 - 91FF FFFF Controls EMIFA CE1 range 9200 0000 - 92FF FFFF Controls EMIFA CE1 range 9300 0000 - 93FF FFFF Controls EMIFA CE1 range 9400 0000 - 94FF FFFF Controls EMIFA CE1 range 9500 0000 - 95FF FFFF Controls EMIFA CE1 range 9600 0000 - 96FF FFFF Controls EMIFA CE1 range 9700 0000 - 97FF FFFF Controls EMIFA CE1 range 9800 0000 - 98FF FFFF Controls EMIFA CE1 range 9900 0000 - 99FF FFFF Controls EMIFA CE1 range 9A00 0000 - 9AFF FFFF Controls EMIFA CE1 range 9B00 0000 - 9BFF FFFF Controls EMIFA CE1 range 9C00 0000 - 9CFF FFFF Controls EMIFA CE1 range 9D00 0000 - 9DFF FFFF Controls EMIFA CE1 range 9E00 0000 - 9EFF FFFF Controls EMIFA CE1 range 9F00 0000 - 9FFF FFFF Controls EMIFA CE2 range A000 0000 - A0FF FFFF Controls EMIFA CE2 range A100 0000 - A1FF FFFF Controls EMIFA CE2 range A200 0000 - A2FF FFFF Controls EMIFA CE2 range A300 0000 - A3FF FFFF Controls EMIFA CE2 range A400 0000 - A4FF FFFF Controls EMIFA CE2 range A500 0000 - A5FF FFFF Controls EMIFA CE2 range A600 0000 - A6FF FFFF REGISTER NAME COMMENTS
PRODUCT PREVIEW
0184 8224 0184 8228 0184 822C 0184 8230 0184 8234 0184 8238 0184 823C 0184 8240 0184 8244 0184 8248 0184 824C 0184 8250 0184 8254 0184 8258 0184 825C 0184 8260 0184 8264 0184 8268 0184 826C 0184 8270 0184 8274 0184 8278 0184 827C 0184 8280 0184 8284 0184 8288 0184 828C 0184 8290 0184 8294 0184 8298
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Peripheral Register Descriptions
Table 1-4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE 0184 829C 0184 82A0 0184 82A4 0184 82A8 0184 82AC 0184 82B0 0184 82B4 0184 82B8 0184 82BC 0184 82C0 0184 82C4 0184 82C8 0184 82CC 0184 82D0 0184 82D4 0184 82D8 0184 82DC 0184 82E0 0184 82E4 0184 82E8 0184 82EC 0184 82F0 0184 82F4 0184 82F8 0184 82FC 0184 8300 -0184 83FC 0184 8400 -0187 FFFF ACRONYM MAR167 MAR168 MAR169 MAR170 MAR171 MAR172 MAR173 MAR174 MAR175 MAR176 MAR177 MAR178 MAR179 MAR180 MAR181 MAR182 MAR183 MAR184 MAR185 MAR186 MAR187 MAR188 MAR189 MAR190 MAR191 MAR192 to MAR255 - REGISTER NAME Controls EMIFA CE2 range A700 0000 - A7FF FFFF Controls EMIFA CE2 range A800 0000 - A8FF FFFF Controls EMIFA CE2 range A900 0000 - A9FF FFFF Controls EMIFA CE2 range AA00 0000 - AAFF FFFF Controls EMIFA CE2 range AB00 0000 - ABFF FFFF Controls EMIFA CE2 range AC00 0000 - ACFF FFFF Controls EMIFA CE2 range AD00 0000 - ADFF FFFF Controls EMIFA CE2 range AE00 0000 - AEFF FFFF Controls EMIFA CE2 range AF00 0000 - AFFF FFFF Controls EMIFA CE3 range B000 0000 - B0FF FFFF Controls EMIFA CE3 range B100 0000 - B1FF FFFF Controls EMIFA CE3 range B200 0000 - B2FF FFFF Controls EMIFA CE3 range B400 0000 - B4FF FFFF Controls EMIFA CE3 range B500 0000 - B5FF FFFF Controls EMIFA CE3 range B600 0000 - B6FF FFFF Controls EMIFA CE3 range B700 0000 - B7FF FFFF Controls EMIFA CE3 range B800 0000 - B8FF FFFF Controls EMIFA CE3 range B900 0000 - B9FF FFFF Controls EMIFA CE3 range BA00 0000 - BAFF FFFF Controls EMIFA CE3 range BB00 0000 - BBFF FFFF Controls EMIFA CE3 range BC00 0000 - BCFF FFFF Controls EMIFA CE3 range BD00 0000 - BDFF FFFF Controls EMIFA CE3 range BE00 0000 - BEFF FFFF Controls EMIFA CE3 range BF00 0000 - BFFF FFFF Reserved Reserved Controls EMIFA CE3 range B300 0000 - B3FF FFFF COMMENTS
Table 1-5. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE 0200 0000 0200 0004 0200 0008 0200 000C 0200 0010 0200 0014 - 0200 001C 0200 0020 0200 0024 0200 0028 0200 002C 0200 0030 QSOPT QSSRC QSCNT QSDST QSIDX ACRONYM QOPT QSRC QCNT QDST QIDX REGISTER NAME QDMA options parameter register QDMA source address register QDMA frame count register QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA psuedo source address register QDMA psuedo frame count register QDMA destination address register QDMA psuedo index register
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PRODUCT PREVIEW
Peripheral Register Descriptions
Table 1-6. EDMA Registers (C64x)
HEX ADDRESS RANGE 01A0 0800 - 01A0 FF98 01A0 FF9C 01A0 FFA4 01A0 FFA8 01A0 FFAC 01A0 FFB0 01A0 FFB4 01A0 FFB8 01A0 FFBC 01A0 FFC0 01A0 FFC4 01A0 FFC8 01A0 FFCC 01A0 FFDC ACRONYM - EPRH CIPRH CIERH CCERH ERH EERH ECRH ESRH PQAR0 PQAR1 PQAR2 PQAR3 EPRL PQSR CIPRL CIERL CCERL ERL EERL ECRL ESRL - Reserved Event polarity high register Channel interrupt pending high register Channel interrupt enable high register Channel chain enable high register Event high register Event enable high register Event clear high register Event set high register Priority queue allocation register 0 Priority queue allocation register 1 Priority queue allocation register 2 Priority queue allocation register 3 Event polarity low register Priority queue status register Channel interrupt pending low register Channel interrupt enable low register Channel chain enable low register Event low register Event enable low register Event clear low register Event set low register Reserved REGISTER NAME
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01A0 FFE0 01A0 FFE4 01A0 FFE8 01A0 FFEC 01A0 FFF0 01A0 FFF4 01A0 FFF8 01A0 FFFC 01A1 0000 - 01A3 FFFF
Table 1-7. EDMA Parameter RAM (C64x)
HEX ADDRESS RANGE 01A0 0000 - 01A0 0017 01A0 0018 - 01A0 002F 01A0 0030 - 01A0 0047 01A0 0048 - 01A0 005F 01A0 0060 - 01A0 0077 01A0 0078 - 01A0 008F 01A0 0090 - 01A0 00A7 01A0 00A8 - 01A0 00BF 01A0 00C0 - 01A0 00D7 01A0 00D8 - 01A0 00EF 01A0 00F0 - 01A0 00107 01A0 0108 - 01A0 011F 01A0 0120 - 01A0 0137 01A0 0138 - 01A0 014F 01A0 0150 - 01A0 0167 01A0 0168 - 01A0 017F ACRONYM - - - - - - - - - - - - - - - - REGISTER NAME Parameters for Event 0 (6 words) Parameters for Event 1 (6 words) Parameters for Event 2 (6 words) Parameters for Event 3 (6 words) Parameters for Event 4 (6 words) Parameters for Event 5 (6 words) Parameters for Event 6 (6 words) Parameters for Event 7 (6 words) Parameters for Event 8 (6 words) Parameters for Event 9 (6 words) Parameters for Event 10 (6 words) Parameters for Event 11 (6 words) Parameters for Event 12 (6 words) Parameters for Event 13 (6 words) Parameters for Event 14 (6 words) Parameters for Event 15 (6 words) COMMENTS Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event
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Peripheral Register Descriptions
Table 1-7. EDMA Parameter RAM (C64x) (Continued)
HEX ADDRESS RANGE 01A0 0150 - 01A0 0167 01A0 0168 - 01A0 017F ... 01A0 05D0 - 01A0 05E7 01A0 05E8 - 01A0 05FF 01A0 0600 - 01A0 0617 01A0 0618 - 01A0 062F ... 01A0 07E0 - 01A0 07F7 01A0 07F8 - 01A0 07FF 01A0 0800 - 01A0 0817 ... 01A0 13C8 - 01A0 13DF 01A0 13E0 - 01A0 13F7 01A0 13F8 - 01A0 13FF 01A0 1400 - 01A3 FFFF - - - - - - - - - - - ACRONYM - - REGISTER NAME Parameters for Event 16 (6 words) Parameters for Event 17 (6 words) ... Parameters for Event 62 (6 words) Parameters for Event 63 (6 words) Reload/link parameters for Event 0 (6 words) Reload/link parameters for Event 1 (6 words) ... Reload/link parameters for Event 20 (6 words) Reload/link parameters for Event 21 (6 words) Reload/link parameters for Event 22 (6 words) ... Reload/link parameters for Event 147 (6 words) Scratch pad area (2 words) Reload/link parameters for Event 148 (6 words) Reload/Link Parameters for other Event 0-15 COMMENTS
Reserved The DM64x device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.
Table 1-8. Interrupt Selector Registers (C64x)
HEX ADDRESS RANGE 019C 0000 019C 0004 019C 0008 019C 000C - 019C 01FF 019C 0200 019C 0204 - 019F FFFF ACRONYM MUXH MUXL EXTPOL - PDCTL - REGISTER NAME Interrupt multiplexer high Interrupt multiplexer low External interrupt polarity Reserved Peripheral power-down control register (see Table 1-9) Reserved COMMENTS Selects which interrupts drive CPU interrupts 10-15 (INT10-INT15) Selects which interrupts drive CPU interrupts 4-9 (INT04-INT09) Sets the polarity of the external interrupts (EXT_INT4-EXT_INT7)
Table 1-9. Peripheral Power-Down Control Register
HEX ADDRESS RANGE 019C 0200 ACRONYM PDCTL REGISTER NAME Peripheral power-down control register
Table 1-10. Ethernet MAC (EMAC) Registers
HEX ADDRESS RANGE 01C8 0000 01C8 0004 01C8 0008 01C8 000F 01C8 0010 01C8 0014 01C8 0018 ACRONYM TXIDVER TXCONTROL TXTEARDOWN - RXIDVER RXCONTROL RXTEARDOWN REGISTER NAME Transmit Identification and Version Register Transmit Control Register Transmit Teardown Register Reserved Receive Identification and Version Register Receive Control Register Receive Teardown Register
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PRODUCT PREVIEW
Peripheral Register Descriptions
Table 1-10. Ethernet MAC (EMAC) Registers (Continued)
HEX ADDRESS RANGE 01C8 001C - 01C8 00FF 01C8 0100 01C8 0104 01C8 0108 01C8 010C 01C8 0110 01C8 0114 01C8 0118 - 01C8 011F 01C8 0120 01C8 0124 01C8 0128 01C8 012C 01C8 0130 ACRONYM - RXMBPENABLE RXUNICASTSET RXUNICASTCLEAR RXMAXLEN RXBUFFEROFFSET RXFILTERLOWTHRESH - RX0FLOWTHRESH RX1FLOWTHRESH RX2FLOWTHRESH RX3FLOWTHRESH RX4FLOWTHRESH RX5FLOWTHRESH RX6FLOWTHRESH RX7FLOWTHRESH RX0FREEBUFFER RX1FREEBUFFER RX2FREEBUFFER RX3FREEBUFFER RX4FREEBUFFER RX5FREEBUFFER RX6FREEBUFFER RX7FREEBUFFER MACCONTROL MACSTATUS EMCONTROL - TXINTSTATRAW TXINTSTATMASKED TXINTMASKSET TXINTMASKCLEAR MACINVECTOR MACEOIVECTOR - RXINTSTATRAW RXINTSTATMASKED RXINTMASKSET RXINTMASKCLEAR MACINTSTATRAW MACINTSTATMASKED MACINTMASKSET MACINTMASKCLEAR REGISTER NAME Reserved Receive Multicast/Broadcast/Promiscuous Channel Enable Register Receive Unicast Set Register Receive Unicast Clear Register Receive Maximum Length Register Receive Buffer Offset Register Receive Filter Low Priority Packets Threshold Register Reserved Receive Channel 0 Flow Control Threshold Register Receive Channel 1 Flow Control Threshold Register Receive Channel 2 Flow Control Threshold Register Receive Channel 3 Flow Control Threshold Register Receive Channel 4 Flow Control Threshold Register Receive Channel 5 Flow Control Threshold Register Receive Channel 6 Flow Control Threshold Register Receive Channel 7 Flow Control Threshold Register Receive Channel 0 Free Buffer Count Register Receive Channel 1 Free Buffer Count Register Receive Channel 2 Free Buffer Count Register Receive Channel 3 Free Buffer Count Register Receive Channel 4 Free Buffer Count Register Receive Channel 5 Free Buffer Count Register Receive Channel 6 Free Buffer Count Register Receive Channel 7 Free Buffer Count Register MAC Control Register MAC Status Register Emulation Control Register Reserved Transmit Interrupt Status (Unmasked) Register Transmit Interrupt Status (Masked) Register Transmit Interrupt Mask Set Register Transmit Interrupt Mask Clear Register MAC Input Vector Register MAC EOI Vector Register Reserved Receive Interrupt Status (Unmasked) Register Receive Interrupt Status (Masked) Register Receive Interrupt Mask Set Register Receive Interrupt Mask Clear Register MAC Interrupt Status (Unmasked) Register MAC Interrupt Status (Masked) Register MAC Interrupt Mask Set Register MAC Interrupt Mask Clear Register
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01C8 0134 01C8 0138 01C8 013C 01C8 0140 01C8 0144 01C8 0148 01C8 014C 01C8 0150 01C8 0154 01C8 0158 01C8 015C 01C8 0160 01C8 0164 01C8 0168 01C8 016C 01C8 0170 01C8 0174 01C8 0178 01C8 017C 01C8 0180 01C8 0184 01C8 0188 - 01C8 018F 01C8 0190 01C8 0194 01C8 0198 01C8 019C 01C8 01A0 01C8 01A4 01C8 01A8 01C8 01AC
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Peripheral Register Descriptions
Table 1-10. Ethernet MAC (EMAC) Registers (Continued)
HEX ADDRESS RANGE 01C8 01B0 01C8 01B4 01C8 01B8 01C8 01BC 01C8 01C0 01C8 01C4 01C8 01C8 01C8 01CC 01C8 01D0 01C8 01D4 01C8 01D8 01C8 01DC 01C8 01E0 01C8 01E4 01C8 01E8 01C8 01EC 01C8 01F0 - 01C8 01FF 01C8 0200 01C8 0204 01C8 0208 01C8 020C 01C8 0210 01C8 0214 01C8 0218 01C8 021C 01C8 0220 01C8 0224 01C8 0228 01C8 022C 01C8 0230 01C8 0234 01C8 0238 01C8 023C 01C8 0240 01C8 0244 01C8 0248 01C8 024C 01C8 0250 01C8 0254 01C8 0258 01C8 025C 01C8 0260 01C8 0264 01C8 0268 ACRONYM MACADDRL0 MACADDRL1 MACADDRL2 MACADDRL3 MACADDRL4 MACADDRL5 MACADDRL6 MACADDRL7 MACADDRM MACADDRH MACHASH1 MACHASH2 BOFFTEST TPACETEST RXPAUSE TXPAUSE - RXGOODFRAMES RXBCASTFRAMES RXMCASTFRAMES RXPAUSEFRAMES RXCRCERRORS RXALIGNCODEERRORS RXOVERSIZED RXJABBER RXUNDERSIZED RXFRAGMENTS RXFILTERED RXQOSFILTERED RXOCTETS TXGOODFRAMES TXBCASTFRAMES TXMCASTFRAMES TXPAUSEFRAMES TXDEFERRED TXCOLLISION TXSINGLECOLL TXMULTICOLL TXEXCESSIVECOLL TXLATECOLL TXUNDERRUN TXCARRIERSLOSS TXOCTETS FRAME64 REGISTER NAME MAC Address Channel 0 Lower Byte Register MAC Address Channel 1 Lower Byte Register MAC Address Channel 2 Lower Byte Register MAC Address Channel 3 Lower Byte Register MAC Address Channel 4 Lower Byte Register MAC Address Channel 5 Lower Byte Register MAC Address Channel 6 Lower Byte Register MAC Address Channel 7 Lower Byte Register MAC Address Middle Byte Register MAC Address High Bytes Register MAC Address Hash 1 Register MAC Address Hash 2 Register Backoff Test Register Transmit Pacing Test Register Receive Pause Timer Register Transmit Pause Timer Register Reserved Good Receive Frames Register Broadcast Receive Frames Register Multicast Receive Frames Register Pause Receive Frames Register Receive CRC Errors Register Receive Alignment/Code Errors Register Receive Oversized Frames Register Receive Jabber Frames Register Receive Undersized Frames Register Receive Frame Fragments Register Filtered Receive Frames Register Receive QOS Filtered Frames Register Receive Octet Frames Register Good Transmit Frames Register Broadcast Transmit Frames Register Multicast Transmit Frames Register Pause Transmit Frames Register Deferred Transmit Frames Register Collision Register Single Collision Transmit Frames Register Multiple Collision Transmit Frames Register Excessive Collisions Register Late Collisions Register Transmit Underrun Register Transmit Carrier Sense Errors Register Transmit Octet Frames Register Transmit and Receive 64 Octet Frames Register
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PRODUCT PREVIEW
Peripheral Register Descriptions
Table 1-10. Ethernet MAC (EMAC) Registers (Continued)
HEX ADDRESS RANGE 01C8 026C 01C8 0270 01C8 0274 01C8 0278 01C8 027C 01C8 0280 01C8 0284 01C8 0288 01C8 028C 01C8 0290 - 01C8 02FF 01C8 0300 - 01C8 03FF 01C8 0400 - 01C8 04FF 01C8 0500 - 01C8 05FF ACRONYM FRAME65T127 FRAME128T255 FRAME256T511 FRAME512T1023 FRAME1024TUP NETOCTETS RXSOFOVERRUNS RXMOFOVERRUNS RXDMAOVERRUNS - RXFIFO TXFIFO - TX0HDP TX1HDP TX2HDP TX3HDP TX4HDP TX5HDP TX6HDP TX7HDP RX0HDP RX1HDP RX2HDP RX3HDP RX4HDP RX5HDP RX6HDP RX7HDP TX0INTACK REGISTER NAME Transmit and Receive 65 to 127 Octet Frames Register Transmit and Receive 128 to 255 Octet Frames Register Transmit and Receive 256 to 511 Octet Frames Register Transmit and Receive 512 to 1023 Octet Frames Register Transmit and Receive 1024 or Above Octet Frames Register Network Octet Frames Register Receive Start of Frame Overruns Register Receive Middle of Frame Overruns Register Receive DMA Overruns Register Reserved Processor Test Access Processor Test Access Reserved Transmit Channel 0 DMA Head Descriptor Pointer Register Transmit Channel 1 DMA Head Descriptor Pointer Register Transmit Channel 2 DMA Head Descriptor Pointer Register Transmit Channel 3 DMA Head Descriptor Pointer Register Transmit Channel 4 DMA Head Descriptor Pointer Register Transmit Channel 5 DMA Head Descriptor Pointer Register Transmit Channel 6 DMA Head Descriptor Pointer Register Transmit Channel 7 DMA Head Descriptor Pointer Register Receive Channel 0 DMA Head Descriptor Pointer Register Receive Channel 1 DMA Head Descriptor Pointer Register Receive Channel 2 DMA Head Descriptor Pointer Register Receive Channel 3 DMA Head Descriptor Pointer Register Receive Channel 4 DMA Head Descriptor Pointer Register Receive Channel 5 DMA Head Descriptor Pointer Register Receive Channel 6 DMA Head Descriptor Pointer Register Receive Channel 7 DMA Head Descriptor Pointer Register Transmit Channel 0 Interrupt Acknowledge Register
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01C8 0600 01C8 0604 01C8 0608 01C8 060C 01C8 0610 01C8 0614 01C8 0618 01C8 061C 01C8 0620 01C8 0624 01C8 0628 01C8 062C 01C8 0630 01C8 0634 01C8 0638 01C8 063C 01C8 0640
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SPRS200B
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Peripheral Register Descriptions
Table 1-10. Ethernet MAC (EMAC) Registers (Continued)
HEX ADDRESS RANGE 01C8 0644 01C8 0648 01C8 064C 01C8 0650 01C8 0654 01C8 0658 01C8 065C 01C8 0660 01C8 0664 01C8 0668 01C8 066C 01C8 0670 01C8 0674 01C8 0678 01C8 067C 01C8 0680 - 01C8 06FF 01C8 0700 - 01C8 077F 01C8 0780 - 01C8 0FFF ACRONYM TX1INTACK TX2INTACK TX3INTACK TX4INTACK TX5INTACK TX6INTACK TX7INTACK RX0INTACK RX1INTACK RX2INTACK RX3INTACK RX4INTACK RX5INTACK RX6INTACK RX7INTACK - - - REGISTER NAME Transmit Channel 1 Interrupt Acknowledge Register Transmit Channel 2 Interrupt Acknowledge Register Transmit Channel 3 Interrupt Acknowledge Register Transmit Channel 4 Interrupt Acknowledge Register Transmit Channel 5 Interrupt Acknowledge Register Transmit Channel 6 Interrupt Acknowledge Register Transmit Channel 7 Interrupt Acknowledge Register Receive Channel 0 Interrupt Acknowledge Register Receive Channel 1 Interrupt Acknowledge Register Receive Channel 2 Interrupt Acknowledge Register Receive Channel 3 Interrupt Acknowledge Register Receive Channel 4 Interrupt Acknowledge Register Receive Channel 5 Interrupt Acknowledge Register Receive Channel 6 Interrupt Acknowledge Register Receive Channel 7 Interrupt Acknowledge Register Reserved State RAM Test Access - Processor read and write access to head descriptor pointers and interrupt acknowledge registers. Reserved
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PRODUCT PREVIEW
Peripheral Register Descriptions
Table 1-11. EMAC Wrapper
HEX ADDRESS RANGE 01C8 1000 - 01C8 1FFF 01C8 2000 - 01C8 2FFF - ACRONYM Reserved REGISTER NAME EMAC Control Module Descriptor Memory
Table 1-12. EWRAP Registers
HEX ADDRESS RANGE 01C8 3000 01C8 3004 01C8 3008 01C8 300C - 01C8 37FF ACRONYM EWTRCTRL EWCTL EWINTTCNT - TR control Interrupt control register Interrupt timer count Reserved REGISTER NAME
Table 1-13. Device Configuration Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Enables or disables specific peripherals. This register is also used for power-down of disabled peripherals. Read-only. Provides status of the User's device configuration on reset. Read-only. Provides JTAG ID of the device. 32-bit
01B3 F000
PERCFG
Peripheral Configuration Register
PRODUCT PREVIEW
01B3 F004
DEVSTAT
Device Status Register
01B3 F008 01B3 F00C - 01B3 F014 01B3 F018 01B3 F01C - 01B3 FFFF
JTAGID - PCFGLOCK -
JTAG Identification Register Reserved Peripheral Configuration Lock Register Reserved
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SPRS200B
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Peripheral Register Descriptions
Table 1-14. McBSP 0 Registers
HEX ADDRESS RANGE 018C 0000 0x3000 0000 - 0x33FF FFFF 018C 0004 0x3000 0000 - 0x33FF FFFF 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 018C 002C 018C 0030 018C 0034 018C 0038 018C 003C 018C 0040 - 018F FFFF ACRONYM DRR0 DRR0 DXR0 DXR0 SPCR0 RCR0 XCR0 SRGR0 MCR0 RCERE00 XCERE00 PCR0 RCERE10 XCERE10 RCERE20 XCERE20 RCERE30 XCERE30 - REGISTER NAME McBSP0 data receive register via Configuration Bus McBSP0 data receive register via Peripheral Bus McBSP0 data transmit register via Configuration Bus McBSP0 data transmit register via Peripheral Bus McBSP0 serial port control register McBSP0 receive control register McBSP0 transmit control register McBSP0 sample rate generator register McBSP0 multichannel control register McBSP0 enhanced receive channel enable register 0 McBSP0 enhanced transmit channel enable register 0 McBSP0 pin control register McBSP0 enhanced transmit channel enable register 1 McBSP0 enhanced receive channel enable register 2 McBSP0 enhanced transmit channel enable register 2 McBSP0 enhanced receive channel enable register 3 McBSP0 enhanced transmit channel enable register 3 Reserved McBSP0 enhanced receive channel enable register 1 COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it.
Table 1-15. McBSP 1 Registers
HEX ADDRESS RANGE 0190 0000 0x3400 0000 - 0x37FF FFFF 0190 0004 0x3400 0000 - 0x37FF FFFF 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 0190 0024 0190 0028 0190 002C 0190 0030 0190 0034 0190 0038 0190 003C 0190 0040 - 0193 FFFF ACRONYM DRR1 DRR1 DXR1 DXR1 SPCR1 RCR1 XCR1 SRGR1 MCR1 RCERE01 XCERE01 PCR1 RCERE11 XCERE11 RCERE21 XCERE21 RCERE31 XCERE31 - REGISTER NAME McBSP1 data receive register via Configuration Bus McBSP1 data receive register via peripheral bus McBSP1 data transmit register via configuration bus McBSP1 data transmit register via peripheral bus McBSP1 serial port control register McBSP1 receive control register McBSP1 transmit control register McBSP1 sample rate generator register McBSP1 multichannel control register McBSP1 enhanced receive channel enable register 0 McBSP1 enhanced transmit channel enable register 0 McBSP1 pin control register McBSP1 enhanced receive channel enable register 1 McBSP1 enhanced transmit channel enable register 1 McBSP1 enhanced receive channel enable register 2 McBSP1 enhanced transmit channel enable register 2 McBSP1 enhanced receive channel enable register 3 McBSP1 enhanced transmit channel enable register 3 Reserved COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it.
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PRODUCT PREVIEW
Peripheral Register Descriptions
Table 1-16. Timer 0 Registers
HEX ADDRESS RANGE 0194 0000 0194 0004 0194 0008 0194 000C - 0197 FFFF ACRONYM CTL0 PRD0 CNT0 - REGISTER NAME Timer 0 control register Timer 0 period register Timer 0 counter register Reserved COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
Table 1-17. Timer 1 Registers
HEX ADDRESS RANGE 0198 0000 0198 0004 0198 0008 0198 000C - 019B FFFF ACRONYM CTL1 PRD1 CNT1 - REGISTER NAME Timer 1 control register Timer 1 period register Timer 1 counter register Reserved COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
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Table 1-18. Timer 2 Registers
HEX ADDRESS RANGE 01AC 0000 01AC 0004 01AC 0008 01AC 000C - 01AF FFFF ACRONYM CTL2 PRD2 CNT2 - REGISTER NAME Timer 2 control register Timer 2 period register Timer 2 counter register Reserved COMMENTS Determines the operating mode of the timer, monitors the timer status. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
Table 1-19. HPI Registers
HEX ADDRESS RANGE - 0188 0000 0188 0004 0188 0008 ACRONYM HPID HPIC HPIA (HPIAW) HPIA (HPIAR) REGISTER NAME HPI data register HPI control register HPI address register (Write) HPI address register (Read) HPIA has both Host/CPU read/write access COMMENTS Host read/write access only HPIC has both Host/CPU read/write access
0188 0001 - 018B FFFF - Reserved Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
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SPRS200B
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Peripheral Register Descriptions
Table 1-20. GP0 Registers
HEX ADDRESS RANGE 01B0 0000 01B0 0004 01B0 0008 01B0 000C 01B0 0010 01B0 0014 01B0 0018 01B0 001C 01B0 0020 01B0 0024 01B0 0028 - 01B3 EFFF ACRONYM GPEN GPDIR GPVAL - GPDH GPHM GPDL GPLM GPGC GPPOL - REGISTER NAME GP0 enable register GP0 direction register GP0 value register Reserved GP0 delta high register GP0 high mask register GP0 delta low register GP0 low mask register GP0 global control register GP0 interrupt polarity register Reserved
Table 1-21. PCI Peripheral Registers
01C0 0000 01C0 0004 01C0 0008 01C0 000C 01C0 0010 01C0 0014 01C0 0018 01C0 001C 01C0 0020 01C0 0024 01C0 0028 01C0 002C - 01C1 FFEF 0x01C1 FFF0 0x01C1 FFF4 0x01C1 FFF8 0x01C1 FFFC 01C2 0000 01C2 0004 01C2 0008 01C2 000C - 01C2 FFFF 01C3 0000 01C3 0004 - 01C3 FFFF
RSTSRC PMDCSR PCIIS PCIIEN DSPMA PCIMA PCIMC CDSPA CPCIA CCNT - - HSR HDCR DSPP - EEADD EEDAT EECTL - PCI_TRCNTL -
DSP Reset source/status register Power management DSP control/status register PCI interrupt source register PCI interrupt enable register DSP master address register PCI master address register PCI master control register Current DSP address register Current PCI address register Current byte count register Reserved Reserved Host status register Host-to-DSP control register DSP page register Reserved EEPROM address register EEPROM data register EEPROM control register Reserved PCI transfer request control register Reserved
Table 1-22. VXCO Interpolated Control (VIC) Port Registers
HEX ADDRESS RANGE 01C4 C000 01C4 C004 01C4 C008 01C4 C00C - 01C4 FFFF ACRONYM VICCTL VICIN VPDIV - REGISTER NAME VIC control register VIC input register VIC clock divider register Reserved
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PRODUCT PREVIEW
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Peripheral Register Descriptions
Table 1-23. MDIO Registers
HEX ADDRESS RANGE 01C8 3800 01C8 3804 01C8 3808 01C8 380C 01C8 3810 01C8 3814 01C8 3818 01C8 381C 01C8 3820 01C8 3824 01C8 3828 01C8 382C 01C8 3830 01C8 3834 01C8 3838 - 01C8 3FFF ACRONYM VERSION CONTROL ALIVE LINK LINKINTRAW LINKINTMASKED USERINTRAW USERINTMASKED USERINTMASKSET USERINTMASKCLEAR USERACCESS0 USERACCESS1 USERPHYSEL0 USERPHYSEL1 - MDIO Version Register MDIO Control Register MDIO PHY Alive Indication Register MDIO PHY Link Status Register MDIO Link Status Change Interrupt Register MDIO Link Status Change Interrupt (Masked) Register MDIO User Command Complete Interrupt Register MDIO User Command Complete Interrupt (Masked) Register MDIO User Command Complete Interrupt Mask Set Register MDIO User Command Complete Interrupt Mask Clear Register MDIO User Access Register 0 MDIO User Access Register 1 MDIO User PHY Select Register 0 MDIO User PHY Select Register 1 Reserved REGISTER NAME
PRODUCT PREVIEW
Table 1-24. Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers
HEX ADDRESS RANGE VP0 01C4 0000 01C4 0004 01C4 01C4 01C4 0020 01C4 0024 01C4 0028 01C4 002C 01C4 0030 01C4 0034 01C4 0038 01C4 003C 01C4 0040 01C4 0044 01C4 00C0 01C4 00C4 01C4 00C8 01C4 00CC 01C4 0100 01C4 0104 01C4 0108 01C4 010C 01C4 0110 01C4 0114 VP1 01C4 4000 01C4 4004 01C4 01C4 01C4 4020 01C4 4024 01C4 4028 01C4 402C 01C4 4030 01C4 4034 01C4 4038 01C4 403C 01C4 4040 01C4 4044 01C4 40C0 01C4 40C4 01C4 40C8 01C4 40CC 01C4 4100 01C4 4104 01C4 4108 01C4 410C 01C4 4110 01C4 4114 VP2 01C4 8000 01C4 8004 01C4 01C4 01C4 8020 01C4 8024 01C4 8028 01C4 802C 01C4 8030 01C4 8034 01C4 8038 01C4 803C 01C4 8040 01C4 8044 01C4 80C0 01C4 80C4 01C4 80C8 01C4 80CC 01C4 8100 01C4 8104 01C4 8108 01C4 810C 01C4 8110 01C4 8114 VP_PFUNCx VP_PDIRx VP_PDINx VP_PDOUTx VP_PDSETx VP_PDCLRx VP_PIENx VP_PIPOx VP_PISTATx VP_PICLRx VP_CTLx VP_STATx VP_IEx VP_ISx VC_STATx VC_CTLx VC_ASTRTx VC_ASTOPx VC_ASTRTx VC_ASTOPx ACRONYM VP_PIDx VP_PCRx DESCRIPTION Video Port Peripheral Identification Register Video Port Peripheral Control Register Video Port Test Logic Global Control Register Video Port MISR Results Register Video Port Pin Function Register Video Port Pin Direction Register Video Port Pin Data Input Register Video Port Pin Data Output Register Video Port Pin Data Set Register Video Port Pin Data Clear Register Video Port Pin Interrupt Enable Register Video Port Pin Interrupt Polarity Register Video Port Pin Interrupt Status Register Video Port Pin Interrupt Clear Register Video Port Control Register Video Port Status Register Video Port Interrupt Enable Register Video Port interrupt Status Register Video Capture Channel A Status Register Video Capture Channel A Control Register Video Capture Channel A Field 1 Start Register Video Capture Channel A Field 2 Stop Register Video Capture Channel A Field 2 Start Register Video Capture Channel A Field 1 Stop Register
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Peripheral Register Descriptions
Table 1-24. Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers (Continued)
HEX ADDRESS RANGE VP0 01C4 0118 01C4 011C 01C4 0120 01C4 0140 01C4 0144 01C4 0148 01C4 014C 01C4 0150 01C4 0154 01C4 0158 01C4 015C 01C4 0160 01C4 0180 01C4 0184 01C4 0188 01C4 018C 01C4 0190 01C4 0194 01C4 0198 01C4 019C 01C4 01A0 01C4 01A4 01C4 0200 01C4 0204 01C4 0208 01C4 020C 01C4 0210 01C4 0214 01C4 0218 01C4 021C 01C4 0220 01C4 0224 01C4 0228 01C4 022C 01C4 0230 01C4 0234 01C4 0238 01C4 023C 01C4 0240 01C4 0244 01C4 0248 VP1 01C4 4118 01C4 411C 01C4 4120 01C4 4140 01C4 4144 01C4 4148 01C4 414C 01C4 4150 01C4 4154 01C4 4158 01C4 415C 01C4 4160 01C4 4180 01C4 4184 01C4 4188 01C4 418C 01C4 4190 01C4 4194 01C4 4198 01C4 419C 01C4 41A0 01C4 41A4 01C4 4200 01C4 4204 01C4 4208 01C4 420C 01C4 4210 01C4 4214 01C4 4218 01C4 421C 01C4 4220 01C4 4224 01C4 4228 01C4 422C 01C4 4230 01C4 4234 01C4 4238 01C4 423C 01C4 4240 01C4 4244 01C4 4248 VP2 01C4 8118 01C4 811C 01C4 8120 01C4 8140 01C4 8144 01C4 8148 01C4 814C 01C4 8150 01C4 8154 01C4 8158 01C4 815C 01C4 8160 01C4 8180 01C4 8184 01C4 8188 01C4 818C 01C4 8190 01C4 8194 01C4 8198 01C4 819C 01C4 81A0 01C4 81A4 01C4 8200 01C4 8204 01C4 8208 01C4 820C 01C4 8210 01C4 8214 01C4 8218 01C4 821C 01C4 8220 01C4 8224 01C4 8228 01C4 822C 01C4 8230 01C4 8234 01C4 8238 01C4 823C 01C4 8240 01C4 8244 01C4 8248 ACRONYM VC_AVINTx VC_ATHRLDx VC_AEVTCTx VC_BSTATx VC_BCTLx VC_BSTRTx VC_BSTOPx VC_BSTRTx VC_BSTOPx VC_BVINTx VC_BTHRLDx VC_BEVTCTx TSI_CTLx TSI_CLKINITLx TSI_CLKINITMx TSI_STCLKLx TSI_STCLKMx TSI_STCMPLx TSI_STCMPMx TSI_STMSKLx TSI_STMSKMx TSI_TICKSx VD_STATx VD_CTLx VD_FRMSZx VD_HBLNKx VD_VBLKS1x VD_VBLKE1x VD_VBLKS2x VD_VBLKE2x VD_IMGOFF1x VD_IMGSZ1x VD_IMGOFF2x VD_IMGSZ2x VD_FLDT1x VD_FLDT2x VD_THRLDx VD_HSYNCx VD_VSYNS1x VD_VSYNE1x VD_VSYNS2x DESCRIPTION Video Capture Channel A Vertical Interrupt Register Video Capture Channel A Threshold Register Video Capture Channel A Event Count Register Video Capture Channel B Status Register Video Capture Channel B Control Register Video Capture Channel B Field 1 Start Register Video Capture Channel B Field 1 Stop Register Video Capture Channel B Field 2 Start Register Video Capture Channel B Field 2 Stop Register Video Capture Channel B Vertical Interrupt Register Video Capture Channel B Threshold Register
TCI Capture Control Register TCI Clock Initialization LSB Register TCI Clock Initialization MSB Register TCI System Time Clock LSB Register TCI System Time Clock MSB Register TCI System Time Clock Compare LSB Register TCI System Time Clock Compare MSB Register TCI System Time Clock Compare Mask LSB Register TCI System Time Clock Compare Mask MSB Register TCI System Time Clock Ticks Interrupt Register Video Display Status Register Video Display Control Register Video Display Frame Size Register Video Display Horizontal Blanking Register Video Display Field 1 Vertical Blanking Start Register Video Display Field 1 Vertical Blanking End Register Video Display Field 2 Vertical Blanking Start Register Video Display Field 2 Vertical Blanking End Register Video Display Field 1 Image Offset Register Video Display Field 1 Image Size Register Video Display Field 2 Image Offset Register Video Display Field 2 Image Size Register Video Display Field 1 Timing Register Video Display Field 2 Timing Register Video Display Threshold Register Video Display Horizontal Synchronization Register Video Display Field 1 Vertical Synchronization Start Register Video Display Field 1 Vertical Synchronization End Register Video Display Field 2 Vertical Synchronization Start Register
July 2002 - Revised May 2003
SPRS200B
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PRODUCT PREVIEW
Video Capture Channel B Event Count Register
Peripheral Register Descriptions
Table 1-24. Video Port 0, 1, and 2 (VP0, VP1, and VP2) Control Registers (Continued)
HEX ADDRESS RANGE VP0 01C4 024C 01C4 0250 01C4 0254 01C4 0258 01C4 025C 01C4 0260 01C4 0264 01C4 0268 01C4 026C 7400 000 7400 0008 7400 0010 7400 0020 7400 0028 7400 0030 7600 0000 7600 0008 7600 0010 7600 0020 VP1 01C4 424C 01C4 4250 01C4 4254 01C4 4258 01C4 425C 01C4 4260 01C4 4264 01C4 4268 01C4 426C 7800 0000 7800 0008 7800 0010 7800 0020 7800 0028 7800 0030 7A00 0000 7A00 0008 7A00 0010 7A00 0020 VP2 01C4 824C 01C4 8250 01C4 8254 01C4 8258 01C4 825C 01C4 8260 01C4 8264 01C4 8268 01C4 826C 7C00 0000 7C00 0008 7C00 0010 7C00 0020 7C00 0028 7C00 0030 7E00 0000 7E00 0008 7E00 0010 7E00 0020 ACRONYM VD_VSYNE2x VD_RELOADx VD_DISPEVTx VD_CLIPx VD_DEFVALx VD_VINTx VD_FBITx VD_VBIT1x VD_VBIT2x Y_RSCA CB_SRCA CR_SRCA Y_DSTA CB_DST CR_DST Y_SRCB CB_SRCB CR_SRCB Y_DSTB DESCRIPTION Video Display Field 2 Vertical Synchronization End Register Video Display Counter Reload Register Video Display Display Event Register Video Display Clipping Register Video Display Default Display Value Register Video Display Vertical Interrupt Register Video Display Field Bit Register Video Display Field 1Vertical Blanking Bit Register Video Display Field 2Vertical Blanking Bit Register Y FIFO Source Register A CB FIFO Source Register A CR FIFO Source Register A Y FIFO Designation Register A CB FIFO Designation Register CR FIFO Designation Register Y FIFO Source Register B CB FIFO Source Register b CR FIFO Source Register B Y FIFO Destination Register B
PRODUCT PREVIEW
Table 1-25. McASP0 Control Registers
HEX ADDRESS RANGE 01B4 C000 01B4 C004 01B4 C008 01B4 C00C 01B4 C010 01B4 C014 01B4 C018 01B4 C01C 01B4 C020 01B4 C024 - 01B4 C040 01B4 C044 01B4 C048 01B4 C04C 01B4 C050 01B4 C054 - 01B4 C05C 01B4 C060 ACRONYM PID PWRDEMU - - PFUNC PDIR PDOUT PDIN/PDSET PDCLR - GBLCTL AMUTE DLBCTL DITCTL - RGBLCTL REGISTER NAME Peripheral Identification register [Register value: 0x0010 0101] Power down and emulation management register Reserved Reserved Pin function register Pin direction register Pin data out register Pin data in / data set register Read returns: PDIN Writes affect: PDSET Pin data clear register Reserved Global control register Mute control register Digital Loop-back control register DIT mode control register Reserved Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive.
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Peripheral Register Descriptions
Table 1-25. McASP0 Control Registers (Continued)
HEX ADDRESS RANGE 01B4 C064 01B4 C068 01B4 C06C 01B4 C070 01B4 C074 01B4 C078 01B4 C07C 01B4 C080 01B4 C084 01B4 C088 01B4 C08C - 01B4 C09C 01B4 C0A0 01B4 C0A4 01B4 C0A8 01B4 C0AC 01B4 C0B0 01B4 C0B4 01B4 C0B8 01B4 C0BC 01B4 C0C0 01B4 C0C4 01B4 C0C8 01B4 C0CC 01B4 C0D0 - 01B4 C0FC 01B4 C100 01B4 C104 01B4 C108 01B4 C10C 01B4 C110 01B4 C114 01B4 C118 01B4 C11C 01B4 C120 01B4 C124 01B4 C128 01B4 C12C 01B4 C130 01B4 C134 01B4 C138 01B4 C13C 01B4 C140 ACRONYM RMASK RFMT AFSRCTL ACLKRCTL AHCLKRCTL RTDM RINTCTL RSTAT RSLOT RCLKCHK - XGBLCTL XMASK XFMT AFSXCTL ACLKXCTL AHCLKXCTL XTDM XINTCTL XSTAT XSLOT XCLKCHK XEVTCTL - DITCSRA0 DITCSRA1 DITCSRA2 DITCSRA3 DITCSRA4 DITCSRA5 DITCSRB0 DITCSRB1 DITCSRB2 DITCSRB3 DITCSRB4 DITCSRB5 DITUDRA0 DITUDRA1 DITUDRA2 DITUDRA3 DITUDRA4 REGISTER NAME Receiver format unit bit mask register Receive bit stream format register Receive frame sync control register Receive clock control register High-frequency receive clock control register Receive TDM slot 0-31 register Receiver interrupt control register Status register - Receiver Current receive TDM slot register Receiver clock check control register Reserved Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive. Transmit format unit bit mask register Transmit bit stream format register Transmit frame sync control register Transmit clock control register High-frequency Transmit clock control register Transmit TDM slot 0-31 register Transmit interrupt control register Status register - Transmitter Current transmit TDM slot Transmit clock check control register Transmitter DMA control register Reserved Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file
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PRODUCT PREVIEW
Peripheral Register Descriptions
Table 1-25. McASP0 Control Registers (Continued)
HEX ADDRESS RANGE 01B4 C144 01B4 C148 01B4 C14C 01B4 C150 01B4 C154 01B4 C158 01B4 C15C 01B4 C160 - 01B4 C17C 01B4 C180 01B4 C184 01B4 C188 01B4 C18C 01B4 C190 01B4 C194 01B4 C198 01B4 C19C 01B4 C1A0 - 01B4 C1FC 01B4 C200 01B4 C204 01B4 C208 01B4 C20C 01B4 C210 01B4 C214 01B4 C218 01B4 C21C 01B4 C220 - 01B4 C27C 01B4 C280 01B4 C284 01B4 C288 01B4 C28C 01B4 C290 01B4 C294 01B4 C298 01B4 C29C 01B4 C2A0 - 01B4 FFFF ACRONYM DITUDRA5 DITUDRB0 DITUDRB1 DITUDRB2 DITUDRB3 DITUDRB4 DITUDRB5 - SRCTL0 SRCTL1 SRCTL2 SRCTL3 SRCTL4 SRCTL5 SRCTL6 SRCTL7 - XBUF0 XBUF1 XBUF2 XBUF3 XBUF4 XBUF5 XBUF6 XBUF7 - RBUF0 RBUF1 RBUF2 RBUF3 RBUF4 RBUF5 RBUF6 RBUF7 - REGISTER NAME Left (even TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Reserved Serializer 0 control register Serializer 1 control register Serializer 2 control register Serializer 3 control register Serializer 4 control register Serializer 5 control register Serializer 6 control register Serializer 7 control register Reserved Transmit Buffer for Serializer 0 Transmit Buffer for Serializer 1 Transmit Buffer for Serializer 2 Transmit Buffer for Serializer 3 Transmit Buffer for Serializer 4 Transmit Buffer for Serializer 5 Transmit Buffer for Serializer 6 Transmit Buffer for Serializer 7 Reserved Receive Buffer for Serializer 0 Receive Buffer for Serializer 1 Receive Buffer for Serializer 2 Receive Buffer for Serializer 3 Receive Buffer for Serializer 4 Receive Buffer for Serializer 5 Receive Buffer for Serializer 6 Receive Buffer for Serializer 7 Reserved
PRODUCT PREVIEW
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Peripheral Register Descriptions
Table 1-26. McASP0 Data Registers
HEX ADDRESS RANGE 3C00 0000 - 3C0F FFFF ACRONYM RBUF/XBUFx REGISTER NAME McASPx receive buffers or McASPx transmit buffers via the Peripheral Data Bus. COMMENTS (Used when RSEL or XSEL bits = 0 [these bits are located in the RFMT or XFMT registers, respectively].)
Table 1-27. I2C0 Registers
HEX ADDRESS RANGE 01B4 0000 01B4 0004 01B4 0008 01B4 000C 01B4 0010 01B4 0014 01B4 0018 01B4 001C 01B4 0020 01B4 0024 01B4 0028 01B4 002C 01B4 0030 01B4 0034 01B4 0038 01B4 003C - 01B4 3FFF ACRONYM I2COAR0 I2CIER0 I2CSTR0 I2CCLKL0 I2CCLKH0 I2CCNT0 I2CDRR0 I2CSAR0 I2CDXR0 I2CMDR0 I2CISRC0 - I2CPSC0 I2CPID10 I2CPID20 - I2C0 own address register I2C0 interrupt enable register I2C0 interrupt status register I2C0 clock low-time divider register I2C0 clock high-time divider register I2C0 data count register I2C0 data receive register I2C0 slave address register I2C0 mode register I2C0 interrupt source register Reserved I2C0 prescaler register I2C0 Peripheral Identification register 1 [Value: 0x0000 0101] I2C0 Peripheral Identification register 2 [Value: 0x0000 0005] Reserved I2C0 data transmit register REGISTER NAME
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SPRS200B
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PRODUCT PREVIEW
EDMA Channel Synchronization Events
1.10 EDMA Channel Synchronization Events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 1-28 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels. For the DM642 device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
Table 1-28. TMS320DM642 EDMA Channel Synchronization Events
EDMA CHANNEL 0 EVENT NAME DSP_INT TINT0 TINT1 SD_INTA GPINT4/EXT_INT4 GPINT5/EXT_INT5 GPINT6/EXT_INT6 GPINT7/EXT_INT7 GPINT0 GPINT1 GPINT2 GPINT3 XEVT0 REVT0 XEVT1 REVT1 VP0EVTYA VP0EVTUA VP0EVTVA TINT2 - VP0EVTYB VP0EVTUB VP0EVTVB - AXEVTE0 AXEVTO0 AXEVT0 AREVTE0 HPI/PCI-to-DSP interrupt Timer 0 interrupt Timer 1 interrupt EMIFA SDRAM timer interrupt GP0 event 4/External interrupt pin 4 GP0 event 5/External interrupt pin 5 GP0 event 6/External interrupt pin 6 GP0 event 7/External interrupt pin 7 GP0 event 0 GP0 event 1 GP0 event 2 GP0 event 3 McBSP0 transmit event McBSP0 receive event McBSP1 transmit event McBSP1 receive event VP0 Channel A Y event DMA request VP0 Channel A Cb event DMA request VP0 Channel A Cr event DMA request Timer 2 interrupt None VP0 Channel B Y event DMA request VP0 Channel B Cb event DMA request VP0 Channel B Cr event DMA request None McASP0 transmit even event McASP0 transmit odd event McASP0 transmit event EVENT DESCRIPTION
PRODUCT PREVIEW
48
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-23 24 25 26 27-31 32 33 34 35
McASP0 receive even event In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
SPRS200B
July 2002 - Revised May 2003
EDMA Channel Synchronization Events
Table 1-28. TMS320DM642 EDMA Channel Synchronization Events (Continued)
EDMA CHANNEL 36 37 38 39 40 41 42 43 44 45 46-47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62-63 EVENT NAME AREVTO0 AREVT0 VP1EVTYB VP1EVTUB VP1EVTVB VP2EVTYB VP2EVTUB VP2EVTVB ICREVT0 ICXEVT0 - GPINT8 GPINT9 GPINT10 GPINT11 GPINT12 GPINT13 GPINT14 GPINT15 VP1EVTYA VP1EVTUA VP1EVTVA VP2EVTYA VP2EVTUA VP2EVTVA - McASP0 receive odd event McASP0 receive event VP1 Channel A Y event DMA request VP1 Channel A Cb event DMA request VP1 Channel A Cr event DMA request VP2 Channel A Y event DMA request VP2 Channel A Cb event DMA request VP2 Channel A Cr event DMA request I2C0 receive event I2C0 transmit event None GP0 event 8 GP0 event 9 GP0 event 11 GP0 event 12 GP0 event 13 GP0 event 14 GP0 event 15 VP1 Channel B Y event DMA request VP1 Channel B Cb event DMA request VP1 Channel B Cr event DMA request VP2 Channel B Y event DMA request VP2 Channel B Cb event DMA request VP2 Channel B Cr event DMA request GP0 event 10 EVENT DESCRIPTION
None In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
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PRODUCT PREVIEW
Interrupt Sources and Interrupt Selector
1.11 Interrupt Sources and Interrupt Selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 1-29. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00-INT_03) are non-maskable and fixed. The remaining interrupts (INT_04-INT_15) are maskable and default to the interrupt source specified in Table 1-29. The interrupt source for interrupts 4-15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 1-29. DM642 DSP Interrupts
CPU INTERRUPT NUMBER INT_00 INT_01 INTERRUPT SELECTOR CONTROL REGISTER - - - - MUXL[4:0] MUXL[9:5] MUXL[14:10] MUXL[20:16] MUXL[25:21] MUXL[30:26] MUXH[4:0] MUXH[9:5] MUXH[14:10] MUXH[20:16] MUXH[25:21] MUXH[30:26] - - - - - - - - - - - - - SELECTOR VALUE (BINARY) - - - - 00100 00101 00110 00111 01000 01001 00011 01010 01011 00000 00001 00010 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 INTERRUPT EVENT RESET NMI Reserved Reserved GPINT4/EXT_INT4 GPINT5/EXT_INT5 GPINT6/EXT_INT6 GPINT7/EXT_INT7 EDMA_INT EMU_DTDMA SD_INTA EMU_RTDXRX EMU_RTDXTX DSP_INT TINT0 TINT1 XINT0 RINT0 XINT1 RINT1 GPINT0 Reserved Reserved TINT2 Reserved Reserved ICINT0 Reserved EMAC_MDIO_INT Reserved. Do not use. Reserved. Do not use. GP0 interrupt 4/External interrupt pin 4 GP0 interrupt 5/External interrupt pin 5 GP0 interrupt 6/External interrupt pin 6 GP0 interrupt 7/External interrupt pin 7 EDMA channel (0 through 63) interrupt EMU DTDMA EMIFA SDRAM timer interrupt EMU real-time data exchange (RTDX) receive EMU RTDX transmit HPI/PCI-to-DSP interrupt Timer 0 interrupt Timer 1 interrupt McBSP0 transmit interrupt McBSP0 receive interrupt McBSP1 transmit interrupt McBSP1 receive interrupt GP0 interrupt 0 Reserved. Do not use. Reserved. Do not use. Timer 2 interrupt Reserved. Do not use. Reserved. Do not use. I2C0 interrupt Reserved. Do not use.
INTERRUPT SOURCE
PRODUCT PREVIEW
INT_02 INT_03 INT_04 INT_05 INT_06 INT_07 INT_08 INT_09 INT_10 INT_11 INT_12 INT_13 INT_14 INT_15 - - - - - - - - - - - - -
EMAC/MDIO interrupt Interrupts INT_00 through INT_03 are non-maskable and fixed. Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 1-29 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see the Interrupt Selector and External Interrupts chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
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SPRS200B
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Interrupt Sources and Interrupt Selector
Table 1-29. DM642 DSP Interrupts (Continued)
CPU INTERRUPT NUMBER - - - - - - INTERRUPT SELECTOR CONTROL REGISTER - - - - - - SELECTOR VALUE (BINARY) 11001 11010 11011 11100 11101 11110 - 11111 INTERRUPT EVENT VPINT0 VPINT1 VPINT2 AXINT0 ARINT0 Reserved
INTERRUPT SOURCE
VP0 interrupt VP1 interrupt VP2 interrupt McASP0 transmit interrupt McASP0 receive interrupt
Reserved. Do not use. Interrupts INT_00 through INT_03 are non-maskable and fixed. Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 1-29 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see the Interrupt Selector and External Interrupts chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
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PRODUCT PREVIEW
Signal Groups Description
1.12 Signal Groups Description
CLKIN CLKOUT4/GP0[1] CLKOUT6/GP0[2] CLKMODE1 CLKMODE0 PLLV
Clock/PLL
Reset and Interrupts
RESET NMI GP0[7]/EXT_INT7 GP0[6]/EXT_INT6 GP0[5]/EXT_INT5 GP0[4]/EXT_INT4
PRODUCT PREVIEW
TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 EMU10 EMU11
Reserved
IEEE Standard 1149.1 (JTAG) Emulation
RSV RSV RSV RSV RSV RSV
Peripheral Control/Status
PCI_EN TOUT0/MAC_EN
Control/Status
GP0[15]/PRST GP0[14]/PCLK GP0[13]/PINTA GP0[12]/PGNT GP0[11]/PREQ GP0[10]/PCBE3 GP0[9]/PIDSEL VDAC/GP0[8]/PCI66
GP0
GP0[7]/EXT_INT7 GP0[6]/EXT_INT6 GP0[5]/EXT_INT5 GP0[4]/EXT_INT4 GP0[3]/PCIEEAI CLKOUT6/GP0[2] CLKOUT4/GP0[1] GP0[0]
General-Purpose Input/Output 0 (GP0) Port These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet. These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or GPIO as input-only. These GP0 pins are muxed with the PCI peripheral pins and by default these signals are set up to no function with both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 1-5. CPU and Peripheral Signals
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SPRS200B
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Signal Groups Description
64 AED[63:0] ACE3 ACE2 ACE1 ACE0 20 AEA[22:3] ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0 Byte Enables Memory Map Space Select External Memory I/F Control Data AECLKIN AECLKOUT1 AECLKOUT2 ASDCKE AARE/ASDCAS/ASADS/ASRE AAOE/ASDRAS/ASOE AAWE/ASDWE/ASWE AARDY ASOE3 APDT
Address
Bus Arbitration
AHOLD AHOLDA ABUSREQ
EMIFA (64-bit)
Data VXCO Interpolated Control Port (VIC)
VDAC/GP0[8]/PCI66
Figure 1-6. Peripheral Signals
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PRODUCT PREVIEW
Signal Groups Description
32 HD[15:0]/AD[15:0] HD[31:16]/AD[31:16] HCNTL0/PSTOP HCNTL1/PDEVSEL
Data
HPI (Host-Port Interface) HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME
Register Select Control Half-Word Select
HHWIL/PTRDY (HPI16 ONLY)
32 HD[15:0]/AD[15:0] HD[31:16]/AD[31:16] Data/Address Clock GP0[14]/PCLK
PRODUCT PREVIEW
GP0[10]/PCBE3 HR/W/PCBE2 HDS2/PCBE1 PCBE0
Command Byte Enable
Control
GP0[9]/PIDSEL HCNTL1/PDEVSEL HINT/PFRAME GP0[13]/PINTA HAS/PPAR GP0[15]/PRST HRDY/PIRDY HCNTL0/PSTOP HHWIL/PTRDY
GP0[12]/PGNT GP0[11]/PREQ
Arbitration Error
HDS1/PSERR HCS/PPERR
Serial EEPROM PCI Interface
XSP_DO/MDIO XSP_CS XSP_CLK/MDCLK XSP_DI
These HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For more details on these muxed pins, see the Device Configurations section of this data sheet. These PCI pins (excluding PCBE0 and XSP_CS) are muxed with the HPI or MDIO or GP0 peripherals. By default, these signals function as HPI and no function, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet. These HPI/PCI data pins (HD[31:16/AD[31:16]) are muxed with the EMAC peripheral. By default, these pins function as HPI. For more details on the EMAC pin functions, see the Ethernet MAC (EMAC) peripheral signals section and the terminal functions table portions of this data sheet.
Figure 1-6. Peripheral Signals (Continued)
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Signal Groups Description
McBSP1 VP1D[2]/CLKX1 VP1D[3]/FSX1 VP1D[4]/DX1 VP1D[8]/CLKR1 VP1D[7]/FSR1 VP1D[6]/DR1 VP1D[5]/CLKS1 Transmit
McBSP0 Transmit VP0D[2]/CLKX0 VP0D[3]/FSX0 VP0D[4]/DX0 VP0D[8]/CLKR0 VP0D[7]/FSR0 VP0D[6]/DR0 VP0D[5]/CLKS0
Receive
Receive
Clock
Clock
McBSPs (Multichannel Buffered Serial Ports)
TOUT1/LENDIAN TINP1
Timer 1
Timer 0
TOUT0/MACEN TINP0
Timer 2 Timers
I2C0
SCL0 SDA0
I2C0 These McBSP1 and McBSP0 pins are muxed with the Video Port 1 (VP1) and Video Port 0 (VP0) peripherals, respectively. By default, these signals function as VP1 and VP0, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 1-6. Peripheral Signals (Continued)
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Signal Groups Description
EMAC HD16/AD16/MTXD0 HD17/AD17/MTXD1 HD18/AD18/MTXD2 HD19/AD19/MTXD3 HD24/AD24/MRXD0 HD25/AD25/MRXD1 HD26/AD26/MRXD2 HD27/AD27/MRXD3 HD20/AD20/MTXEN HD29/AD29/MRXER HD28/AD28/MRXDV HD21/AD21/MCOL HD30/AD30/MCRS
Transmit MDIO
Receive
Input/Output
XSP_DO/MDIO
Error Detect and Control
Clock
XSP_CLK/MDCLK
PRODUCT PREVIEW
HD22/AD22/MTCLK HD31/AD31/MRCLK
Clocks Ethernet MAC (EMAC) and MDIO
These EMAC pins are muxed with the upper data pins of the HPI or PCI peripherals. By default, these signals function as HPI. For more details on these muxed pins, see the Device Configurations section of this data sheet. These MDIO pins are muxed with the PCI peripherals. By default, these signals function as PCI. For more details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 1-6. Peripheral Signals (Continued)
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Signal Groups Description
STCLK VP0CLK0 VP0CLK1 VP0CTL0 VP0CTL1 VP0CTL2
Timing and Control Logic
VP0D[0] VP0D[1] VP0D[2]/CLKX0 VP0D[3]/FSX0 VP0D[4]/DX0 VP0D[5]/CLKS0 VP0D[6]/DR0 VP0D[7]/FSR0 VP0D[8]/CLKR0 VP0D[9]
Capture/Display Buffer (2560 Bytes)
VP0D[10] VP0D[11] VP0D[12]/ACLKR0 VP0D[13]/AFSR0 VP0D[14]/AHCLKR0 VP0D[15]/AMUTEIN0 VP0D[16]/AMUTE0 VP0D[17]/ACLKX0 VP0D[18]/AFSX0 VP0D[19]/AHCLKX0 Channel A
Capture/Display Buffer (2560 Bytes)
Channel B uses only the VP0D[19:10] bidirectional pins
Channel B
Video Port 0 (VP0) Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit), TSI (8-bit) capture pipeline modes and BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display pipeline modes. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture pipeline modes and can display synchronized RAW Video data with Channel A. The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).
Figure 1-6. Peripheral Signals (Continued)
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Signal Groups Description
STCLK VP1CLK0 VP1CLK1 VP1CTL0 VP1CTL1 VP1CTL2
Timing and Control Logic
VP1D[0] VP1D[1] VP1D[2]/CLKX1 VP1D[3]/FSX1 VP1D[4]/DX1 VP1D[5]/CLKS1 VP1D[6]/DR1 VP1D[7]/FSR1 VP1D[8]/CLKR1 VP1D[9]
Capture/Display Buffer (2560 Bytes)
VP1D[10] VP1D[11] VP1D[12]/AXR0[0] VP1D[13]/AXR0[1] VP1D[14]/AXR0[2] VP1D[15]/AXR0[3] VP1D[16]/AXR0[4] VP1D[17]/AXR0[5] VP1D[18]/AXR0[6] VP1D[19]/AXR0[7] Channel A
PRODUCT PREVIEW
Capture/Display Buffer (2560 Bytes)
Channel B uses only the VP1D[19:10] bidirectional pins
Channel B
Video Port 1 (VP1) Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit), TSI (8-bit) capture pipeline modes and BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display pipeline modes. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture pipeline modes and can display synchronized RAW Video data with Channel A. The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).
Figure 1-6. Peripheral Signals (Continued)
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Signal Groups Description
STCLK VP2CLK0 VP2CLK1 VP2CTL0 VP2CTL1 VP2CTL2
Timing and Control Logic
VP2D[0] VP2D[1] VP2D[2] VP2D[3] VP2D[4] VP2D[5] VP2D[6] VP2D[7] VP2D[8] VP2D[9]
Capture/Display Buffer (2560 Bytes)
VP2D[10] VP2D[11] VP2D[12] VP2D[13] VP2D[14] VP2D[15] VP2D[16] VP2D[17] VP2D[18] VP2D[19] Channel A
Capture/Display Buffer (2560 Bytes)
Channel B uses only the VP2D[19:10] bidirectional pins
Channel B
Video Port 2 (VP2) Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit), TSI (8-bit) capture pipeline modes and BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display pipeline modes. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture pipeline modes and can display synchronized RAW Video data with Channel A. The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).
Figure 1-6. Peripheral Signals (Continued)
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Signal Groups Description
(Transmit/Receive Data Pins) VP1D[12]/AXR0[0] VP1D[13]/AXR0[1] VP1D[14]/AXR0[2] VP1D[15]/AXR0[3] 8-Serial Ports Flexible Partitioning Tx, Rx, OFF
(Transmit/Receive Data Pins) VP1D[16]/AXR0[4] VP1D[17]/AXR0[5] VP1D[18]/AXR0[6] VP1D[19]/AXR0[7]
(Receive Bit Clock) VP0D[12]/ACLKR0 VP0D[14]/AHCLKR0 (Receive Master Clock) Transmit Clock Check Circuit Receive Clock Generator Transmit Clock Generator
(Transmit Bit Clock) VP0D[17]/ACLKX0 VP0D[19]/AHCLKX0 (Transmit Master Clock)
PRODUCT PREVIEW
Receive Clock Check Circuit
VP0D[13]/AFSR0 (Receive Frame Sync or Left/Right Clock)
Receive Frame Sync
Transmit Frame Sync
VP0D[18]/AFSX0 (Transmit Frame Sync or Left/Right Clock) VP0D[16]/AMUTE0 VP0D[15]/AMUTEIN0
Error Detect (see Note A)
Auto Mute Logic
McASP0 (Multichannel Audio Serial Port 0)
NOTES: A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 1-6. Peripheral Signals (Continued)
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Device Configurations
2
Device Configurations
On the DM642 device, bootmode and certain device configurations/peripheral selections are determined at device reset, while other device configurations/peripheral selections are software-configurable via the peripheral configurations register (PERCFG) [address location 0x01B3F000] after device reset.
2.1
Peripheral Selection at Device Reset
Some DM642 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose input/output pins GP0[15:9], PCI and its internal EEPROM, EMAC, MDIO, and VIC). Other DM642 peripherals (i.e., the Timers, I2C0, and the GP0[7:0] pins), are always available.
*
HPI, GP0[15:9], PCI, EEPROM (internal to PCI), EMAC, and VIC peripherals The PCI_EN and MAC_EN pins are latched at reset. They determine specific peripheral selection, summarized in Table 2-1.
Table 2-1. PCI_EN, HD5, and MAC_EN Peripheral Selection (HPI, GP0[15:9], PCI, EMAC, MDIO, and VIC)
PERIPHERAL SELECTION PCI_EN Pin [E2] 0 0 0 0 1 PCI_EEAI Pin [L5] 0 0 0 0 1 HD5 Pin [Y1] 0 0 1 1 X MAC_EN Pin [C5] 0 1 0 1 X HPI Data Lower Disabled Disabled HPI Data Upper Hi-Z Hi-Z PERIPHERALS SELECTED 32-Bit PCI Disabled Disabled Disabled Disabled EEPROM (Internal to PCI) Disabled Disabled Disabled Disabled EMAC and MDIO Disabled Disabled Disabled GP0[15:9] Disabled
*
If the PCI is disabled (PCI_EN = 0), the HPI peripheral is enabled and based on the HD5 and MAC_EN pin configuration at reset, HPI16 mode or EMAC and MDIO can be selected. When the PCI is disabled (PCI_EN = 0), the GP0[15:9] pins can also be programmed as GPIO, provided the GPxEN and GPxDIR bits are properly configured. This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI pins (PCBE0 and XSP_CS) are tied-off (Hi-Z). Also, the multiplexed GP0/PCI pins can be used as GPIO with the proper software configuration of the GPIO enable and direction registers (for more details, see Table 2-9).
*
If the PCI is enabled (PCI_EN = 1), the HPI peripheral is disabled. This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed GP0/PCI pins function as PCI pins (for more details, see Table 2-9).
* *
The MAC_EN pin, in combination with the PCI_EN and HD5 pins, controls the selection of the EMAC and MDIO peripherals (for more details, see Table 2-2). The PCI_EN pin (= 1) and the PCI_EEAI pin control the whether the PCI initializes its internal registers via external EEPROM (PCI_EEAI = 1) or if the internal default values are used instead (PCI_EEAI = 0).
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Table 2-2. HPI vs. EMAC Peripheral Pin Selection
CONFIGURATION SELECTION GP0[0] Pin [M5] 0 0 0 0 HD5 Pin [Y1] 0 0 1 1 MAC_EN Pin [C5] 0 1 0 1 Hi-Z HD[15:0] HPI16 HPI16 HPI32 (HD[31:0]) used for EMAC PERIPHERALS SELECTED HD[31:16] Hi-Z used for EMAC
2.2
Device Configuration at Device Reset
Table 2-3 describes the DM642 device configuration pins, which are set up via external pullup/pulldown resistors through the specified EMIFA address bus pins (AEA[22:19]), and the TOUT1/LENDIAN, GP0[3]/PCIEEAI, and the HD5 pins (all of which are latched during device reset).
Table 2-3. DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI, and HD5)
PRODUCT PREVIEW
CONFIGURATION PIN TOUT1/LENDIAN
NO.
FUNCTIONAL DESCRIPTION Device Endian mode (LEND) 0 - System operates in Big Endian mode 1 - System operates in Little Endian mode (default) Bootmode [1:0] 00 - No boot (default mode) 01 - HPI/PCI boot (based on PCI_EN pin) 10 - Reserved 11 - EMIFA boot EMIFA input clock select Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 - AECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved PCI EEPROM Auto-Initialization (PCIEEAI) PCI auto-initialization via external EEPROM 0 - PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified PCI default values (default). 1 - PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1). Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. For more information on the PCI EEPROM default values, see the PCI chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). HPI peripheral bus width (HPI_WIDTH) 0 - HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state.) 1 - HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) (Also see the PCI_EN; TOUT0/MAC_EN functional description in this table)
B5
AEA[22:21]
[U23, V24]
AEA[20:19]
[V25, V26]
GP0[3]/PCIEEAI
L5
HD5/AD5
Y1
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Table 2-3. DM642 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI, and HD5) (Continued)
CONFIGURATION PIN NO. Peripheral Selection PCI_EN; TOUT0/MAC_EN [E2; C5] 00 01 10 11 - - - - HPI (default mode) [HPI32, if HD5 = 1; HPI16 if HD5 = 0 EMAC and MDIO; HPI16, if HD5 = 0; HPI disabled, if HD5 = 1 PCI Reserved FUNCTIONAL DESCRIPTION
2.3
Peripheral Selection After Device Reset
Video Ports, McBSP1, McBSP0, McASP0 and I2C0 The DM642 device has designated registers for peripheral configuration (PERCFG), device status (DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration module and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these registers via the CFGBUS. The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the Video Ports (VP0, VP1, VP2) McBSP0, McBSP1, McASP0, and I2C0 peripherals. For more detailed information on the PERCFG register control bits, see Figure 2-1 and Table 2-4.
31 Reserved R-0 23 Reserved R-0 15 Reserved R-0 7 Reserved R-0 6 VP2EN R/W-0 5 VP1EN R/W-0 4 VP0EN R/W-0 3 I2C0EN R/W-0 2 MCBSP1EN R/W-1 1 MCBSP0EN R/W-1 0
24
16
8
MCASP0EN R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 2-1. Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 - 0x01B3F003]
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Table 2-4. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions
BIT 31:7 NAME Reserved Reserved. Read-only, writes have no effect. VP2 Enable bit. Determines whether the VP2 peripheral is enabled or disabled. (This feature allows power savings by disabling the peripheral when not in use.) 0 = VP2 is disabled, and the module is powered down (default). 1 = VP2 is enabled. VP1 Enable bit. Determines whether the VP1 peripheral is enabled or disabled. 0 = VP1 is disabled, and the module is powered down (default). (This feature allows power savings by disabling the peripheral when not in use.) 1 = VP1 is enabled . VP0 Enable bit. Determines whether the VP0 peripheral is enabled or disabled. 0 = VP0 is disabled, and the module is powered down (default). (This feature allows power savings by disabling the peripheral when not in use.) 1 = VP0 is enabled. Inter-integrated circuit 0 (I2C0) enable bit. Selects whether I2C0 peripheral is enabled or disabled (default). 0 = I2C0 is disabled, and the module is powered down (default). 1 = I2C0 is enabled. Video Port 1 (VP1) lower data pins vs. McBSP1 enable bit. Selects whether VP1 peripheral lower-data pins or the McBSP1 peripheral is enabled. 0 = VP1 lower-data pins are enabled and function (if VP1EN=1), McBSP1 is disabled; the remaining VP1 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit settings. 1 = McBSP1 is enabled, VP1 lower-data pin functions are disabled (default). Video Port 0 (VP0) lower data pins vs. McBSP0 enable bit. Selects whether VP0 peripheral lower-data pins or the McBSP1 peripheral is enabled. 0 = VP0 lower-data pins are enabled and function (if VP0EN=1), McBSP0 is disabled; the remaining VP0 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit settings. 1 = McBSP0 is enabled, VP0 lower-data pin functions are disabled (default). McASP0 vs. VP0/VP1 upper-data pins select bit. Selects whether the McASP0 peripheral or the VP0 and VP1 upper-data pins are enabled. 0 = McASP0 is disabled; VP0 and VP1 upper-data pins are enabled; and the VP0 and VP1 lower-data pins are dependent on the MCBSP0EN and VP0EN, and MCSBP1EN and VP1EN bits, respectively. 1 = McASP0 is enabled; VP0 and VP1 upper-data pins are disabled; and the VP0 and VP1 lower-data pins are dependent on the MCBSP0EN and VP0EN, and MCSBP1EN and VP1EN bits, respectively. DESCRIPTION
6
VP2EN
5
VP1EN
4
VP0EN
PRODUCT PREVIEW
3
I2C0EN
2
MCBSP1EN
1
MCBSP0EN
0
MCASP0EN
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2.3.1 Peripheral Configuration Lock
By default, the McASP0, VP0, VP1, VP2, and I2C peripherals are disabled on power up. In order to use these peripherals on the DM642 device, the peripheral must first be enabled in the Peripheral Configuration register (PERCFG). Software muxed pins should not be programmed to switch functionalities during run-time. Care should also be taken to ensure that no accesses are being performed before disabling the peripherals. To help minimize power consumption in the DM642 device, unused peripherals may be disabled. Figure 2-2 shows the flow needed to enable (or disable) a given peripheral on the DM642 device.
Unlock the PERCFG Register Using the PCFGLOCK Register
Write to PERCFG Register to Enable/Disable Peripherals
Read from PERCFG Register
Wait 128 CPU Cycles Before Accessing Enabled Peripherals
Figure 2-2. Peripheral Enable/Disable Flow Diagram
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A 32-bit key (value = 0x10C0010C) must be written to the Peripheral Configuration Lock register (PCFGLOCK) in order to unlock access to the PERCFG register. Reading the PCFGLOCK register determines whether the PERCFG register is currently locked (LOCKSTAT bit = 1) or unlocked (LOCKSTAT bit = 0), see Figure 2-3. A peripheral can only be enabled when the PERCFG register is "unlocked" (LOCKSTAT bit = 0). Read Accesses
31 Reserved R-0 1 0 LOCKSTAT R-1
Write Accesses
31 LOCK W-0 0
PRODUCT PREVIEW
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 2-3. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] - Read/Write Accesses Table 2-5. PCFGLOCK Register Selection Bit Descriptions - Read Accesses
BIT 31:1 NAME Reserved Reserved. Read-only, writes have no effect. Lock status bit. Determines whether the PERCFG register is locked or unlocked. 0 = Unlocked, read accesses to the PERCFG register allowed. 1 = Locked, write accesses to the PERCFG register do not modify the register state [default]. Reads are unaffected by Lock Status. DESCRIPTION
0
LOCKSTAT
Table 2-6. PCFGLOCK Register Selection Bit Descriptions - Write Accesses
BIT 31:0 NAME LOCK DESCRIPTION Lock bits. 0x10C0010C = Unlocks PERCFG register accesses.
Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the PERCFG register with the necessary enable bits set. Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation between the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the PERCFG register after the write is issued forces the CPU to wait for the write to the PERCFG register to occur. Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128 CPU cycles before accessing the enabled peripheral. The user must ensure that no accesses are performed to a peripheral while it is disabled.
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2.3.2 Device Status Register Description
The device status register depicts the status of the device peripheral selection. For the actual register bit names and their associated bit field descriptions, see Figure 2-4 and Table 2-7.
31 Reserved R-0 23 Reserved R-0 15 14 Reserved R-0 7 Reserved R-x 6 CLKMODE1 R-x 5 CLKMODE0 R-x 4 LENDIAN R-x 13 12 11 MAC_EN R-x 3 BOOTMODE1 R-x 10 HPI_WIDTH R-x 2 BOOTMODE0 R-x 9 PCI_EEAI R-x 1 AECLKINSEL1 R-x 8 PCI_EN R-x 0 AECLKINSEL0 R-x 16 24
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 2-4. Device Status Register (DEVSTAT) Description - 0x01B3 F004 Table 2-7. Device Status (DEVSTAT) Register Selection Bit Descriptions
BIT 31:12 NAME Reserved Reserved. Read-only, writes have no effect. EMAC enable bit. Shows the status of whether EMAC peripheral is enabled or disabled (default). 0 = EMAC is disabled, and the module is powered down (default). 1 = EMAC is enabled. This bit has no effect if the PCI peripheral is enabled (PCI_EN = 1). HPI bus width control bit. Shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode (default). 0 = HPI operates in 16-bit mode. (default). 1 = HPI operates in 32-bit mode. PCI EEPROM auto-initialization bit (PCI auto-initialization via external EEPROM). Shows the status of whether the PCI module initializes internal registers via external EEPROM or if the internal PCI default values are used instead (default). 9 PCI_EEAI 0 = PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified PCI default values (default). 1 = PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1). PCI enable bit. Shows the status of whether the EMAC peripheral is enabled or disabled (default). 0 = PCI disabled. (default). 1 = PCI enabled. Global select for the PCI vs. HPI/EMAC/MDIO/GPIO peripherals. 7 Reserved Reserved. Read-only, writes have no effect. DESCRIPTION
11
MAC_EN
10
HPI_WIDTH
8
PCI_EN
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Device Configurations
Table 2-7. Device Status (DEVSTAT) Register Selection Bit Descriptions (Continued)
BIT NAME DESCRIPTION Clock mode select bits Shows the status of whether the CPU clock frequency equals the input clock frequency X1 (Bypass), x6, or x12. Clock mode select for CPU clock frequency (CLKMODE[1:0]) 00 - Bypass (x1) (default mode) 01 - x6 10 - x12 11 - Reserved For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. Device Endian mode (LEND) Shows the status of whether the system is operating in Big Endian mode or Little Endian mode (default). 0 - System is operating in Big Endian mode 1 - System is operating in Little Endian mode (default) Bootmode configuration bits Shows the status of what device bootmode configuration is operational. Bootmode [1:0] 00 - No boot (default mode) 01 - HPI/PCI boot (based on PCI_EN pin) 10 - Reserved 11 - EMIFA boot EMIFA input clock select Shows the status of what clock mode is enabled or disabled for the EMIF. Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 - AECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved
6
CLKMODE1
5
CLKMODE0
4
LENDIAN
3
BOOTMODE1
PRODUCT PREVIEW
2
BOOTMODE0
1
AECLKINSEL1
0
AECLKINSEL0
2.3.3 JTAG ID Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the DM642 device, the JTAG ID register resides at address location 0x01B3 F004. The register hex value for the DM642 device is: 0x0007 902F. For the actual register bit names and their associated bit field descriptions, see Figure 2-5 and Table 2-8.
31-28 VARIANT (4-Bit) R-0000 27-12 PART NUMBER (16-Bit) R-0000 0000 0111 1001 11-1 MANUFACTURER (11-Bit) R-0000 0010 111 0 LSB R-1
Legend: R = Read only; -n = value after reset
Figure 2-5. JTAG ID Register Description - TMS320DM642 Register Value - 0x0007 902F Table 2-8. JTAG ID Register Selection Bit Descriptions
BIT 31:28 27:12 11-1 0 NAME VARIANT PART NUMBER MANUFACTURER LSB Variant (4-Bit) value. DM642 value: 0000. Part Number (16-Bit) value. DM642 value: 0000 0000 0111 1001. Manufacturer (11-Bit) value. DM642 value: 0000 0010 111. LSB. This bit is read as a "1" for DM642. DESCRIPTION
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2.4
Multiplexed Pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some of these pins are configured by software, and the others are configured by external pullup/pulldown resistors only at reset. Those muxed pins that are configured by software should not be programmed to switch functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 2-9 identifies the multiplexed pins on the DM642 device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed functions.
2.5
Debugging Considerations
It is recommended that external connections be provided to device configuration pins, including AEA[22:19], HD5/AD5, PCI_EN, and TOUT0/MAC_EN. Although internal pullup/pulldown resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the AEA bus (AEA[18:0]). Do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
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Device Configurations
Table 2-9. DM642 Device Multiplexed Pins
MULTIPLEXED PINS NAME NO. DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION These pins are software-configurable. To use these pins as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output To use the PCI auto-initialization EEPROM (PCIEEAI) the PCI needs to be enabled (PCI_EN = 1): 0 - PCI auto-init through EEPROM disabled (default). 1 - PCI auto-init through EEPROM is enabled. GP0[3]/PCIEEAI L5 PCIEEAI GP3EN = 0 (disabled) To use GP0[3] as a GPIO pin, the PCI needs to be disabled (PCI_EN = 0), the GP3EN bits in the GPIO Enable Register and the GP3DIR bits in the GPIO Direction Register must be properly configured. GP3EN = 1: GP3 pin enabled GP3DIR = 0: GP3 pin is an input GP3DIR = 1: GP3 pin is an output The VDAC output pin function is default. To use GP0[8] as a GPIO pin, the PCI needs to be disabled (PCI_EN = 0), the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GP8EN = 1: GP8 pin enabled GP8DIR = 0: GP8 pin is an input GP8DIR = 1: GP8 pin is an output To use the PCI66 pin function, which changes the PCI operating frequency selection, the PCI needs to be enabled (PCI_EN = 1): 0 - PCI operates at 66 MHz (default). 1 - PCI operates at 33 MHz. To use GP0[15:9] as GPIO pins, the PCI needs to be disabled (PCI_EN = 0), the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output
CLKOUT4/GP0[1]
D6
CLKOUT4
GP1EN = 0 (disabled)
CLKOUT6/GP0[2]
C6
CLKOUT6
GP2EN = 0 (disabled)
PRODUCT PREVIEW
VDAC/GP0[8]/PCI66
AD1
PCI66
GP8EN = 0 (disabled) MAC_EN = 0 (disabled)
GP0[9]/PIDSEL GP0[10]/PCBE3 GP0[11]/PREQ GP0[12]/PGNT GP0[13]/PINTA GP0[14]/PCLK GP0[15]/PRST VP1D[19]/AXR0[7] VP1D[18]/AXR0[6] VP1D[17]/AXR0[5] VP1D[16]/AXR0[4] VP1D[15]/AXR0[3] VP1D[14]/AXR0[2] VP1D[13]/AXR0[1]
K3 J2 F1 H4 G4 C1 G3 AB12 AB11 AC11 AD11 AE11 AC10 AD10 None VP1EN bit = 0 (disabled) MCASP0EN bit = 0 (disabled) By default, no function is enabled upon reset. To enable the Video Port 1 data pins, the VP1EN bit in the PERCFG register must be set to a 1. (McASP0 data pins are disabled). To enable the McASP0[7:0] data pins, the MCASP0EN bit in the PERCFG register must be set to a 1. (VP1 upper data pins are disabled). None GPxEN = 0 (disabled) PCI_EN = 0 (disabled)
VP1D[12]/AXR0[0] AC9 All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0]. For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
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Table 2-9. DM642 Device Multiplexed Pins (Continued)
MULTIPLEXED PINS NAME VP1D[8]/CLKR1 VP1D[7]/FSR1 VP1D[6]/DR1 VP1D[5]/CLKS1 VP1D[4]/DX1 VP1D[3]/FSX1 VP1D[2]/CLKX1 VP0D[19]/AHCLKX0 VP0D[18]/AFSX0 VP0D[17]/ACLKX0 VP0D[16]/AMUTE0 VP0D[15]/AMUTEIN0 VP0D[14]/AHCLKR0 VP0D[13]/AFSR0 VP0D[12]/ACLKR0 VP0D[8]/CLKR0 VP0D[7]/FSR0 VP0D[6]/DR0 VP0D[5]/CLKS0 VP0D[4]/DX0 VP0D[3]/FSX0 VP0D[2]/CLKX0 NO. AD8 AC7 AD7 AE7 AC6 AD6 AE6 AC12 AD12 AB13 AC13 AD13 AB14 AC14 AD14 AE15 AB16 AC16 AD16 AE16 AF16 AF17 By default, no functions enabled upon reset (PCI is disabled). To enable the PCI peripheral, an external pullup resistor (1 k) must be provided on the PCI_EN pin (setting PCI_EN = 1 at reset) To enable the MDIO peripheral (which also enables the EMAC peripheral), an external pullup resistor (1 k) must be provided on the MAC_EN pin (setting MAC_EN = 1 at reset) None VP0EN bit = 0 (disabled) MCBSP0EN bit = 1 (enabled) By default, the McBSP0 peripheral function is enabled upon reset (MCBSP0EN bit = 1). To enable the Video Port 0 data pins, the VP0EN bit in the PERCFG register must be set to a 1. None VP0EN bit = 0 (disabled) MCASP0EN bit = 0 (disabled) By default, no function is enabled upon reset. To enable the Video Port 0 data pins, the VP0EN bit in the PERCFG register must be set to a 1. (McASP0 control pins are disabled). To enable the McASP0 control pins, the MCASP0EN bit in the PERCFG register must be set to a 1. (VP0 upper data pins are disabled). McBSP1 functions VP1EN bit = 0 (disabled) MCBSP1EN bit = 1 (enabled) By default, the McBSP1 peripheral, function is enabled upon reset (MCBSP1EN bit = 1). To enable the Video Port 1 data pins, the VP1EN bit in the PERCFG register must be set to a 1. DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION
XSP_CLK/MDCLK
R5 None PCI_EN = 0 (disabled) MAC_EN = 0 (disabled)
XSP_DO/MDIO
P5
HAS/PPAR HCNTL1/PDEVSEL HCNTL0/PSTOP HDS1/PSERR HDS2/PCBE1 HR/W/PCBE2 HHWIL/PTRDY HINT/PFRAME HCS/PPERR
P3 P1 R3 R2 T2 M1 N3 N4 R1
HAS HCNTL1 HCNTL0 HDS1 HDS2 HR/W HHWIL (HPI16 only) HINT HCS PCI_EN = 0 (disabled) By default, HPI is enabled upon reset (PCI is disabled). To enable the PCI peripheral, an external pullup resistor (1 k) must be provided on the PCI_EN pin (setting PCI_EN = 1 at reset).
HRDY/PIRDY N1 HRDY All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0]. For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
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Configuration Examples
Table 2-9. DM642 Device Multiplexed Pins (Continued)
MULTIPLEXED PINS NAME NO. DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION By default, HPI is enabled upon reset (PCI is disabled). To enable the PCI peripheral, an external pullup resistor (1 k) must be provided on the PCI_EN pin (setting PCI_EN = 1 at reset).
HD[23,15:0]/AD[23,15:0]
HD[23, 15:0]
PCI_EN = 0 (disabled)
HD31/AD31/MRCLK HD30/AD30/MCRS HD29/AD29/MRXER HD28/AD28/MRXDV HD27/AD27/MRXD3 HD26/AD26/MRXD2 HD25/AD25/MRXD1 HD24/AD24/MRXD0 HD22/AD22/MTCLK HD21/AD21/MCOL
G1 H3 G2 J4 H2 J3 J1 K4 L4 K2 L3 L2 M4 M2
HD31 HD30 HD29 HD28 HD27 HD26 HD25 HD24 HD22 HD21 HD20 HD19 HD18 HD17 PCI_EN = 0 (disabled) MAC_EN = 0 (disabled) By default, HPI is enabled upon reset (PCI is disabled). To enable the PCI peripheral, an external pullup resistor (1 k) must be provided on the PCI_EN pin (setting PCI_EN = 1 at reset). To enable the EMAC peripheral, an external pullup resistor (1 k) must be provided on the MAC_EN pin (setting MAC_EN = 1 at reset).
PRODUCT PREVIEW
HD20/AD20/MTXEN HD19/AD19/MTXD3 HD18/AD18/MTXD2 HD17/AD17/MTXD1
HD16/AD16/MTXD0 M3 HD16 All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0]. For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
2.6
Configuration Examples
Figure 2-6 through Figure 2-8 illustrate examples of peripheral selections that are configurable on the DM642 device.
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Configuration Examples
64 AED[63:0] PCI EMIFA AECLKIN, AARDY, AHOLD AEA[22:3], ACE[3:0], ABE[7:0], AECLKOUT1, AECLKOUT2, ASDCKE, ASOE3, APDT, AHOLDA, ABUSREQ, AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, AAWE/ASDWE/ASWE CLKIN, CLKMODE0, CLKMODE1 EMAC MRXD[3:0], MRXER, MRXDV, MCOL, MCRS, MTCLK, MRCLK MDIO, MDCLK MDIO TIMER1 TOUT1/LENDIAN STCLK VP0CLK0 VP0CLK1, VP0CTL[2:0], VP0D[19:0] VP0 (20-Bit) TIMER0 TOUT0/MACEN TIMER2 CLKOUT4, CLKOUT6, PLLV
HD[15:0] HRDY, HINT HCNTL0, HCNTL1, HHWIL, HAS, HR/W, HCS, HDS1, HDS2 MTXD[3:0], MTXEN
16 HPI (16-Bit)
Clock and System
TINP1
TINP0
McBSP0
GP0 and EXT_INT
GP0[15:9, 3:0] GP0[7:4]
McASP0 Control I2C0 McASP0 Data
SCL0 SDA0
McBSP1
VIC
VDAC/GP0[8]/PCI66
STCLK VP1CLK0 VP1CLK1, VP1CTL[2:0], VP1D[19:0] VP1 (20-Bit) VP2 (20-Bit)
STCLK VP2CLK0 VP2CLK1, VP2CTL[2:0], VP2D[19:0]
Shading denotes a peripheral module not available for this configuration. STCLK supports all three video ports (VP2, VP1, and VP0). PERCFG Register Value: External Pins: 0x0000 0078 PCI_EN = 0 GP0[3]/PCIEEAI = 0 HD5 = 0 TOUT0/MAC_EN = 1
Figure 2-6. Configuration Example A (3 20-Bit Video Ports + HPI + EMAC + MDIO + I2C0 + EMIF + 3 Timers)
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Configuration Examples
64 AED[63:0] PCI EMIFA AECLKIN, AARDY, AHOLD AEA[22:3], ACE[3:0], ABE[7:0], AECLKOUT1, AECLKOUT2, ASDCKE, ASOE3, APDT, AHOLDA, ABUSREQ, AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, AAWE/ASDWE/ASWE CLKIN, CLKMODE0, CLKMODE1 EMAC MRXD[3:0], MRXER, MRXDV, MCOL, MCRS, MTCLK, MRCLK MDIO, MDCLK MDIO TIMER1 TOUT1/LENDIAN TIMER2 CLKOUT4, CLKOUT6, PLLV
HD[15:0] HRDY, HINT HCNTL0, HCNTL1, HHWIL, HAS, HR/W, HCS, HDS1, HDS2 MTXD[3:0], MTXEN
16 HPI (16-Bit)
Clock and System
TINP1
PRODUCT PREVIEW
STCLK VP0CLK0 VP0CLK1, VP0CTL[2:0], VP0D[19:10] CLKR0, FSR0, DR0, CLKS0, DX0, FSX0, CLKX0 VP0 (10-Bit) TIMER0
TINP0 TOUT0/MACEN
McBSP0
GP0 and EXT_INT
GP0[15:9, 3:0] GP0[7:4]
McASP0 Control I2C0 McASP0 Data
SCL0 SDA0
CLKR1, FSR1, DR1, CLKS1, DX1, FSX1, CLKX1 STCLK VP1CLK0 VP1CLK1, VP1CTL[2:0], VP1D[19:10]
McBSP1
VIC
VDAC/GP0[8]/PCI66
STCLK VP1 (10-Bit) VP2 (20-Bit) VP2CLK0 VP2CLK1, VP2CTL[2:0], VP2D[19:0]
Shading denotes a peripheral module not available for this configuration. STCLK supports all three video ports (VP2, VP1, and VP0) PERCFG Register Value: Extenal Pins: 0x0000 007E PCI_EN = 0 GP0[3]/PCIEEAI = 0 HD5 = 0 TOUT0/MAC_EN = 1
Figure 2-7. Configuration Example B (2 10-Bit Video Ports + 2 McBSPs + EMAC + MDIO + I2C0 + EMIF) [Possible Video IP Phone Application]
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Configuration Examples
64 AED[63:0] PCI EMIFA AECLKIN, AARDY, AHOLD AEA[22:3], ACE[3:0], ABE[7:0], AECLKOUT1, AECLKOUT2, ASDCKE, ASOE3, APDT, AHOLDA, ABUSREQ, AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, AAWE/ASDWE/ASWE CLKIN, CLKMODE0, CLKMODE1 EMAC MRXD[3:0], MRXER, MRXDV, MCOL, MCRS, MTCLK, MRCLK MDIO, MDCLK MDIO TIMER1 TOUT1/LENDIAN STCLK VP0CLK0 VP0CLK1, VP0CTL[2:0], VP0D[9:0] VP0 (10-Bit) TIMER0 TOUT0/MACEN TIMER2 CLKOUT4, CLKOUT6, PLLV
HD[15:0] HRDY, HINT HCNTL0, HCNTL1, HHWIL, HAS, HR/W, HCS, HDS1, HDS2 MTXD[3:0], MTXEN
16 HPI (16-Bit)
Clock and System
TINP1
TINP0
McBSP0 AHCLKX0, AFSX0, ACLKX0, AMUTE0, AMUTEIN0, AHCLKR0, AFSR0, ACLKR0 AXR0[7:0]
GP0 and EXT_INT
GP0[15:9, 3:0] GP0[7:4]
McASP0 Control I2C0 McASP0 Data
SCL0 SDA0
McBSP1
VIC
VDAC/GP0[8]/PCI66
STCLK VP1CLK0 VP1CLK1, VP1CTL[2:0], VP1D[9:0] VP1 (10-Bit) VP2 (20-Bit)
STCLK VP2CLK0 VP2CLK1, VP2CTL[2:0], VP2D[19:0]
Shading denotes a peripheral module not available for this configuration. STCLK supports all three video ports (VP2, VP1, and VP0). PERCFG Register Value: Extenal Pins: 0x0000 0079 PCI_EN = 0 GP0[3]/PCIEEAI = 0 HD5 = 0 TOUT0/MAC_EN = 1
Figure 2-8. Configuration Example C (2 10-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF) [Possible Set-Top Box Application]
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Terminal Functions
2.7
Terminal Functions
The terminal functions table (Table 2-10) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configurations section of this data sheet.
PRODUCT PREVIEW
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Table 2-10. Terminal Functions
SIGNAL NAME NO. TYPE IPD/ IPU CLOCK/PLL CONFIGURATION CLKIN CLKOUT4/GP0[1] CLKOUT6/GP0[2] CLKMODE1 CLKMODE0 PLLV TMS TDO TDI TCK TRST EMU11 EMU10 EMU9 EMU8 EMU7 EMU6 EMU5 EMU4 EMU3 EMU2 EMU1 EMU0 RESET AC2 D6 C6 AE4 AA2 V6 E15 B18 A18 A16 D14 D17 C17 B17 D16 A17 C16 B16 D15 C15 B15 C14 A15 P4 I I/O/Z I/O/Z I I A# I O/Z I I I I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I IPU IPU IPU IPU IPD IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPD IPD IPD IPD IPD Clock Input. This clock is the input to the on-chip PLL. Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 1 pin (I/O/Z). Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 2 pin (I/O/Z). Clock mode select * Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12. For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. PLL voltage supply JTAG EMULATION JTAG test-port mode select JTAG test-port data out JTAG test-port data in JTAG test-port clock JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG compatibility statement portion of this data sheet. Emulation pin 11. Reserved for future use, leave unconnected. Emulation pin 10. Reserved for future use, leave unconnected. Emulation pin 9. Reserved for future use, leave unconnected. Emulation pin 8. Reserved for future use, leave unconnected. Emulation pin 7. Reserved for future use, leave unconnected. Emulation pin 6. Reserved for future use, leave unconnected. Emulation pin 5. Reserved for future use, leave unconnected. Emulation pin 4. Reserved for future use, leave unconnected. Emulation pin 3. Reserved for future use, leave unconnected. Emulation pin 2. Reserved for future use, leave unconnected. Emulation pin 1|| Emulation pin 0|| Device reset DESCRIPTION
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS NMI B4 I IPD Nonmaskable interrupt, edge-driven (rising edge) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin. # A = Analog signal (PLL Filter) || The EMU0 and EMU1 pins are internally pulled up with 30-k resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k resistor.
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Terminal Functions
Table 2-10. Terminal Functions
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS (CONTINUED) GP0[7]/EXT_INT7 GP0[6]/EXT_INT6 GP0[5]/EXT_INT5 GP0[4]/EXT_INT4 GP0[15]/PRST GP0[14]/PCLK GP0[13]/PINTA GP0[12]/PGNT GP0[11]/PREQ GP0[10]/PCBE3 GP0[9]/PIDSEL E1 F2 F3 F4 G3 C1 G4 H4 F1 J2 K3 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z IPU IPU IPU IPU General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The default after reset setting is GPIO enabled as input-only. * When these pins function as External Interrupts [by selecting the corresponding interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]). General-purpose input/output (GP0) 15 pin (I/O/Z) or PCI reset (I). No function at default. GP0 14 pin (I/O/Z) or PCI clock (I). No function at default. GP0 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. GP0 12 pin (I/O/Z) or PCI bus grant (I). No function at default. GP0 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. GP0 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. GP0 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. GP0 3 pin (I/O/Z) and PCI EEPROM Auto-Initialization (EEAI). If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. 0 - PCI auto-initialization through EEPROM is disabled (default). 1 - PCI auto-initialization through EEPROM is enabled. GP0 0 pin (I/O/Z) [default] or device selection (I) [default] The general-purpose 0 pin (GP0[0]) (I/O/Z) can be programmed as GPIO 0 (input only) [default] or as GP0[0] (output only) pin or output as a general-purpose interrupt (GP0INT) signal (output only). This pin must remain low during device reset. VXCO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC) output [output only] [default] or this pin can be programmed as a GP0 8 pin (I/O/Z) or PCI frequency selection (PCI66). If the PCI peripheral is enabled (PCI_EN pin = 1), then: 0 - PCI operates at 66 MHz (default). 1 - PCI operates at 33 MHz. If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 2 pin (I/O/Z). Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GP0 1 pin (I/O/Z).
PRODUCT PREVIEW
GP0[3]/PCIEEAI
L5
IPD
GP0[0]
M5
I/O/Z
IPD
VDAC/ GP0[8]/PCI66
AD1
I/O/Z
IPD
CLKOUT6/ GP0[2] CLKOUT4/ GP0[1]
C6 D6
I/O/Z I/O/Z
IPD IPD
HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR EMAC PCI enable pin. This pin and the MAC_EN pin control the selection (enable/disable) of the HPI, EMAC, MDIO, and GP0[15:8], or PCI peripherals. The pins work in conjunction to enable/disable these peripherals (for more details, see the Device Configurations section of this data sheet).
PCI_EN
E2
I
IPD
HINT/PFRAME N4 I/O/Z Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR EMAC (CONTINUED) HCNTL1/ PDEVSEL HCNTL0/ PSTOP HHWIL/PTRDY HR/W/PCBE2 HAS/PPAR HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HD31/AD31/MRCLK HD30/AD30/MCRS HD29/AD29/MRXER HD28/AD28/MRXDV HD27/AD27/MRXD3 HD26/AD26/MRXD2 HD25/AD25/MRXD1 HD24/AD24/MRXD0 HD23/AD23 HD22/AD22/MTCLK HD21/AD21/MCOL HD20/AD20/MTXEN HD19/AD19/MTXD3 HD18/AD18/MTXD2 HD17/AD17/MTXD1 HD16/AD16/MTXD0 HD15/AD15 HD14/AD14 HD13/AD13 HD12/AD12 HD11/AD11 HD10/AD10 HD9/AD9 HD8/AD8 HD7/AD7 P1 R3 N3 M1 P3 R1 R2 T2 N1 G1 H3 G2 J4 H2 J3 J1 K4 K1 L4 K2 L3 L2 M4 M2 M3 T3 U1 U3 U2 U4 V1 V3 V2 For superset devices like DM642, the HD31/AD31 through HD16/AD16 pins can also function as EMAC transmit/receive or control pins (when PCI_EN pin = 0; MAC_EN pin = 1). For more details on the EMAC pin functions, see the Ethernet MAC (EMAC) peripheral section of this table and for more details on how to configure the EMAC pin, see the device configuration section of this data sheet. I/O/Z HD5 pin = 1: HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) As PCI data-address bus (PCI_EN pin = 1) * Used for transfer of data and address As HPI data bus (PCI_EN pin = 0) * Used for transfer of data, address, and control * Host-Port bus width user-configurable at device reset via a 10-k resistor pullup/ pulldown resistor on the HD5 pin: HD5 pin = 0: HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the high-impedance state.) Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z) or EMAC transmit/receive or control pins I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Host control - selects between control, address, or data registers (I) [default] or PCI device select (I/O/Z). Host control - selects between control, address, or data registers (I) [default] or PCI stop (I/O/Z) Host half-word select - first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z) Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z) Host address strobe (I) [default] or PCI parity (I/O/Z) Host chip select (I) [default] or PCI parity error (I/O/Z) Host data strobe 1 (I) [default] or PCI system error (I/O/Z) Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z) Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z).
W2 HD6/AD6 W4 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR EMAC (CONTINUED) HD5/AD5 Y1 Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z) or EMAC transmit/receive or control pins As HPI data bus (PCI_EN pin = 0) * Used for transfer of data, address, and control * Host-Port bus width user-configurable at device reset via a 10-k resistor pullup/ pulldown resistor on the HD5 pin: HD5 pin = 0: HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the high-impedance state.) I/O/Z HD2/AD2 Y4 HD5 pin = 1: HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) As PCI data-address bus (PCI_EN pin = 1) * Used for transfer of data and address AA1 For superset devices like DM642, the HD31/AD31 through HD16/AD16 pins can also function as EMAC transmit/receive or control pins (when PCI_EN pin = 0; MAC_EN pin = 1). For more details on the EMAC pin functions, see the Ethernet MAC (EMAC) peripheral section of this table and for more details on how to configure the EMAC pin, see the device configuration section of this data sheet. I/O/Z I/O/Z O I/O/Z I I/O/Z IPD IPD IPU IPU PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off. General-purpose input/output (GP0) 15 pin (I/O/Z) or PCI reset (I). No function at default. PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is tied-off. PCI serial interface clock (O) [default] or MDIO serial clock input/output (I/O/Z). PCI serial interface data in (I) [default]. In PCI mode, this pin is connected to the output data pin of the serial PROM. PCI serial interface data out (O) [default] or MDIO serial data input/output (I/O/Z). In PCI mode, this pin is connected to the input data pin of the serial PROM. GP0 14 pin (I/O/Z) or PCI clock (I). No function at default.
HD4/AD4
W3
HD3/AD3
Y2
PRODUCT PREVIEW
HD1/AD1
HD0/AD0
Y3
PCBE0 GP0[15]/PRST XSP_CS XSP_CLK/MDCLK XSP_DI XSP_DO/MDIO GP0[14]/PCLK GP0[13]/PINTA
V4 G3 T4 R5 R4 P5 C1 G4
GP0 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. I/O/Z GP0[12]/PGNT H4 GP0 12 pin (I/O/Z) or PCI bus grant (I). No function at default. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
HOST-PORT INTERFACE (HPI) OR PERIPHERAL COMPONENT INTERCONNECT (PCI) OR EMAC (CONTINUED) GP0[11]/PREQ F1 GP0 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. GP0[10]/PCBE3 J2 GP0 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. I/O/Z GP0[9]/PIDSEL K3 GP0 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. GP0 3 pin (I/O/Z) and PCI EEPROM Auto-Initialization (EEAI). If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. 0 - PCI auto-initialization through EEPROM is disabled (default). 1 - PCI auto-initialization through EEPROM is enabled. VXCO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC) output [output only] [default] or this pin can be programmed as a GP0 8 pin (I/O/Z) or PCI frequency selection (PCI66). If the PCI peripheral is enabled (PCI_EN pin = 1), then: 0 - PCI operates at 66 MHz (default). 1 - PCI operates at 33 MHz. If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
GP0[3]/PCIEEAI
L5
I/O/Z
IPD
VDAC/ GP0[8]/PCI66
AD1
I/O/Z
IPD
EMIFA (64-BIT) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ACE3 ACE2 ACE1 ACE0 ABE7 ABE6 ABE5 ABE4 ABE3 ABE2 ABE1 ABE0 APDT AHOLDA AHOLD L26 K23 K24 K25 T22 T23 R25 R26 M25 M26 L23 L24 M22 N22 W24 O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O I IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU EMIFA peripheral data transfer, allows direct transfer between external peripherals EMIFA hold-request-acknowledge to the host EMIFA hold request from the host EMIFA (64-BIT) - BUS ARBITRATIONk EMIFA byte-enable control * Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. * Byte-write enables for most types of memory * Can be directly connected to SDRAM read and write mask signal (SDQM) EMIFA memory space enables * Enabled by bits 28 through 31 of the word address * Only one pin is asserted during any external data access
ABUSREQ P22 O IPU EMIFA bus request output I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
EMIFA (64-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL AECLKIN H25 I IPD EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the AEA[20:19] pins. AECLKIN is the default for the EMIFA input clock. EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4. EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) frequency]. EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable * For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between ASADS and ASRE: If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal. If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal. EMIFA asynchronous memory output-enable/SDRAM strobe/programmable synchronous interface output-enable row-address
AECLKOUT2 AECLKOUT1
J23 J26
O/Z O/Z
IPD IPD
AARE/ ASDCAS/ ASADS/ASRE
J25
O/Z
IPU
PRODUCT PREVIEW
AAOE/ ASDRAS/ ASOE AAWE/ ASDWE/ ASWE ASDCKE ASOE3
J24
O/Z
IPU
K26
O/Z
IPU
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable EMIFA SDRAM clock-enable (used for self-refresh mode). * If SDRAM is not in system, ASDCKE can be used as a general-purpose output. EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface)
L25 R22
O/Z O/Z
IPU IPU
AARDY L22 I IPU Asynchronous memory ready input I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU EMIFA (64-BIT) - ADDRESS AEA22 AEA21 AEA20 AEA19 AEA18 AEA17 AEA16 AEA15 AEA14 AEA13 AEA12 AEA11 AEA10 AEA9 AEA8 AEA7 AEA6 AEA5 AEA4 AEA3 U23 V24 V25 V26 V23 U24 U25 U26 T24 T25 R23 R24 P23 P24 P26 N23 N24 N26 M23 M24 EMIFA (64-BIT) - DATA AED63 AED62 AED61 AED60 AED59 AED58 AED57 AED56 AED55 AED54 AED53 AED52 AED51 AED50 AED49 AED48 AED47 AF24 AF23 AE23 AD23 AD22 AE22 AD21 AE21 AC21 AF21 AD20 AE20 AC20 AF20 AC19 AD19 W23 I/O/Z IPU EMIFA external data O/Z IPD EMIFA external address (doubleword address) * Also controls initialization of DSP modes at reset (I) via pullup/pulldown resistors - Boot mode (AEA[22:21]): 00 - No boot (default mode) 01 - HPI/PCI boot (based on PCI_EN pin) 10 - Reserved 11 - EMIFA boot - EMIF clock select - AEA[20:19]: Clock mode select for EMIFA (AECLKIN_SEL[1:0]) 00 - AECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved For more details, see the Device Configurations section of this data sheet. DESCRIPTION
AED46 Y26 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU EMIFA (64-BIT) - DATA (CONTINUED) AED45 AED44 AED43 AED42 AED41 AED40 AED39 AED38 AED37 AED36 AED35 AED34 Y23 Y25 Y24 AA26 AA23 AA25 AA24 AB23 AB25 AB24 AC26 AC25 AD25 AD26 C26 C25 D26 D25 E24 E25 F24 F25 F23 F26 G24 G25 G23 G26 H23 H24 C19 D19 A20 D20 B20 C20 A21 D21 I/O/Z IPU EMIFA external data DESCRIPTION
PRODUCT PREVIEW
AED33 AED32 AED31 AED30 AED29 AED28 AED27 AED26 AED25 AED24 AED23 AED22 AED21 AED20 AED19 AED18 AED17 AED16 AED15 AED14 AED13 AED12 AED11 AED10 AED9 AED8
AED7 B21 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Table 2-10. Terminal Functions (Continued)
SIGNAL NAME AED6 AED5 AED4 AED3 AED2 AED1 AED0 XSP_CLK/MDCLK XSP_DO/MDIO NO. C21 A23 C22 B22 B23 A24 B24 MANAGEMENT DATA INPUT/OUTPUT (MDIO) R5 P5 I/O/Z I/O/Z IPD IPU PCI serial interface clock (O) [default] or MDIO serial clock input/output (I/O/Z). PCI serial interface data out (O) [default] or MDIO serial data input/output (I/O/Z). In PCI mode, this pin is connected to the input data pin of the serial PROM. I/O/Z IPU EMIFA external data TYPE IPD/ IPU EMIFA (64-BIT) - DATA (CONTINUED) DESCRIPTION
VCX0 INTERPOLATED CONTROL PORT (VIC)
VDAC/ GP0[8]/PCI66
AD1
I/O/Z
IPD
VIDEO PORTS (VP0, VP1, AND VP2) STCLK AC1 I IPD The STCLK signal drives the hardware counter on the video ports. VIDEO PORT 2 (VP2) VP2D[19] VP2D[18] VP2D[17] VP2D[16] VP2D[15] VP2D[14] VP2D[13] VP2D[12] VP2D[11] VP2D[10] VP2D[9] VP2D[8] VP2D[7] VP2D[6] VP2D[5] VP2D[4] VP2D[3] E13 E12 D12 C12 B12 E11 D11 C11 B11 A11 D10 C10 B10 A10 D9 C9 B9 I/O/Z IPD Video port 2 (VP2) data input/output (I/O/Z) [default]
VP2D[2] A9 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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VXCO Interpolated Control Port (VIC) single-bit digital-to-analog converter (VDAC) output [output only] [default] or this pin can be programmed as a GP0 8 pin (I/O/Z) or PCI frequency selection (PCI66). If the PCI peripheral is enabled (PCI_EN pin = 1), then: 0 - PCI operates at 66 MHz (default). 1 - PCI operates at 33 MHz. If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME VP2D[1] VP2D[0] VP2CLK1 VP2CLK0 VP2CTL2 VP2CTL1 VP2CTL0 VP1D[19]/AXR0[7] VP1D[18]/AXR0[6] VP1D[17]/AXR0[5] VP1D[16]/AXR0[4] NO. D8 C8 A13 A7 C7 D7 B8 AB12 AB11 AC11 AD11 AE11 AC10 AD10 AC9 AD9 AE9 AC8 AD8 AC7 AD7 AE7 AC6 AD6 AE6 AF6 AF5 AF10 AF8 AD5 AE5 I/O/Z IPD I VP1 clock 1 (I/O/Z) [default] VP1 clock 0 (I) [default] VP1 control 2 (I/O/Z) [default] VP1 control 1 (I/O/Z) [default] I/O/Z IPD Video port 1 (VP1) data input/output (I/O/Z) [default] or McASP0 data pins (I/O/Z) or McBSP1 data input/output (I/O/Z) For more details on the McBSP1 pin functions or the McASP0 data pin functions, see McBSP1 or McASP0 data sections of this table. I/O/Z I IPD I/O/Z Video port 2 (VP2) data input/output (I/O/Z) [default] VP2 clock 1 (I/O/Z) [default] VP2 clock 0 (I) [default] VP2 control 2 (I/O/Z) [default] VP2 control 1 (I/O/Z) [default] VP2 control 0 (I/O/Z) [default] VIDEO PORT 1 (VP1) OR MCASP0 DATA TYPE IPD/ IPU VIDEO PORT 2 (VP2) (CONTINUED) DESCRIPTION
PRODUCT PREVIEW
VP1D[15]/AXR0[3] VP1D[14]/AXR0[2] VP1D[13]/AXR0[1] VP1D[12]/AXR0[0] VP1D[11] VP1D[10] VP1D[9] VP1D[8]/CLKR1 VP1D[7]/FSR1 VP1D[6]/DR1 VP1D[5]/CLKS1 VP1D[4]/DX1 VP1D[3]/FSX1 VP1D[2]/CLKX1 VP1D[1] VP1D[0] VP1CLK1 VP1CLK0 VP1CTL2 VP1CTL1
VP1CTL0 AF4 VP1 control 0 (I/O/Z) [default] I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Table 2-10. Terminal Functions (Continued)
SIGNAL NAME VP0D[19]/AHCLKX0 VP0D[18]/AFSX0 VP0D[17]/ACLKX0 VP0D[16]/AMUTE0 VP0D[15]/AMUTEIN0 VP0D[14]/AHCLKR0 VP0D[13]/AFSR0 VP0D[12]/ACLKR0 VP0D[11] VP0D[10] VP0D[9] VP0D[8]/CLKR0 VP0D[7]/FSR0 VP0D[6]/DR0 VP0D[5]/CLKS0 VP0D[4]/DX0 VP0D[3]/FSX0 VP0D[2]/CLKX0 VP0D[1] VP0D[0] VP0CLK1 VP0CLK0 VP0CTL2 VP0CTL1 VP0CTL0 NO. AC12 AD12 AB13 AC13 AD13 AB14 AC14 AD14 AB15 AC15 AD15 AE15 AB16 AC16 AD16 AE16 AF16 AF17 AE18 AF18 AF12 AF14 AD17 AC17 AE17 - I/O/Z I/O/Z I IPD VP0 clock 1 (I/O/Z) [default] VP0 clock 0 (I) [default] VP0 control 2 (I/O/Z) [default] VP0 control 1 (I/O/Z) [default] VP0control 0 (I/O/Z) [default] TIMER 2 No external pins. The timer 2 peripheral pins are not pinned out as external pins. TIMER 1 Timer 1 output (O/Z) or device endian mode (I). Also controls initialization of DSP modes at reset via pullup/pulldown resistors - Device Endian mode 0 - Big Endian 1 - Little Endian (default) For more details on LENDIAN, see the Device Configurations section of this data sheet. I/O/Z IPD Video port 0 (VP0) data input/output (I/O/Z) [default] or McASP0 control pins (I/O/Z) or McBSP0 data input/output (I/O/Z) For more details on the McBSP0 pin functions or the McASP0 control pin functions, see McBSP0 or McASP0 control sections of this table. TYPE IPD/ IPU DESCRIPTION
VIDEO PORT 0 (VP0) OR MCASP0 CONTROL
TOUT1/LENDIAN
B5
O/Z
IPU
TINP1 A5 I IPD Timer 1 or general-purpose input I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU TIMER 0 Timer 0 output (O/Z) or MAC enable select bit (I) MAC enable pin. This pin and the MAC_EN pin control the selection (enable/disable) of the HPI, EMAC, MDIO, and GP0[15:9], or PCI peripherals. The pins work in conjunction to enable/disable these peripherals (for more details, see the Device Configurations section of this data sheet). For more details, see the Device Configurations section of this data sheet. Timer 0 or general-purpose input I2C0 clock. I2C0 data. Video Port 1 (VP1) input/output data 8 pin (I/O/Z) [default] or McBSP1 receive clock (I/O/Z) VP1 input/output data 7 pin (I/O/Z) [default] or McBSP1 receive frame sync (I/O/Z) VP1 input/output data 6 pin (I/O/Z) [default] or McBSP1 receive data (I) VP1 input/output data 5 pin (I/O/Z) [default] or McBSP1 external clock source (I) (as opposed to internal) VP1 input/output data 4 pin (I/O/Z) [default] or McBSP1 transmit data (O/Z) VP1 input/output data 3 pin (I/O/Z) [default] or McBSP1 transmit frame sync (I/O/Z) VP1 input/output data 2 pin (I/O/Z) [default] or McBSP1 transmit clock (I/O/Z) Video Port 0 (VP0) input/output data 8 pin (I/O/Z) [default] or McBSP0 receive clock (I/O/Z) VP0 input/output data 7 pin (I/O/Z) [default] or McBSP0 receive frame sync (I/O/Z) VP0 input/output data 6 pin (I/O/Z) [default] or McBSP0 receive data (I) VP0 input/output data 5 pin (I/O/Z) [default] or McBSP0 external clock source (I) (as opposed to internal) VP0 input/output data 4 pin (I/O/Z) [default] or McBSP0 transmit data (O/Z) DESCRIPTION
TOUT0/MAC_EN
C5
O/Z
IPD
TINP0 SCL0 SDA0
A4 E4 D3
I I/O/Z I/O/Z
IPD -- --
INTER-INTEGRATED CIRCUIT 0 (I2C0)
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) VP1D[8]/CLKR1 AD8 AC7 AD7 AE7 AC6 AD6 AE6 I/O/Z I/O/Z I I I/O/Z I/O/Z I/O/Z IPD IPD IPD IPD IPD IPD IPD
PRODUCT PREVIEW
VP1D[7]/FSR1 VP1D[6]/DR1 VP1D[5]/CLKS1 VP1D[4]/DX1 VP1D[3]/FSX1 VP1D[2]/CLKX1
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) VP0D[8]/CLKR0 VP0D[7]/FSR0 VP0D[6]/DR0 VP0D[5]/CLKS0 VP0D[4]/DX0 VP0D[3]/FSX0 AE15 AB16 AC16 AD16 AE16 AF16 I/O/Z I/O/Z I I O/Z I/O/Z IPD IPD IPU IPD IPU IPD
VP0 input/output data 3 pin (I/O/Z) [default] or McBSP0 transmit frame sync (I/O/Z) VP0D[2]/CLKX0 AF17 I/O/Z IPD VP0 input/output data 2 pin (I/O/Z) [default] or McBSP0 transmit clock (I/O/Z) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU ETHERNET MAC (EMAC) HD31/AD31/MRCLK HD30/AD30/MCRS HD29/AD29/MRXER HD28/AD28/MRXDV HD27/AD27/MRXD3 HD26/AD26/MRXD2 HD25/AD25/MRXD1 HD24/AD24/MRXD0 HD22/AD22/MTCLK HD21/AD21/MCOL HD20/AD20/MTXEN HD19/AD19/MTXD3 HD18/AD18/MTXD2 HD17/AD17/MTXD1 HD16/AD16/MTXD0 G1 H3 G2 J4 H2 J3 J1 K4 L4 K2 L3 L2 M4 M2 M3 I I I I I I I I I I O/Z O/Z O/Z O/Z O/Z EMAC Media Independent I/F (MII) data, clocks, and control pins for Transmit/Receive. MII transmit clock (MTCLK), Transmit clock source from the attached PHY. MII transmit data (MTXD[3:0]), Transmit data nibble synchronous with transmit clock (MTCLK). MII transmit enable (MTXEN), This signal indicates a valid transmit data on the transmit data pins (MTDX[3:0]). MII collision sense (MCOL) Assertion of this signal during half-duplex operation indicates network collision. During full-duplex operation, transmission of new frames will not begin if this pin is asserted. MII carrier sense (MCRS) Indicates a frame carrier signal is being received. MII receive data (MRXD[3:0]), Receive data nibble synchronous with receive clock (MRCLK). MII receive clock (MRCLK), Receive clock source from the attached PHY. MII receive data valid (MRXDV), This signal indicates a valid data nibble on the receive data pins (MRDX[3:0]). and MII receive error (MRXER), Indicates reception of a coding error on the receive data. DESCRIPTION
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) CONTROL VP0D[19]/AHCLKX0 VP0D[18]/AFSX0 VP0D[17]/ACLKX0 VP0D[16]/AMUTE0 VP0D[15]/AMUTEIN0 VP0D[14]/AHCLKR0 VP0D[13]/AFSR0 VP0D[12]/ACLKR0 AC12 AD12 AB13 AC13 AD13 AB14 AC14 AD14 I/O/Z I/O/Z I/O/Z O/Z I/O/Z I/O/Z I/O/Z I/O/Z IPD IPD IPD IPD IPD IPD IPD IPD VP0 input/output data 19 pin (I/O/Z) [default] or McASP0 transmit high-frequency master clock (I/O/Z). VP0 input/output data 18 pin (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z). VP0 input/output data 17 pin (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z). VP0 input/output data 16 pin (I/O/Z) [default] or McASP0 mute output (O/Z). VP0 input/output data 15 pin (I/O/Z) [default] or McASP0 mute input (I/O/Z). VP0 input/output data 14 pin (I/O/Z) [default] or McASP0 receive high-frequency master clock (I/O/Z). VP0 input/output data 13 pin (I/O/Z) [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z). VP0 input/output data 12 pin (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z).
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) DATA VP1D[19]/AXR0[7] VP1D[18]/AXR0[6] VP1D[17]/AXR0[5] VP1D[16]/AXR0[4] VP1D[15]/AXR0[3] VP1D[14]/AXR0[2] VP1D[13]/AXR0[1] VP1D[12]/AXR0[0] AB12 AB11 AC11 AD11 AE11 AC10 AD10 AC9 I/O/Z IPD VP0 input/output data pins [19:12] (I/O/Z) [default] or McASP0 TX/RX data pins [7:0] (I/O/Z).
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Terminal Functions
Table 2-10. Terminal Functions
SIGNAL NAME NO. TYPE IPD/ IPU RESERVED FOR TEST RSV RSV H7 R6 E14 W7 AA3 RSV AB3 AC4 AD3 AF3 SUPPLY VOLTAGE PINS A2 Reserved (leave unconnected, do not connect to power or ground) Reserved. This pin must be connected directly to CVDD for proper device operation. Reserved. This pin must be connected directly to DVDD for proper device operation. DESCRIPTION
PRODUCT PREVIEW
A25 B1 B2 B14 B25 B26 C3 C24 D4 D23 E5 E7 DVDD E8 E10 E17 E19 E20 E22 F9 F12 F15 F18 G5 G22 H5 H22 J6 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) S 3.3-V supply voltage
90
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED) J21 K5 K22 M6 M21 N2 P25 R21 U5 U22
W5 W22 W25 Y5 DVDD Y22 AA9 AA12 AA15 AA18 AB5 AB7 AB8 AB10 AB17 AB19 AB20 AB22 AC23 AD24 AE1 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) S 3.3-V supply voltage
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V21
Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED) AE2 AE13 AE25 DVDD AE26 AF2 AF25 F6 F7 F20 F21 S 3.3-V supply voltage
PRODUCT PREVIEW
G6 G7 G8 G10 G11 G13 G14 G16 G17 G19 CVDD G20 G21 H20 K7 K20 L7 L20 M12 M14 N7 N13 N15 N20 P7 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) S 1.2-V supply voltage (-500 device) 1.4 V supply voltage (-600 devices)
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED) P12 P14 P20 R13 R15 T7 T20 U7 U20 W20
Y7 Y8 CVDD Y10 Y11 Y13 Y14 Y16 Y17 Y19 Y20 Y21 AA6 AA7 AA20 AA21 GROUND PINS A1 A3 A6 A8 VSS A12 A14 A19 A22 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) GND Ground pins S 1.2-V supply voltage (-500 device) 1.4 V supply voltage (-600 devices)
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PRODUCT PREVIEW
Y6
Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU GROUND PINS A26 B3 B6 B7 B13 B19 C2 C4 C13 C18 DESCRIPTION
PRODUCT PREVIEW
C23 D1 D2 D5 D13 VSS D18 D22 D24 E3 E6 E9 E16 E18 E21 E23 E26 F5 F8 F10 F11 F13 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) GND Ground pins
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU GROUND PINS (CONTINUED) F14 F16 F17 F19 F22 G9 G12 G15 G18 H1 DESCRIPTION
H21 H26 J5 J7 J20 VSS J22 K6 K21 L1 L6 L21 M7 M13 M15 M20 N5 N6 N12 N14 N21 N25 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) GND Ground pins
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PRODUCT PREVIEW
H6
Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU GROUND PINS (CONTINUED) P2 P6 P13 P15 P21 R7 R12 R14 R20 T1 DESCRIPTION
PRODUCT PREVIEW
T5 T6 T21 T26 U6 VSS U21 V5 V7 V20 V22 W1 W6 W21 W26 Y9 Y12 Y15 Y18 AA4 AA5 AA8 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) GND Ground pins
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU GROUND PINS (CONTINUED) AA10 AA11 AA13 AA14 AA16 AA17 AA19 AA22 AB1 AB2 AB4 AB9 AB18 AB21 AB26 VSS AC3 AC5 AC18 AC22 AC24 AD2 AD4 AD18 AE3 AE8 AE10 AE12 AE14 AE19 AE24 AF1 AF7 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) GND Ground pins AB6 DESCRIPTION
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Terminal Functions
Table 2-10. Terminal Functions (Continued)
SIGNAL NAME NO. AF9 AF11 AF13 VSS AF15 AF19 AF22 AF26 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) GND Ground pins TYPE IPD/ IPU GROUND PINS (CONTINUED) DESCRIPTION
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Development Support
2.8
Development Support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, XDS, and TMS320 are trademarks of Texas Instruments.
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Device and Development-Support Tool Nomenclature
2.9
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow:
TMX TMP TMS Experimental device that is not necessarily representative of the final device's electrical specifications Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification Fully qualified production device
Support tool development evolutionary flow:
PRODUCT PREVIEW
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a final product and Texas Instruments reserves the right to change or discontinue these products without notice. TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GDK), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -600 is 600 MHz). Figure 2-9 provides a legend for reading the complete device name for any TMS320C6000 DSP platform member.
TMS320 is a trademark of Texas Instruments.
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Device and Development-Support Tool Nomenclature
TMX 320 DM642 GDK PREFIX TMX = Experimental device TMP = Prototype device TMS = Qualified device SMX= Experimental device, MIL SMJ = MIL-PRF-38535, QML SM = High Rel (non-38535) () 600 DEVICE SPEED RANGE 500 (500-MHz CPU, 100-MHz EMIF, 33-MHz PCI) 600 (600-MHz CPU, 133-MHz EMIF, 66-MHz PCI) TEMPERATURE RANGE (DEFAULT: 0C TO 90C) Blank = 0C to 90C, commercial temperature A = -40C to 105C, extended temperature
DEVICE FAMILY 320 = TMS320t DSP family
PACKAGE TYPE GDK = 548-pin plastic BGA GNZ = 548-pin plastic BGA DEVICE DM64x DSP: 642 641
Figure 2-9. TMS320DM64x DSP Device Nomenclature (Including the TMS320DM642 Device)
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For more details, see the recommended operating conditions portion of this data sheet. BGA = Ball Grid Array
Documentation Support
2.10 Documentation Support
Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on the C6000 DSP platform of devices, such as the 64-/32-/16-bit external memory interfaces (EMIFs), enhanced direct-memory-access (EDMA) controller, multichannel buffered serial ports (McBSPs), 32-/16-bit host-port interfaces (HPIs), a peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); general-purpose timers, general-purpose input/output port (GP0), and power-down modes. This guide also includes information on internal data and program memories. The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x digital signal processor, and discusses the application areas that are enhanced by the C64x DSP VelociTI.2 VLIW architecture. The TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629) describes the functionality of the Video Port and VIC Port peripherals. The TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041) describes the functionality of the McASP peripheral. TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Peripheral Reference Guide (literature number SPRU175) describes the functionality of the I2C peripheral. TMS320C6000 DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628) describes the functionality of the EMAC and MDIO peripherals. TMS320DM642 Technical Overview (literature number SPRU615) describes the TMS320DM642 architecture including details of its peripherals. This document also shows several example applications such as using the DM642 device in development of IP phones, video-on-demand set-top boxes, and surveillance digital video recorders. The TMS320DM642 Digital Signal Processor Silicon Errata (literature number SPRZ196) describes the known exceptions to the functional specifications for particular silicon revisions of the TMS320DM642 device. The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to properly use IBIS models to attain accurate timing analysis for a given system. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
PRODUCT PREVIEW
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Clock PLL
2.11 Clock PLL
Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 2-10 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes. To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended ranges of supply voltage and operating case temperature table and the input and output clocks electricals section).
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Clock PLL
3.3 V CPU Clock EMI filter C1 10 F C2 0.1 F /8 PLLV /4 CLKMODE0 CLKMODE1 /2 Peripheral Bus, EDMA Clock, L2 Clock Timer Internal Clock CLKOUT4, Peripheral Clock (AUXCLK for McASP), McBSP Internal Clock CLKOUT6
PLLMULT PLL x6, x12
/6
CLKIN
PLLCLK
1 0
00 01 10
/4
PRODUCT PREVIEW
ECLKIN AEA[20:19] Internal to DM642 EMIF
/2
00 01 10
EK2RATE (GBLCTL.[19,18])
(For the PLL Options, CLKMODE Pins Setup, and PLL Clock Frequency Ranges, see Table 9.)
ECLKOUT1
ECLKOUT2
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000 DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 2-10. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
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Clock PLL
Table 2-11. TMS320DM642 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time
GDK PACKAGE - 23 x 23 mm BGA, GNZ PACKAGE - 27 x 27 mm BGA CLKMODE1 CLKMODE0 0 0 1 0 1 0 CLKMODE (PLL MULTIPLY FACTORS) Bypass (x1) x6 x12 CLKIN RANGE (MHz) 30-75 30-75 30-50 CPU CLOCK FREQUENCY RANGE (MHz) 30-75 180-450 360-600 CLKOUT4 RANGE (MHz) 7.5-18.8 45-112.5 90-150 CLKOUT6 RANGE (MHz) 5-12.5 30-75 60-100 75 TYPICAL LOCK TIME (s) N/A
1 1 Reserved - - - - - These clock frequency range values are applicable to a DM642-600 speed device. For -500 device speed values, see the CLKIN timing requirements table for the specific device speed. Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the DM642 device to one of the valid PLL multiply clock modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass). Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s.
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Multichannel Audio Serial Port (McASP0) Peripheral
2.12 Multichannel Audio Serial Port (McASP0) Peripheral
The TMS320DM642 device includes one multichannel audio serial port (McASP) interface peripheral (McASP0). The McASP is a serial port optimized for the needs of multi-channel audio applications. The McASP consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. The McASP module also includes a pool of 16 shift registers that may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO). The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial format. The McASP can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the same format. However, the transmit and receive formats need not be the same. Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio data (for example, passing control information between two DSPs). The McASP peripheral has additional capability for flexible clock generation, and error detection/handling, as well as error management. For more detailed information on and the functionality of the McASP peripheral, see the TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041).
PRODUCT PREVIEW
2.12.1
McASP Block Diagram
Figure 2-11 illustrates the major blocks along with external signals of the TMS320DM642 McASP0 peripheral; and shows the 8 serial data [AXR] pins. The McASP also includes full general-purpose I/O (GPIO) control, so any pins not needed for serial transfers can be used for general-purpose I/O.
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Multichannel Audio Serial Port (McASP0) Peripheral
McASP0 Transmit Frame Sync Generator
DIT RAM Transmit Clock Check (HighFrequency)
AFSX0
Transmit Clock Generator
AHCLKX0 ACLKX0
Error Detect Receive Clock Check (HighFrequency) DMA Transmit Transmit Data Formatter INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO
AMUTE0 AMUTEIN0
Receive Clock Generator
AHCLKR0 ACLKR0
Serializer 0 Serializer 1 Serializer 2 Serializer 3 Serializer 4 Serializer 5 Serializer 6 Serializer 7
AXR0[0] AXR0[1] AXR0[2] AXR0[3] AXR0[4] AXR0[5] AXR0[6] AXR0[7]
DMA Receive
Receive Data Formatter
GPIO Control
Figure 2-11. McASP0 Configuration
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Receive Frame Sync Generator
AFSR0
I2C
2.13 I2C
The I2C module on the TMS320DM642 may be used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate with other controllers in a system or to implement a user interface. The I2C port supports:
* * * * * * *
Compatible with Philips I2C Specification Revision 2.1 (January 2000) Fast Mode up to 400 Kbps (no fail-safe I/O buffers) Noise Filter to Remove Noise 50 ns or less Seven- and Ten-Bit Device Addressing Modes Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality Events: DMA, Interrupt, or Polling Slew-Rate Limited Open-Drain Output Buffers
PRODUCT PREVIEW
Figure 2-12 is a block diagram of the I2C0 module.
I2C0 Module Clock Prescale I2CPSCx Peripheral Clock (CPU/4)
SCL
Bit Clock Generator Noise Filter I2CCLKHx I2CCLKLx
Control I2COARx I2CSARx I2CMDRx Own Address Slave Address Mode Data Count
I2C Clock
Transmit I2CXSRx Transmit Shift Transmit Buffer Interrupt/DMA Noise Filter Receive I2CDRRx Receive Buffer Receive Shift I2CIERx I2CSTRx I2CISRCx Interrupt Enable Interrupt Status Interrupt Source I2CCNTx
I2CDXRx SDA I2C Data
I2CRSRx
NOTE A: Shading denotes control/status registers.
Figure 2-12. I2C0 Module Block Diagram
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PCI
2.14 PCI
On the DM642 device, the PCI interface is multiplexed with the 32-bit Host Port Interface (HPI), or with a combination of 16-bit HPI and EMAC/MDIO. This provides the following flexibility options to the user:
* * *
32-bit 66 MHz PCI bus 32-bit HPI Combination of 16-bit HPI and EMAC/MDIO
The PCI port for the TMS320C600 supports connection of the DSP to a PCI host via the integrated PCI master/slave bus interface. For the C64x devices, like the DM642, the PCI port interfaces to the DSP via the EDMA internal address generation hardware. This architecture allows for both PCI Master and Slave transactions, while keeping the EDMA channel resources available for other applications. For more details on the PCI port peripheral module, see the "PCI" chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
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Video Port
2.15 Video Port
The TMS320DM642 device has three video port peripherals. The video port peripheral can operate as a video capture port, video display port, or as a transport stream interface (TSI) capture port. The port consists of two channels: A and B. A 5120-byte capture/display buffer is splittable between the two channels. The entire port (both channels) is always configured for either video capture or display only. Separate data pipelines control the parsing and formatting of video capture or display data for each of the BT.656, Y/C, raw video, and TSI modes.
For video capture operation, the video port may operate as two 8/10-bit channels of BT.656 or raw video capture; or as a single channel of 8/10-bit BT.656, 8/10-bit raw video, 16/20-bit Y/C video, 16/20-bit raw video, or 8-bit TSI. For video display operation, the video port may operate as a single channel of 8/10-bit BT.656; or as a single channel of 8/10-bit BT.656, 8/10-bit raw video, 16/20 bit Y/C video, or 16/20-bit raw video. It may also operate in a two channel 8/10-bit raw mode in which the two channels are locked to the same timing. Channel B is not used during single channel operation.
PRODUCT PREVIEW
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VIC
2.16 VIC
The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output (VDAC pin). Typical D/A converters provide a discrete output level for every value of the digital word that is being converted. This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A converter by choosing a few widely spaced output levels and interpolating values between them. The interpolating mechanism causes the output to oscillate rapidly between the levels in such a manner that the average output represents the value of input code. In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented to interpolate between these levels with a rapidly changing signal. The frequency of interpolation is dependent on the resolution needed. When the video port is used in transport stream interface (TIS) mode, the VIC port is used to control the system clock, VCXO, for MPEG transport stream. The VIC supports the following features:
* * *
Single interpolation for D/A conversion Programmable precision from 9-to-16 bits Interface for register accesses
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EMAC
2.17 EMAC
The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. The EMAC controls the flow of packet data from the DSP to the PHY. The MDIO module controls PHY configuration and status monitoring. Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to control device reset, interrupts, and system priority.
PRODUCT PREVIEW
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MDIO
2.18 MDIO
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The management data input/output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor.
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Power-Supply Sequencing
2.19 Power-Supply Sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time (>1 second) if the other supply is below the proper operating voltage.
2.19.1
Power-Supply Design Considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 2-13).
I/O Supply DVDD Schottky Diode
PRODUCT PREVIEW
Core Supply
C6000 DSP CVDD
VSS
GND
Figure 2-13. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
2.20 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supply and 30 for the I/O supply. These caps need to be close to the DSP, no more than 1.25 cm maximum distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest available capacitance value. As with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered.
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Power-Down Operation
2.21 Power-Down Operation
The DM642 device can be powered down in three ways:
* * *
Power-down due to pin configuration Power-down due to software configuration - relates to the default state of the peripheral configuration bits in the PERCFG register. Power-down during run-time via software configuration
On the DM642 device, the HPI, PCI, and EMAC and MDIO peripherals are controlled (selected) at the pin level during chip reset (e.g., PCI_EN, HD5, and MAC_EN pins). The McASP0, McBSP0, McBSP1, VP0, VP1, VP2, and I2C0 peripheral functions are selected via the peripheral configuration (PERCFG) register bits. For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the Device Configurations section of this document.
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IEEE 1149.1 JTAG Compatibility Statement
2.22 IEEE 1149.1 JTAG Compatibility Statement
The TMS320DM642 DSP requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the DSP core, TRST initializes the DSP's emulation logic. Both resets are required for proper operation. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and DSP's emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise the DSP's boundary scan functionality. For maximum reliability, the TMS320DM642 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
PRODUCT PREVIEW
When using this type of JTAG controller, assert TRST to intialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the low-to-high transition of TRST must be "seen" to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet.
2.23 EMIF Device Speed
The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets the following requirements:
* * * * *
1 bank (maximum of 2 chips) of SDRAM connected to EMIF up to 1 bank of buffers connected to EMIF EMIF trace lengths between 1 and 3 inches 183-MHz SDRAM for 133-MHz operation 143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met. Verification of AC timings is mandatory when using configurations other than those specified above. TI recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see the Terminal Functions table for the EMIF output signals).
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Bootmode
2.24 Bootmode
The DM642 device resets using the active-low signal RESET. While RESET is low, the device is held in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and states of device pins during reset. The release of RESET starts the processor running with the prescribed device configuration and boot mode. The DM642 has three types of boot modes:
*
Host boot If host boot is selected, upon release of RESET, the CPU is internally "stalled" while the remainder of the device is released. During this period, an external host can initialize the CPU's memory space as necessary through the host interface, including internal configuration registers, such as those that control the EMIF or other peripherals. For the DM642 device, the HPI peripheral is used for host boot if PCI_EN = 0, and the PCI peripheral is used if PCI_EN = 1. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration logic to bring the CPU out of the "stalled" state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs while the CPU is still internally "stalled". Also, DSPINT brings the CPU out of the "stalled" state only if the host boot process is selected. All memory may be written to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the "stalled" state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
*
EMIF boot (using default ROM timings) Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0 by the EDMA using the default ROM timings, while the CPU is internally "stalled". The data should be stored in the endian format that the system is using. In this case, the EMIF automatically assembles consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is released from the "stalled" state and starts running from address 0.
*
No boot With no boot, the CPU begins direct execution from the memory located at address 0. If SDRAM is used in the system, the CPU is internally "stalled" until the SDRAM initialization is complete. Note: operation is undefined if invalid code is located at address 0.
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PRODUCT PREVIEW
Electrical Specifications
3
3.1
Electrical Specifications
Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 2.3 V DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage ranges: (except PCI), VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V (PCI), VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Output voltage ranges: (except PCI), VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V (PCI), VOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Operating case temperature ranges, TC: (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65_C to 150_C Supply voltage ranges:
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
PRODUCT PREVIEW
3.2
CVDD CVDD DVDD VSS VIH VIL VIP VIHP VILP
Recommended Operating Conditions
MIN Supply voltage, Core (-500 device) Supply voltage, Core (-600 device) Supply voltage, I/O Supply ground High-level input voltage (except PCI) Low-level input voltage (except PCI) Input voltage (PCI) High-level input voltage (PCI) Low-level input voltage (PCI) -0.5 0.5DVDD -0.5 1.14 1.36 3.14 0 2 0.8 DVDD + 0.5 DVDD + 0.5 0.3DVDD 90 NOM 1.2 1.4 3.3 0 MAX 1.26 1.44 3.46 0 UNIT V V V V V V V V V
TC Operating case temperature 0 _C Future variants of the C64x DSPs may operate at voltages ranging from 1.2 V to 1.4 V to provide a range of system power/performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of C64x devices.
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Electrical Specifications
3.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS DVDD = MIN, IOHP = -0.5 mA, DVDD = MIN, IOH = MAX DVDD = 3.3 V IOL = MAX DVDD = 3.3 V MIN 2.4 0.9DVDD 0.4 0.1DVDD 10 50 -150 100 -100 150 -50 10 -16 -8 -0.5 16 8 1.5 10 TBD TBD TBD 10 TYP MAX UNIT V V V V uA uA uA uA mA mA High-level output voltage (except PCI) High-level output voltage (PCI) Low-level output voltage (except PCI) Low-level output voltage (PCI)
VOH VOHP VOL VOLP
IOLP = 1.5 mA, VI = VSS to DVDD no opposing internal resistor VI = VSS to DVDD opposing internal pullup resistor VI = VSS to DVDD opposing internal pulldown resistor
II
Input current (except PCI)
IIP
Input leakage current (PCI)
0 < VIP < DVDD = 3.3 V EMIF, CLKOUT4, CLKOUT6, EMUx Timer, TDO, GPIO (Excluding GP[15:9, 2, 1]), McBSP PCI/HPI EMIF, CLKOUT4, CLKOUT6, EMUx Timer, TDO, GPIO (Excluding GP[15:9, 2, 1]), McBSP PCI/HPI
IOH
High-level output current
mA mA mA uA mA mA mA pF
IOL
Low-level output current
IOZ ICDD IDDD Ci
Off-state output current Core supply current# I/O supply current# Input capacitance
VO = DVDD or 0 V CVDD = 1.4 V, CPU clock = 600 MHz CVDD = 1.2 V, CPU clock = 500 MHz DVDD = 3.3 V, CPU clock = 600 MHz
Co Output capacitance 10 pF For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs. These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4, respectively. # Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6414/15/16 Power Consumption Summary application report (literature number SPRA811).
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PRODUCT PREVIEW
mA
Electrical Specifications
3.4
Parameter Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42
3.5 nH Transmission Line Z0 = 50 (see note)
Output Under Test
Device Pin (see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
PRODUCT PREVIEW
Figure 3-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.
3.4.1 Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.
Vref = 1.5 V
Figure 3-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks, VILP MAX and VIHP MIN for PCI input clocks, and VOLP MAX and VOHP MIN for PCI output clocks.
Vref = VIH MIN (or VOH MIN or VIHP MIN or VOHP MIN) Vref = VIL MAX (or VOL MAX or VILP MAX or VOLP MAX)
Figure 3-3. Rise and Fall Transition Time Voltage Reference Levels
3.4.2 Signal Transition Rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
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Electrical Specifications
3.5
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 3-1 and Figure 3-4). Figure 3-4 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device.
Table 3-1. Board-Level Timing Example (see Figure 3-4)
1 2 3 4 5 6 7 8 9 10 11 ECLKOUTx (Output from DSP) 1 ECLKOUTx (Input to External Device) Control Signals (Output from DSP) 3 4 5 Control Signals (Input to External Device) Data Signals (Output from External Device) Data Signals (Input to DSP) 6 7 8 2 Clock route delay Minimum DSP hold time Minimum DSP setup time External device hold time requirement External device setup time requirement Control signal route delay External device hold time External device access time DSP hold time requirement DSP setup time requirement Data route delay
10 11
9
Control signals include data for Writes. Data signals are generated during Reads from an external device.
Figure 3-4. Board-Level Input/Output Timings
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PRODUCT PREVIEW
NO.
DESCRIPTION
Input and Output Clocks
4
Input and Output Clocks
Table 4-1. Timing Requirements for CLKIN for -500 Devices (see Figure 4-1)
-500
NO. 1 2 3 4 tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN low Transition time, CLKIN
PLL MODE x12 MIN 24 0.4C 0.4C 5 MAX 33.3
PLL MODE x6 MIN 13.3 0.4C 0.4C 5 MAX 33.3
x1 (BYPASS) MIN 13.3 0.45C 0.45C 1 MAX 33.3
UNIT ns ns ns ns
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
Table 4-2. Timing Requirements for CLKIN for -600 Devices (see Figure 4-1)
-600 NO. PLL MODE x12 MIN MAX 33.3 tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN low Transition time, CLKIN 20 0.4C 0.4C 5 PLL MODE x6 MIN 13.3 0.4C 0.4C 5 MAX 33.3 x1 (BYPASS) MIN 13.3 0.45C 0.45C 1 MAX 33.3 ns ns ns ns UNIT
PRODUCT PREVIEW
1 2 3 4
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
1 2 CLKIN 3
4
4
Figure 4-1. CLKIN Timing
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Input and Output Clocks
Table 4-3. Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 (see Figure 4-2)
-500 -600 NO. PARAMETER CLKMODE = x1, x6, x12 MIN 1 2 3 4 tc(CKO4) tw(CKO4H) tw(CKO4L) tt(CKO4) Cycle time, CLKOUT4 Pulse duration, CLKOUT4 high Pulse duration, CLKOUT4 low Transition time, CLKOUT4 4P - 0.7 2P - 0.7 2P - 0.7 MAX 4P + 0.7 2P + 0.7 2P + 0.7 1 ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. P = 1/CPU clock frequency in nanoseconds (ns)
1 2 CLKOUT4 3
4
4
Figure 4-2. CLKOUT4 Timing
Table 4-4. Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 (see Figure 4-3)
-500 -600 NO. PARAMETER CLKMODE = x1, x6, x12 MIN 1 2 3 4 tc(CKO6) tw(CKO6H) tw(CKO6L) tt(CKO6) Cycle time, CLKOUT6 Pulse duration, CLKOUT6 high Pulse duration, CLKOUT6 low Transition time, CLKOUT6 6P - 0.7 3P - 0.7 3P - 0.7 MAX 6P + 0.7 3P + 0.7 3P + 0.7 1 ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. P = 1/CPU clock frequency in nanoseconds (ns)
1 2 CLKOUT6 3
4
4
Figure 4-3. CLKOUT6 Timing
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PRODUCT PREVIEW
Input and Output Clocks
Table 4-5. Timing Requirements for AECLKIN for EMIFA (see Figure 4-4)
NO. 1 2 3 4 tc(EKI) tw(EKIH) tw(EKIL) tt(EKI) Cycle time, AECLKIN Pulse duration, AECLKIN high Pulse duration, AECLKIN low Transition time, AECLKIN -500 -600 MIN 6 3.38 3.38 2 MAX 16P ns ns ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the 600 devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. On the 500 devices, 100-MHz operation is achievable if the requirements of the EMIF Device Speed section are met.
1 2
4
PRODUCT PREVIEW
AECLKIN 3 4
Figure 4-4. ECLKIN Timing for EMIFA
Table 4-6. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the EMIFA Module#|| (see Figure 4-5)
NO. 1 2 3 4 5 6 tc(EKO1) tw(EKO1H) tw(EKO1L) tt(EKO1) td(EKIH-EKO1H) td(EKIL-EKO1L) PARAMETER Cycle time, AECLKOUT1 Pulse duration, AECLKOUT1 high Pulse duration, AECLKOUT1 low Transition time, AECLKOUT1 Delay time, AECLKIN high to AECLKOUT1 high Delay time, AECLKIN low to AECLKOUT1 low 1 1 -500 -600 MIN E - 0.7 EH - 0.7 EL - 0.7 MAX E + 0.7 EH + 0.7 EL + 0.7 1 8 8 ns ns ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. # E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. || EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
AECLKIN 6 5 AECLKOUT1 2 1 3
4
4
Figure 4-5. AECLKOUT1 Timing for the EMIFA Module
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Input and Output Clocks
Table 4-7. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module (see Figure 4-6)
NO. 1 2 3 4 5 6 tc(EKO2) tw(EKO2H) tw(EKO2L) tt(EKO2) td(EKIH-EKO2H) td(EKIH-EKO2L) PARAMETER MIN Cycle time, AECLKOUT2 Pulse duration, AECLKOUT2 high Pulse duration, AECLKOUT2 low Transition time, AECLKOUT2 Delay time, ECLKIN high to AECLKOUT2 high Delay time, ECLKIN high to AECLKOUT2 low 3 3 NE - 0.7 0.5NE - 0.7 0.5NE - 0.7 -500 -600 MAX NE + 0.7 0.5NE + 0.7 0.5NE + 0.7 1 8 8 ns ns ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. N = the EMIF input clock divider; N = 1, 2, or 4.
5 AECLKIN
6
1 2 AECLKOUT2 3 4 4
Figure 4-6. AECLKOUT2 Timing for the EMIFA Module
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PRODUCT PREVIEW
Asynchronous Memory Timing
5
Asynchronous Memory Timing
Table 5-1. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module (see Figure 5-1 and Figure 5-2)
NO. 3 4 6 7 tsu(EDV-AREH) th(AREH-EDV) tsu(ARDY-EKO1H) th(EKO1H-ARDY) Setup time, AEDx valid before AARE high Hold time, AEDx valid after AARE high Setup time, AARDY valid before AECLKOUT1 high Hold time, AARDY valid after AECLKOUT1 high
-500 -600 MIN 6.5 1 3 1 MAX
UNIT ns ns ns
ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers.
Table 5-2. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module (see Figure 5-1 and Figure 5-2)
PRODUCT PREVIEW
NO. 1 2 5 8 9 tosu(SELV-AREL) toh(AREH-SELIV) td(EKO1H-AREV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKO1H-AWEV)
PARAMETER Output setup time, select signals valid to AARE low Output hold time, AARE high to select signals invalid Delay time, AECLKOUT1 high to AARE valid Output setup time, select signals valid to AAWE low Output hold time, AAWE high to select signals invalid
-500 -600 MIN RS * E - 1.5 RH * E - 1.9 1 WS * E - 1.7 WH * E - 1.8 7 MAX
UNIT ns ns ns ns ns
10 Delay time, AECLKOUT1 high to AAWE valid 1.3 7.1 ns RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT1 period in ns for EMIFA Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0].
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Asynchronous Memory Timing
Setup = 2 AECLKOUT1 1 ACEx 1 ABE[7:0] 1 AEA[22:3] Address 3 4 AED[63:0] 1 AAOE/ASDRAS/ASOE 5 AARE/ASDCAS/ASADS/ASRE AAWE/ASDWE/ASWE 6 AARDY AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. 7 6 5 Read Data 2 BE 2 2 2 Strobe = 3 Not Ready Hold = 2
7
Figure 5-1. Asynchronous Memory Read Timing for EMIFA
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PRODUCT PREVIEW
Asynchronous Memory Timing
Setup = 2 AECLKOUT1 8 ACEx 8 ABE[7:0] 8 AEA[22:3] 8 AED[63:0] AAOE/ASDRAS/ASOE AARE/ASDCAS/ASADS/ASRE 10 10 Write Data Address 9 BE 9 9 9 Hold = 2
Strobe = 3
Not Ready
PRODUCT PREVIEW
AAWE/ASDWE/ASWE 7 6 AARDY AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. 6 7
Figure 5-2. Asynchronous Memory Write Timing for EMIFA
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Programmable Synchronous Interface Timing
6
Programmable Synchronous Interface Timing
Table 6-1. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module (see Figure 6-1)
-500 -600 MIN 2 1.5 MAX UNIT ns ns
NO. 6 7 tsu(EDV-EKOxH) th(EKOxH-EDV) Setup time, read AEDx valid before AECLKOUTx high Hold time, read AEDx valid after AECLKOUTx high
MIN 3.1 1.5
MAX
Table 6-2. Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for EMIFA Module (see Figure 6-1-Figure 6-3)
-500 NO. 1 2 3 4 5 8 9 10 11 td(EKOxH-CEV) td(EKOxH-BEV) td(EKOxH-BEIV) td(EKOxH-EAV) td(EKOxH-EAIV) td(EKOxH-ADSV) td(EKOxH-OEV) td(EKOxH-EDV) td(EKOxH-EDIV) td(EKOxH-WEV) PARAMETER Delay time, AECLKOUTx high to ACEx valid Delay time, AECLKOUTx high to BEx valid Delay time, AECLKOUTx high to ABEx invalid Delay time, AECLKOUTx high to AEAx valid Delay time, AECLKOUTx high to AEAx invalid Delay time, AECLKOUTx high to ASADS/ASRE valid Delay time, AECLKOUTx high to, ASOE valid Delay time, AECLKOUTx high to AEDx valid Delay time, AECLKOUTx high to AEDx invalid 1.3 1.3 1.3 1.3 6.4 6.4 6.4 1.3 1.3 6.4 1.3 1.3 1.3 4.9 4.9 4.9 MIN 1.3 MAX 6.4 6.4 1.3 4.9 -600 MIN 1.3 MAX 4.9 4.9 UNIT ns ns ns ns ns ns ns ns
12 Delay time, AECLKOUTx high to ASWE valid 1.3 6.4 1.3 4.9 ns The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1). - Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
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ns
Programmable Synchronous Interface Timing
READ latency = 2 AECLKOUTx 1 ACEx ABE[7:0] AEA[22:3] 2 BE1 4 EA1 EA2 6 AED[63:0] 8 AARE/ASDCAS/ASADS/ ASRE 9 AAOE/ASDRAS/ASOE AAWE/ASDWE/ASWE 9 Q1 EA3 EA4 7 Q2 Q3 Q4 8 3 BE2 BE3 BE4 5 1
PRODUCT PREVIEW
The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFA CE Space Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1). - Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2 AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/AsWE operate as ASADS/ASRE, ASOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 6-1. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)
130
SPRS200B
July 2002 - Revised May 2003
Programmable Synchronous Interface Timing
AECLKOUTx 1 ACEx 2 BE1 4 EA1 10 AED[63:0] AARE/ASDCAS/ASADS/ASRE AAOE/ASDRAS/ASOE 12 AAWE/ASDWE/ASWE The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1). - Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2 AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE, respectively, during programmable synchronous interface accesses. 12 10 Q1 8 3 BE2 BE3 BE4 5 EA2 EA3 EA4 11 Q2 Q3 Q4 8 1
ABE[7:0]
AEA[22:3]
Figure 6-2. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)
July 2002 - Revised May 2003
SPRS200B
131
PRODUCT PREVIEW
Programmable Synchronous Interface Timing
Write Latency = 1 AECLKOUTx 1 ACEx ABE[7:0] AEA[22:3] AED[63:0] 8 AARE/ASDCAS/ASADS/ ASRE AAOE/ASDRAS/ASOE 12 AAWE/ASDWE/ASWE 12 2 BE1 4 EA1 10 EA2 10 Q1 EA3 Q2 EA4 11 Q3 Q4 8 3 BE2 BE3 BE4 5 1
PRODUCT PREVIEW
The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1). - Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, AsOE, and ASWE, respectively, during programmable synchronous interface accesses.
Figure 6-3. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1)
132
SPRS200B
July 2002 - Revised May 2003
Synchronous DRAM Timing
7
Synchronous DRAM Timing
Table 7-1. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 7-1)
-500 -600 MIN 0.6 1.8 MAX UNIT ns ns
NO. 6 7 tsu(EDV-EKO1H) th(EKO1H-EDV) Setup time, read AEDx valid before AECLKOUT1 high Hold time, read AEDx valid after AECLKOUT1 high
MIN 2.1 2.5
MAX
Table 7-2. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM Cycles for EMIFA Module (see Figure 7-1-Figure 7-8)
-500 NO. 1 2 3 4 5 8 9 10 11 12 13 14 td(EKO1H-CEV) td(EKO1H-BEV) td(EKO1H-BEIV) td(EKO1H-EAV) td(EKO1H-EAIV) td(EKO1H-CASV) td(EKO1H-EDV) td(EKO1H-EDIV) td(EKO1H-WEV) td(EKO1H-RAS) td(EKO1H-ACKEV) td(EKO1H-PDTV) PARAMETER Delay time, AECLKOUT1 high to ACEx valid Delay time, AECLKOUT1 high to ABEx valid Delay time, AECLKOUT1 high to ABEx invalid Delay time, AECLKOUT1 high to AEAx valid Delay time, AECLKOUT1 high to AEAx invalid Delay time, AECLKOUT1 high to ASDCAS valid Delay time, AECLKOUT1 high to AEDx valid Delay time, AECLKOUT1 high to AEDx invalid Delay time, AECLKOUT1 high to ASDWE valid Delay time, AECLKOUT1 high to ASDRAS valid Delay time, AECLKOUT1 high to ASDCKE valid Delay time, AECLKOUT1 high to PDT valid 1.3 1.3 1.3 1.3 1.3 6.4 6.4 6.4 6.4 1.3 1.3 6.4 6.4 1.3 1.3 1.3 1.3 1.3 4.9 4.9 4.9 4.9 1.3 6.4 1.3 1.3 4.9 4.9 MIN 1.3 MAX 6.4 6.4 1.3 4.9 -600 MIN 1.3 MAX 4.9 4.9 UNIT ns ns ns ns ns ns ns ns ns ns ns ns
July 2002 - Revised May 2003
SPRS200B
133
PRODUCT PREVIEW
Synchronous DRAM Timing
READ AECLKOUT1 1 ACEx ABE[7:0] 4 Bank 4 Column 4 AEA13 6 AED[63:0] AAOE/ASDRAS/ASOE D1 7 D2 D3 D4 2 BE1 5 3 BE2 BE3 BE4 1
AEA[22:14] AEA[12:3]
5
5
PRODUCT PREVIEW
AARE/ASDCAS/ASADS/ ASRE AAWE/ASDWE/ASWE
8
8
14 PDT
14
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11, respectively. PDTRL equals 00 (zero latency) in Figure 7-1.
Figure 7-1. SDRAM Read Command (CAS Latency 3) for EMIFA
134
SPRS200B
July 2002 - Revised May 2003
Synchronous DRAM Timing
WRITE AECLKOUT1 1 ACEx 2 ABE[7:0] 4 AEA[22:14] 4 AEA[12:3] 4 AEA13 9 AED[63:0] AAOE/ASDRAS/ASOE AARE/ASDCAS/ASADS/ ASRE 11 AAWE/ASDWE/ASWE 14 PDT AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as AsDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 7-2. 14 11 D1 9 D2 D3 D4 10 Column 5 Bank 5 BE1 5 4 BE2 BE3 BE4 3 2
Figure 7-2. SDRAM Write Command for EMIFA
July 2002 - Revised May 2003
SPRS200B
135
PRODUCT PREVIEW
8
8
Synchronous DRAM Timing
ACTV AECLKOUT1 1 ACEx ABE[7:0] 4 Bank Activate 4 Row Address 4 Row Address 5 1
AEA[22:14] AEA[12:3]
5
5
AEA13 AED[63:0]
12 AAOE/ASDRAS/ASOE AARE/ASDCAS/ASADS/ ASRE AAWE/ASDWE/ASWE
12
PRODUCT PREVIEW
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses.
Figure 7-3. SDRAM ACTV Command for EMIFA
DCAB AECLKOUT1 1 ACEx ABE[7:0] AEA[22:14, 12:3] 4 AEA13 AED[63:0] 12 AAOE/ASDRAS/ASOE AARE/ASDCAS/ASADS/ ASRE AAWE/ASDWE/ASWE AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. 12 5 1
11
11
Figure 7-4. SDRAM DCAB Command for EMIFA
136
SPRS200B
July 2002 - Revised May 2003
Synchronous DRAM Timing
DEAC AECLKOUT1 1 ACEx ABE[7:0] 4 AEA[22:14] AEA[12:3] 4 AEA13 AED[63:0] 12 AAOE/ASDRAS/ASOE AARE/ASDCAS/ASADS/ ASRE AAWE/ASDWE/ASWE AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. 12 5 Bank 5 1
Figure 7-5. SDRAM DEAC Command for EMIFA
REFR AECLKOUT1 1 ACEx ABE[7:0] AEA[22:14, 12:3] 1
AEA13 AED[63:0]] 12 AAOE/ASDRAS/ASOE AARE/ASDCAS/ASADS/ ASRE 8 8 12
AAWE/ASDWE/ASWE AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses.
Figure 7-6. SDRAM REFR Command for EMIFA
July 2002 - Revised May 2003
SPRS200B
137
PRODUCT PREVIEW
11
11
Synchronous DRAM Timing
MRS AECLKOUT1 1 ACEx ABE[7:0] 4 MRS value 5 1
AEA[22:3] AED[63:0]
12 AAOE/ASDRAS/ ASOE AARE/ASDCAS/ASADS/ ASRE AAWE/ASDWE/ASWE
12
8
8
11
11
PRODUCT PREVIEW
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses.
Figure 7-7. SDRAM MRS Command for EMIFA
TRAS cycles Self Refresh AECLKOUT1 ACEx ABE[7:0] AEA[22:14, 12:3] AEA13 AED[63:0] AAOE/ASDRAS/ASOE End Self-Refresh
AARE/ASDCAS/ ASADS/ASRE
AAWE/ASDWE/ASWE 13 ASDCKE AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS, respectively, during SDRAM accesses. 13
Figure 7-8. SDRAM Self-Refresh Timing for EMIFA
138
SPRS200B
July 2002 - Revised May 2003
HOLD/HOLDA Timing
8
HOLD/HOLDA Timing
Table 8-1. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module (see Figure 8-1)
-500 -600 MIN E MAX UNIT ns
NO. 3 toh(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
MIN E
MAX
Table 8-2. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA Cycles for EMIFA Module (see Figure 8-1)
-500 NO. 1 2 4 5 6 7 td(HOLDL-EMHZ) td(EMHZ-HOLDAL) td(HOLDH-EMLZ) td(EMLZ-HOLDAH) td(HOLDL-EKOHZ) td(HOLDH-EKOLZ) PARAMETER Delay time, HOLD low to EMIFA Bus high impedance Delay time, EMIF Bus high impedance to HOLDA low Delay time, HOLD high to EMIF Bus low impedance Delay time, EMIFA Bus low impedance to HOLDA high Delay time, HOLD low to AECLKOUTx high impedance Delay time, HOLD high to AECLKOUTx low impedance MIN 2E 0 2E 0 2E 2E MAX 2E 7E 2E 7E -600 MIN 2E 0 2E 0 2E 2E MAX 2E 7E 2E 7E UNIT ns ns ns ns ns
DSP Owns Bus
External Requestor Owns Bus 3
DSP Owns Bus
HOLD 2 HOLDA EMIFA Bus 1 C64x 4 C64x 5
AECLKOUTx 6 AECLKOUTx EMIFA Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT. 7
Figure 8-1. HOLD/HOLDA Timing for EMIFA
July 2002 - Revised May 2003
SPRS200B
139
PRODUCT PREVIEW
ns E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. EMIFA Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT. The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 8-1. All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
BUSREQ Timing
9
BUSREQ Timing
Table 9-1. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module (see Figure 9-1)
-500 NO. 1 td(AEKO1H-ABUSRV) PARAMETER Delay time, AECLKOUT1 high to ABUSREQ valid MIN 0.6 MAX 7.1 -600 MIN 1 MAX 5.5 UNIT ns
AECLKOUT1
1 ABUSREQ
1
Figure 9-1. BUSREQ Timing for EMIFA
PRODUCT PREVIEW
140 SPRS200B
July 2002 - Revised May 2003
Reset Timing
10
Reset Timing
Table 10-1. Timing Requirements for Reset (see Figure 10-1)
-500 -600 MIN MAX s
NO. 1 16 17 tw(RST) tsu(boot) Width of the RESET pulse Setup time, boot configuration bits valid before RESET high
UNIT
ns th(boot) Hold time, boot configuration bits valid after RESET high 4E or 4C ns AEA[22:19], LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], PCIEEAI, and HD5/AD5 are the boot configuration pins during device reset. E = 1/ECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns. Select the MIN parameter value, whichever value is larger.
250 4E or 4C
Table 10-2. Switching Characteristics Over Recommended Operating Conditions During Reset# (see Figure 10-1)
NO. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 td(RSTL-ECKI) td(RSTH-ECKI) td(RSTL-ECKO1HZ) td(RSTH-ECKO1V) td(RSTL-EMIFZHZ) td(RSTH-EMIFZV) td(RSTL-EMIFHIV) td(RSTH-EMIFHV) td(RSTL-EMIFLIV) td(RSTH-EMIFLV) td(RSTL-LOWIV) td(RSTH-LOWV) td(RSTL-ZHZ) td(RSTH-ZV) PARAMETER Delay time, RESET low to ECLKIN synchronized internally Delay time, RESET high to ECLKIN synchronized internally Delay time, RESET low to ECLKOUT1 high impedance Delay time, RESET high to ECLKOUT1 valid Delay time, RESET low to EMIF Z high impedance Delay time, RESET high to EMIF Z valid Delay time, RESET low to EMIF high group invalid Delay time, RESET high to EMIF high group valid Delay time, RESET low to EMIF low group invalid Delay time, RESET high to EMIF low group valid Delay time, RESET low to low group invalid Delay time, RESET high to low group valid Delay time, RESET low to Z group high impedance Delay time, RESET high to Z group valid 0 2P 8P 0 11P 2E 8P + 20E 2E 16E 2E 8P + 20E -500 -600 MIN 2E 2E 2E 8P + 20E 3P + 4E 8P + 20E MAX 8P + 20E ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. # EMIF Z group consists of: AEA[22:3], AED[63:0], ACE[3:0], ABE[7:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT. EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low) Low group consists of: XSP_CS, XSP_CLK/MDCLK, and XSP_DO/MDIO; all of which apply only when PCI EEPROM is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet. Z group consists of: HD[31:0]/AD[31:0] and the muxed EMAC output pins, XSP_CLK/MDCLK, XSP_DO/MDIO, VP0D[2]/CLKX0, VP1D[2]/CLKX1, VP0D[3]/FSX0, VP1D[3]/FSX1, VP0D[4]/DX0, VP1D[4]/DX1, VP0D[8]/CLKR0, VP1D[8]/CLKR1, VP0D[7]/FSR0, VP1D[7]/FSR1, TOUT0, TOUT1, VDAC/GP0[8]/PCI66, GP0[7:0], GP0[10]/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP0[13]/PINTA, GP0[11]/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, VP0D[19:9, 6,5,1,0], VP1D[19:9, 6,5,1,0], and VP2D[19:0].
July 2002 - Revised May 2003
SPRS200B
141
PRODUCT PREVIEW
3P + 20E
ns
Reset Timing
CLKOUT4 CLKOUT6 1 RESET 2 AECLKIN 4 AECLKOUT1 AECLKOUT2 6 EMIF Z Group 8 EMIF High Group 10 11 9 7 5 3
PRODUCT PREVIEW
EMIF Low Group 12 Low Group 14 Z Group 17 Boot and Device Configuration Inputs EMIF Z group consists of: 16 13
15
AEA[22:3], AED[63:0], ACE[3:0], ABE[7:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT. EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low) Low group consists of: XSP_CS, XSP_CLK/MDCLK, and XSP_DO/MDIO; all of which apply only when PCI EEPROM is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet. Z group consists of: HD[31:0]/AD[31:0] and the muxed EMAC output pins, XSP_CLK/MDCLK, XSP_DO/MDIO, VP0D[2]/CLKX0, VP1D[2]/CLKX1, VP0D[3]/FSX0, VP1D[3]/FSX1, VP0D[4]/DX0, VP1D[4]/DX1, VP0D[8]/CLKR0, VP1D[8]/CLKR1, VP0D[7]/FSR0, VP1D[7]/FSR1, TOUT0, TOUT1, VDAC/GP0[8]/PCI66, GP0[7:0], GP0[10]/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP0[13]/PINTA, GP0[11]/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, VP0D[19:9, 6,5,1,0], VP1D[19:9, 6,5,1,0], and VP2D[19:0]. If AEA[22:19], LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], PCIEEAI, and HD5/AD5 pins are actively driven, care must be taken to ensure no timing contention between parameters 6, 7, 14, 15, 16, and 17. Boot and Device Configurations Inputs (during reset) include: AEA[22:19],LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], PCIEEAI, and HD5/AD5 The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.
Figure 10-1. Reset Timing
142
SPRS200B
July 2002 - Revised May 2003
External Interrupt Timing
11
External Interrupt Timing
Table 11-1. Timing Requirements for External Interrupts (see Figure 11-1)
-500 -600 MIN MAX ns ns
NO. 1 2 tw(ILOW) tw(IHIGH) Width of the interrupt pulse low Width of the interrupt pulse high
UNIT
4P 4P
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2
1 EXT_INTx, NMI
Figure 11-1. External/NMI Interrupt Timing
July 2002 - Revised May 2003
SPRS200B
143
PRODUCT PREVIEW
Multichannel Audio Serial Port (McASP) Timing
12
Multichannel Audio Serial Port (McASP) Timing
Table 12-1. Timing Requirements for McASP (see Figure 12-1 and Figure 12-2)
-500 -600 MIN MAX ns ns ns ns ns ns ns ns ns ns ns ns
NO. 1 2 3 4 5 6 7 8 tc(AHCKRX) tw(AHCKRX) tc(CKRX) tw(CKRX) tsu(FRXC-KRX) th(CKRX-FRX) tsu(AXR-CKRX) th(CKRX-AXR) Cycle time, AHCLKR/X Pulse duration, AHCLKR/X high or low Cycle time, ACLKR/X Pulse duration, ACLKR/X high or low Setup time, AFSR/X input valid before ACLKR/X latches data Hold time, AFSR/X input valid after ACLKR/X latches data Setup time, AXR input valid before ACLKR/X latches data Hold time, AXR input valid after ACLKR/X latches data ACLKR/X ext ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext
UNIT
20 10 33 16.5 5 5 5 5 5 5 5 5
PRODUCT PREVIEW
Table 12-2. Switching Characteristics Over Recommended Operating Conditions for McASP (see Figure 12-1 and Figure 12-2)
NO. 9 10 11 12 13 14 15 tc(AHCKRX) tw(AHCKRX) tc(CKRX) tw(CKRX) td(CKRX-FRX) td(CKRX-AXRV) tdis(CKRX-AXRHZ) PARAMETER MIN Cycle time, AHCLKR/X Pulse duration, AHCLKR/X high or low Cycle time, ACLKR/X Pulse duration, ACLKR/X high or low Delay time, ACLKR/X transmit edge to AFSX/R output valid Delay time, ACLKR/X transmit edge to AXR output valid Disable time, AXR high impedance following last data bit from ACLKR/X transmit edge ACLKR/X int ACLKR/X int ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext 20 10 33 16.5 0 0 0 0 0 0 10 10 10 10 10 10 -500 -600 MAX ns ns ns ns ns ns ns ns ns ns UNIT
144
SPRS200B
July 2002 - Revised May 2003
Multichannel Audio Serial Port (McASP) Timing
2 1 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 4 3 ACLKR/X (Falling Edge Polarity) ACLKR/X (Rising Edge Polarity) 6 5 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 4 2
Figure 12-1. McASP Input Timings
July 2002 - Revised May 2003
SPRS200B
145
PRODUCT PREVIEW
Multichannel Audio Serial Port (McASP) Timing
10 9 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 12 12 10
11 ACLKR/X (Falling Edge Polarity) ACLKR/X (Rising Edge Polarity)
13 13 AFSR/X (Bit Width, 0 Bit Delay)
13 13
AFSR/X (Bit Width, 1 Bit Delay)
PRODUCT PREVIEW
AFSR/X (Bit Width, 2 Bit Delay) 13 AFSR/X (Slot Width, 0 Bit Delay) 13 13
AFSR/X (Slot Width, 1 Bit Delay) 14 AFSR/X (Slot Width, 2 Bit Delay) 14 14 14 14 14 15
AXR[n] (Data Out/Transmit) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31
Figure 12-2. McASP Output Timings
146
SPRS200B
July 2002 - Revised May 2003
Inter-Integrated Circuits (I2C) Timing
13
Inter-Integrated Circuits (I2C) Timing
Table 13-1. Timing Requirements for I2C Timings (see Figure 13-1)
-500 -600
NO.
STANDARD MODE MIN MAX
FAST MODE MIN 2.5 0.6 0.6 1.3 0.6 100 0 MAX
UNIT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
tc(SCL)
Cycle time, SCL
10 4.7 4 4.7 4 250 0 4.7 1000 1000 300 300 4 400
s s s s s ns 0.9 300 300 300 300 50 400 s ns ns ns ns s ns pF s
Setup time, SCL high before SDA low (for a repeated START tsu(SCLH-SDAL) condition) Hold time, SCL low after SDA low (for a START and a repeated th(SCLL-SDAL) START condition) tw(SCLL) tw(SCLH) Pulse duration, SCL low Pulse duration, SCL high
tsu(SDAV-SDLH) Setup time, SDA valid before SCL high th(SDA-SDLL) Hold time, SDA valid after SCL low (For I2C bus devices) tw(SDAH) tr(SDA) tr(SCL) tf(SDA) Pulse duration, SDA high between STOP and START conditions Rise time, SDA Rise time, SCL Fall time, SDA
20 + 0.1Cb# 20 + 0.1Cb# 20 + 0.1Cb# 0.6 0
tf(SCL) Fall time, SCL tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) tw(SP) Cb# Pulse duration, spike (must be suppressed) Capacitive load for each bus line
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. # Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 11 SDA 8 4 10 SCL 1 7 3 Stop Start Repeated Start 12 3 2 5 6 14 13 9
Stop
Figure 13-1. I2C Receive Timings
July 2002 - Revised May 2003
SPRS200B
147
PRODUCT PREVIEW
1.3 20 + 0.1Cb#
Inter-Integrated Circuits (I2C) Timing
Table 13-2. Switching Characteristics for I2C Timings (see Figure 13-2)
-500 -600 NO. PARAMETER STANDARD MODE MIN 16 17 18 19 20 21 22 23 24 25 26 27 28 tc(SCL) Cycle time, SCL td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) Delay time, SDA low to SCL low (for a START and a repeated td(SDAL-SCLL) START condition) tw(SCLL) tw(SCLH) Pulse duration, SCL low Pulse duration, SCL high 10 4.7 4 4.7 4 250 0 4.7 1000 1000 300 300 4 MAX FAST MODE MIN 2.5 0.6 0.6 1.3 0.6 100 0 1.3 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 0.6 0.9 300 300 300 300 10 MAX s s s s s ns s s ns ns ns ns s pF UNIT
td(SDAV-SDLH) Delay time, SDA valid to SCL high tv(SDLL-SDAV) Valid time, SDA valid after SCL low (For I2C bus devices) tw(SDAH) tr(SDA) tr(SCL) tf(SDA) Pulse duration, SDA high between STOP and START conditions Rise time, SDA Rise time, SCL Fall time, SDA
PRODUCT PREVIEW
tf(SCL) Fall time, SCL td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition)
29 Cp Capacitance for each I2C pin 10 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. 26 SDA 23 19 25 SCL 16 22 18 Stop Start Repeated Start 27 18 17 20 21 28 24
Stop
Figure 13-2. I2C Transmit Timings
148
SPRS200B
July 2002 - Revised May 2003
Host-Port Interface (HPI) Timing
14
Host-Port Interface (HPI) Timing
-500 -600 MIN MAX ns ns ns ns ns ns ns ns ns ns ns Setup time, select signals valid before HSTROBE low Hold time, select signals valid after HSTROBE low Pulse duration, HSTROBE low Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals valid before HAS low Hold time, select signals valid after HAS low Setup time, host data valid before HSTROBE high Hold time, host data valid after HSTROBE high Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. Setup time, HAS low before HSTROBE low Hold time, HAS low after HSTROBE low
Table 14-1. Timing Requirements for Host-Port Interface Cycles (see Figure 14-1 through Figure 14-8)
NO. 1 2 3 4 10 11 12 13 14 18 19 tsu(SELV-HSTBL) th(HSTBL-SELV) tw(HSTBL) tw(HSTBH) tsu(SELV-HASL) th(HASL-SELV) tsu(HDV-HSTBH) th(HSTBH-HDV) th(HRDYL-HSTBL) tsu(HASL-HSTBL) th(HSTBL-HASL) 5 2.4 4P 4P 5 2 5 2.8 2 2 2.1 UNIT
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL. Select the parameter value of 4P or 12.5 ns, whichever is larger.
Table 14-2. Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface Cycles (see Figure 14-1 through Figure 14-8)
NO. 6 7 8 9 15 16 td(HSTBL-HRDYH) td(HSTBL-HDLZ) td(HDV-HRDYL) toh(HSTBH-HDV) td(HSTBH-HDHZ) td(HSTBL-HDV) PARAMETER MIN Delay time, HSTROBE low to HRDY high# Delay time, HSTROBE low to HD low impedance for an HPI read Delay time, HD valid to HRDY low Output hold time, HD valid after HSTROBE high Delay time, HSTROBE high to HD high impedance Delay time, HSTROBE low to HD valid (HPI16 only) 1.3 2 -3 1.5 12 4P + 8 -500 -600 MAX 4P + 8 ns ns ns ns ns ns UNIT
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. # This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is full.
July 2002 - Revised May 2003
SPRS200B
149
PRODUCT PREVIEW
Host-Port Interface (HPI) Timing
HAS 1 HCNTL[1:0] 1 HR/W 1 HHWIL HSTROBE HCS 7 HD[15:0] (output) 6 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 1st half-word 8 2nd half-word 15 9 16 15 9 3 4 3 2 1 2 2 1 2 1 2 2
PRODUCT PREVIEW
Figure 14-1. HPI16 Read Timing (HAS Not Used, Tied High)
HAS 10 HCNTL[1:0] 11 10 HR/W 11 10 HHWIL HSTROBE HCS 7 HD[15:0] (output) 6 1st half-word 8 2nd half-word 18 15 9 16 9 3 4 18 15 10 11 10 11 19 11 10 19 11
HRDY For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 14-2. HPI16 Read Timing (HAS Used)
150
SPRS200B
July 2002 - Revised May 2003
Host-Port Interface (HPI) Timing
HAS 1 2 HCNTL[1:0] 1 HR/W 1 HHWIL 3 4 HSTROBE HCS 12 HD[15:0] (input) 1st half-word 6 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 14 2nd half-word 13 12 13 3 2 1 2 2 1 2
1 2
Figure 14-3. HPI16 Write Timing (HAS Not Used, Tied High)
19 HAS 10 HCNTL[1:0] 11 10 HR/W 11 10 HHWIL 3 4 HSTROBE HCS HD[15:0] (input) 1st half-word 6 HRDY 14 18 12 10 10 11 10
19 11
11
11
18 13 2nd half-word 12 13
For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 14-4. HPI16 Write Timing (HAS Used)
July 2002 - Revised May 2003
SPRS200B
151
PRODUCT PREVIEW
Host-Port Interface (HPI) Timing
HAS 1 HCNTL[1:0] 1 HR/W HSTROBE HCS 7 HD[31:0] (output) 6 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 8 9 15 3 2 2
Figure 14-5. HPI32 Read Timing (HAS Not Used, Tied High)
PRODUCT PREVIEW
19 HAS 11 10 HCNTL[1:0] 11 10 HR/W 18 HSTROBE HCS 7 HD[31:0] (output) 6 HRDY For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 8 9 15 3
Figure 14-6. HPI32 Read Timing (HAS Used)
152
SPRS200B
July 2002 - Revised May 2003
Host-Port Interface (HPI) Timing
HAS 1 HCNTL[1:0] 1 HR/W 3 HSTROBE HCS 12 HD[31:0] (input) 6 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 14 13 2 2
Figure 14-7. HPI32 Write Timing (HAS Not Used, Tied High)
19 HAS 11 10 HCNTL[1:0] 11 10 HR/W 3 18 HSTROBE HCS 12 HD[31:0] (input) 6 HRDY For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 14 13
Figure 14-8. HPI32 Write Timing (HAS Used)
July 2002 - Revised May 2003
SPRS200B
153
PRODUCT PREVIEW
Peripheral Component Interconnect (PCI) Timing
15
Peripheral Component Interconnect (PCI) Timing
Table 15-1. Timing Requirements for PCLK (see Figure 15-1)
-500 [33 MHz] -600 [66 MHz] MIN 15 (or 4P) 6 6 1.5 4 MAX UNIT ns ns ns V/ns
NO. 1 2 3 tc(PCLK) tw(PCLKH) tw(PCLKL) tsr(PCLK) Cycle time, PCLK Pulse duration, PCLK high Pulse duration, PCLK low
MIN 30 (or 4P) 11 11
MAX
4 v/t slew rate, PCLK 1 4 For 3.3-V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN. P = 1/CPU clock frequency in ns. For example when running parts at 600 MHz, use P = 1.67 ns. Select the parameter value, whichever is larger.
1 2 PCLK
4
0.4 DVDD V MIN Peak to Peak for 3.3V signaling
PRODUCT PREVIEW
3 4
Figure 15-1. PCLK Timing Table 15-2. Timing Requirements for PCI Reset (see Figure 15-2)
NO. 1 2 tw(PRST) tsu(PCLKA-PRSTH) Pulse duration, PRST Setup time, PCLK active before PRST high PCLK 1 PRST 2 -500 -600 MIN 1 100 MAX ms s UNIT
Figure 15-2. PCI Reset (PRST) Timing
154
SPRS200B
July 2002 - Revised May 2003
Peripheral Component Interconnect (PCI) Timing
Table 15-3. Timing Requirements for PCI Inputs (see Figure 15-3)
-500 NO. 4 5 tsu(IV-PCLKH) th(IV-PCLKH) Setup time, input valid before PCLK high Hold time, input valid after PCLK high PCLK 4 5 33 MHz MIN 7 0 MAX -600 66 MHz MIN 3 0 MAX ns ns UNIT
PCI Input
Inputs Valid
Figure 15-3. PCI Input Timing (33-/66-MHz) Table 15-4. Switching Characteristics Over Recommended Operating Conditions for PCI Outputs (see Figure 15-4)
-500 NO. 1 2 3 td(PCLKH-OV) td(PCLKH-OLZ) td(PCLKH-OHZ) PARAMETER Delay time, PCLK high to output valid Delay time, PCLK high to output low impedance Delay time, PCLK high to output high impedance PCLK 1 PCI Output 2 3 1 33 MHz MIN 2 2 28 MAX 11 -600 66 MHz MIN 2 2 14 MAX 6 ns ns ns UNIT
Figure 15-4. PCI Output Timing (33-/66-MHz)
July 2002 - Revised May 2003
SPRS200B
155
PRODUCT PREVIEW
Peripheral Component Interconnect (PCI) Timing
Table 15-5. Timing Requirements for Serial EEPROM Interface (see Figure 15-5)
NO. 8 9 tsu(DIV-CLKH) th(CLKH-DIV) Setup time, XSP_DI valid before XSP_CLK high Hold time, XSP_DI valid after XSP_CLK high -500 -600 MIN 50 0 MAX ns ns UNIT
Table 15-6. Switching Characteristics Over Recommended Operating Conditions for Serial EEPROM Interface (see Figure 15-5)
NO. 1 2 3 4 5 tw(CSL) td(CLKL-CSL) td(CSH-CLKH) tw(CLKH) tw(CLKL) tosu(DOV-CLKH) PARAMETER MIN Pulse duration, XSP_CS low Delay time, XSP_CLK low to XSP_CS low Delay time, XSP_CS high to XSP_CLK high Pulse duration, XSP_CLK high Pulse duration, XSP_CLK low Output setup time, XSP_DO valid after XSP_CLK high -500 -600 TYP 4092P 0 2046P 2046P 2046P 2046P 2046P MAX ns ns ns ns ns ns ns UNIT
PRODUCT PREVIEW
6 7
toh(CLKH-DOV) Output hold time, XSP_DO valid after XSP_CLK high P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2
1 XSP_CS 3 XSP_CLK 6 XSP_DO 8 XSP_DI 9 7 4 5
Figure 15-5. PCI Serial EEPROM Interface Timing
156
SPRS200B
July 2002 - Revised May 2003
Multichannel Buffered Serial Port (McBSP) Timing
16
Multichannel Buffered Serial Port (McBSP) Timing
Table 16-1. Timing Requirements for McBSP (see Figure 16-1)
-500 -600 MIN 4P 0.5tc(CKRX) - 1 9 1.3 6 3 8 0.9 3 3.1 9 1.3 6 3 ns ns ns ns ns ns MAX ns ns
NO. 2 3 5 6 7 8 10 11 tc(CKRX) tw(CKRX) tsu(FRH-CKRL) th(CKRL-FRH) tsu(DRV-CKRL) th(CKRL-DRV) tsu(FXH-CKXL) th(CKXL-FXH) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Setup time, external FSR high before CLKR low Hold time, external FSR high after CLKR low Setup time, DR valid before CLKR low Hold time, DR valid after CLKR low Setup time, external FSX high before CLKX low Hold time, external FSX high after CLKX low CLKR/X ext CLKR/X ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext
UNIT
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. The maximum bit rate for McBSP-to-McBSP communications is 75 MHz for -600 devices and 66 MHz for -500 devices; therefore, the minimum CLKR/X clock cycle is either four times the CPU cycle time (4P), or 13.3 ns (75 MHz) for -600 devices [or 15 ns (66 MHz) for -500 devices], whichever value is larger. For example, when running parts at 600 MHz (P = 1.67 ns), use 13.3 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 500 MHz (P = 2 ns), use 15 ns as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a Master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a Slave. This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
July 2002 - Revised May 2003
SPRS200B
157
PRODUCT PREVIEW
Multichannel Buffered Serial Port (McBSP) Timing
Table 16-2. Switching Characteristics Over Recommended Operating Conditions for McBSP (see Figure 16-1)
NO. PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Delay time, CLKR high to internal FSR valid Delay time, CLKX high to internal FSX valid Disable time, DX high impedance following last data bit from CLKX high Delay time, CLKX high to DX valid Delay time, FSX high to DX valid CLKR/X int CLKR/X int CLKR int CLKX int 9 12 13 td(CKXH-FXV) tdis(CKXH-DXHZ) td(CKXH-DXV) CLKX ext CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext -500 -600 MIN 1 2 3 4 td(CKSH-CKRXH) tc(CKRX) tw(CKRX) td(CKRH-FRV) 1.4 4P C - 1# -2.1 -1.7 1.7 -3.9 -2.1 -3.9 + D1|| -2.1 + D1|| -2.3 1.9 MAX 10 ns ns C + 1# 3 3 9 4 9 4 + D2|| 9 + D2|| 5.6 ns 9 ns ns ns ns ns UNIT
PRODUCT PREVIEW
14
td(FXH-DXV)
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. The maximum bit rate for McBSP-to-McBSP communications is 75 MHz for -600 devices and 66 MHz for -500 devices; therefore, the minimum CLKR/X clock cycle is either four times the CPU cycle time (4P), or 13.3 ns (75 MHz) for -600 devices [or 15 ns (66 MHz) for -500 devices], whichever value is larger. For example, when running parts at 600 MHz (P = 1.67 ns), use 13.3 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 500 MHz (P = 2 ns), use 15 ns as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a Master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a Slave. # C = H or L S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see footnote above). || Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P
158
SPRS200B
July 2002 - Revised May 2003
Multichannel Buffered Serial Port (McBSP) Timing
CLKS 1 3 3 CLKR 4 FSR (int) 5 FSR (ext) 7 DR 2 3 CLKX 9 FSX (int) 11 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) 10 3 Bit(n-1) 8 (n-2) (n-3) 6 4 2
Figure 16-1. McBSP Timing Table 16-3. Timing Requirements for FSR When GSYNC = 1 (see Figure 16-2)
NO. 1 2 tsu(FRH-CKSH) th(CKSH-FRH) Setup time, FSR high before CLKS high Hold time, FSR high after CLKS high -500 -600 MIN 4 4 MAX ns ns UNIT
CLKS 1 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) 2
Figure 16-2. FSR Timing When GSYNC = 1
July 2002 - Revised May 2003
SPRS200B
159
PRODUCT PREVIEW
Multichannel Buffered Serial Port (McBSP) Timing
Table 16-4. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 16-3)
-500 -600 NO. MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low 12 4 MAX SLAVE MIN 2 - 12P 5 + 24P MAX ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 16-5. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 16-3)
-500 -600 NO. PARAMETER MASTER MIN MAX T+3 L+3 4 L+3 4P + 3 8P + 1.8 12P + 17 16P + 17 12P + 2.8 20P + 17 T-2 L-2 -2 L-2 SLAVE MIN MAX ns ns ns ns ns ns UNIT
PRODUCT PREVIEW
1 2 3 6 7 8
th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ) td(FXL-DXV)
Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX low Disable time, DX high impedance following last data bit from FSX high Delay time, FSX low to DX valid
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 3 Bit(n-1) 5 (n-2) (n-3) (n-4) (n-2) (n-3) (n-4) 2
Figure 16-3. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
160
SPRS200B
July 2002 - Revised May 2003
Multichannel Buffered Serial Port (McBSP) Timing
Table 16-6. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 16-4)
-500 -600 NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 12P 5 + 24P MAX ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 16-7. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 16-4)
-500 -600 NO. PARAMETER MASTER MIN 1 2 3 6 7 th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) tdis(CKXL-DXHZ) td(FXL-DXV) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX low Delay time, FSX low to DX valid L-2 T-2 -2 -2 H-2 MAX L+3 T+3 4 12P + 4 4 12P + 3 H+4 8P + 2 20P + 17 20P + 17 16P + 17 SLAVE MIN MAX ns ns ns ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
CLKX 1 FSX 6 Bit 0 7 Bit(n-1) 4 DR Bit 0 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
DX
Figure 16-4. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
July 2002 - Revised May 2003
SPRS200B
161
PRODUCT PREVIEW
Multichannel Buffered Serial Port (McBSP) Timing
Table 16-8. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 16-5)
-500 -600 NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 12P 5 + 24P MAX ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 16-9. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 16-5)
-500 -600 NO. PARAMETER MASTER MIN MAX T+3 H+3 4 12P + 4 H+3 4P + 3 8P + 2 12P + 17 16P + 17 20P + 17 T-2 H-2 -2 H-2 SLAVE MIN MAX ns ns ns ns ns ns UNIT
PRODUCT PREVIEW
1 2 3 6 7 8
th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ) tdis(FXH-DXHZ) td(FXL-DXV)
Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX high Disable time, DX high impedance following last data bit from FSX high Delay time, FSX low to DX valid
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX). CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 Bit(n-1) 5 (n-2) (n-3) (n-4) 3 (n-2) (n-3) (n-4) 2
Figure 16-5. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
162
SPRS200B
July 2002 - Revised May 2003
Multichannel Buffered Serial Port (McBSP) Timing
Table 16-10. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 16-6)
-500 -600 NO. MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 12P 5 + 24P MAX ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 16-11. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 16-6)
-500 -600 NO. PARAMETER MASTER MIN 1 2 3 6 7 th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) td(FXL-DXV) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX high Delay time, FSX low to DX valid H-2 T-2 -2 -2 L-2 MAX H+3 T+1 4 12P + 4 4 12P + 3 L+4 8P + 2 20P + 17 20P + 17 16P + 17 SLAVE MIN MAX ns ns ns ns ns UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
CLKX 1 FSX 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 7 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
Figure 16-6. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
July 2002 - Revised May 2003
SPRS200B
163
PRODUCT PREVIEW
Video Port Timing (VP0, VP1, VP2)
17
Video Port Timing (VP0, VP1, VP2)
Table 17-1. Timing Requirements for Video Capture Mode for VPxCLKINx (see Figure 17-1)
VCLKIN timing (Video Capture Mode)
-500 -600 MIN 1 2 3 4 tc(VKI) tw(VKIH) tw(VKIL) tt(VKI) Cycle time, VPxCLKINx Pulse duration, VPxCLKINx high Pulse duration, VPxCLKINx low Transition time, VPxCLKINx 12.5 5.4 5.4 2 MAX ns ns ns ns
NO.
UNIT
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
1 2 3
4
PRODUCT PREVIEW
VPxCLKINx
4
Figure 17-1. Video Port Capture VPxCLKINx TIming
17.1 STCLK Timing
Table 17-2. Timing Requirments for STCLK (see Figure 17-2)
NO. 1 2 3 4 tc(STCLK) tw(STCLKH) tw(STCLKL) tt(STCLK) Cycle time, STCLK Pulse duration, STCLK high Pulse duration, STCLK low Transition time, STCLK -500 -600 MIN 33.3 16 16 2 MAX ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
1 2 STCLK 3
4
4
Figure 17-2. STCLK Timing
164
SPRS200B
July 2002 - Revised May 2003
Video Port Timing (VP0, VP1, VP2)
17.2 Video Data and Control Timing (Video Capture Mode)
Table 17-3. Timing Requirements in Video Capture Mode for Video Data and Control Inputs (see Figure 17-3)
NO. 1 2 3 4 tsu(VDATV-VKIH) Setup time, VPxDx valid before VPxCLKINx high th(VDATV-VKIH) Hold time, VPxDx valid after VPxCLKINx high tsu(VCTLV-VKIH) Setup time, VPxCTLx valid before VPxCLKINx high th(VCTLV-VKIH) Hold time, VPxCTLx valid after VPxCLKINx high -500 -600 MIN 2.4 0.5 2.4 0.5 MAX ns ns ns ns UNIT
VPxCLKINx 1 2
VPxD[19:0] (Input) 3 4 VPxCTLx (Input)
Figure 17-3. Video Port Capture Data and Control Input Timing
July 2002 - Revised May 2003
SPRS200B
165
PRODUCT PREVIEW
Video Port Timing (VP0, VP1, VP2)
17.3 VCLKIN Timing (Video Display Mode)
Table 17-4. Timing Requirements for Video Display Mode for VPxCLKINx (see Figure 17-4)
NO. 1 2 3 tc(VKI) tw(VKIH) tw(VKIL) tt(VKI) Cycle time, VPxCLKINx Pulse duration, VPxCLKINx high Pulse duration, VPxCLKINx low -500 -600 MIN 9 4.1 4.1 2 MAX ns ns ns ns UNIT
4 Transition time, VPxCLKINx The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
1 2 VPxCLKINx 3
4
PRODUCT PREVIEW
4
Figure 17-4. Video Port Display VPxCLKINx Timing
17.4 Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx and VPxCLKOUTx (Video Display Mode)
Table 17-5. Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to VPxCLKINx and VPxCLKOUTx (see Figure 17-5)
NO. 13 14 15 16 tsu(VCTLV-VKIH) th(VCTLV-VKIH) tsu(VCTLV-VKOH) th(VCTLV-VKOH) Setup time, VPxCTLx valid before VPxCLKINx high Hold time, VPxCTLx valid after VPxCLKINx high Setup time, VPxCTLx valid before VPxCLKOUTx high Hold time, VPxCTLx valid after VPxCLKOUTx high -500 -600 MIN 2.4 0.5 7.4 -0.9 MAX ns ns ns ns UNIT
Assuming non-inverted VPxCLKOUTx signal.
166
SPRS200B
July 2002 - Revised May 2003
Video Port Timing (VP0, VP1, VP2)
Table 17-6. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx (see Figure 17-5)
NO. 1 2 3 4 5 6 7 8 9 10 11 tc(VKO) tw(VKOH) tw(VKOL) tt(VKO) td(VKIH-VKOH) td(VKIL-VKOL) td(VKIH-VKOL) td(VKIL-VKOH) td(VKIH-VPOUTV) td(VKIH-VPOUTIV) td(VKOH-VPOUTV) td(VKOH-VPOUTIV) PARAMETER Cycle time, VPxCLKOUTx Pulse duration, VPxCLKOUTx high Pulse duration, VPxCLKOUTx low Transition time, VPxCLKOUTx Delay time, VPxCLKINx high to VPxCLKOUTx high Delay time, VPxCLKINx low to VPxCLKOUTx low Delay time, VPxCLKINx high to VPxCLKOUTx low Delay time, VPxCLKINx low to VPxCLKOUTx high Delay time, VPxCLKINx high to VPxOUT valid Delay time, VPxCLKINx high to VPxOUT invalid Delay time, VPxCLKOUTx high to VPxOUT valid Delay time, VPxCLKOUTx high to VPxOUT invalid 1.7 4 1.4 1.4 1.4 1.4 -500 -600 MIN V - 0.7 VH - 0.7 VL - 0.7 MAX V + 0.7 VH + 0.7 VL + 0.7 1 5 5 5 5 9 ns ns ns ns ns ns ns ns ns ns ns ns UNIT
12 -0.2 V = the video input clock (VPxCLKINx) period in ns. VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns. Assuming non-inverted VPxCLKOUTx signal. VPxOUT consists of VPxCTLx and VPxD[19:0]
VPxCLKINx 5 VPxCLKOUTx [VCLK2P = 0] VPxCLKOUTx (Inverted) [VCLK2P = 1] 4 7 1 3 2 6
4 8 12 10 15 16 14 13
11 VPxCTLx, VPxD[19:0] (Outputs) 9
VPxCTLx (Input)
Figure 17-5. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to VPxCLKINx and VPxCLKOUTx
July 2002 - Revised May 2003
SPRS200B
167
PRODUCT PREVIEW
Video Port Timing (VP0, VP1, VP2)
17.5 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx)
Table 17-7. Timing Requirements for Dual-Display Sync Mode for VPxCLKINx (see Figure 17-6)
NO. 1 tskr(VKI) Skew rate, VPxCLKINx before VPyCLKINy -500 -600 MIN MAX 500 ps UNIT
VPxCLKINx
1 VPyCLKINy
Figure 17-6. Video Port Dual-Display Sync Timing
PRODUCT PREVIEW
168 SPRS200B
July 2002 - Revised May 2003
Ethernet Media Access Controller (EMAC) Timing
18
Ethernet Media Access Controller (EMAC) Timing
Table 18-1. Timing Requirements for MRCLK (see Figure 18-1)
-500 -600 MIN MAX ns ns ns 3 ns
NO. 1 2 3 tc(MRCLK) tw(MRCLKH) tw(MRCLKL) tt(MRCLK) Cycle time, MRCLK Pulse duration, MRCLK high Pulse duration, MRCLK low
UNIT
25 11 11
4 Transition time, MRCLK The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
1 2 MRCLK 3
4
4
Figure 18-1. MRCLK Timing (EMAC - Receive) Table 18-2. Timing Requirements for MTCLK (see Figure 18-1)
NO. 1 2 3 tc(MTCLK) tw(MTCLKH) tw(MTCLKL) tt(MTCLK) Cycle time, MTCLK Pulse duration, MTCLK high Pulse duration, MTCLK low -500 -600 MIN 400 180 180 5 MAX ns ns ns ns UNIT
4 Transition time, MTCLK The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
1 2 MTCLK 3
4
4
Figure 18-2. MTCLK Timing (EMAC - Transmit)
July 2002 - Revised May 2003
SPRS200B
169
PRODUCT PREVIEW
Ethernet Media Access Controller (EMAC) Timing
Table 18-3. Timing Requirements for EMAC MII Receive 10/100 Mbit/s (see Figure 18-3)
NO. 1 2 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high MIN 8 8 MAX UNIT ns ns
Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER.
MRXD3-MRXD0 is driven by the PHY on the falling edge of MRCLK. MRXD3-MRXD0 timing must be met during clock periods when MRXDV is asserted. MRXDV is asserted and deasserted by the PHY on the falling edge of MRCLK. MRXER is driven by the PHY on the falling edge of MRCLK (xx = 00-01).
1 2 MRCLK (Input)
MRXD3-MRXD0, MRXDV, MRXER (Inputs)
PRODUCT PREVIEW
Figure 18-3. EMAC Receive Interface Timing Table 18-4. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s (see Figure 18-4)
NO. 1 td(MTCLKH-MTXD) PARAMETER Delay time, MTCLK high to transmit selected signals valid MIN 5 MAX 25 UNIT ns
Transmit selected signals include: MTXD3-MTXD0, and MTXEN.
MTXD3-MTXD0 is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and deasserted by the reconciliation sublayer synchronous to the MTCLK rising edge.
1 MTCLK (Input)
MTXD3-MTXD0, MTXEN (Outputs)
Figure 18-4. EMAC Transmit Interface Timing
170
SPRS200B
July 2002 - Revised May 2003
Management Data Input/Output (MDIO) Timing
19
NO. 1 2 3 4 5
Management Data Input/Output (MDIO) Timing
Table 19-1. Timing Requirements for MDIO Input (see Figure 19-1)
MIN tc(MDCLK) tw(MDCLK) tt(MDCLK) tsu(MDIO-MDCLKH) th(MDCLKH-MDIO) Cycle time, MDCLK Pulse duration, MDCLK high/low Transition time, MDCLK Setup time, MDIO data input valid before MDCLK high Hold time, MDIO data input valid after MDCLK high 10 10 400 180 5 MAX UNIT ns ns ns ns ns
1
MDCLK
4 5
Figure 19-1. MDIO Input Timing Table 19-2. Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see Figure 19-2)
NO. 7 td(MDCLKL-MDIO) PARAMETER Delay time, MDCLK low to MDIO data output valid MIN MAX 100 UNIT ns
1
MDCLK
7
MDIO (output)
Figure 19-2. MDIO Output Timing
July 2002 - Revised May 2003
SPRS200B
171
PRODUCT PREVIEW
MDIO (input)
Timer Timing
20
Timer Timing
Table 20-1. Timing Requirements for Timer Inputs (see Figure 20-1)
-500 -600 MIN MAX ns ns
NO. 1 2 tw(TINPH) tw(TINPL) Pulse duration, TINP high Pulse duration, TINP low
UNIT
8P 8P
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
Table 20-2. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs (see Figure 20-1)
NO. 3 4 tw(TOUTH) tw(TOUTL) Pulse duration, TOUT high Pulse duration, TOUT low PARAMETER -500 -600 MIN 8P - 3 8P - 3 MAX ns ns UNIT
PRODUCT PREVIEW
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2 1 TINPx 3 TOUTx 4
Figure 20-1. Timer Timing
172
SPRS200B
July 2002 - Revised May 2003
General-Purpose Input/Output (GPIO) Port Timing
21
General-Purpose Input/Output (GPIO) Port Timing
Table 21-1. Timing Requirements for GPIO Inputs (see Figure 21-1)
-500 -600 MIN MAX ns ns
NO. 1 2 tw(GPIH) tw(GPIL) Pulse duration, GPIx high Pulse duration, GPIx low
UNIT
8P 8P
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access the GPIO register through the CFGBUS.
Table 21-2. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 21-1)
NO. 3 4 tw(GPOH) tw(GPOL) Pulse duration, GPOx high Pulse duration, GPOx low PARAMETER -500 -600 MIN 32P 32P MAX ns UNIT ns
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. 2 1 GPIx 3 GPOx 4
Figure 21-1. GPIO Port Timing
July 2002 - Revised May 2003
SPRS200B
173
PRODUCT PREVIEW
JTAG Test-Port Timing
22
JTAG Test-Port Timing
Table 22-1. Timing Requirements for JTAG Test Port (see Figure 22-1)
-500 -600 MIN MAX ns ns ns
NO. 1 3 4 tc(TCK) tsu(TDIV-TCKH) th(TCKH-TDIV) Cycle time, TCK Setup time, TDI/TMS/TRST valid before TCK high Hold time, TDI/TMS/TRST valid after TCK high
UNIT
35 10 9
Table 22-2. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 22-1)
NO. 2 td(TCKL-TDOV) PARAMETER Delay time, TCK low to TDO valid -500 -600 MIN -3 MAX 18 ns UNIT
PRODUCT PREVIEW
1 TCK 2 TDO 4 3 TDI/TMS/TRST 2
Figure 22-1. JTAG Test-Port Timing
174
SPRS200B
July 2002 - Revised May 2003
Mechanical Data
23
Mechanical Data
PLASTIC BALL GRID ARRAY
23.1 Ball Grid Array Mechanical Data Drawing (GDK) GDK (S-PBGA-N548)
23,10 SQ 22,90 21,10 SQ 20,90 0,80 0,40
AF AE AD AC AB AA Y W V U T R N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26 P
20,00 TYP
0,80
0,40
A1 Corner
Bottom View 0,50 NOM 2,80 MAX
Seating Plane 0,55 0,45 0,10 0,12
0,45 0,35
4203481-3/B 07/02
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Flip chip application only.
July 2002 - Revised May 2003
SPRS200B
175
PRODUCT PREVIEW
Mechanical Data
Table 23-1. Thermal Resistance Characteristics (S-PBGA Package) [GDK]
NO 1 2 3 4 5 6 RJA Junction-to-free air RJC RJB Junction-to-case Junction-to-board C/W 3.3 7.92 18.2 15.3 13.7 12.2 0.37 0.47 7 PsiJT Junction-to-package top 0.57 0.7 11.4 11 8 PsiJB Junction-to-board 10.7 10.2 Air Flow (m/s) N/A N/A 0.00 0.5 1.0 2.00 0.00 0.5 1.0 2.00 0.00 0.5 1.0 2.00
PRODUCT PREVIEW
m/s = meters per second
176
SPRS200B
July 2002 - Revised May 2003
Mechanical Data
23.2 Ball Grid Array Mechanical Data Drawing (GNZ) GNZ (S-PBGA-N548) PLASTIC BALL GRID ARRAY
27,20 SQ 26,80 25,20 SQ 24,80
AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9
25,00 TYP 1,00 0,50
1,00
0,50
A1 Corner
11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26
Bottom View
2,80 MAX 0,50 NOM Seating Plane 0,70 0,50 0,10 0,15
0,60 0,40
4202595-5/E 12/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Flip chip application only. Substrate color may vary.
July 2002 - Revised May 2003
SPRS200B
177
PRODUCT PREVIEW
Mechanical Data
Table 23-2. Thermal Resistance Characteristics (S-PBGA Package) [GNZ]
NO 1 2 3 4 5 6 RJA Junction-to-free air RJC RJB Junction-to-case Junction-to-board C/W 3.3 7.46 17.4 14.0 12.3 10.8 0.37 0.47 7 PsiJT Junction-to-package top 0.57 0.7 11.4 11 8 PsiJB Junction-to-board 10.7 10.2 Air Flow (m/s) N/A N/A 0.00 0.5 1.0 2.00 0.00 0.5 1.0 2.00 0.00 0.5 1.0 2.00
PRODUCT PREVIEW
m/s = meters per second
178
SPRS200B
July 2002 - Revised May 2003

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