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| TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 * * * Single Chip Parallel MIMD DSP Over 1.5 Billion RISC-like Operations per Second Master Processor (MP) - 32-Bit RISC Processor - IEEE-754 Floating Point - 4K-Byte Instruction Cache - 4K-Byte Data Cache Two Parallel Processors (PPs) - 32-Bit Advanced DSP Processors - 64-Bit Opcode Provides Many Parallel Operations per Cycle - 4K-Byte Instruction Cache, 4K-Byte Parameter RAM, and 8K Bytes of Data RAM per PP Transfer Controller (TC) - 64-Bit Data Transfers - Up to 480M-Byte/s Transfer Rate - 32-Bit Addressing - Direct EDO DRAM/VRAM Interface - Direct SDRAM Interface - Dynamic Bus Sizing - Intelligent Queuing and Cycle Prioritization GGP PACKAGE (BOTTOM VIEW) * * * * * * * * Big or Little Endian Operation 44K Bytes of On-Chip RAM 4G-Byte Address Space 16.6 ns Cycle Time 3.3-V Operation IEEE 1149.1 Test Port (JTAG) description The TMS320C82 is a single chip, MIMD (multiple instruction/multiple data) parallel processor capable of performing over 1.5 billion operations per second. It consists of a 32-bit RISC Master Processor with a 120-MFlop IEEE Floating Point Unit, two 32-bit parallel-processing DSPs (PPs), and a Transfer Controller with up to 480 Mbyte/sec transfer rate. All the processors are tightly coupled via an on-chip crossbar which provides shared access to on-chip RAM. This performance and programmability make the `C82 ideally suited for video, imaging, and high-speed telecommunication applications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 Copyright (c) 1998 Texas Instruments Incorporated 1 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 architecture FPU PP1 (DSP) L 32 32 PP0 (DSP) I 64 MP OCR I 64 G L 32 G 32 C/D 64 I 32 32 TAP Crossbar Instruction Cache Instruction Cache Figure 1. `C82 Block Diagram Showing Datapaths The `C82 Block Diagram shows the major components of the `C82: the Master Processor (MP), Parallel Processors (PPs), Transfer Controller (TC), and JTAG Emulation Interface. Shared access to on-chip . Each PP can RAMs is achieved through the Crossbar. Crossbar connections are represented by perform three accesses per cycle through its Local, Global, and Instruction ports. The MP can access two RAMs per cycle through its Crossbar/Data and Instruction ports and the TC can access one RAM through its crossbar interface. Thus, up to nine simultaneous accesses are supported in each cycle. Addresses can be changed every cycle, allowing the crossbar matrix to be changed on a cycle-by-cycle basis. Contention between processors for the same RAM in the same cycle is resolved by a round-robin priority scheme. In addition to the Crossbar, a 32-bit data path exists between the MP and the TC. This allows the MP to access TC control registers which are memory-mapped into the MP's memory space. 2 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 Instruction Cache Parameter RAM Parameter RAM Parameter RAM TC Data RAM 1 Data RAM 0 Data RAM 1 Data RAM 0 Data Cache TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 pin assignments - numerical listing PIN NO. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 FUNCTION NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PIN NO. B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 FUNCTION NC NC /DBEN VDD STATUS0 /CAS/DQM6 VSS VDD /CAS/DQM1 VSS /HACK CLKOUT LF CLKIN VDD /XPT3 VSS VDD /EINT1 /TRST EMU1 VDD AD31 AD29 NC NC PIN NO. C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 FUNCTION NC /DDIN NC VDD VSS VDD /CAS/DQM5 /CAS/DQM3 /CAS/DQM2 /CAS/DQM0 VDD VSS VDD VSSPLL /HREQ /XPT2 /XPT0 /EINT3 TCK TDI EMU0 TDO AD30 NC VDD NC PIN NO. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 FUNCTION NC /TRG/CAS VSS NC STATUS1 /CAS/DQM7 VSS /CAS/DQM4 VDD VSS REQ VSS VDDPLL VSS /RESET /XPT1 /LINT4 /EINT2 TMS VSS VDD VSS NC AD28 VSS NC POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 3 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 pin assignments - numerical listing (continued) PIN NO. E1 E2 E3 E4 E23 E24 E25 E26 F1 F2 F3 F4 F23 F24 F25 F26 G1 G2 G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 H23 H24 H25 H26 J1 J2 J3 J4 FUNCTION NC VSS /W VSS AD27 VSS AD26 NC NC /RL VDD DSF VDD AD25 VDD NC NC /EXCEPT0 /RAS VDD AD24 AD23 VSS NC NC READY VDD /EXCEPT1 AD22 AD21 VDD NC NC RCA0 VSS VSS PIN NO. J23 J24 J25 J26 K1 K2 K3 K4 K23 K24 K25 K26 L1 L2 L3 L4 L23 L24 L25 L26 M1 M2 M3 M4 M23 M24 M25 M26 N1 N2 N3 N4 N23 N24 N25 N26 FUNCTION VDD AD20 AD19 NC NC VDD RCA1 VSS VSS VSS AD18 NC NC VDD RCA2 VDD VSS AD17 VDD NC NC VSS RCA3 VDD VDD AD16 VDD NC NC VSS RCA4 VSS VSS VSS AD15 NC PIN NO. P1 P2 P3 P4 P23 P24 P25 P26 R1 R2 R3 R4 R23 R24 R25 R26 T1 T2 T3 T4 T23 T24 T25 T26 U1 U2 U3 U4 U23 U24 U25 U26 V1 V2 V3 V4 FUNCTION NC VDD RCA5 VDD AD13 VDD AD14 NC NC RCA6 VSS RCA7 VSS AD11 AD12 NC NC VSS VSS RCA8 AD9 AD10 VSS NC NC VDD RCA9 VDD AD8 VDD VDD NC NC VDD RCA10 VSS PIN NO. V23 V24 V25 V26 W1 W2 W3 W4 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB23 AB24 AB25 AB26 FUNCTION VSS AD7 VSS NC NC RCA11 VSS VSS VDD AD6 VSS NC NC RCA12 VDD RCA13 VDD AD5 VDD NC NC VDD VDD VDD VSS AD3 AD4 NC NC RCA14 VSS RCA15 VDD AD2 VSS NC 4 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 pin assignments - numerical listing (continued) PIN NO. AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 FUNCTION NC VSS VSS NC AD34 AD36 AD38 VDD VDD AD42 AD43 AD45 AD47 AD49 VSS AD52 AD54 AD56 AD57 AD59 VDD VSS NC VDD AD1 NC PIN NO. AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 FUNCTION NC RCA16 NC VDD VSS VDD VSS AD40 AD41 VSS AD44 AD46 AD48 VDD AD50 VSS AD53 AD55 VDD VSS AD60 VSS VSS NC AD0 NC PIN NO. AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 FUNCTION NC NC AD32 AD33 AD35 AD37 AD39 VDD VSS VSS VDD VSS VSS VDD VDD AD51 VDD VSS VDD AD58 VDD AD61 AD62 AD63 NC NC PIN NO. AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 FUNCTION NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 5 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 pin assignments - alphabetical listing FUNCTION AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AD39 PIN NO. AD25 AC25 AB24 AA24 AA25 Y24 W24 V24 U23 T23 T24 R24 R25 P23 P25 N25 M24 L24 K25 J25 J24 H24 H23 G24 G23 F24 E25 E23 D24 B24 C23 B23 AE3 AE4 AC5 AE5 AC6 AE6 AC7 AE7 FUNCTION AD40 AD41 AD42 AD43 AD44 AD45 AD46 AD47 AD48 AD49 AD50 AD51 AD52 AD53 AD54 AD55 AD56 AD57 AD58 AD59 AD60 AD61 AD62 AD63 /CAS/DQM0 /CAS/DQM1 /CAS/DQM2 /CAS/DQM3 /CAS/DQM4 /CAS/DQM5 /CAS/DQM6 /CAS/DQM7 CLKIN CLKOUT /DBEN /DDIN DSF /EINT1 /EINT2 /EINT3 PIN NO. AD8 AD9 AC10 AC11 AD11 AC12 AD12 AC13 AD13 AC14 AD15 AE16 AC16 AD17 AC17 AD18 AC18 AC19 AE20 AC20 AD21 AE22 AE23 AE24 C10 B9 C9 C8 D8 C7 B6 D6 B14 B12 B3 C2 F4 B19 D18 C18 FUNCTION EMU0 EMU1 /EXCEPT0 /EXCEPT1 /HACK /HREQ /LINT4 LF /RAS RCA0 RCA1 RCA2 RCA3 RCA4 RCA5 RCA6 RCA7 RCA8 RCA9 RCA10 RCA11 RCA12 RCA13 RCA14 RCA15 RCA16 READY REQ /RESET /RL STATUS0 STATUS1 TCK TDI TDO TMS /TRG/CAS /TRST PIN NO. C21 B21 G2 H4 B11 C15 D17 B13 G3 J2 K3 L3 M3 N3 P3 R2 R4 T4 U3 V3 W2 Y2 Y4 AB2 AB4 AD2 H2 D11 D15 F2 B5 D5 C19 C20 C22 D19 D2 B20 6 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 pin assignments - alphabetical listing (continued) FUNCTION VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD PIN NO. B4 B8 B15 B18 B22 C4 C6 C11 C13 C25 D9 D21 F3 F23 F25 G4 H3 H25 J23 K2 L2 L4 L25 M4 M23 M25 P2 P4 P24 U2 U4 FUNCTION VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDPLL VSS VSS VSS VSS PIN NO. U24 U25 V2 W23 Y3 Y23 Y25 AA2 AA3 AA4 AB23 AC8 AC9 AC21 AC24 AD4 AD6 AD14 AD19 AE8 AE11 AE14 AE15 AE17 AE19 AE21 D13 B7 B10 B17 C5 FUNCTION VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PIN NO. C12 D3 D7 D10 D12 D14 D20 D22 D25 E2 E4 E24 G25 J3 J4 K4 K23 K24 L23 M2 N2 N4 N23 N24 R3 R23 T2 T3 T25 V4 V23 FUNCTION VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSPLL /W /XPT0 /XPT1 /XPT2 /XPT3 PIN NO. V25 W3 W4 W25 AA23 AB3 AB25 AC2 AC3 AC15 AC22 AD5 AD7 AD10 AD16 AD20 AD22 AD23 AE9 AE10 AE12 AE13 AE18 C14 E3 C17 D16 C16 B16 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 7 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 signal descriptions NAME I/O DESCRIPTION LOCAL MEMORY INTERFACE AD63-AD40 AD39-AD32 AD31-AD0 RCA16-RCA0 /DBEN /DDIN /EXCEPT1-/EXCEPT0 READY I/O I/O I/O O O O I I Data. The upper 24 bits of data are read in/driven out over this bus. Data/Status. This bus drives out the access code at row time. During column time, bits 39-32 of data are read in/driven out over this bus. Address/Data. Outputs the 32-bit address at row time. During column time, the lower 32 bits of data are read in/driven out on this bus. Address. Outputs the multiplexed row/column addresses. Data buffer enable. This signal drives the active-low output enables on bidirectional transceivers which may be used to buffer input and output data on AD63-AD0. Data direction indicator. Indicates the direction that data needs to pass through the transceivers. A low on this signal indicates a transfer from external memory into the `C82. Memory exception. Two-bit encodings on these inputs request retries, faults, or configuration cache flushes. Additionally, these inputs are used to indicate the cycle type for refreshes. Ready. Indicates that the external device is ready to complete the memory cycle. This signal is driven inactive low by external circuitry to insert wait states into a memory cycle. READY is also used at reset to determine the endianness of the `C82. If READY is low at the rising edge of /RESET, the `C82 will operate in big-endian mode. If READY is high, the `C82 will operate in little-endian mode. /RL STATUS1-STATUS0 O O Row latch. The high-to-low transition of /RL can be used to latch the source information, status code, and 32-bit byte address present on AD39-AD0 at row time. Status. Two-bit encoded outputs which indicate row, column, XPT end and idle conditions on the bus. DRAM, VRAM, AND SDRAM CONTROL /CAS/DQM7-/CAS/DQM0 DSF /RAS /TRG/CAS O O O O Column address strobes. These outputs drive the /CAS inputs of DRAMs and VRAMs or the DQM inputs of SDRAMs. The eight strobes provide byte write access to memory. Special function. This signal is used to select special VRAM functions such as block write, load color register, and split register transfers, and SGRAM block writes. Row address strobe. The /RAS output drives the /RAS inputs of DRAMs, VRAMs, and SDRAMs. Transfer/output enable or column address strobe. /TRG/CAS is used as an output enable for DRAMs and VRAMs and as a transfer enable for VRAMs. /TRG/CAS also drives the /CAS inputs of SDRAMs. /W O Write enable. /W is driven active-low prior to /CAS during DRAM/VRAM write cycles. During VRAM transfer cycles, /W is used to control the direction of the transfer. For SDRAM writes, /W is driven low concurrent with the DQM signals, and is also low during DCAB cycles. 8 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 signal descriptions (continued) NAME I/O HOST INTERFACE /HACK O Host acknowledge. The `C82 will drive this output low following an active /HREQ, to indicate that it has driven the local memory bus signals to high impedance and is relinquishing the bus. /HACK is driven high asynchronously following /HREQ being detected inactive, and the `C82 will resume driving the bus. Host request. An external device drives this input active-low to request ownership of the local memory bus. When /HREQ is inactive high, the `C82 will own and drive the bus. /HREQ is internally synchronized to the `C82's internal clock. /HREQ is used at reset to determine the power-up state of the MP. If /HREQ is low at the rising edge of /RESET, the MP will come up running. If /HREQ is high, the MP will remain halted until the first interrupt occurrence on /EINT3. Internal cycle request. This signal provides an indication that the `C82 is receiving a high-priority request (urgent refresh or XPT request). External logic can monitor this signal to determine if it is necessary to relinquish the local memory bus to the `C82. SYSTEM CONTROL CLKIN LF CLKOUT /EINT1, /EINT2, /EINT3 I I O I Input clock. This clock is used to generate the internal `C82 clocks to which all processor functions are synchronous. Loop filter. An external filter is connected to this pin to provide filtering for the C82's on-chip PLL circuitry. Local output clock. This clock provides a way to synchronize external circuitry to internal timings. This clock is internally phase-locked to CLKIN. Edge-triggered interrupts. These signals allow external devices to interrupt the MP on one of three interrupt levels (/EINT1 being the highest priority). The interrupts are rising-edge triggered. /EINT3 also serves as an unhalt signal. If the MP is powered-up halted, the first rising edge on /EINT3 will cause the MP to unhalt and fetch its reset vector. (The /EINT3 interrupt pending bit will not be set in this case.) Level-triggered interrupt. This input provides an active-low level-triggered interrupt to the MP. Its priority falls below that of the edge-triggered interrupts. Any interrupt request should remain active-low until it is recognized by the `C82. The /LINT4 interrupt service routine is expected to clear the interrupt condition. Reset. The /RESET input is driven low to reset the `C82 (all processors). During reset, all internal registers are set to their initial state and all output pins are driven to high-impedance levels with the exception of CLKOUT, /HACK, and REQ, which continue to be driven. During the rising edge of /RESET, the MP reset mode and the `C82's operating endian are determined by the levels of /HREQ and READY pins, respectively. External Packet Transfer. These encoded inputs are used by external devices to request a highpriority external packet transfer (XPT) by the TC. Fifteen XPT codes are supported. Code 1111 indicates that no request is being submitted. The XPT inputs should remain valid until the TC begins servicing the request. EMULATION CONTROL EMU0, EMU1 TCK TDI TDO TMS /TRST I/O I I O I I Emulation pins. These two pins are used to support emulation host interrupts, special functions targeted at a single processor, and multiprocessor halt event communications. Test clock. This input provides the clock for the `C82's JTAG logic allowing it to be compatible with other JTAG devices, controllers, and test equipment designed for different clock rates. Test data input. This pin provides input data for all JTAG instructions and data scans of the `C82. Test data output. This pin provides output data for all JTAG instructions and data scans of the `C82. Test mode select. This signal controls the JTAG state machine. DESCRIPTION /HREQ I REQ O /LINT4 I /RESET I /XPT3-/XPT0 I Test reset. This input resets the `C82's JTAG module. When active-low, all boundary scan logic is disabled, allowing normal `C82 operation. This pin has an internal pullup and may be left unconnected during normal operation. This pin has an internal pulldown and may be left unconnected during normal operation. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 9 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 signal descriptions (continued) NAME VDD VDDPLL VSS VSSPLL I/O POWER Power. Nominal 3.3-volt power supply inputs. Power. Nominal 3.3-volt power supply input for the on-chip PLL. Ground. Electrical ground inputs. Ground. Electrical ground input for the on-chip PLL (tied to VSS internally). DESCRIPTION For proper operation, all VDD and Vss pins must be connected externally. VDD3 L1 D13 VDDPLL C3 R1 B13 C2 C1 C14 LF L1 R1 C1 C2 C3 EMI filter 10 (1%) 150nF (10%) 3.3nF (10%) 10uF (10%) VSSPLL TMS320C82 NOTE: To ensure proper operation, the on-chip PLL should be powered with a stable supply. To minimize noise injection into the PLL, it is suggested that an external EMI filter be applied as shown. The RC filter network on the LF pin provides an external filter for the PLL. Figure 2. PLL Support Circuitry 10 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 memory map The `C82 has a 4G-byte address space. The lower 32M bytes are used to address internal RAM and memory-mapped registers. 0xFFFFFFFF 0x01800FFF E xtern al M em o ry (4 0 6 4 M b ytes) R eserved (8 1 2 8 K b ytes) 0x01011000 0x01010FFF 0x01010000 0x0100FFFF M P P aram eter R A M (4 K b ytes) R eserved (8 0 6 3 K b ytes) M em o ry-M ap p ed T C R eg isters R eserved (2 8 K b ytes) M P In stru c tio n C ach e (4 K b ytes) R eserved (2 8 K b ytes ) M P D ata C ac h e (4 K b ytes) R eserved (4 8 K b ytes) PP1 Instruction Cache (4K bytes) 0x02000000 0x01FFFFFF 0x01820200 0x018201FF 0x01820000 0x0181FFFF 0x01819000 0x01818FFF 0x01818000 0x01817FFF 0x01811000 0x01810FFF 0x01810000 0x0180FFFF 0x01804000 0x01803FFF 0x01803000 0x01802FFF 0x01802000 0x01801FFF 0x01801000 R eserved (5 6 K b ytes) P P 1 P aram eter R A M (4 K b ytes) P P 0 P aram ater R A M (4 K b ytes) R eserved (1 6 M b ytes) 0x0000A000 0x00009FFF 0x00009000 0x00008FFF 0x00008000 0x00007FFF 0x00002000 0x00001FFF 0x00001000 0x00000FFF 0x00000000 0x01002000 0x01001FFF 0x01001000 0x01000FFF 0x01000000 0x00FFFFFF P P 1 D ata R A M 1 (4 K b ytes) P P 0 D ata R A M 1 (4 K b ytes) R eserved (2 4 K b ytes) P P 1 D ata R A M 0 (4 K b ytes) P P 0 D ata R A M 0 (4 K b ytes) R eserved (4 K b ytes) P P 0 In stru c tio n C ach e (4 K b ytes) Figure 3. TMS320C82 Memory Map POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 11 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 master processor architecture The Master Processor (MP) is a 32-bit RISC processor with an integral IEEE-754 floating-point unit. The MP has been designed for executing C code and is capable of performing at over 130k dhrystones. Major tasks which the MP will typically perform are: * * * Task control and user interface Information processing and analysis IEEE-754 floating point (including graphics transforms) functional block diagram Figure 4 shows a block diagram of the master processor. * 32-bit RISC processor - Load/store architecture - 3 operand arithmetic and logical instructions * 4K-byte instruction cache and 4K-byte data cache - 4-way set associative - LRU replacement - Data writeback * 4K-byte non-cached parameter RAM * Thirty-one 32-bit general-purpose registers * Register and accumulator scoreboard * 15-bit or 32-bit immediate constants * 32-bit byte-addressing * Scalable timer R e giste r File B a rre l R o tato r M a sk G en e ra tor Ze ro C om p arato r In te g e r A LU L e ftm o st/R ig h tm o st O n e Tim e r C o ntro l R e g iste rs Instructio n R e giste r P ro gram Co u n te rs P C In cre m e n ter E m ula tio n L o gic In stru ction C ache C on tro lle r E n dia n M ultip le xe rs Da ta C a ch e Co n tro ller D o ub le-P re cisio n Floa tin g -P o in t Ad d e r D o ub le-P re cisio n Flo a tin g-Po int A ccu m ula to rs D o ub le-P re cisio n Flo ating -P o in t M u ltiplie r (S in g le -P re cision C ore) Key features of the MP include: * Leftmost-one and rightmost-one logic * IEEE-754 floating-point hardware - Four double-precision floating-point vector accumulators - Vector floating-point instructions - Floating-point operation and parallel load or store - Multiply and accumulate * High performance - 60 MIPS - 120 MFLOPS - Over 130,000 Dhrystones S coreb o a rd C ro ssb a r In te rfa ce Figure 4. MP Block Diagram 12 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 general-purpose registers The MP contains 31 32-bit general-purpose registers, R1 - R31. Register R0 always reads as zero and writes to it are discarded. Double-precision values are always stored in an even-odd register pair with the higher numbered register always holding the sign bit, and exponent. The R0/R1 pair is not available for this use. A scoreboard keeps track of which registers are awaiting loads or the result of a previous instruction and stalls the pipeline until the register contains valid data. As a recommended software convention, R1 is typically used as a stack pointer and R31 as a return address link register. Zero/Discard R1 R2/R3 R2 R4/R5 R3 R4 R5 : R30/R31 : 64-Bit Register Pairs : R30 R31 32-Bit Registers : : : Not Available Figure 5. MP General-Purpose Registers The 32-bit registers may contain signed-integer, unsigned-integer, or single-precision floating-point values. Signed and unsigned bytes and halfwords are sign-extended or zero-filled. Doublewords may be stored in a 64-bit even/odd register pair. Double-precision floating-point values are referenced using the even register number or the register pair. Figure 6 through Figure 8 show the register data formats. single-precision floating-point signed 32-bit integer u nsigned 32-bit integer 31 30 29 28 27 2 6 25 24 23 22 21 2 0 19 18 17 16 15 1 4 13 12 11 10 9 SEEEEEEEEMMMMMMMMMMMMMM MS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SI II IIII II IIII II IIII II 9 I 8 M 8 I 8 U 7 M 7 I 7 U 6 M 6 I 6 U 5 M 5 I 5 U 4 M 4 I 4 U 3 M 3 I 3 U 2 M 2 I 2 U 1 M 1 I 1 U 0 M LS 0 I LS 0 U LS MS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 UUUUUUUUUUUUUUUUUUUUUUU MS Figure 6. MP Register 32-Bit Data Formats POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 13 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 general-purpose registers (continued) signed byte 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SSSSSSSSSSSSSSSSSSSSSSS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0000000000000000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 SSSSSSSSSSSSSSSSSIIIII 9 0 9 I 8 S 8 0 8 I 8 U 7 S MS unsigned byte signed halfword unsigned halfword 7 U 6 U 5 U 5 I 5 U 4 U 4 I 4 U 3 U 3 I 3 U 2 U 2 I 2 U 1 U 1 I 1 U 6 I 5 I 4 I 3 I 2 I 1 I 0 I LS 0 U LS 0 I LS 0 U LS MS 76 II 7 U 6 U MS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0000000000000000UUUUUUU MS Figure 7. MP Register 8-Bit and 16-Bit Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 M ost Significant 32-Bit W ord MS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Least Significant 32-Bit W ord MS odd register even register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SEEEEEEEEEEEMMMMMMMMMMM MS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 MMMMMMMMMMMMMMMMMMMMMMM double-precision floating-point 8 M 8 M 7 M 7 M 6 M 6 M 5 M 5 M 4 M 4 M 3 M 3 M 2 M 2 M 1 M 1 M 9 8 7 6 5 4 3 2 1 0 LS 0 LS 0 M 0 M LS odd register even register 9 8 7 6 5 4 3 2 1 Figure 8. MP Register 64-Bit Data double-precision floating-point accumulators There are four double-precision floating-point registers to accumulate intermediate floating-point results. 63 a0 a1 a2 a3 MSB Accumulator 0 Accumulator 1 Accumulator 2 Accumulator 3 LSB 0 Figure 9. Floating-Point Accumulators 14 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 control registers In addition to the general-purpose registers, there are a number of control registers that are used to represent the state of the processor. The control register numbers of the accessible registers are shown in Table 1. Table 1. MP Control Registers NUMBER 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 PKTREQ TCOUNT TSCALE FLTOP FLTADR FLTTAG FLTDTL FLTDTH PPERROR FPST IE INTPEN NAME EPC EIP CONFIG DESCRIPTION Exception Program Counter Exception Instruction Pointer Configuration Reserved Interrupt Pending Reserved Interrupt Enable Reserved Floating-Point Status Reserved PP Error Indicators Reserved Reserved Packet Request Register Current Counter Value Counter Reload Value Faulting Operation Faulting Address Faulting Tag Faulting Data (low) Faulting Data (high) NUMBER 0x0015-0x001F 0x0020 0x0021 0x0022-0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035-0x0038 0x0039 0x003A 0x003B-0x01FF 0x0200 - 0x020F 0x0300 0x0400-0x040F 0x0500 0x4000 0x4001 0x4002 ITAG0-15 ILRU DTAG0-15 DLRU IN0P IN1P OUTP BRK1 BRK2 ANASTAT MPC MIP SYSSTK SYSTMP NAME Reserved System Stack Pointer System Temporary Register Reserved Emulator Exception Program Cntr Emulator Exception Instruction Ptr Reserved ECOMCNTL Emulator Communication Control Emulation Analysis Status Reg Reserved Emulation Breakpoint 1 Reg. Emulation Breakpoint 2 Reg. Reserved Instruction Cache Tags 0 to 15 Instruction Cache LRU Register Data Cache Tags 0 to 15 Data Cache LRU Register Vector Load Pointer 0 Vector Load Pointer 1 Vector Store Pointer DESCRIPTION POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 15 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 pipeline registers The MP uses a three-stage Fetch, Execute, Access pipeline. The primary pipeline registers are manipulated implicitly by branch and trap instructions and are not accessible by the user. The exception and emulation pipeline registers are user-accessible as control registers. All pipeline registers are 32 bits. Table 2. MP FEA Pipeline Registers Program Exe cution M od e N ormal E xce p tion E mulation Prog ra m C ou nter In stru ction Po inter In stru ction R e gister PC IP IR EPC E IP M PC M IP * * * * Instruction Register (IR): Instruction Pointer (IP): Program Counter (PC): contains the instruction being executed points to the instruction being executed points to the instruction being fetched Exception/Emulator Instruction Pointer (EIP/MIP): points to the instruction that would have been executed had the exception / emulation trap not occurred. from the exception / emulation trap. * Exception/Emulator Program Counter (EPC/MPC): points to the instruction to be fetched on returning config register (0x0002) The CONFIG register controls or reflects the state of certain options. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ERTHX Reserved Type Deriv 8 7 654 Release 3 210 Reserved E - Endian Mode; 0 = big endian, 1 = little endian, Read only Type - Number of PPs in device, Read only R - PP Data RAM Round Robin; 0 = variable, 1 = fixed, Read/Write Deriv - C8x family derivative, Read only (0x2) T - TC PT Round Robin; 0 = variable, 1 = fixed, Read/Write Release - TMS320C82 version number, Read only H - High-Priority MP Events; 0 = disabled, 1 = enabled , Read/Write X - Externally Initiated Packet Transfers; 0 = disabled, 1 = enabled, Read/Write Figure 10. CONFIG Register interrupt enable register (0x0006) The IE register contains enable bits for each of the interrupts/traps. The global interrupt enable bit (ie) and the individual interrupt enable must be set in order for an interrupt to occur. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 pe x4 x3 bp pb pc mi p1 p0 io mf x2 x1 ti pe - PP error x4 - external interrupt 4 (LINT4) x3 - external interrupt 3 (EINT3) bp - bad packet transfer pb - packet transfer busy pc - packet transfer complete mi - message (MP self) interrupt p1 - PP1 message interrupt p0 - PP0 message interrupt io - integer overflow mf - memory fault x2 - external interrupt 2 (EINT2) x1 - external interrupt 1 (EINT1) ti - MP timer interrupt 9 8 7 fx 65 fu fo 4 3 fz 2 fi 1 0 ie fx - floating point inexact fu - floating point underflow fo - floating point overflow fz - floating point divide by zero fi - floatin g point invalid ie - global interrupt enable Figure 11. IE Register 16 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 interrupt pending register (0x0004) The bits in INTPEN show the current state of each interrupt/trap. Pending interrupts will not occur unless the ie bit and corresponding interrupt enable bit are set (note: some memory faults are nonmaskable). Software must write a "1" to the appropriate INTPEN bit to clear an interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 pe x4 x3 bp pb pc m i p1 p0 io m f x2 x1 ti 9 8 7 fx 6 fu 5 fo 4 3 fz 2 fi 1 0 Figure 12. INTPEN Register floating-point status register (0x0008) FPST contains status and control information for the FPU. Bits 17-21 are read/write FPU control bits. Bits 22-26 are read/write accumulated status bits. All other bits show the status of the last FPU instruction to complete and are read-only bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 destination ai az ao au ax sm fs vm drm opcode e1 eo pd dest - destination register ai - accumulated value invalid az - accumulated divide by zero ao - accumulated overflow au - accumulated underflow ax - accumulated inexact sm - sequential mode select fs - floating point stall vm - vector fast mode drm - rounding 00 - nearest 10 - positive 01 - zero 11 -negative opcode - last opcode e1 - 10th MSB of exponent e0 - 9th MSB of exponent pd - destination precision 00 - single float 10 - signed int 01 - double float 11 - unsigned int 8 7 rm 6 54 mo i 3 z 2 o 1 u 0 x rm - rounding 00 - nearest 10 positive 01 - zero 11 -negative mo - int multiply overflow i - invalid z - divide by zero o - overflow u - underflow x - inexact Figure 13. FPST Register PP error register (0x000A) The bits in the PPERROR register reflect Parallel Processor errors. The MP may use these when a PP Error occurs to determine the cause of the error. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R eserv ed hh PP# 1 0 R eserv ed i i R eserv ed f f PP# 1 0 PP# 1 0 h - PP halted i - PP illegal instruction f - PP fault type; 0 = icache, 1 = DEA Figure 14. PPERROR Register packet transfer request register (0x000D) PKTREQ controls the submission and priority of packet-transfer requests. currently active. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 It also indicates if a PT is 7 6 5 4 3 2 1 0 R es erve d I - im m e d ia te (u rg e n t) p rio rity se le cte d F - h ig h (fo re g ro u n d ) p rio r ity s e le cte d IFSQP S - su sp e n d p a cke t tra n sfe r P - su b m it p a cke t tr a n sfe r r e q u e st Q - p a ck e t tra n sfe r q u e u e d ; R e a d o n ly Figure 15. PKTREQ Register POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 17 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 memory fault registers The five read-only memory fault registers contain information about memory address exceptions. 3 1 30 2 9 2 8 2 7 26 2 5 2 4 2 3 22 2 1 2 0 19 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 FL TOP (0 x0 0 10 ) 8 7 6 5 4 3 2 1 0 D e st R e se rve d K SZ idxR 8 R es erve d 7 6 5 4 3 B lo ck 2 1 0 3 1 3 0 29 2 8 2 7 2 6 25 2 4 2 3 2 2 21 2 0 1 9 1 8 17 1 6 1 5 1 4 13 1 2 1 1 1 0 9 FL TTA G (0 x0 0 11 ) 2 2 -B it C a ch e T a g A d d re ss S ub b lo ck PDPDPDPD 3 8 7 2 6 5 1 4 3 0 2 1 0 3 1 30 2 9 2 8 2 7 26 2 5 2 4 2 3 22 2 1 2 0 19 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 FL TA D R (0 x0 0 12 ) FL TD TH (0 x0 0 13 ) FL TD TL (0 x0 0 14 ) F a u ltin g A d d re ss A cc es se d b y In struc tio n F a u ltin g W rite M o st S ig n ifica n t D ata W o rd F a u ltin g W rite Le a st S ig n ifica n t D ata W o rd De st - de stina tio n re giste r K - kind o f o pe ra tio n 0 0 - lo ad 1 0 - store 0 1 - u n sign e d lo ad 11 - ca ch e flu sh /cle a n S Z - size of d a ta 00 - 8 b it 1 0 - 3 2 bit 01 - 1 6 b it 1 1 - 64 b it i - M P icache fa u lt d - M P d ca ch e fau lt x - D E A fa ult R - m o d ifie d re tu rn se q ue n ce B lo ck - fa ultin g blo ck n um b er P - su b blo ck p re se nt D - dirty b it se t Figure 16. Memory Fault Registers cache registers The ILRU and DLRU registers track least recently used information for the sixteen instruction cache and sixteen data cache blocks. The ITAGxx registers contain block addresses and the present flags for each subblock. DTAGxx registers are identical to ITAGxx registers but include dirty bits for each subblock. ILRU 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 (0x0300) mru nmru nlru lru mru nmru nlru lru mru nmru nlru lru DLRU (0x0500) 7 6 5 4 3 2 1 0 mru nmru nlru set 0 P P 2 1 P 0 lru set 3 set 2 set 1 ITAG0-15 (0x0200 0x020F) 22-bit Tag Address Subblock P 3 DTAG0-15 (0x0400 0x040F) 22-bit Tag Address Subblock nlru - next least recently used block lru - least recently used block PDPDPDPD 3 2 1 0 P - subblock present D - subblock dirty mru nmru - most recently used block - next most recently used block mru, nmru, nlru, and lru have the value 0, 1, 2, or 3 representing the block number and are mutually exclusive for each set. Figure 17. Cache Registers 18 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 cache architecture The MP contains two four-way set associative 4K caches--one for instructions and one for data. Each cache is divided into four sets with four blocks in each set. Each block represents 256 bytes of contiguous instructions or data and is aligned to a 256-byte address boundary. Each block is partitioned into eight subblocks that each contain sixteen 32-bit words and are aligned to 64-byte boundaries within the block. Cache misses cause one subblock to be loaded into cache. Figure 18 shows the cache architecture for one of the four sets in each cache. Figure 19 shows how addresses map into the cache using the cache tags and address bits. Block 0 Block 1 Subblocks Block2 Block 3 Set 0 Tag Reg 0 (Block 0) Tag Reg 1 (Block 1) Tag Reg 2 (Block 2) Tag Reg 3 (Block 3) LRU in Set 0 NLRU in Set 0 NMRU in Set 0 MRU in Set 0 LRU stack for Set 0 Figure 18. MP Cache Architecture (x4 Sets) 32-Bit Logical Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 T T T T T T T T T T T T T T T T T T T T T T 8 7 s 6 5 4 3 2 1 0 SS sWWWWB B On-Chip MP 4K Cache RAMs Bank 0 Bank 1 Set 0 Set 1 Set 2 Set 3 11 10 9 8 7 s 6 5 4 3 2 1 0 SSAA sWWWWB B Address in On-Chip Cache Bank T - tag address bits S - set select bits (0-3) s - subblock (within block) select (0-3) W - Word (within subblock) select (0-15) B - Byte (within word) select (0-3) A - Block select (which tag matched) (0-3) Figure 19. Cache Addressing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 19 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 MP parameter RAM The parameter RAM is a non-cacheable, 4K-byte, on-chip RAM which contains MP interrupt vectors, MP requested TC task buffers, and a general-purpose area. Figure 20 shows the parameter RAM address map. 0x010100000x0101007F 0x010100800x010100BF 0x010100C00x010100FB 0x010100FC0x010100FF 0x010101000x0101017F 0x010101800x0101021F 0x010102200x0101029F 0x010102A00x01010FFF Suspended PT Parameters (128 Bytes) Reserved (64 Bytes) XPT Linked List Start Addresses (60 Bytes) MP Linked List Start Address Off-Chip to Off-Chip PT Buffer (128 Bytes) Interrupt and Trap Vectors (160 Bytes) XPT Off-Chip to Off-Chip PT Buffer (128 Bytes) General-Purpose RAM (3424 Bytes) XPTf Linked List Start Add. XPTe Linked List Start Add. XPTd Linked List Start Add. XPTc Linked List Start Add. XPTb Linked List Start Add. XPTa Linked List Start Add. XPT9 Linked List Start Add. XPT8 Linked List Start Add. XPT7 Linked List Start Add. XPT6 Linked List Start Add. XPT5 Linked List Start Add. XPT4 Linked List Start Add. XPT3 Linked List Start Add. XPT2 Linked List Start Add. XPT1 Linked List Start Add. 0x010100C0 0x010100C4 0x010100C8 0x010100CC 0x010100D0 0x010100D4 0x010100D8 0x010100DC 0x010100E0 0x010100E4 0x010100E8 0x010100EC 0x010100F0 0x010100F4 0x010100F8 Figure 20. MP Parameter RAM 20 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 MP interrupt vectors The MP interrupts and traps and their vector addresses are shown in Table 3 and Table 4. Table 3. Maskable Interrupts IE BIT (TRAP #) 0 2 3 5 6 7 8 9 10 11 12 14 15 16 17 18 19 25 26 27 28 29 30 31 NAME ie fi fz fo fu fx f0 f1 ti x1 x2 mf io p0 p1 p2 p3 mi pc pb bp x3 x4 pe VECTOR ADDRESS 0x01010180 0x01010188 0x0101018C 0x01010194 0x01010198 0x0101019C 0x010101A0 0x010101A4 0x010101A8 0x010101AC 0x010101B0 0x010101B8 0x010101BC 0x010101C0 0x010101C4 0x010101C8 0x010101CC 0x010101E4 0x010101E8 0x010101EC 0x010101F0 0x010101F4 0x010101F8 0x010101FC Floating-point invalid Floating-point divide by zero Floating-point overflow Floating-point underflow Floating-point inexact Reserved Reserved MP timer External interrupt 1 (/EINT1) External interrupt 2 (/EINT2) Memory fault Integer overflow PP0 message PP1 message Reserved Reserved MP message Packet transfer complete Packet transfer busy Bad packet transfer External interrupt 3 (/EINT3) External interrupt 4 (/LINT4) PP error MASKABLE INTERRUPT TRAP NUMBER 32 33 34 35 36 37 38 39 72 to 415 er NAME e1 e2 e3 e4 fe Table 4. Nonmaskable Traps VECTOR ADDRESS 0x01010200 0x01010204 0x01010208 0x0101020C 0x01010210 0x01010214 0x01010218 0x0101021C 0x010102A0 to 0x010107FC NONMASKABLE TRAP Emulator trap1 (reserved) Emulator trap2 (reserved) Emulator trap3 (reserved) Emulator trap4 (reserved) Floating-point error Reserved Illegal MP instruction Reserved System- or user-defined POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 21 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 MP opcode formats The three basic classes of MP instruction opcodes are short immediate, three register, and long immediate. The opcode structure for each class of instruction is shown in Figure 21. S h o rt Im m e d ia te 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 D e st S o u rce 2 O p co d e 1 5 -B it Im m e d ia te 4 3 2 1 0 Three R e g iste r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 D e st S o u rce 2 11 O pcode 0 O p tio n s 6 5 4 321 S o u rce 1 0 Long Im m e d ia te 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 D e st S o u rce 2 11 O pcode 1 O p tio n s 3 2 -B it L o n g Im m e d ia te 6 5 4 321 S o u rce 1 0 Figure 21. MP Opcode Formats MP opcode summary The opcode formats for the MP are shown in Table 5 through Table 7. Table 8 summarizes the master processor instruction set. 22 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 MP opcode summary (continued) Table 5. Short Immediate Opcodes 3 1 3 0 2 9 2 8 27 2 6 2 5 2 4 23 2 2 2 1 2 0 1 9 18 1 7 1 6 1 5 14 1 3 1 2 1 1 1 0 9 8 7 6 5 4 D e st So u rce 0000000 U n sign e d Im m e d ia te D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st S o urce L in k L in k B ITNU M B ITNU M Co n d D e st D e st D e st F E So u rce So u rce So u rce So u rce So u rce So u rce So u rce So u rce So u rce S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 B a se B a se B a se S o u rce 2 B a se So u rce So u rce So u rce S o u rce 2 S o u rce 2 S o u rce 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 M M M M 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 1 SZ SZ SZ 0 A A A A A 0 U U M n SZ U 1 0 0 1 0 0 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 U nsig n ed Tra p N u m b e r U n sign e d Im m e d ia te U n sig n e d C o ntro l R e g iste r N um b er U n sig n e d C o ntro l R e g iste r N um b er U n sig n e d C o ntro l R e g iste r N um b er i i i i i i i i n n n n n n n n E n d m a sk E n d m a sk E n d m a sk E n d m a sk E n d m a sk E n d m a sk E n d m a sk E n d m a sk U n sign e d Im m e d ia te U n sign e d Im m e d ia te U n sign e d Im m e d ia te U n sign e d Im m e d ia te U n sign e d Im m e d ia te U n sign e d Im m e d ia te U n sign e d Im m e d ia te U n sign e d Im m e d ia te U n sign e d Im m e d ia te U n sign e d Im m e d ia te S ign e d O ffse t S ign e d O ffse t S ign e d O ffse t S ign e d O ffse t S ign e d O ffse t S ign e d O ffse t S ign e d O ffse t S ign e d O ffse t S ign e d O ffse t S ign e d Im m e dia te S ign e d Im m e dia te S ign e d Im m e dia te M o d ify, write m o dified a dd re ss b a ck to reg iste r R o ta te sen se fo r sh iftin g Size (0 =b yte , 1 =h a lfw ord, 2= w ord, 3 =d ou b le w o rd ) U n sig n e d fo rm R o ta te R o ta te R o ta te R o ta te R o ta te R o ta te R o ta te R o ta te 3 2 1 0 illo p 0 tra p cm n d rd cr sw cr b rcr sh ift.d z sh ift.d m sh ift.d s sh ift.e z sh ift.e m sh ift.e s sh ift.iz sh ift.im a nd .tt a n d.tf a n d.ft xo r o r.tt an d .ff xno r o r.tf o r.ft o r.ff ld ld .u st d ca ch e b sr jsr bb z bbo b cn d cm p add su b - Re se rved b it (co de a s 0) A A n n ul de lay slo t in stru ctio n if b ra n ch ta ke n E E m ula tio n tra p b it F C lea r p re se n t fla gs i In ve rt e nd m ask POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 23 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 MP opcode summary (continued) Table 6. Long Immediate and Three Register Opcodes 3 1 3 0 2 9 2 8 27 2 6 2 5 2 4 23 2 2 2 1 2 0 1 9 18 1 7 1 6 1 5 14 1 3 1 2 1 1 1 0 9 ----E-----110000001I--D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st D e st S o urce L in k L in k B ITNU M B ITNU M Co n d D e st D e st D e st F So u rce So u rce So u rce So u rce So u rce So u rce So u rce So u rce So u rce S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 S o u rce 2 B a se B a se B a se S o u rce 2 B a se So u rce So u rce So u rce S o u rce 2 S o u rce 2 S o u rce 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 M M M M 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 1 SZ SZ SZ 0 A A A A A 0 U U 0 0 1 0 0 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I i i i i i i i i S S S 0 n n n n n n n n D D D 0 8 7 6 5 4 321 IN D TR S o urce 1 IN D C R IN D C R IN D C R R o ta te R o ta te R o ta te R o ta te R o ta te R o ta te R o ta te R o ta te S o urce 1 S o urce 1 S o urce 1 S o urce 1 S o urce 1 S o urce 1 S o urce 1 S o urce 1 S o urce 1 S o urce 1 O ffse t O ffse t O ffse t S o urce 1 O ffse t O ffse t Targ e t Targ e t Targ e t S o urce 1 S o urce 1 S o urce 1 0 tra p cm n d rd cr sw cr b rcr sh ift.d z sh ift.d m sh ift.d s sh ift.e z sh ift.e m sh ift.e s sh ift.iz sh ift.im a nd .tt a n d.tf a n d.ft xo r o r.tt an d .ff xno r o r.tf o r.ft o r.ff ld ld .u st d ca ch e b sr jsr bb z bbo b cn d cm p add su b E n d m a sk E n d m a sk E n d m a sk E n d m a sk E n d m a sk E n d m a sk E n d m a sk E n d m a sk - - R e se rve d b it (cod e a s 0 ) D Dire ct exte rn a l a cce ss b it E E m u la tio n trap b it F C le a r presen t fla g s i In ve rt en d m a sk l L o ng im m e d ia te M M o dify, w rite m o d ifie d ad d re ss b ack to re g iste r n Ro ta te se n se for shiftin g S S cale o ffse t b y d a ta size SZ S ize (0 =b yte , 1 = ha lfw ord, 2 =w ord, 3 =d o ub lew o rd ) 24 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 MP opcode summary (continued) Table 7. Miscellaneous Instruction Opcode 3 1 3 0 29 2 8 2 7 2 6 25 24 2 3 2 2 2 1 20 1 9 1 8 1 7 16 15 1 4 1 3 1 2 11 1 0 9 11110-000I -mP M e m D st So u rce 2 /De st M e m D st M e m D st M e m D st M e m D st M e m D st M e m D st M e m D st De st De st De st De st De st De st De st De st De st a C d I m So u rce 2 /De st So u rce 2 /De st D e st D e st D e st S o urce 2 S o urce 2 S o urce 2 S o urce 2 S o urce 2 S o urce 2 S o urce 2 S o u rce S o u rce 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 a a a a 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 I I I I I I I I I I I I I I C a a a a m m m m m m m P P P P P P P Z Z P2 P2 P2 P2 RM P2 8 Z PD d 7 d d d 6 m m m m m m m m P1 P1 P1 P1 P1 P1 P1 5 s s s s s 4 321 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 S ou rce1 0 va d d vsu b vm p y vm su b vrn d(FP) vrnd (In t) vm ac vm sc fa d d fsu b fm p y fd iv frn dx fcm p fsq rt lm o rm o e sto p illo p F PD PD PD PD PD PD Re se rve d (co d e a s 0 ) Flo a tin g -p oin t a ccu m ula to r se lect C o nsta n t o p e ra nd s ra th er th a n re g iste r D estin ation p re cisio n for vecto r (0 =sp, 1 =d p ) Lo n g -im m e d ia te 3 2 -b it d ata P aralle l m e m o ry o p e ra tio n sp e cifie r P De st p re cisio n for p a ra lle l lo a d /sto re (0 =sin gle , 1 =d o ub le) P 1 P re cisio n o f so u rce 1 op e ra n d P 2 P re cisio n o f so u rce 2 op e ra n d P D P re cisio n o f d e stin a tio n re su lt R M R o u nd ing M o d e (0 = N, 1 =Z, 2 =P , 3 =M ) s S ca le offse t by da ta size Z U se 0 ra the r tha n accu m u la to r POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 25 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 MP opcode summary (continued) Table 8. Summary of MP Opcodes INSTRUCTION add and.tt and.ff and.ft and.tf bbo bbz bcnd br brcr bsr cmnd cmp dcache estop fadd fcmp fdiv fmpy frndx fsqrt fsub illop jsr ld ld.u lmo or.tt DESCRIPTION Signed integer add Bitwise AND Bitwise AND with 1's complement Bitwise AND with 1's complement Bitwise AND with 1's complement Branch bit one Branch bit zero Branch conditional Branch always Branch control register Branch and save return Send command Integer compare Flush data cache subblock Emulation stop Floating-point add Floating-point compare Floating-point divide Floating-point multiply Floating-point convert/round Floating-point square root Floating-point subtract Illegal operation Jump and save return Load signed into register Load unsigned into register Leftmost one Bitwise OR INSTRUCTION or.ff or.ft or.tf rdcr rmo shift.dz shift.dm shift.ds shift.ez shift.em shift.es shift.iz shift.im st sub swcr trap vadd vmac vmpy vmsc vmsub vrnd(FP) vrnd(Int) vsub xnor xor DESCRIPTION Bitwise OR with 1's complement Bitwise OR with 1's complement Bitwise OR with 1's complement Read control register Rightmost one Shift, disable mask, zero extend Shift, disable mask, merge Shift, disable mask, sign extend Shift, enable mask, zero extend Shift, enable mask, merge Shift, enable mask, sign extend Shift, invert mask, zero extend Shift, invert mask, merge Store register into memory Signed integer subtract Swap control register Trap Vector floating-point add Vector floating-point multiply and add to accumulator Vector floating-point multiply Vector floating-point multiply and subtract from accumulator Vector floating-point subtract accumulator from source Vector round with floating-point input Vector round with integer input Vector floating-point subtract Bitwise exclusive NOR Bitwise exclusive OR 26 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 parallel processor architecture The Parallel Processor (PP) is a 32-bit integer digital signal processor (DSP) optimized for imaging and graphics applications. The PP can execute in parallel a multiply, ALU operation, and two memory accesses within a single instruction. This internal parallelism allows a single PP to achieve over 500 million operations per second for certain algorithms. The PP has a three-input ALU that supports all 256 three input Boolean combinations and many combinations of arithmetic and Boolean functions. Data merging and bit-to-byte, bit-to-word, and bit-to-halfword translations are supported by hardware in the input data path to the ALU. Typical tasks performed by a PP include: * Pixel-intensive processing - Motion estimation - Convolution - PixBLTs - Warp - Histogram - Mean square error * Domain transforms - DCT - FFT - Hough * Core graphics functions - Line - Circle - Shaded fills - Fonts * Image Analysis - Segmentation - Feature extraction * Bit-stream encoding/decoding - Data merging - Table look-ups functional block diagram Figure 22 shows a block diagram of a parallel processor. Key features of the PP include: * 64-bit instruction word (supports multiple parallel operations) * 3-stage pipeline for fast instruction cycle * Numerous registers - 8 data, 10 address, 6 index registers - 20 other user-visible registers * Data Unit - 16x16 integer multiplies (optional 8x8) - Splittable 3-input ALU - 32-bit barrel rotator - Mask generator - Multiple-status flag expander for translations to/from 1 bit-per-pixel space. - Conditional assignment of results - Conditional source selection - Special processing hardware leftmost one / rightmost one leftmost bit change / rightmost bit change data unit * Memory addressing - 2 address units (global and local) provide up to two 32-bit accesses in parallel with data unit operation. - 12 addressing modes (immediate and indexed) - Byte, halfword, and word addressability - Scaled indexed addressing - Conditional assignment for loads - Conditional source selection for stores * Program flow - Three hardware loop controllers zero overhead looping / branching nested loops multiple loop endpoints - Instruction cache management - PC mapped to register file - Interrupts for messages and context switching * Algebraic assembly language POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 27 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 functional block diagram (continued) Data Unit Data Registers M ultiplier Data Path ALU Data Path Expander M ask Generator Barrel Rotator Three-Input ALU Status Registers Local Address Unit Local D estination/Source Global Address Unit sp=a6=a14 a8-a12, a15 x8-x10 G loba l D estination a0-a4, a7 x0-x2 G loba l S ou rce Local Data Path Global Data Path Program Flow Control Unit Repl A/S Repl A/S 64 Three Zero-O verhead Loop/Branch Controllers Instruction and Cache Control 32 32 Local D ata P ort G lobal D ata P ort R epl - R eplicate hardw are A /S - A lign/sign ex tend hardw are Instruc tion P ort IA P LA P G A P IA P - Instruction address port LA P - Local address port G A P - G lobal address port Figure 22. PP Block Diagram 28 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP registers The PP contains many general-purpose registers. It also has a number of status registers and configuration registers. All PP registers are 32-bit registers. Below are the accessible registers of the various PP blocks. Data Unit Registers Data Registers d0/EALU operation d1 d2 d3 d4 d5 d6 d7 Multiple Flags mf Status sr Address Unit Registers Global Address Unit Address Registers Index Registers a8 a9 a10 a11 a12 a14/sp a15=0 Stack Pointer Same Physical Register x8 x9 x10 Local Address Unit Address Registers Index Registers a0 a1 a2 a3 a4 a6/sp a7=0 x0 x1 x2 PFC Unit Registers PC-Related Registers pc (br, call) iprs ipa (read only) ipe (read only) Cache Tags tag0 (read only) tag1 (rread only) tag2 (read only) tag3 (read only) Loop Control lctl Loop Addresses ls0 ls1 ls2 le0 le1 le2 Loop Counts lr0 lr1 lr2 lc0 lc1 lc2 Interrupts intflg inten Communications comm Figure 23. PP Registers POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 29 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 data unit registers The data unit contains eight 32-bit general-purpose data registers (d0-d7) referred to as the D registers. The d0 register also acts as the control register for EALU operations. d0 register When used as the EALU control register, d0 has the format shown in Figure 24. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FMOD A EALU Function Code SNEFTC I S N E F T 9 8 7 M 6 R 5 U 4 3 2 DBR 1 0 DMS FMOD - function modifiers A - arithemetic enable C - EALU carry-in I - invert-carry-in sign extend nonmultiple mask explicit multiple carry-in expanded mf ALU saturate DMS - default multiply shift amount M - split multiply R - rounded multiply U - saturate multiplier output DBR - default barrel rotate amount Figure 24. d0 Format for EALU Operations mf register The multiple flags (mf) register records status information from each split ALU segment for multiple arithmetic operations. The mf register may be expanded to generate a mask for the ALU. 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 8 7 6 5 4 3 2 1 0 Figure 25. mf Register Format sr register The status register (sr) contains status and control bits for the PP ALU. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 N C V Z L 9 8 7 6 R 5 4 Msize 3 2 1 Asize 0 MSS N - negative status bit C - carry status bit V - overflow status bit Z - zero status bit L - latched overflow (sticky) MSS - mf status selection 00 - set by zero 10 - set by extended result 01 - set by sign 11 - reserved R - rotation bit Msize - expander data size Asize - split ALU data size Figure 26. sr Register Format 30 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 address unit registers address registers The address unit contains ten 32-bit address registers which contain the base address for address computations or may be used for general-purpose data. The registers a0 - a4 are used for local address computations and registers a8-a12 are used for global address computations. index registers The six 32-bit index registers contain index values for use with the address registers in address computations or may be used for general-purpose data. Registers x0-x2 are used by the local address unit and registers x8-x10 are used by the global address unit. stack pointer The stack pointer contains the address of the top of the PP's system stack. The stack pointer is addressed as a6 by the local address unit and as a14 by the global address unit. 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 W o rd -A lign e d A d d re ss 8 7 6 5 4 3 2 1 0 0 0 Figure 27. sp Register Format zero register The zero registers are read-as-zero address registers for the local address unit (a7) and global address unit (a15). Writes to the registers are ignored and may be specified when operational results are to be discarded. 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Figure 28. Zero Registers PFC Unit Registers loop registers The loop registers control three levels of zero-overhead loops. The 32-bit loop start registers (ls0 - ls2) and loop end registers (le0 - le2) contain the starting and ending addresses for the loops. The loop counter registers (lc0 - lc2) contain the number of repetitions remaining in their associated loops. The lr0 - lr2 registers are loop reload registers used to support nested loops. The format for the loop control register (lctl) is shown in Figure 29. There are also six special write-only mappings of the loop reload registers. The lrs0 - lrs2 codes are used for fast initialization of lsn, lrn, and lcn registers for multi-instruction loops while the lrse0 - lrse2 codes are used for single instruction-loop fast initialization. 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 E L C D2 le 2 8 7 E 6 5 L C D1 le 1 4 3 E 2 1 L C D0 le 0 0 E - lo o p e n d e na b le LC D n - loo p co un te r de sig na to r 0 0 0 - N o ne 01 0 - lc1 0 0 1 - lc0 0 1 1 - lc2 1xx - re se rve d Figure 29. lctl Register POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 31 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 pipeline registers The pfc unit contains a pointer to each stage of the PP pipeline. The pc contains the program counter which points to the instruction being fetched. The ipa points to the instruction in the address stage of the pipeline and the ipe points to the instruction in the execute stage of the pipeline. The instruction pointer return-fromsubroutine (iprs) register contains the return address for a subroutine call. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 pc PC (29-Bit Doubleword Address) G - global interrupt enable 0 disable interrupts 1 enable interrupts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ipa 32-Bit Copy of the Previous pc Register Value 9 L - loop inhibit 0 loop logic enabled 1 loop logic disabled 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 G 0 L 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ipe 32-Bit Copy of the Previous ipa Register Value 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 iprs 29-Bit Doubleword Return Address 9 8 7 6 5 4 3 2 - 1 - 0 - Figure 30. Pipeline Registers interrupt registers The interrupt enable register (inten) allows individual interrupts to be enabled and configures intflg operation. The interrupt flag register (intflg) contains interrupt flag bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 inten r r r r r r EE P P 1 M S G P P 0 M S G EEEE M P M S G P T E N D PP TT EQ R R E T A S K 8 7 6 5 4 3 2 1 0 -W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 intflg r r r E W 0 1 r r r r I I I I I I I - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - -reserved (write as 0) -enable interrupt -write mode -writing 1 clears intflg -writing 1 sets intflg PPnMSG -PPn message interrupt MPMSG -MP message interrupt PTEND -packet transfer complete PTERR -packet transfer error PTQ -packet transfer queued TASK -MP task interrupt Figure 31. PP Interrupt Registers 32 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 communication register The comm register contains the packet transfer handshake bits and PP indicator bits. 31 30 29 2 8 27 2 6 25 24 23 2 2 21 2 0 19 18 17 1 6 15 1 4 13 12 11 1 0 HSQP----- ------ ------ H - high p riority p acke t transfer S - packet tran sfer suspend 9 8 7 6 5 4 3 2 10 - PP PP# - pp n um b er (read only) 0 - p p0 1 - pp 1 Figure 32. comm Register cache tag registers The tag0 - tag3 registers contain the tag address and subblock present bits for each cache block. 31 30 29 2 8 27 2 6 25 24 23 2 2 21 2 0 19 18 17 1 6 15 1 4 13 12 11 1 0 9 2 2-Bit Tag Address P P - present b it LRU - least recently used code 00 - m ru 1 0 - next lru 01 - ne xt m ru 1 1 - lru subblock # 7 8 P 6 7 P 5 6 P 4 5 P 3 4 P 2 3 P 1 2 P 0 10 L RU Figure 33. Cache Tag Registers PP cache architecture Each of the two PPs has its own 4K-byte instruction cache. Each cache is divided into four blocks and each block is divided into eight subblocks containing 16 64-bit instructions each. Cache misses cause one subblock to be loaded into cache. Figure 34 shows the cache architecture for one of the four sets in each cache. Figure 35 shows how addresses map into the cache using the cache tags and address bits. 0 1 (b lo c k 0 , s u b 0 ) (b lo c k 0 , s u b 1 ) 2 (b lo c k 0 , s u b 2 ) Block 0 Block 1 Block2 tag0 (Block 0) tag1 (Block 1) tag2 (Block 2) tag3 (Block 3) Subblocks . . . . 30 31 (b lo c k 3 , su b 6 ) (b lo c k 3 , su b 7 ) LRU NLRU NMRU MRU LRU stack Block 3 Figure 34. PP Cache Architecture 32-Bit PC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 22-bit tag value 9 8 sub 7 6 5 4 3 2 1 0 instruction ignored sub - subblock Figure 35. pc Register Cache Address Mapping POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 33 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP parameter RAM The parameter RAM is a noncacheable, 4K-byte, on-chip RAM which contains PP interrupt vectors, PP requested TC task buffers, and a general-purpose area. Figure 36 shows the parameter RAM address map. Suspended PT Parameters (128 Bytes) Reserved (120 Bytes) DEA/Cache Fault Address PP Linked List Start Address Off-Chip to Off-Chip PT Buffer (128 Bytes) Interrupt Vectors (128 Bytes) General-Purpose RAM (3572 Bytes Less Stack Size) 0x0100#000-0x0100#07F 0x0100#080-0x0100#0F7 0x0100#0F8-0x0100#0FB 0x0100#0FC-0x0100#0FF 0x0100#100-0x0100#17F 0x0100#180-0x0100#1FF 0x0100#200 Application - Dependent Boundary Stack Stack State Information After Reset (12 Bytes) 0x0100#FF0 Stack Pointer After Reset 0x0100#FF4-0x0100#FFF # - PP number Figure 36. PP Parameter RAM PP interrupt vectors The PP interrupts and their vector addresses are shown in Table 9. Table 9. PP Interrupt Vectors VECTOR NAME TASK PTQ PTERR PTEND MPMSG PP0MSG PP1MSG ADDRESS 0x0100#1B8 0x0100#1C4 0x0100#1C8 0x0100#1CC 0x0100#1D0 0x0100#1E0 0x010101E4 INTERRUPT Task Interrupt Packet Transfer Queued Packet Transfer Error Packet Transfer End MP Message PP0 Message PP1 Message 34 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP data unit architecture The data unit has independent data paths for the ALU and the multiplier, each with its own set of hardware functions. The multiplier data path includes a 16x16 multiplier, a halfword swapper and rounding hardware. The ALU data path includes a 32-bit three-input ALU, a barrel rotator, mask generator, mf expander, left/right most one and left/right most bit change logic, and several multiplexers. src1/src2/ src4/ dstc/0 src2 src4 src1/ 0x1 dst/ dst1 dst2 src3 0 d0 mf Rotate Amount Multiplexer LMO, RMO, LMBC, RMBC Mask Generator Multiplexer Expander Mask Generator Barrel Rotator Multiplier (Splittable) Scale Round Swap/Merge A C Port Multiplexer Barrel Rotator Input Sign Bit B C Three-Input ALU (Splittable) ALU Function Code Logic N,C,V,Z,L src1 - any register, D reg. only for l/rmo, l/rmbc hardware src2 - D reg. or sometimes 5/32-bit immediate src3 - D reg. only src4 - D reg. only dst/dst1 - any register mf dst2 - D reg. only dstc - D reg. only (dest companion reg source) 0x1 - Constant 0 - Constant d0 - 5 LSBs of d0 Figure 37. Data Unit Block Diagram POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 35 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP data unit architecture (continued) The PP's ALU can be split into one 32-bit ALU, two 16-bit ALUs or four 8-bit ALUs. Figure 38 shows the multiple arithmetic data flow for the case of a four 8-bit split of the ALU (called multiple-byte arithmetic). The ALU operates as independent parallel ALUs where each ALU receives the same function code. 32 m f R e g iste r 4 R ota te C le a r Expa n d er (Re p lica te) 8 8 8 8 sr(C ) A B C -O u t 8 C C -IN C-IN L o g ic A B C -O ut 8 C C -IN C -IN L og ic A B C -O u t 8 C C -IN C-IN L o g ic A B C -O ut 8 C C -IN C -IN L og ic C , Z, S, or E C , Z, S, or E C , Z, S, or E C, Z, S, o r E Figure 38. Multiple-Byte Arithmetic Data Flow During EALU operations, the split ALU outputs may be saturated/clamped at maximum or minimum values. The ALU saturate feature is controlled by the T bit and the N bit in d0, as shown in Table 10. Saturation may only be specified for 32-bit signed arithmetic. Table 10. ALU Saturate/Clamp Option DO (EALU) NON-MULTIPLE MASK/SATURATE-CLAMP OPTION N 0 0 1 1 T 0 1 0 1 Normal operation Reserved Non-multiple mask Saturate-clamp-signed option 32-BIT SIGNED ALU: Result = 0x7FFFFFFF Result = 0x80000000 if if ~Cout[31] & Cin[31] Cout[31] & ~Cin[31] Saturate at max positive value Clamp at most negative value 36 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP multiplier The PP's hardware multiplier can perform one 16x16 multiply with a 32-bit result or two 8x8 multiplies with two 16-bit results in a single cycle. A 16x16 multiply may use signed or unsigned operands as shown in Figure 39. 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 8 7 6 5 S ig n e d In pu t XXXXXXXXXXXXXXXXS 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 SS S ig n e d x S ign e d R e su lt 8 7 6 5 4 3 2 1 0 4 3 2 1 0 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 8 7 6 5 XXXXXXXXXXXXXXXX U n sig n e d In pu t 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 U n sig n ed x U nsig n ed R esult 8 7 6 5 4 3 2 1 0 4 3 2 1 0 Figure 39. 16 x 16 Multiplier Data Formats When performing two simultaneous 8x8 split multiplies. The first input word contains unsigned byte operands and the second input word may contain signed or unsigned byte operands. These formats are shown in Figure 40 and Figure 41. 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 XXXXXXXXXXXXXXXX U nsig n ed in p u t 1 b 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 XXXXXXXXXXXXXXXXS S ig n ed in p u t 2 b 8 7 6 54321 Un sig ne d in p ut 1 a 54321 Sig ne d in p ut 2 a 3 2 1 0 8 7 S 6 0 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 8 7 6 5 4 S 1b x 2 b sig ne d result S 1 a x 2 a sig n e d re su lt 0 Figure 40. Signed Split-Multiply Data Formats 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 XXXXXXXXXXXXXXXX U nsig n ed in p u t 1 b 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 XXXXXXXXXXXXXXXX U nsig n ed in p u t 2 b 8 7 6 54321 Un sig ne d in p ut 1 a 54321 Un sig ne d in p ut 2 a 3 2 1 0 8 7 6 0 3 1 3 0 29 2 8 2 7 2 6 2 5 24 2 3 2 2 2 1 20 1 9 1 8 1 7 1 6 15 1 4 1 3 1 2 11 1 0 9 8 7 6 5 4 1b x 2 b u n sig n e d re su lt 1 a x 2a un sig ne d re su lt 0 Figure 41. Unsigned Split-Multiply Data Formats POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 37 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP multiplier (continued) Additionally, 16 x 16 multiplies may take on another form wherein the multiplier output is rounded by adding bit 15 to bit 16 of the result. The upper 16 bits of the result are written to the upper 16 bits of the destination register, while the lower 16 bits are filled with bits 31-16 of the first multiply source operand. This allows back-to-back multiplies to produce two rounded results, as shown below. 31 A 31 D on 't Care 31 D on 't Care First Instruction d 4 =r d 1 * d2 31 Roun ded B x C1 Seco nd Instruction d 4 =r d 4 * d3 31 Roun ded A x C 2 1 6 15 Rounded B x C1 0 d4 1 6 15 A 0 d4 1 6 15 C2 1 6 15 C1 0 d3 1 6 15 B 0 d2 0 d1 Figure 42. 16 x 16 Rounded Multiply During MPY||EALU operations, the multiplier output may be saturated as specified by the U bit in d0. Saturation is valid only for left shift of 0 and 1, as shown in Table 11. Like the ALU saturation option, multiplier saturation may only be specified during EALUs, and is valid only for signed multiplies. Multiplier and ALU saturation may be independently specified in a given EALU. Saturation is specified using the t function modifier. Table 11. Multiplier Saturation DMS X 0 0 1 X 0 1 X U 0 1 1 1 MULTIPLIER SATURATE OPTION No saturation set result to 0x3FFFFFFF (instead of 0x40000000) set result to 0x7FFFFFFF (instead of 0x80000000) No saturation When rounding is enabled, the 16 LSBs of the result are protected (i.e., unaffected by the saturation option). In this case a pre-saturated result of 0x4000XXXX (DMS = 00) will be saturated to 0x3FFFXXXX, and a presaturated result of 0x7FFFXXXX (DMS = 01) is saturated to 0x8000XXXX. Saturation should not be specified with split multiplies. The || symbol indicates operations are to be performed in parallel. 38 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP program flow control unit architecture The program flow control unit performs instruction fetching and decoding, loop control, and handshaking with the transfer controller. The pfc unit architecture is shown in Figure 43. pc in cre m e nte r ip rs C a ch e C on tro ller ip a ip e L o o p C o ntro lle r 0 ls0 le 0 Ta g C o m p a rato rs Ta g Re g iste rs P re se nt B its LRU S ta ck C o m p a ra to r lr0 lctl In stru ctio n De co d e FA E P ipe lin e C on tro l d e cr. lc0 C o ntro l S ign a l G en e ra tio n Lo o p C o n trol ze ro L o o p C o ntro lle r 1 In stru ction L o o p C o ntro lle r 2 Co n tro l In stru ctio n S ign a l A dd re ss Figure 43. Program Flow Control Unit Block Diagram The PP has a three-stage fetch, address, execute pipeline as shown in Figure 44. The pc, ipa, and ipe registers point to the address of the instruction in each stage of the pipeline. On each cycle in which the pipeline advances, ipa is copied into ipe, pc is copied into ipa, and the pc is incremented by one instruction (8 bytes). In stru ctio n One Two T h re e T1 F e tch T2 T3 A d d re ss E xe cu te F e tch F e tc h T4 T5 pc ip a ip e A d d re ss E xe cu te A d d re ss E xe cu te Figure 44. FAE Instruction Pipeline POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 39 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP address unit architecture The PP has both a local and global address unit which operate independently of each other. The address units support twelve different addressing modes. In place of performing a memory access, either or both of the address units can perform an address computation that is written directly to a PP register instead of being used for a memory access. This address unit arithmetic provides additional arithmetic operation to supplement the data unit during compute-intensive algorithms. F ro m G lo b a l D e s tin a tio n B u s O ffse t T o G lo b a l S o u rce B u s F r o m G lo b a l D e stin a tio n B u s O ffs e t T o G lo b a l S o u rc e B u s sp = a 6 (lo ca l) sp = a 7 (g lo b a l) a0 - a4 (a 7 = 0 ) a8 - a12 (a 1 5 = 0 ) x0 - x2 x8 - x1 0 pba, dba P P -R e la tive M u ltip le xe r In d e x M u ltip le xe r S ca le D a ta S iz e pba, dba P P -R e la tiv e M u ltip le xe r In d e x M u ltip le xe r S ca le D a ta S ize In d e x S ca le r In d e x S ca le r 3 2 -B it A d d e r/S u b tra cte r U n it 3 2 -B it A d d e r/S u b tra cte r U n it P r e in d e x/P o stin d e x M u ltip le xe r P re in d e x/ P o stin d e x P r e in d e x/P o stin d e x M u ltip le xe r P re in d e x/ P o stin d e x L o ca l A d d r e ss P o rt G lo b a l A d d re ss P o rt Figure 45. Address Unit Architecture 40 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP instruction set PP instructions are represented by algebraic expressions for the operations performed in parallel by the multiplier, ALU, global address unit, and local address unit. The expressions use the || symbol to indicate operations that are to be performed in parallel. The PP ALU operator syntax is shown in Table 12. The data unit operations (multiplier and ALU) are summarized in Table 13 and the parallel transfers (global and local) are summarized in Table 14. Table 12. PP Operators by Precedence OPERATOR src1 [n] src1-1 () @mf % %% %! %%! \\ << >>u >> or >>s & ^ | + =[cond] =[cond.pro] = FUNCTION Select odd (n=true) or even (n=false) register of D register pair based on negative condition code Subexpression delimiters Expander operator Mask generator Nonmultiple mask generator (EALU only) Modified mask generator (0xFFFFFFFF output for 0 input) Nonmultiple shift right mask generator (EALU only) Rotate left Shift left (pseudo-op for rotate and mask) Unsigned shift right Signed shift right Bitwise AND Bitwise XOR Bitwise OR Addition Subtraction Conditional assignment Conditional assignment with status protection Equate POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 41 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP instruction set (continued) Table 13. Summary of Data Unit Operations Operation Description Syntax Examples Operation Description Syntax Examples Operation Description Syntax Example Operation Description Syntax Examples Operation Description Syntax Base set ALUs Perform an ALU operation specifying ALU function, 2 src and 1 dest operand, and operand routing. ALU function is one of 256 three-input Boolean operations or one of 16 arithmetic operations combined with one of 16 function modifiers dst = [fmod] [ cond [.pro] ] ALU_EXPRESSION d6 = (d6 ^ d4) & d2 d3 = [nn.nv] d1 -1 EALU || ROTATE Perform an extended ALU (EALU) operation (specified in d0) with one of two data routings to the ALU and optionally write the barrel rotator output to a second dest register. ALU operation is one of 256 Boolean or 256 arithmetic. dst1 = [ cond [.pro] ] ealu (src2, [dst2 = ] [ cond ] src1 n src1-1 \\ src3, [%] src4) dst1 = [fmod] [ cond [.pro] ] ealu (label:EALU_EXPRESSION [ || dst2 = cond src1 [ n src1-1 \\ src3]) d7 = [nn] ealu(d2, d6 = [nn] d3\\d1, %d4) d3 = mzc ealu(mylabel: d4 + (d5\\d6 & %d7) || d1 = d5\\d6) MPY || ADD Perform a 16x16 multiply with optional parallel add or subtract. Condition code applies to both multiply and add. dst2 = [sign] [ cond ] src3 * src4 [ || dst = [ cond [.pro] ] src2 + src1 [ n src1 -1] ] dst2 = [sign] [ cond ] src3 * src4 [ || dst = [ cond [.pro] ] src2 - src1 [ n src1 -1] ] d7 = u d6 * d5 || d5 = d4 - d1 MPY || SADD Perform a 16x16 multiply with a parallel right-shift and add or subtract. Condition code applies to both multiply and shift and add. dst2 = [sign] [ cond ] src3 * src4 || dst = [ cond [.pro] ] src2 + src1 [ n src1 -1] >> -d0 dst2 = [sign] [ cond ] src3 * src4 || dst = [ cond [.pro] ] src2 - src1 [ n src1 -1] >> -d0 d7 = u d6 * d5 || d5 = d4 - d1 >> -d0 MPY || EALU Perform a multiply and an optional parallel EALU. Multiply can use rounding, scaling, or splitting features. Generic Form: dst2 = [sign] [ cond ] src3 * src4 || dst = [ cond [.pro] ] ealu[f] (src2, src1 [ n src1 -1] \\ d0, %d0) dst2 = [sign] [ cond ] src3 * src4 || ealu() Explicit Form: dst2 = [sign] [opt] [ cond ] src3 * src4 [< dint eint dloop eloop qwait nop [ ] - optional parameter extension - square brackets ([ ]) must be used sign - u=unsigned, s=signed cond - condition code f - use 1's complement of d0 fmod - function modifier pro - protect status bits dms - default multiply shift amount 42 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP instruction set (continued) Table 14. Summary of Parallel Transfers Operation Description Syntax Examples Operation Description Syntax Examples Operation Description Syntax Examples Operation Description Syntax Examples Operation Description Syntax Example Operation Description Syntax Example Load Transfer from memory into PP register dst = [sign] [size] [ cond ] * addrexp dst = [sign] [size] [ cond ] * an.element d3 = u h [n] * (a9++=[2]) d1 = * a2.sMY_ELEMENT Store Transfer from PP register into memory * addrexp = [size] src [ n src-1] * an.element = [size] src [ n src-1] * --a2 = d3 *a9.sMY_ELEMENT = a3 Address Unit Arithmetic Compute address and store in PP register. dst = [size] [ cond ] & * addrexp dst = [size] [ cond ] & * an.element d2 = &*(a3 + x0) a1 = &*a9.sMY_ELEMENT Move Transfer from PP register to PP register dst = [g] [ cond ] src x2 = mf d1 = g d3 Field Extract Move Transfer from PP register to PP register extracting and right-aligning one byte or halfword dst = [sign] [size item] d3 = u b2 d1 Field Replicate Move Transfer from PP register to PP register replicating the LSbyte or LShalfword to 32 bits. dst = r [size] cond src d7 = rh d3 cond - condition code g - use global unit size - b=byte, h=halfword, w=word (default) item - 0=byte0/halfword0, 1=byte1/halfword1, 2=byte2, 3=byte3 [ ] - optional parameter extension - square brackets ([ ]) must be used sign - u=unsigned, s=signed POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 43 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP opcode formats A PP instruction uses a 64-bit opcode. The opcode is essentially divided into a data unit portion and a parallel transfer portion. There are five data unit opcode formats comprising bits 39-63 of the opcode. Bits 0-38 of the opcode specify one of ten parallel transfer formats. An alphabetical list of the mnemonics used in Figure 46 for the data unit and parallel transfer portions of the opcode are shown in Table 15 and Table 16, respectively. D ata Unit F orm ats 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 011 oper src3 dst2 dst1 src1 src4 src2 Parallel Transfers 1 1 1 00 010 T ransfer Form ats 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lm ode d e size s La G im /X L 0bank L G m ode reg e size s Ga Lim /X Lm ode Lm ode Lm ode 00 Lm ode 00000000d cond cond cond cond d d reg e size s e size s e size s e size s La La La La 0 Lrm 0 itm 1 Lrm 0 Lrm itm dstbank dstbank bank bank dstbank dstbank bank Adstbank L0000 L0001 L00 L G m ode reg src src reg src src srcbank e size D e size s As1bank srcbank e size D e size s As1bank dst dst Ga --dst dst Ga Lim /X Lim /X 0 G rm Lim /X ----1 G rm 1. Double Parallel 2. M ove || Local 3. Field M ove || Local 4. Local (Long O ffset) 5. G lobal (Long O ffset) 6. Non-D DU || Local 7. Conditional D U || Conditional M ode 8. Conditional D U || Conditional Field M ove 9. Conditional D U || Conditional G lobal 10. Conditional Non-D DU class class class A A A ALU O peration ALU O peration ALU O peration dst dst dst src1 src1 src1 0 11 im m . src2 src2 dstbank O peration Reserved s1bnk Parallel Transfers Parallel Transfers cond 32-B it Im m ediate Parallel Transfers 103210 A . S ix-O p e ra n d (M P Y ||A D D , e tc .) B . B a se S e t A L U (5 -B it Im m e d ia te ) C . B a se S e t A L U (R e g iste r src2 ) D . B a se S e t A L U (3 2 -B it Im m e d ia te ) E . M isce lla n e o u s 10001-0-0-0-0------0 Reserved Local Long O ffset / X G lobal Long O ffset / X c rgNCVZ0 - c rgNCVZ0 c r g N C V Z G im /X c r -NCVZ0 - - Adstbank L 0 0 1 - - - -0000 -0001 L G m ode -001---- ------ Figure 46. PP Opcode Formats 44 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP opcode formats (continued) Table 15. Data Unit Mnemonics MNEMONIC A ALU Operation class cond dst dst1 dst2 dstbank imm.src2 32-Bit Immediate oper Operation src1 src2 src3 src4 s1bank FUNCTION A = 1 selects arithmetic operations, A = 0 selects boolean operations For Boolean operation (A=0), select the eight ALU function signals. For Arithmetic operation (A=1), odd bits specify the ALU function and even bits define the ALU function modifiers. Operation class, determines routing of ALU operands. condition code D register destination or lower three bits of non-D register code. ALU dest. for MPY||ADD, MPY||EALU, or EALU||ROTATE operation. D register or lower three bits of non-D register code Multiply dest. for MPY||ADD or MPY||EALU operation or rotate dest. for EALU||ROTATE operation. D register. ALU register bank. 5-bit immediate for src2 of ALU operation. 32-bit immediate for src2 of ALU operation. Six-operand data unit operation (MPY||ADD, MPY||SADD, MPY||EALU, EALU||ROTATE, divi) Miscellaneous operation ALU source 1 register code (D register unless srcbank or s1bank is used) D register used as ALU source 2 D register for multiplier source (MPY||ADD or MPY||EALU) or rotate amount (EALU||ROTATE) D register for ALU C port operand or EALU||ROTATE mask generator input or multiplier source 2 for MPY||ADD, MPY||EALU Bits 5-3 of src1 register code (bit 6 assumed to be 0) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 45 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP opcode formats (continued) Table 16. Parallel Transfer Mnemonics MNEMONIC 0bank Adstbnk As1bank bank c C cond d D dst dstbank e g Ga Gim / X Gmode Grm itm L La Lim / X Lmode Lrm N r reg s size src srcbank V Z FUNCTION Bits 5-3 of global transfer source/destination register code (bit 6 assumed to be 0) Bits 6-3 of ALU destination register code Bits 6-3 of ALU source 1 register code Bits 6-3 of global (or local) store source or load destination Conditional choice of D register for src1 operand of the ALU Protect status register's carry bit Condition code D register or lower three bits of register code for local transfer source/destination Duplicate least significant data during moves The three lower bits of the register code for move or field move destination Bits 6-3 of move destination register code Sign extend local (bit 31), sign extend global (bit 9) Conditional global transfer Global address register for load, store, or address unit arithmetic Global address unit immediate offset or index register Global unit addressing mode Global PP-relative addressing mode Number of item selected for field extract move L = 1 selects load operation, L = 0 selects store / address unit arithmetic operation Local address register for load, store or address unit arithmetic Local address unit immediate offset or index register Local unit addressing mode Local PP-relative addressing mode Protect status register's negative bit Conditional write of ALU result Register number used with bank or 0bank for global load, store or address unit arithmetic Enable index scaling. Additional index bit for byte accesses or arithmetic operations (bit 28, local; bit 6, global) Size of data transfer (bits 30-29, local; bits 8-7, global) Three lower bits of register code for register-register move source or non-field moves. D register source for field move Bits 6-3 of register code for register-register move source Protect status register's overflow bit [protects L (latched overflow) also] Protect status register's zero bit Unused bit (fill with 0) 46 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP opcode formats (continued) Table 17 summarizes the supported parallel transfer formats, their formats, and whether the transfers are local or global. It also indicates the allowed ALU operations and whether conditions and status protection are supported. Table 17. Parallel Transfer Format Summary ALU Operands Format Double parallel Move | Local Field move | Local Global (long offset) Local (long offset) Non-D DU | Local Conditional move Cond. field move Cond. global Cond. non-D DU 32-bit imm. base ALU DU - data unit dst1 D D D D D Any D D D Any Any src1 D D D D D Any D D D Any Lower Cond No No No No No No Yes Yes Yes Yes Yes Status Protection No No No No No No Yes Yes Yes Yes No s/d - source/destination register Move src dst Any Any D Any Any Any D Any Global Transfer Load/Store/AUA s/d Lower Any Any Index X/short X/long X/short Rel No Yes Yes Rel - relative addressing support Any D s/d D D D Local Transfer Load/Store/AUA Index X/short X/short X/short X/long X/short Rel No Yes No Yes Yes Port Local Local Local Global Global - AUA - address unit arithmetic Table 18 shows the encoding used in the opcodes to specify particular PP registers. A 3-bit register field contains the three LSBs. The register codes are used for the src, src1, src2, src3, src4, dst, dst1, dst2, d, reg, Ga, La, Gim/X, and Lim/X opcode fields. The four MSBs specify the register bank which is concatenated to the register field for the full 7-bit code. The register bank codes are used for the dstbank, s1bnk, srcbank, 0bank, bank, Adstbnk, and As1bank opcode fields. When no associated bank is specified for a register field in the opcode, the D register bank is assumed. When the MSB of the bank code is not specified in the opcode (as in 0bank and s1bank) it is assumed to be 0, indicating a lower register. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 47 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PP opcode formats (continued) Table 18. PP Register Codes Lower Registers (MSB of Bank = 0) Coding Bank 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0001 0001 0001 0001 0010 0010 0010 0010 0010 0010 0010 0010 0011 0011 0011 0011 0011 0011 0011 0011 Reg 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Register a0 a1 a2 a3 a4 reserved a6 (sp) a7 (zero) a8 a9 a10 a11 a12 reserved a14 (sp) a15 (zero) x0 x1 x2 reserved reserved reserved reserved reserved x8 x9 x10 reserved reserved reserved reserved reserved Coding Bank 0100 0100 0100 0100 0100 0100 0100 0100 0101 0101 0101 0101 0101 0101 0101 0101 0110 0110 0110 0110 0110 0110 0110 0110 0111 0111 0111 0111 0111 0111 0111 0111 Reg 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Register d0 d1 d2 d3 d4 d5 d6 d7 reserved sr mf reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pc/call ipa/br ipe # iprs inten intflg comm lctl Coding Bank 1000 1000 1000 1000 1000 1000 1000 1000 1001 1001 1001 1001 1001 1001 1001 1001 1010 1010 1010 1010 1010 1010 1010 1010 1011 1011 1011 1011 1011 1011 1011 1011 Reg 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Register reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Upper Registers (MSB of Bank = 1) Coding Bank 1100 1100 1100 1100 1100 1100 1100 1100 1101 1101 1101 1101 1101 1101 1101 1101 1110 1110 1110 1110 1110 1110 1110 1110 1111 1111 1111 1111 1111 1111 1111 1111 Reg 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Register lc0 lc1 lc2 reserved lr0 lr1 lr2 reserved lrse0 lrse1 lrse2 reserved lrs0 lrs1 lrs2 reserved ls0 ls1 ls2 reserved le0 le1 le2 reserved reserved reserved reserved reserved tag0 # tag1 # tag2 # tag3 # # read only 48 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 data unit operation code For data unit opcode Format A, a 4-bit operation code specifies one of sixteen six-operand operations and an associated data path. See Table 19 for six-operand operation codes. Table 19. Six-Operand Format Operation Codes oper Field Bit 60 59 58 57 0 0 1 1 1 u u 0 0 1 0 1 f 1 u s f k 0 s Operation Type MPY || ADD MPY || EALU EALU || ROTATE divi MPY || SADD u - unsigned s - subtract f - 1's complement function code k - use mask or mf expander operation class code The base set ALU opcodes (Formats B, C, D) use an operation class code to specify one of eight different routings to the A, B, and C ports of the ALU. See Table 20. Table 20. Base Set ALU Class Summary Class Destination dst 000 001 dst dst 010 dst 011 100 dst dst 101 dst 110 dst 111 \\ - rotate left % - Mask generation A Port src2 dstc dstc dstc src2 src2 dstc src1 B Port src1 src1 d0 \\ src1 src1 \\ src2 d0 \\ src1 d0 \\ src1 src1 \\ src2 1 @mf - expand function dstc - companion D reg. C Port @mf src2 %src2 %src2 %d0 @mf src2 src2 ALU operation code For base set ALU Boolean opcodes (A=0), the ALU function is formed by a sum of Boolean products selected by the ALU Operation opcode bits as shown in Table 21. For base set arithmetic opcodes (A=1), the four odd ALU Operation bits specify an arithmetic operation as described in Table 22, while the four even bits specify one of the ALU function modifiers as shown in Table 23. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 49 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 ALU operation code (continued) Table 21. Base Set ALU Boolean Function Codes OPCODE BIT 58 57 56 55 54 53 52 51 PRODUCT TERM A&B&C ~A & B & C A & ~B & C ~A & ~B & C A & B & ~C ~A & B & ~C A & ~B & ~C ~A & ~B & ~C Table 22. Base Set Arithmetics OPCODE BITS CARRY IN ALGEBRAIC DESCRIPTION NATURAL FUNCTION MODIFIED FUNCTION (IF DIFFERENT FROM NATURAL FUNCTION) 57 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 55 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 53 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 51 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x 1 0 1 1 1 C(n) 1/0 1 0 ~C(n) 0/1 0 0 0 1 0 0 A - (B | C) A + (B & ~C) A-C A - (B | ~C) A-B A - (B & @mf | -B & ~@mf) A + |B| A - (B & C) A + (B & C) A + (B & @mf | -B & ~@mf) A - |B| A+B A + (B | ~C) A+C A - (B & ~C) A + (B | C) (A & C) + (B & C) A - B <1< A + B <0< A-C A - B >1> A-B A+B/A-B A+B/A-B A - B>0> A + B>0> A-B/A+B A-B/A+B A+B A + B >1> A+C A - B <0< A + B <1< field A + B >0> - zero-extend shift right >1> - one-extend shift right (A + (B & C)) if sign=0 if class 0 or 5 if class 1-4 or 6-7, A+B if sign=1 if class 0 or 5 if class 1-4 or 6-7, A-B if sign=1 (A - (B & C)) if sign=0 C(n) - LSB of each part of C port register <0< - zero-extend shift left <1< - one-extend shift left 50 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 ALU operation code (continued) Table 23. Function Modifier Codes FUNCTION MODIFIER BITS 58 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 56 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 54 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 52 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Normal operation cin %! if maskgen instruction, lmo if not maskgen %! and cin if maskgen instruction, rmo if not maskgen A port = 0 A port = 0 and cin A port = 0 and %! if maskgen, lmbc if not maskgen A port = 0, %! and cin if maskgen, rmbc if not maskgen mf bit(s) set by carry out(s). (mc) mf bit(s) set based on status register MSS field. (me) Rotate mf by Asize, mf bit(s) set by carry out(s). (mrc) Rotate mf by Asize, mf bit(s) set based on status register MSS field. (mre) Clear mf, mf bit(s) set by carry out(s). (mzc) Clear mf, mf bit(s) set based on status register MSS field. (mze) No setting of bits in mf register. (mx) Reserved lmo - leftmost one rmo - rightmost one lmbc - leftmost bit change rmbc - rightmost bit change MODIFICATION PERFORMED cin - carry in %! - modified mask generator miscellaneous operation code For data unit opcode Format E, the Operation field selects one of the miscellaneous operations. Table 24. Miscellaneous Operation Codes OPCODE BITS 43 0 0 0 0 0 0 0 0 1 42 0 0 0 0 0 0 0 1 x 41 0 0 0 0 1 1 1 x x 40 0 0 1 1 0 0 1 x x 39 0 1 0 1 0 1 x x x nop qwait eint dint eloop dloop reserved reserved reserved No data unit operation. Status not modified. Wait until comm Q bit is clear Global interrupt enable Global interrupt disable Global loop enable Global loop disable MNEMONIC OPERATION POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 51 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 addressing mode codes The Lmode (bits 35-38) and Gmode (bits 13-16) of the opcode specify the local and global transfer for various parallel transfer opcode formats (Lmode in formats 1,2,3,4, and 6 and Gmode in formats 1,5, and 9). The coding for the addressing mode fields is shown in Table 25. Table 25. Addressing Mode Codes CODING 00xx 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 *(an ++= xm) *(an --= xm) *(an ++= imm) *(an --= imm) *(an + xm) *(an - xm) *(an + imm) *(an - imm) *(an += xm) *(an -= xm) *(an += imm) *(an -= imm) EXPRESSION DESCRIPTION Nop (nonaddressing mode operation) Postaddition of index register, with modify Postsubtraction of index register, with modify Postaddition of immediate, with modify Postsubtraction of immediate, with modify Preaddition of index register Presubtraction of index register Preaddition of immediate Presubtraction of immediate Preaddition of index register, with modify Presubtraction of index register, with modify Preaddition of immediate, with modify Presubtraction of immediate, with modify imm - immediate offset an - address register in l/g address unit xm - index register in same unit as an register L, e codes The L and e bits combine to specify the type of parallel transfer performed. For the local transfer, L and e are bits 21 and 31, respectively. For the global transfer, L and e are bits 17 and 9, respectively. Table 26. Parallel Transfer Type L 1 1 0 0 e 0 1 0 1 PARALLEL TRANSFER Zero-extend load Sign-extend load Store Address unit arithmetic 52 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 size codes The size code specifies the data transfer size. For field moves (parallel transfer Format 3), only byte and halfword data sizes are valid. See Table 27. Table 27. Transfer Data Size CODING 00 01 10 11 DATA SIZE Byte (8 bits) Halfword (16 bits) Word (32 bits) Reserved relative addressing mode codes The Lrm and Grm opcode fields allow the local address or global address units, respectively to select PP-relative addressing as shown in Table 28. Table 28. Relative Addressing Mode Codes CODING 00 01 10 11 RELATIVE ADDRESSING MODE Normal (absolute addressing) Reserved PP-relative dba PP-relative pba dba - Data RAM 0 base is base address pba - Parameter RAM base is base address condition codes In the four conditional parallel transfer opcodes (Formats 7-10), this field specifies one of sixteen condition codes to be applied to the data unit operation source, data unit result, or global transfer based on the setting of the c, r, and g bits, respectively. The condition codes are shown in Table 29. For the 32-bit immediate data unit opcode (Format D), the condition applies to the data unit result only. Table 29. Condition Codes CONDITION BITS 35 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 34 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 33 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 32 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 u p ls hi lt le ge gt hs, c lo, nc eq, z ne, nz v nv n nn Unconditional (default) Positive Lower than or same Higher than Less than Less than or equal Greater than or equal Greater than Higher than or same, carry Lower than, no carry Equal, zero Not equal, not zero Overflow No overflow Negative Nonnegative None ~N & ~Z ~C | Z C & ~Z (N & ~V) | (~N & V) (N & ~V) | (~N & V) | Z (N & V) | (~N & ~V) (N & V & ~Z) | (~N & ~V & ~Z) C ~C Z ~Z V ~V N ~N MNEMONIC DESCRIPTION STATUS BIT COMBINATION POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 53 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 EALU operations Extended ALU (EALU) operations allow the execution of more advanced ALU functions than those specified in the base set ALU opcodes. The opcode for EALU instructions contains the operands for the operation while the d0 register extends the opcode by specifying the EALU operation to be performed. The format of d0 for EALU operations is shown in Figure 24. EALU Boolean functions EALU operations support all 256 Boolean ALU functions plus the flexibility to add 1 or a carry-in to Boolean sum. The Boolean function performed by the ALU is: (F0 & (~A & ~B & ~C)) | F1 & (A & ~B & ~C) | F2 & (~A & B & ~C) | F3 & (A & B & ~C) | F4 & (~A & ~B & C) | F5 & (A & ~B & C) | F6 & (~A & B & C) | F7 & (A & B & C)) [+1 | +cin] Table 30. EALU Boolean Function Codes d0 BIT 26 25 24 23 22 21 20 19 ALU FUNCTION SIGNAL F7 F6 F5 F4 F3 F2 F1 F0 A&B&C ~A & B & C A & ~B & C ~A & ~B & C A & B & ~C ~A & B & ~C A & ~B & ~C ~A & ~B & ~C PRODUCT TERM EALU arithmetic functions EALU operations support all 256 arithmetic functions provided by the three-input ALU plus the flexibility to add 1 or a carry-in to the result. The arithmetic function performed by the ALU is: f(A,B,C) = A & f1(B,C) + f2(B,C) [+1 | cin] f1(B,C) and f2(B,C) are independent Boolean combinations of the B and C ALU inputs. The ALU function is specified by selecting the desired f1 and f2 subfunction and then XORing the f1 and f2 code from Table 31 to create the ALU function code for bits 19-26 of d0. Additional operations such as absolute values and signed shifts can be performed using d0 bits which control the ALU function based on the sign of one of the inputs. 54 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 EALU arithmetic functions (continued) Table 31. ALU f1(B,C) and f2(B,C) Subfunctions f1 CODE 00 AA 88 22 A0 0A 80 2A A8 02 08 A2 8A 20 28 82 f2 CODE 00 FF CC 33 F0 0F C0 3F FC 03 0C F3 CF 30 3C C3 0 -1 B -B -1 C -C -1 B&C -(B & C) - 1 B|C -(B | C) - 1 B & ~C -(B & ~C) -1 B | ~C -(B | ~C) -1 (B & ~C) | ((-B - 1) & C) (B & C) | ((-B - 1) & ~C) Zero the term -1 (All 1s) B Negate B C Negate C Force bits in B to 0 where bits in C are 0 Force bits in B to 0 where bits in C are 0 and negate Force bits in B to 1 where bits in C are 1 Force bits in B to 1 where bits in C are 1 and negate Force bits in B to 0 where bits in C are 1 Force bits in B to 0 where bits in C are 1 and negate Force bits in B to 1 where bits in C are 0 Force bits in B to 1 where bits in C are 0 and negate Choose B if C = all 0s and -B if C = all 1s Choose B if C = all 1s and -B if C = all 0s SUBFUNCTION COMMON USAGE transfer controller architecture The transfer controller (TC) is a combined memory controller and DMA (direct memory access) machine. It handles the movement of data within the `C82 system as requested by the master processor, parallel processors, and external devices. The transfer controller performs the following data movement and memory control functions: * MP and PP instruction cache fills * MP data cache fills and dirty block write-back * MP and PP direct external accesses (DEAs) * MP and PP packet transfers * Externally initiated packet transfers (XPTs) * Shift register transfer (SRT) packet transfers for updating VRAM-based frame buffers * DRAM/SDRAM refresh * Host bus request TC functional block diagram A functional block diagram of the transfer controller is shown in Figure 47. Key features of the TC include: * Crossbar Interface - 64-bit data path - Single-cycle access * External Memory Interface - 4 GByte address range POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 55 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 TC functional block diagram (continued) - Internal memory configuration-cache stores up to six sets of bank information. Features programmable: bus size : 8, 16, 32, or 64 bits page size bank size address multiplexing cycle timing block-write mode bank priority - Big or little endian operation * Cache, VRAM, refresh controller - Programmable refresh rate - VRAM block write support * Independent Src and Dst addressing - Autonomous addressing based on packet transfer parameters - Data read and write at different rates - Numerous data merging and alignment functions performed during transfer * Intelligent request prioritization Src Mux and Alignment Crossbar Interface Src Controller Src Control Registers Packet Transfer FIFO Cache Buffer Dst Mux and Alignment External Memory Interface Dst Controller Dst Control Registers Memory Configuration Cache 64 64 64 64 Cache, VRAM, and Refresh Controller Request Queuing and Prioritization MP Requests PP Requests XPT Requests Host Requests Figure 47. TC Block Diagram transfer controller registers The TC contains four on-chip memory-mapped registers accessible by the MP. REFCNTL register (0x01820000) The REFCNTL register controls refresh cycles. 3 1 3 0 29 2 8 2 7 2 6 25 2 4 2 3 2 2 21 2 0 1 9 1 8 17 1 6 1 5 1 4 13 1 2 1 1 1 0 9 8 7 6 R P AR L D RE FR A TE R P A RL D - refre sh p se u d o-ad d re ss re loa d va lu e 5 4 3 2 1 0 R E FR A TE - re fresh inte rva l (in clo ck cycle s) Figure 48. REFCNTL Register 56 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PTMIN register (0x01820004) The PTMIN register determines the minimum number of cycles that a packet transfer will execute before being suspended by a higher-priority packet transfer. Short-form XPTs may interrupt long-form PTs without suspending them. 3 1 3 0 29 2 8 2 7 2 6 25 2 4 2 3 2 2 21 2 0 1 9 1 8 17 1 6 1 5 1 4 13 1 2 1 1 1 0 9 P TM IN 8 7 6 5 4 3 2 1 0 Figure 49. PTMIN Register PTMAX register (0x01820008) The PTMAX register determines the maximum number of cycles after PTMIN has elapsed that a packet transfer will execute before timing out. 3 1 3 0 29 2 8 2 7 2 6 25 2 4 2 3 2 2 21 2 0 1 9 1 8 17 1 6 1 5 1 4 13 1 2 1 1 1 0 9 PTM A X 8 7 6 5 4 3 2 1 0 Figure 50. PTMAX Register FLTSTS register (0x0182000C) The FLTSTS register indicates the cause of a memory-access fault. Fault status bits are cleared by writing a 1 to the appropriate bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PC PC PP PP PP # 1 0 PP # 1 0 XPT - Faulting XPT M - M P packet transfer fault 9 8 7 6 XPT 5 4 3 2 1 0 M PC - PPx cache / DEA fault PP - PPx packet transfer fault Figure 51. FLTSTS Register packet transfer parameters The most efficient method for data movement in a TMS320C82 system is through the use of packet transfers (PTs). Packet transfers allow the TC to autonomously move blocks of data between a specified src and dst memory region. Requests for the TC to execute a packet transfer may be made by the MP, PPs, or external devices. A packet transfer parameter table describing the data packet and how it is to be transferred must be programmed in on-chip memory before the transfer is requested. The TC on the TMS320C82 supports short- and long-form packet transfers. The PT parameter tables for both formats are shown in Figure 52 and Figure 53. 31 Ne xt E ntry A dd re ss P T O ption s Src S ta rt/B ase A d d re ss D st S ta rt/B ase A d d re ss S rc B C ou n t Dst B C ou n t S rc A C ou n t Dst A C ou n t 0 PT PT+ 4 PT+ 8 PT+ 1 2 PT+ 1 6 PT+ 2 0 PT+ 2 4 PT+ 2 8 31 S rc B P itch D st B P itch S rc C P itch / G u ide Ta ble P o in te r D st C P itch / Gu ide Ta ble P o in te r Tra n sp a re ncy / C o lo r W o rd 0 Tra n sp a re ncy / C o lo r W o rd 1 Re se rved Re se rved * w ords a re sw appe d in big e nd ia n m ode 0 PT+ 3 2 PT+ 3 6 PT+ 4 0 PT+ 4 4 PT+ 4 8 * PT+ 5 2 * PT+ 5 6 PT+ 6 0 Src C C o un t / # of En tries Dst C Co u n t / # o f E n trie s PT - 6 4-byte a ligne d on-chip starting ad dress o f param eter table Figure 52. Packet Transfer Parameter Table - Long Form POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 57 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 packet transfer parameters (continued) 31 Ne xt E ntry A dd re ss P T Op tio n s A C o u nt S rc S ta rt A d d re ss D st Sta rt A dd re ss 0 PT PT+ 4 PT+ 8 PT+ 1 2 PT - 1 6-byte a ligne d on-chip starting ad dress o f param eter table Figure 53. Packet Transfer Parameter Table - Short Form PT options field The PT Options field of the parameter table controls the type of Src and Dst transfer that the TC performs. The format of the options field is shown in Figure 54. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S PTS I RDC RDB RA RSC RSB SF X PAM STM SUM DTM DUM Short form A count S - Stop bit PTS - PT status 00 - active 10 - fault on src 01 - suspended 11 - fault on dst I - Interrupt when complete RDC - Reverse dst C addressing (Short form: Dst update) RDA - Reverse A addressing STM/DTM - src/dst transfer mode RSC - Reverse src C addressing 000 - dimensioned 100 - var delta guided (Short form: Src update) 001 - fill * 101 - var offset guided RSB - Reverse src B addressing 010 - circular 110 - fixed delta-guided SF - Short form select 011 - LUT * 111 - fixed offset-guided X - Exchange src & dst parameters SUM/DUM - src/dst update mode PAM - pt Access mode 00 - none 01 - add C pitch Long Form PTs Short Form PTs 01 - add B pitch 11 - add C pitch & reverse 000 - normal 000 - normal 001 - pdt 001 - pdt * valid for src only 010 - block write 010 - split register srt (read only) 011 - srt 011 - full srt (read only) 100 - 8-bit tran 100 - Reserved 101 - 16-bit tran 101 - Reserved 110 - 32-bit tran 110 - Reserved 111 - 64-bit tran 111 - Reserved Reserved Figure 54. PT Options Field 58 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 LOCAL MEMORY INTERFACE status codes The TMS320C82 outputs status information on two busses which describe the type of cycle being performed. During row time, status codes are output on AD[39:32] and STATUS[1:0]. The cycle type may be latched using /RL and used by external logic to perform memory bank decoding or enable special hardware features. The STATUS[1:0] pins indicate idle cycles and ending XPT accesses. Table 32. Row Time Status Codes (AD[39:32]) AD[39:36] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SOURCE `C82 XPT1 XPT2 XPT3 XPT4 XPT5 XPT6 XPT7 XPT8 XPT9 XPTa XPTb XPTc XPTd XPTe XPTf AD[35:32] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ACTIVITY Read Write PDT Read PDT Write PT Full SRT Read Reserved PT Split SRT Read Reserved SDRAM MRS Block Write Reserved Load Color Register Refresh SDRAM DCAB Bank Configuration Idle Table 33. Memory Cycle Status STATUS[1:0] 0 0 1 1 0 1 0 1 ACTIVITY Idle/DCAB/Drain Row access XPT end Column access POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 59 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 memory bank configuration Before an access can begin, the `C82 must know certain information about the memory bank it is addressing. Information about the bus size, address shifting, memory speed, and bank size is read in during a special configuration cycle and stored in an on-chip memory configuration cache. The `C82 memory configuration cache holds up to six entries, which are maintained with a multi-priority level least recently used algorithm. The memory configuration cache is only accessible by the TC; software may not modify the contents of the cache. The bank configuration fields are read in over the AD bus in four consecutive bytewide reads, and have the format shown in Figure 55. A D[7:0] or A D[6 3:5 6] 6543210 TO PS RBW PL B WS MS CT AS BS R C A[ 1:0] 0 0 1 1 0 1 0 1 7 FUNCTION GROUP cy cle timing addr ess control bus size bank prop erties E Figure 55. Bank Configuration Cycle Fields memory exceptions Retry and fault conditions are encoded on the /EXCEPT[1:0] pins on the `C82. Additionally, a configuration cache flush may be requested over these pins. The /EXCEPT[1:0] codes are shown in Table 34. Table 34. Memory Exception Codes /EXCEPT[1:0] 0 0 1 1 0 1 0 1 MEMORY EXCEPTION Configuration cache flush Fault Retry or page request None Support for exceptions is not mandatory. Exception support may be enabled or disabled on a bank-by-bank basis. During the bank configuration cycle, if the E bit is set to one, exception support will be enabled for that particular bank. When E is set to 0, except codes of 00 and 01 are ignored during accesses to that bank. Page requests are not sensitive to the E bit. read turn around Data is driven by, and read into, the `C82 over the AD[63:0] bus. Additionally, at row time address and status information is output over this bus. Because of this, the potential exists for a drive conflict, particularly when reading from slow devices such as EPROMs. To compensate for this, extra cycles may be added to the end of read bursts to allow memories and drivers to turn off. Similarly, PDT write cycles contain the minimum number of turnoff cycles as their PDT read cycle counterparts. The number of turnoff cycles is controlled by the TO field in the bank configuration cache entry. The TO encodings are shown in Table 35. Table 35. TO (Turnoff) Cycle Encoding TO(1:0) 0 0 1 1 0 1 0 1 EXTRA TURNOFF CYCLES None 1 2 3 60 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 cycle time selection The `C82 supports fourteen sets of memory timings to interface with various memory types. The cycle timing is selected by the value input in the CT(3:0) field during a bank configuration cycle. The selected timing remains in effect for all accesses made to that bank while its configuration is in cache. Table 36. Cycle Timing Selection CT(3:0) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CYCLE TIMING DRAM: pipelined 1 cycle/column EDO DRAM: unpipelined 1 cycle/column EDO DRAM: unpipelined 2 cycle/column EDO DRAM: unpipelined 3 cycle/column EDO SRAM: synchronous 1 cycle/column SRAM: asynchronous 1 cycle/column SRAM: asynchronous 2 cycle/column SRAM: asynchronous 3 cycle/column SDRAM: burst length 1; CAS latency 2 SDRAM: burst length 1; CAS latency 3 SDRAM: burst length 1; CAS latency 4 Reserved SDRAM: burst length 2; CAS latency 2 SDRAM: burst length 2; CAS latency 3 SDRAM: burst length 2; CAS latency 4 Reserved POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 61 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 page sizing Whenever the `C82 performs an external access, it must track the current page boundary of the addressed bank. When a page boundary is crossed, a new row access must be performed. This is accomplished by comparing certain bits of the logical address bus. Because the location of the logical address on the RCA[16:0] bus is dependent on bus size (controlled by BS(1:0)), page size is also affected by the BS(1:0) inputs. Table 37 outlines the effective page sizes as a function of PS(3:0) and BS(1:0). Table 37. Page Size PS(3:0) BS(1:0) LOGICAL ADDRESS BITS COMPARED None None None None 31:3 31:4 31:5 31:6 31:4 31:5 31:6 31:7 31:5 31:6 31:7 31:8 31:6 31:7 31:8 31:9 31:7 31:8 31:9 31:10 31:8 31:9 31:10 31:11 31:9 31:10 31:11 31:12 PAGE SIZE PS(3:0) BS(1:0) LOGICAL ADDRESS BITS COMPARED 31:10 31:11 31:12 31:13 31:11 31:12 31:13 31:14 31:12 31:13 31:14 31:15 31:13 31:14 31:15 31:16 31:14 31:15 31:16 31:17 31:15 31:16 31:17 31:18 31:16 31:17 31:18 31:19 31:17 31:18 31:19 31:20 PAGE SIZE 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 byte 2 bytes 4 bytes 8 bytes 8 bytes 16 bytes 32 bytes 64 bytes 16 bytes 32 bytes 64 bytes 128 bytes 32 bytes 64 bytes 128 bytes 256 bytes 64 bytes 128 bytes 256 bytes 512 bytes 128 bytes 256 bytes 512 bytes 1K byte 256 bytes 512 bytes 1K byte 2K bytes 512 bytes 1K byte 2K bytes 4K bytes 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1K byte 2K bytes 4K bytes 8K bytes 2K bytes 4K bytes 8K bytes 16K bytes 4K bytes 8K bytes 16K bytes 32K bytes 8K bytes 16K bytes 32K bytes 64K bytes 16K bytes 32K bytes 64K bytes 128K bytes 32K bytes 64K bytes 128K bytes 256K bytes 64K bytes 128K bytes 256K bytes 512K bytes 128K bytes 256K bytes 512K bytes 1M byte 62 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 address multiplexing In order to support various RAM devices, the TMS320C82 provides multiplexed row and column addresses on the RCA bus. A full 32-bit address is always output on AD[31:0] at row time. This value can be latched with /RL to provide bank-decoding. The actual address lines to memory should be connected to the RCA bus. In order to support a wide variety of memory types, the logical address output on RCA is a function of both bus size and address shift. The row-column address multiplexing on the RCA bus is shown in Table 39. Memories and peripherals should be physically connected to RCA[N:0], where N is the number of address pins on the device. As the logical address bits output on the RCA bus is a function of both address shift and bus size, this connection is valid regardless of the memory architecture. When performing peripheral device packet transfers, the lower bits (logical address bits 0, 1, and 2) may be lost depending on the configuration of the memory bank. To compensate for this, the B bit may be set for memory banks which must support PDTs. When set, the TC will place the missing lower address bits on the upper bits of the RCA bus during PDT accesses. External logic may decode these bits to access the byte information. The bit replacement functionality is shown in Table 38. Note that the row address output on RCA[16:0] is unaffected. Table 38. PDT Address Bit Replacement (B=1) BUS WIDTH 1 byte 2 bytes 4 bytes 8 bytes 16 16 0 1 2 15 15 16 0 1 LOGICAL ADDRESS BITS OUTPUT ON RCA[16:0] DURING COLUMN TIME 14 13 12 11 10 9 8 7 6 5 4 3 2 14 15 16 0 13 14 15 16 12 13 14 15 11 12 13 14 10 11 12 13 9 10 11 12 8 9 10 11 7 8 9 10 6 7 8 9 5 6 7 8 4 5 6 7 3 4 5 6 2 3 4 5 1 1 2 3 4 0 0 1 2 3 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 63 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 address multiplexing (continued) Table 39. RCA Address Multiplexing (B = 0) Cycle Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col Row Col AS[2:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 BS[1:0] 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 16 x 19 x 18 31 17 30 16 x 19 31 18 30 17 29 16 31 19 30 18 29 17 28 16 30 19 29 18 28 17 27 16 29 19 28 18 27 17 26 16 28 19 27 18 26 17 25 16 27 19 26 18 25 17 24 16 19 19 18 18 17 17 16 16 15 x 18 31 17 30 16 29 15 31 18 30 17 29 16 28 15 30 18 29 17 28 16 27 15 29 18 28 17 27 16 26 15 28 18 27 17 26 16 25 15 27 18 26 17 25 16 24 15 26 18 25 17 24 16 23 15 18 18 17 17 16 16 15 15 14 31 17 30 16 29 15 28 14 30 17 29 16 28 15 27 14 29 17 28 16 27 15 26 14 28 17 27 16 26 15 25 14 27 17 26 16 25 15 24 14 26 17 25 16 24 15 23 14 25 17 24 16 23 15 22 14 17 17 16 16 15 15 14 14 13 30 16 29 15 28 14 27 13 29 16 28 15 27 14 26 13 28 16 27 15 26 14 25 13 27 16 26 15 25 14 24 13 26 16 25 15 24 14 23 13 25 16 24 15 23 14 22 13 24 16 23 15 22 14 21 13 16 16 15 15 14 14 13 13 12 29 15 28 14 27 13 26 12 28 15 27 14 26 13 25 12 27 15 26 14 25 13 24 12 26 15 25 14 24 13 23 12 25 15 24 14 23 13 22 12 24 15 23 14 22 13 21 12 23 15 22 14 21 13 20 12 15 15 14 14 13 13 12 12 Logical address bits output on RCA (16:0) 11 10 9 8 7 6 5 28 27 26 25 24 23 22 14 13 12 11 10 9 8 27 26 25 24 23 22 21 13 12 11 10 9 8 7 26 25 24 23 22 21 20 12 11 10 9 8 7 6 25 24 23 22 21 20 19 11 10 9 8 7 6 5 27 26 25 24 23 22 21 14 13 12 11 10 9 8 26 25 24 23 22 21 20 13 12 11 10 9 8 7 25 24 23 22 21 20 19 12 11 10 9 8 7 6 24 23 22 21 20 19 18 11 10 9 8 7 6 5 26 25 24 23 22 21 20 14 13 12 11 10 9 8 25 24 23 22 21 20 19 13 12 11 10 9 8 7 24 23 22 21 20 19 18 12 11 10 9 8 7 6 23 22 21 20 19 18 17 11 10 9 8 7 6 5 25 24 23 22 21 20 19 14 13 12 11 10 9 8 24 23 22 21 20 19 18 13 12 11 10 9 8 7 23 22 21 20 19 18 17 12 11 10 9 8 7 6 22 21 20 19 18 17 16 11 10 9 8 7 6 5 24 23 22 21 20 19 18 14 13 12 11 10 9 8 23 22 21 20 19 18 17 13 12 11 10 9 8 7 22 21 20 19 18 17 16 12 11 10 9 8 7 6 21 20 19 18 17 16 15 11 10 9 8 7 6 5 23 22 21 20 19 18 17 14 13 12 11 10 9 8 22 21 20 19 18 17 16 13 12 11 10 9 8 7 21 20 19 18 17 16 15 12 11 10 9 8 7 6 20 19 18 17 16 15 14 11 10 9 8 7 6 5 22 21 20 19 18 17 16 14 13 12 11 10 9 8 21 20 19 18 17 16 15 13 12 11 10 9 8 7 20 19 18 17 16 15 14 12 11 10 9 8 7 6 19 18 17 16 15 14 13 11 10 9 8 7 6 5 14 13 12 11 10 9 8 14 13 12 11 10 9 8 13 12 11 10 9 8 7 13 12 11 10 9 8 7 12 11 10 9 8 7 6 12 11 10 9 8 7 6 11 10 9 8 7 6 5 11 10 9 8 7 6 5 4 21 7 20 6 19 5 18 4 20 7 19 6 18 5 17 4 19 7 18 6 17 5 16 4 18 7 17 6 16 5 15 4 17 7 16 6 15 5 14 4 16 7 15 6 14 5 13 4 15 7 14 6 13 5 12 4 7 7 6 6 5 5 4 4 3 20 6 19 5 18 4 17 3 19 6 18 5 17 4 16 3 18 6 17 5 16 4 15 3 17 6 16 5 15 4 14 3 16 6 15 5 14 4 13 3 15 6 14 5 13 4 12 3 14 6 13 5 12 4 11 3 6 6 5 5 4 4 3 3 2 19 5 18 4 17 3 16 2 18 5 17 4 16 3 15 2 17 5 16 4 15 3 14 2 16 5 15 4 14 3 13 2 15 5 14 4 13 3 12 2 14 5 13 4 12 3 11 2 13 5 12 4 11 3 10 2 5 5 4 4 3 3 2 2 1 18 4 17 3 16 2 15 1 17 4 16 3 15 2 14 1 16 4 15 3 14 2 13 1 15 4 14 3 13 2 12 1 14 4 13 3 12 2 11 1 13 4 12 3 11 2 10 1 12 4 11 3 10 2 9 1 4 4 3 3 2 2 1 1 0 17 3 16 2 15 1 14 0 16 3 15 2 14 1 13 0 15 3 14 2 13 1 12 0 14 3 13 2 12 1 11 0 13 3 12 2 11 1 10 0 12 3 11 2 10 1 9 0 11 3 10 2 9 1 8 0 3 3 2 2 1 1 0 0 64 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 user-defined wait states Some memory architectures (most notably DRAM and SDRAM) may require wait states to be added to the `C82's external interface. For memories and peripherals requiring a larger row time for decoding purposes, the R bit may be set in the configuration cache entry for those memory banks which will cause the `C82 to automatically insert a single additional state into row time of the external memory cycle. For DRAM and SRAM accesses, the additional state is inserted between ad2 and rl1 (with /RAS high). For SDRAM accesses, the state is inserted between ac2 and the column pipeline (to increase the time between ACTV and a READ/WRT command). Table 40. Row (R) Time Wait State Selection MEMORY TYPE CT=00xx (EDO DRAM) R 0 1 CT=01xx (SRAM) 0 1 CT=1xxx (SDRAM) 0 1 None 1 between ad2 and rl1 (/RAS high) None 1 between ad2 and rl1 (/RAS high) None 1 between ac2 and first column access ADDITIONAL CYCLE INSERTED Additionally, the WS field in the configuration cache entry for each memory bank allows the user to automatically insert a predefined number of wait states into the column time pipeline without using the READY input. This significantly enhances the `C82s ability to interface with slower peripherals at higher clock rates. When WS(1:0) is set to a nonzero value, wait states will be inserted into the column time pipeline. If the READY signal is asserted, then additional wait states will be inserted as per the normal sampling mechanism of the READY input (during the final cycle of each column access). Similar to the READY input, the WS(1:0) field should only be set to a nonzero value for 2 and 3 cyc/col accesses. Wait states inserted due to this field will output a status code of 11 (column time) on STATUS[1:0] so that the system may differentiate between the default wait states and pipeline bubbles. Table 41. WS (Wait State) Encoding ADDITIONAL CYCLES MEMORY TYPE WS[1:0] 00 CT=001x (EDO DRAM) 01 10 11 00 CT=011x (SRAM) 01 10 11 None 1 low 1 low, 1 high 2 low, 1 high None 1 low 2 low 3 low INSERTED (REFERENCES /CAS/DQM) Note: The WS(1:0) field should be set to 00 for single-cycle memory banks. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 65 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 block write support The TMS320C82 supports three modes of VRAM block write. The block-write mode is selectable so that software may specify block writes without knowing what type of block-write the addressed memory supports. Block writes are only supported for 64-bit busses. During block-write and load-color-register cycles, the block-write mode specified by the BW(1:0) bits of the bank configuration block will be used. Table 42 lists the block-write modes associated with the BW(1:0) bits. Table 42. Block Write Selection BW(1:0) 00 01 10 11 BLOCK-WRITE MODE Simulated Reserved 4x 8x bus sizing The `C82 supports data bus sizes of 8, 16, 32, or 64 bits. The value input in the BS(1:0) field of the bankconfiguration cycle indicates the bus size of the addressed memory. This determines the maximum number of bytes that the `C82 can transfer during each column access. If the number of bytes to be transferred exceeds the bus size, multiple accesses will automatically be performed to complete the transfer. Table 43. Bus Size Selection BS(1:0) 00 01 10 11 8 bits 16 bits 32 bits 64 bits BUS SIZE The selected bus size also determines which portion of the data bus will be used for the transfer. For 64-bit memory, the entire data bus is used. For 32-bit memory, AD[31:0] are used in little-endian mode and AD[63:32] are used in big-endian mode. 16-bit busses use AD[15:0] and AD[63:48]; and 8-bit busses use AD[7:0] and AD[63:56] for little- and big-endian, respectively. The `C82 always aligns data to the proper portion of the bus and activates the appropriate /CAS/DQM strobes. During read cycles, all /CAS/DQM strobes will be active (low). During write cycles, only those /CAS/DQM strobes corresponding to bytes actually being written will be activated. cache priority level The `C82 memory configuration cache can contain up to six entries. Once full, memory accesses to unconfigured banks require that one of the entries in cache be flushed and a configuration cycle for the desired bank be performed. The cache uses a multilevel, least-recently-used algorithm to determine which entry to flush. Because certain entries (i.e., code space, data space) may pertain to more time-critical functions than others, each of the six entries in the cache can be assigned a priority of high, medium, or low; indicated by the PL(1:0) bits of the configuration cycle fields for that bank. The LRU algorithm is implemented for each priority level separately; that is, when it becomes necessary to discard an entry, the least recently used entry of lowest priority present is discarded. The priority level encoding is shown below. Table 44. Cache Priority Levels PL(1:0) 0 0 0 1 1 0 1 1 PRIORITY LEVEL Low Medium Reserved High 66 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 bank size Since many memory types may require the same configuration, the bank configuration contains a memorybank-size field called MS(4:0). This field specifies the size of the memory bank to which the cache entry pertains, and thus which address bits should be compared to determine if a cache miss has occurred. The MS(4:0) codings are shown in Table 45. Table 45. Memory Bank Size MS(4:0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ADDRESS BITS COMPARED None 31 31:30 31:29 31:28 31:27 31:26 31:25 31:24 31:23 31:22 31:21 31:20 31:19 31:18 31:17 31:16 31:15 31:14 31:13 31:12 31:11 31:10 31:9 31:8 31:7 31:6 31:5 31:4 31:3 31:2 31:1 4G bytes 2G bytes 1G byte 512M bytes 256M bytes 128M bytes 64M bytes 32M bytes 16M bytes 8M bytes 4M bytes 2M bytes 1M byte 512K bytes 256K bytes 128K bytes 64K bytes 32K bytes 16K bytes 8K bytes 4K bytes 2K bytes 1K bytes 512 bytes 256 bytes 128 bytes 64 bytes 32 bytes 16 bytes 8 bytes 4 bytes 2 bytes BANK SIZE refresh controller The `C82 has an on-chip refresh controller that schedules refresh cycles to be performed by the TC. Refresh rate is programmable via the TC's REFCNTL register. A refresh pseudo-address is output on AD[16:1] during refreshes, which may be used for bank-decoding. The refresh pseudo-address is decremented once for each refresh cycle that is performed. When it decrements to 0, it is reloaded with the value in the upper 16 bits of the REFCNTL register. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 67 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 refresh controller (continued) A refresh cycle is indicated by the status code 0x00001100 on AD[39:32] at row time. During a refresh cycle, information input on /EXCEPT[1:0] tells the TC what type of refresh cycle to perform. The /EXCEPT[1:0] encoding for refresh cycles is shown in Table 46. A retried refresh cycle is immediately terminated, and the refresh pseudo-address is not decremented. Table 46. Refresh Cycles /EXCEPT[1:0] 0 0 1 1 0 1 0 1 REFRESH MODE DRAM (3 cycles /RAS high) DRAM (4 cycles /RAS high) Retry SDRAM SDRAM support The TMS320C82 provides direct support for synchronous DRAM (SDRAM) and graphics RAM (SGRAM). During `C82 power-up refresh cycles, the external system must signal the presence of these memories by inputting an /EXCEPT[1:0] code of 11. This causes the `C82 to perform an SDRAM deactivate (DCAB) command. Additionally, the `C82 will perform an SDRAM mode register set (MRS) cycle following a memory bank configuration cycle if that cycle specifies an SDRAM cycle timing code. No further MRS cycles will be performed for that bank as long as it remains in cache. The MRS cycle is required to initialize the SDRAM for operation. Information about the burst length and read latency (CAS latency) is input to the SDRAM via its address inputs. The MRS value generated by the `C82 is shown in Figure 56. It should be noted that CAS latency four reads are intended for use with CAS latency three SDRAMs, and thus the MRS cycle is performed as such. SDRAM Mode Register Bit 11 0 10 0 9 0 8 0 7 0 6 0 5 1 4 3 0 2 0 1 0 0 CT2 CT1|CT0 CT0-CT2 as input during the cache configuration cycle Figure 56. MRS Value Because the MRS register is programmed through the SDRAM address inputs, the alignment of the MRS data to the `C82 logical address bits is adjusted for the bus size as shown in Figure 57. The appearance of the MRS bits on the `C82 physical address bus (RCA[16:0]) is dependent on the address multiplexing as selected by the AS(2:0) field. C82 Logical Address Bits BS(1:0) 00 01 10 11 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 X X X X X X X 11 10 9 8 7 9 8 7 6 8 7 6 5 7 6 5 4 6 5 4 3 5 4 3 2 4 3 2 1 3 2 1 0 2 1 0 X 1 0 X X 0 X X X X 11 10 9 8 X 11 10 9 X 11 10 Figure 57. MRS Value Alignment 68 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 memory cycles TMS320C82 external memory cycles are generated by the TC's external memory controller. The controller's state machine generates a sequence of states which define the transition of the memory interface signals. The state sequence is dependent on the cycle timing selected for the bank being accessed. Memory cycles consist of row states and the column pipeline. end reset & host req reset rst en re s e t q h o s t re idle dr es et en d s ho q t re rhz host req always alw ays ad1 alw ay s DCAB # write read EXCEPT=00 mrs proceed xtnd mr rex EXCEPT=01 didle re ad w r it e turn on ! turn off rf4 ex xtn d ce wait pti rw xtnd rf3 always SRAM # DRAM & !xtnd cbr !xt nd AM DR h rfrs ad2 SD RA M DCAB dcab PT PD & e writ SR S turn off tu rn o ff rto turn (read # PDPT write) & (CT=0101 # CT=011x # CT=0010 # turn off ) rf2 always rf rs h ac1 rl1 SRAM w ri te wait SRA srs always DR AM drn rf1 wait rfrsh ac2 rea d srsi always SDRAM read SDRAM write rl2 wr ite w ri te wait rcl proceed exi spin Column Pipeline new page Figure 58. Memory Cycle State Diagram row states The row states make up the row time of each memory access. They occur when each new page access begins. The transition indicators determine the conditions that cause transitions to another state. pipelined 1 cyc/col write ! turn off s off !x tn d read off d M rea POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 proceed 69 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 row states (continued) Table 47. Row Time Memory States STATE ad1 ad2 rl1 rl2 ac1 ac2 mrs cbr rw rcl srs srsi rex rf1 rf2 rf3 rf4 exi didle dcab drn rto address and status. State is repeated if idle. The second address state, common to all memory accesses. /RL is asserted and /DDIN is driven according to the data transfer direction. READY is sampled. For DRAM and SRAM cycles. /RAS is asserted, AD[63:0] is placed in high impedance, and /DBEN is asserted if required. READY is sampled during cbr refresh cycles. For DRAM cycles. Transitions of /TRG/CAS, /W, and /DSF may occur. State ensures sufficient /RAS low time before /CAS/DQM[7:0] are activated. READY is sampled. For SDRAM cycles. ACTV command is generated on /RAS, /TRG/CAS, and /W. /DBEN is asserted if required, and AD[63:0] is placed in high impedance. For SDRAM cycles. No transitions occur, but state ensures sufficient time between ACTV command and subsequent READ or WRT commands. MRS command cycle. Occurs before rl1 for DRAM refreshes to ensure /CAS/DQM is asserted a sufficient amount of time prior to assertion of /RAS. For all DRAM cycles, one or more of these states may be inserted if the previous page access was to the same bank. No transitions occur. State ensures sufficient /RAS high time. Column pipeline load; common to all SRAM write cycles. One or more of these states may be inserted to ensure that the pipeline is properly loaded. READY is sampled. For SDRAM SRS cycles. /DBEN is asserted. For SDRAM SRS cycles. Idle cycle required to allow the pipeline to load. Row time exception state. Ensures sufficient /RAS low time before returning to state ad1. State may be repeated as required. First refresh cycle. Common to all refreshes. No signal transitions occur. Second refresh cycle. Common to all refreshes. No signal transitions occur. Third refresh cycle. Common to all refreshes. No signal transitions occur. For slow (/EXCEPT[1:0] = 01) DRAM refresh cycles. Fourth refresh cycle which allows an additional cycle of /RAS low time. One or more of these states may be inserted when exceptions are enabled for the addressed bank of memory. State may be repeated as required. State is not present if exceptions are not supported. Idle cycle for SDRAM write cycles ensures enough time between the WRT command and bank deactivation (DCAB). Deactivation cycle for SDRAM cycles. For 1 cycle/column pipelined DRAM writes, all /CAS/DQM[7:0] are activated to drain the DRAM pipeline. Turnoff cycle for all DRAM and SRAM reads; and DRAM and nonsynchronous SRAM PDT writes. All output signals except for /RL are driven inactive. Additional rto cycles will be performed according to the value of the TO[1:0] bank configuration field. rst rhz Reset state. During reset, all `C82 signals with the exceptions of /HACK, REQ, and CLKOUT are placed in the high-impedance state. High-impedance state. Occurs during host requests and repeats until bus is released by the host. All `C82 signals with the exceptions of /HACK, REQ, and CLKOUT are placed in the high-impedance state. DESCRIPTION The first address state, common to all memory accesses. All signals are driven inactive and outputs are 70 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 row states (continued) Table 48. State Transition Indicators INDICATOR any cycle /EXCEPT=xx exception retry wait spin new page turn off xtnd Continuation of current cycle. State change occurs for indicated /EXCEPT[1:0] value (as latched in ad2). Memory exception--retry, fault, or configuration cache flush request. /EXCEPT = 10. READY input sampled low in ad2, rl1 (CBR refresh only), rl2, rcl, and last column state; repeat current state. Internally generated wait state to allow TC pipeline to load/resolve contention. The next access requires a page change (new row access) Turn off, specified by default or by TO[1:0] field in bank configuration. Internally generated transition to insert additional cycles in order to support exceptions. DESCRIPTION external memory timing examples The following sections contain descriptions of the various C82 memory cycles and illustrate the signal transitions for those cycles. Memory cycles may be separated into three basic categories: DRAM cycles for use with EDO DRAM and VRAM; SRAM cycles for use with SRAM and peripherals; and SDRAM cycles for use with SDRAM and SGRAM. DRAM cycles The DRAM cycles are page-mode accesses consisting of a row access followed by one or more column accesses. Column accesses may be one, two, or three clock cycles in length with 2 and 3 cycle accesses allowing the insertion of wait states to accommodate slow devices. Idle cycles can occur after necessary column accesses have completed or between column accesses due to "bubbles" in the TC data flow pipeline. The pipeline diagrams in Figure 59 show the pipeline stages for each access type and when the /CAS/DQM signal corresponding to the column access is activated. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 71 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 DRAM cycles (continued) /CAS /DQM Col A Col B Col C Idle -/A A/B B/C C/c1 c2 c1 c3 c2 c1 c3 c2 ci c3 ci ci /CAS /DQM Col A Col B Col C Idle A c1 c1 c1 ci B C Pipelined 1 cycle/column EDO (CT=0000) reads, read transfers, split-read transfers Pipelined 1 cycle/column (CT = 0000) writes, LCRs, block writes /CAS /DQM Col A Col B A c1 c1 c1 ci B C /CAS /DQM Col A Col B Col C Idle A c1 B c2 c1 C c2 c1 c2 ci ci Col C Idle Nonpipelined 1 cycle/column EDO (CT = 0001) reads, read transfers, split-read transfers Nonpipelined 1 cycle/column (CT=0001) writes, LCRs, block writes /CAS /DQM Col A c1 /CAS /DQM Col A c1 A c2 c3 c1 B C A c2 c1 B C c2 c3 c1 c2 c3 ci ci ci idle Col C Col B Col B c2 c1 c2 ci ci Col C idle 2 cycle/column EDO (CT=0010) reads, read transfers, split-read transfers /CAS /DQM Col A c1 2 cycle/column (CT=0010) writes, LCRs, block writes /CAS /DQM Col A c1 A c2 - A c3 c4 c1 B c5 c2 - B C C A c2 - A c3 c1 B B C C c3 c4 c1 c5 c2 c3 c4 ci c5 ci ci ci ci Col C Col B c2 c3 c1 c2 c3 ci ci ci Col B Col C idle 3 cycle/column EDO (CT=0011) reads, read transfers, split-read transfers 3 cycle/column (CT=0011) writes, LCRs, and block writes Figure 59. DRAM Cycle Column Pipelines 72 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read cycles Read cycles transfer data or instructions from external memory to the `C82. The cycles can occur as a result of a packet transfer, cache request, or DEA request. During the cycle, /W is held high, /TRG/CAS is driven low after /RAS to enable memory output drivers, and /DBEN and /DDIN are low so that data transceivers may drive into the `C82. During column time, the TC places AD[63:0] into high impedance, allowing it to be driven by the memory, and latches input data during the appropriate column state. The TC always reads 64 bits and extracts and aligns the appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. During peripheral device packet transfers, /DBEN and /DDIN remain high. For DRAM reads, the minimum number of cycles between ad1 and the first column access is four whether exceptions are supported or not. ad1 State ad2 rl1 rl2 col col col col col col ad1 Note2 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c2 c1 c3 c2 c1 c3 c2 c1 c3 c2 c3 3/2 01 3/2 3/2 11 3/2 11 3/2. 11 3/2. 11 3/2. 3/2. 00 3/2. Col A Col B Col C Col D -/A A/B. A B/C. B C/D. C D/ D Low unless Peripheral Data Transfer Notes: 1. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. 2. Turnoff cycles will be inserted between rto and ad1 as specified by the bank configuration. Figure 60. 1 cycle/column Pipelined EDO DRAM Read Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 73 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read cycles (continued) ad1 State ad2 rl1 rl2 col col col col ad1 Note 2 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c2 c1 c2 c1 c2 3/2 01 3/2 3/2 11 3/2 11 3/2 11 3/2 00 3/2 Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. 2. Turnoff cycles will be inserted between rto and ad1 as specified by the bank configuration. Figure 61. 1 cycle/column EDO DRAM Read Cycle 74 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read cycles (continued) ad1 State ad2 rl1 rl2 col col col col col col col rto Note 2 ad1 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC. Row Note 1 c1 c2 c3 c1 c2 c3 c1 c2 c3 3/2. 01 3/2. 3/2. 3/2. 11 3/2. 3/2. 11 3/2. 3/2. 11 3/2. 3/2. 00 3/2. Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. 2. Turnoff cycles will be inserted between rto and ad1 as specified by the bank configuration. Figure 62. 2 cycles/column EDO DRAM Read Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 75 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read cycles (continued) ad1 State ad2 rl1 rl2 col col col col col col col col col col col ad1 Note 2 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC. Row Note 1 c1 c2 c3 c4 c1 c5 c2 c3 c4 c1 c5 c2 c3 c4 c5 3/2. 01 3/2. 3/2. 3/2. 11 3/2. 3/2. 3/2. 11 3/2. 3/2. 3/2. 11 3/2. 3/2. 3/2. 00 3/2. Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 4 cycles. 2. Turnoff cycles will be inserted between rto and ad1 as specified by the bank configuration. Figure 63. 3 cycle/column EDO DRAM Read Cycle 76 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 write cycles Write cycles transfer data from the `C82 to external memory. These cycles can occur as a result of a packet transfer, a DEA request, or an MP data cache write-back. During the cycle /TRG/CAS is held high, /W is driven low after the fall of /RAS to enable early write cycles, and /DDIN is high so that data transceivers drive toward memory. The TC drives data out on AD[63:0] and indicates valid bytes by activating the appropriate /CAS/DQM strobes. During peripheral device packet transfers, /DBEN remains high and AD[63:0] is placed in high impedance so that the peripheral device may drive data into the memory. Additionally, the number of turnoff cycles identified by the TO(1:0) field for the addressed bank of memory will be applied during PDT write cycles. Exceptions are not supported in the following diagrams. Support for exceptions increases the minimum number of cycles between ad1 and the first column state from 4 to 6. ad1 State ad2 rl1 rl2 col col col drn ad1 Note 2 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c1 c1 3/2 01 3/2 3/2 11 3/2 11 3/2 11 3/2 00 3/2 Col A Col B Col C A A B B C C drn Low unless Peripheral Data Transfer Notes: 1. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. 2. During peripheral data transfer, turnoff cycles will be inserted prior to ad1 as specified by the bank configuration. Figure 64. 1 cycle/column Pipelined DRAM Write Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 77 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 write cycles (continued) ad1 State ad2 rl1 rl2 col col col ad1 Note 2 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c1 c1 3/2 01 3/2 3/2 11 3/2 11 3/2 11 3/2 Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. 2. During peripheral data transfer, turnoff cycles will be inserted prior to ad1 as specified by the bank configuration. Figure 65. 1 cycle/column DRAM Write Cycle 78 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 write cycles (continued) ad1 State ad2 rl1 rl2 col col col col col col ad1 Note 2 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c2 c1 c2 c1 c2 3/2 01 3/2 3/2 3/2 11 3/2. 3/2. 11 3/2. 3/2. 11 3/2. Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. 2. During peripheral data transfer, turnoff cycles will be inserted prior to ad1 as specified by the bank configuration. Figure 66. 2 cycle/column DRAM Write Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 79 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 write cycles (continued) ad1 State ad2 rl1 rl2 col col col col col col col col col ad1 Note 2 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c2 c3 c1 c2 c3 c1 c2 c3 3/2. 01 3/2. 3/2. 3/2. 11 3/2. 3/2. 3/2. 11 3/2. 3/2. 3/2. 11 3/2. 3/2. Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 4 cycles. 2. During peripheral data transfer, turnoff cycles will be inserted prior to ad1 as specified by the bank configuration. Figure 67. 3 cycle/column DRAM Write Cycle 80 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 load color register cycles Load color register (LCR) cycles are used to load a VRAM's color register prior to performing a block write. LCR cycles are supported only on 64-bit data busses. Because an LCR writes into a VRAM, it closely resembles a normal write cycle. The difference is that the DSF output is high at both the fall of /RAS and the fall of /CAS/DQM. Also, because the VRAM color register is a single location, only one column access occurs. The row address output by the TC is used for bank decode only. Normally all VRAM banks should be selected during an LCR cycle because another LCR will not occur when a block write memory page change occurs. The column address output during an LCR is likewise irrelevant as the VRAM color register is the only location written. All /CAS/DQM strobes are active during an LCR cycle. If exception support for a given bank is enabled, the /EXCEPT[1:0] inputs are sampled during LCR column states and must be at valid levels. A retry code (/EXCEPT[1:0] = 10) at column time has no effect, however, because only one column access is performed. If the BW (block write) field of the configuration cache entry for the given bank indicate that the addressed memory supports only simulated block writes, the LCR cycle will be changed into a normal write cycle at the start of the simulated block write. Exceptions are not supported in the following diagrams. Support for exceptions increases the minimum number of cycles between ad1 and the first column state from 4 to 6. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 81 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 load color register cycles (continued) ad1 State Note 1 ad2 rl1 rl2 col ad1 ad Col c1 CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Color Row Address Note 2 3/2 01 3/2 3/2 11 3/2 Notes: 1. These timings apply to piplined and nonpiplined 1 cycle/column DRAM. 2. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. Figure 68. 1 cycle/column Load Color Register (LCR) Cycle 82 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 load color register cycles (continued) ad1 State Col c1 c2 ad2 rl1 rl2 col col ad1 ad CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Color Row Address Note 1 3/2 01 3/2 3/2 3/2 11 3/2 Note 1: Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. Figure 69. 2 cycle/column Load Color Register (LCR) Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 83 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 load color register cycles (continued) ad1 State Col c1 c2 c3 ad2 rl1 rl2 col col col ad1 ad CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Color Row Address Note 1 3/2 01 3/2 3/2 3/2 11 3/2 3/2 Note 1: Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 4 cycles. Figure 70. 3 cycle/column Load Color Register (LCR) Cycle 84 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 block-write cycles Block-write cycles cause the data stored in the VRAM color registers to be written to the memory locations enabled by the appropriate data bits on the AD[63:0] bus. This allows up to a total of 64 bytes (depending on the block-write type) to be written in a single column access. The TMS320C82 supports 4x and 8x blockwrites. Selection of block-write type is controlled by the BW field input during the appropriate bank configuration cycle. A block-write cycle is indicated by a row-time status code of 1001 output on AD[35:32]. The block-write cycle is identical to a standard write cycle with the following exceptions: * * * * DSF is high at the fall of /CAS/DQM, enabling the block-write function of the VRAMs. Only 64-bit data bus widths are supported; consequently, all /CAS/DQM signals will be active (low). Block writes always begin with a new row access. Upon completion of a block-write, the memory interface returns to the ad1 state to await the next access. The address output on AD[63:0] during column accesses represent the column locations to be written using the color register value. Depending on the type of block-write being performed, all of the data bits may not be used by the VRAM. The two or three LSBs of address output on RCA[16:0] are ignored by the VRAMs because the column locations are specified by the value on the data bus. * Exceptions are not supported in Figure 71, Figure 72, and Figure 73. Support for exceptions increases the minimum number of cycles between ad1 and the first column state from 4 to 6. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 85 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 block-write cycles (continued) ad1 State ad2 rl1 rl2 col col col ad1 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c1 c1 3/2 01 3/2 3/2 11 3/2 11 3/2 11 3/2 Col A Col B Col C A B C Note 1: Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. Figure 71. 1 cycle/column Block-Write Cycle 86 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 block-write cycles (continued) ad1 State ad2 rl1 rl2 col col col col col col ad1 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC. Row Note 1 c1 c2 c1 c2 c1 c2 3/2. 01 3/2. 3/2. 3/2. 11 3/2. 3/2. 11 3/2. 3/2. 11 3/2. Col A Col B Col C A B C Note 1: Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. Figure 72. 2 cycle/column Block-Write Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 87 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 block-write cycles (continued) ad1 State ad2 rl1 rl2 col col col col col col col col col ad1 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c2 c3 c1 c2 c3 c1 c2 c3 3/2. 01 3/2. 3/2. 3/2. 11 3/2. 3/2. 3/2. 11 3/2. 3/2. 3/2. 11 3/2. 3/2. Col A Col B Col C A B C Note 1: Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 4 cycles. Figure 73. 3 cycle/column Block-Write Cycle 88 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read and split-read transfers Read and split-read transfers resemble a standard read cycle. These cycles are performed as the result of a packet transfer submission to the TC which specifies the SRT mode. The `C82 supports both read and split-read transfers. These cycles are designed to transfer a row of data from the VRAM memory array into the VRAM SAM register. Since no data is actually transferred over the system bus during an SRT cycle, the AD[63:0] bus is placed in high impedance. The /TRG/CAS output is driven low prior to the fall of /RAS to indicate a transfer cycle. Only a single column access is performed, therefore, while /EXCEPT[1:0] are required to be at valid levels, retries will have no effect if asserted at column time. The value output on RCA[16:0] at column time represents the SAM tap point. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 89 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read and split-read transfers (continued) ad1 State ad2 rl1 rl2 col ad1 ad Col c1 CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 3/2 01 3/2 3/2 11 3/2 Tap Addr. 0 for Full xfer; 1 for Split xfer Notes: 1. Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. 2. These timings apply to piplined and nonpiplined 1 cycle/column DRAM. Figure 74. 1 cycle/column Memory-to-Register Transfer Cycle 90 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read and split-read transfers (continued) ad1 State ad2 rl1 rl2 col col ad1 ad Col c1 c2 CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 3/2 01 3/2 3/2 3/2 11 3/2 Tap Address 0 for Full xfer; 1 for Split xfer Note 1: Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 3 cycles. Figure 75. 2 cycle/column Memory-to-Register Transfer Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 91 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read and split-read transfers (continued) ad1 State ad2 rl1 rl2 col col col ad1 ad Col c1 c2 c3 CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 3/2 01 3/2 3/2 3/2 11 3/2. 3/2 Tap Address 0 for Full Transfer; 1 for Split Transfer Note 1: Additional cycles will be inserted between ad2 and rl1 as required to ensure RAS- high of at least 4 cycles. Figure 76. 3 cycle/column Memory-to-Register Transfer Cycle 92 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 DRAM refresh cycle The DRAM refresh cycle is performed when the TC (/EXCEPT[1:0] = 0X) at the start of a refresh cycle. The TC cycles, wherein the refresh address is generated internal to the pseudo-address (used for refresh bank decode) on RCA[16:1]. for each refresh that is performed. ad1 State CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Refresh pseudo-address Note 1 receives a DRAM cycle timing input performs /CAS-before-/RAS (CBR) refresh memory device. The `C82 outputs a 16-bit The pseudo-address is decremented once ad2 cbr rl1 rf1 rf2 rf3 ad1 ad 3/2 0/1 01 Note 1: RAS- cannot be high for less than the 3 cycles required when /EXCEPT[1:0] = 00. An additional cycle will be inserted between cbr and rl1 when /EXCEPT[1:0] = 01. An additional cycle will be inserted between rf3 and ad1 when /EXCEPT[1:0] = 01. Figure 77. DRAM Refresh POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 93 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SRAM cycles Similar to DRAM cycles, the SRAM cycles are page-mode accesses consisting of a row access followed by one or more column accesses. Column accesses may be one, two, or three clock cycles in length with 2 and 3 cycle accesses allowing the insertion of wait states to accommodate slow devices. Idle cycles can occur after necessary column accesses have completed or between column accesses due to "bubbles" in the TC data flow pipeline. The pipeline diagrams in Figure 78 show the pipeline stages for each access type and when the /CAS/DQM signal corresponding to the column access is activated. 94 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SRAM cycles (continued) /CAS/DQM Col A Col B Col C Idle A c1 B c2 c1 C c3 c2 c1 c3 c2 ci c3 ci ci /CAS/DQM Col A Col B Col C Idle A c1 c1 c1 ci B C Synchronous SRAM (CT=0100) reads Synchronous SRAM (CT = 0100) writes /CAS/DQM Col A Col B Col C Idle A c1 B C /CAS/DQM Col A Col B A c1 B C c1 c1 ci c1 c1 ci Col C Idle Asynchronous 1 cycle/column SRAM (CT = 0101) reads /CAS/DQM Col A c1 A c2 Col B c1 c2 Col C Idle 2 cycle/column SRAM (CT=0110) reads c1 c2 ci ci B C Asynchronous 1 cycle/column (CT=0101) writes /CAS/DQM Col A A c1 c2 Col B c1 c2 Col C Idle 2 cycle/column (CT=0110) writes c1 c2 ci ci B C /CAS/DQM Col A c1 A c2 - A c3 c1 B B C C /CAS/DQM Col A c1 A c2 - A c3 c1 B B C C c2 c3 c1 c2 c3 ci ci ci Col C Col B c2 c3 c1 c2 c3 ci ci ci Col B Col C Idle 3 cycle/column SRAM (CT=0111) reads 3 cycle/column (CT=0111) writes Figure 78. SRAM Cycle Column Pipelines POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 95 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read cycles SRAM read cycles transfer data or instructions from external memory to the `C82. SRAM read cycles are designed to interface with SRAM and other peripherals with SRAM-like I/O interfaces. During the cycle, /W is held high, /TRG/CAS is driven low after /RAS to enable memory output drivers, and /DBEN and /DDIN are low so that data transceivers may drive into the `C82. During column time, the TC places AD[63:0] into high impedance, allowing it to be driven by the memory, and latches input data during the appropriate column state. The TC always reads 64 bits and extracts and aligns the appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. During peripheral device packet transfers, /DBEN and /DDIN remain high. Exceptions are not supported in Figure 79, Figure 80, Figure 81, and Figure 82. Support for exceptions increases the minimum number of cycles between ad1 and the first column state from 3 to 4. 96 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read cycles (continued) ad1 State ad2 rl1 col col col col idle idle ad1 Note 2 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c2 c1 c3 c2 c1 c3 c2 c1 c3 c2 c3 3/2. 01 3/2. 11 3/2. 11 3/2. 11 3/2. 11 3/2. 3/2. 00 3/2. Col A Col B Col C Col D A B C A D B C D Low unless Peripheral Data Transfer Notes: 1. No RAS- high time requirements apply to these cycles. 2. Turnoff cycles will be inserted between rto and ad1 as specified by the bank configuration. Figure 79. Synchronous SRAM Read Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 97 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read cycles (continued) ad1 State ad2 rl1 col col col rto Note 2 ad1 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c1 c1 3/2 01 3/2 11 3/2 11 3/2 11 3/2 00 3/2 Col A Col B Col C A A B B C C Low Unless Perip. Data Transfer Notes: 1. No RAS- high time requirements apply to these cycles. 2. Additional turnoff cycles will be inserted between rto and ad1 as specified by the bank configuration. Figure 80. 1 cycle/column SRAM Read Cycle 98 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read cycles (continued) ad1 State ad2 rl1 col col col col col col rto Note 2 ad1 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c2 c1 c2 c1 c2 3/2 01 3/2 3/2 11 3/2 3/2. 11 3/2. 3/2. 11 3/2. 00 3/2. Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. No RAS- high time requirements apply to these cycles. 2. Additional turnoff cycles will be inserted between rto and ad1 as specified by the bank configuration. Figure 81. 2 cycle/column SRAM Read Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 99 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 read cycles (continued) ad1 State ad2 rl1 col col col col col col col col col rto Note 2 ad1 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c2 c3 c1 c2 c3 c1 c2 c3 3/2. 01 3/2. 3/2. 11 3/2. 3/2. 3/2. 11 3/2. 3/2. 3/2. 11 3/2. 3/2. 00 3/2. Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. No RAS- high time requirements apply to these cycles. 2. Additional turnoff cycles will be inserted between rto and ad1 as specified by the bank configuration. Figure 82. 3 cycle/column SRAM Read Cycle 100 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 write cycles Write cycles transfer data from the `C82 to external memory. These cycles can occur as a result of a packet transfer, a DEA request, or an MP data cache write-back. During the cycle /TRG/CAS is held high, /W is driven low after the fall of /RAS to enable early write cycles, and /DDIN is high so that data transceivers drive toward memory. The TC drives data out on AD[63:0] and indicates valid bytes by activating the appropriate /CAS/DQM strobes. The /CAS/DQM signals may be used as chip enables (/CE) for SRAMs and peripherals (i.e., /CE-controlled writes). During peripheral device packet transfers, /DBEN remains high and AD[63:0] is placed in high impedance so that the peripheral device may drive data into the memory. Additionally, the number of turnoff cycles identified by the TO(1:0) field for the addressed bank of memory will be applied during PDT write cycles. Exceptions are not supported in Figure 83, Figure 84, Figure 85, and Figure 86. Support for exceptions increases the minimum number of cycles between ad1 and the first column state from 4 to 6. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 101 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 write cycles (continued) ad1 State ad2 rl1 rcl col col col Note 2 ad1 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c1 c1 3/2 01 3/2 00 3/2 11 3/2 11 3/2 11 3/2 Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. No RAS- high time requirements are applicable to these cycles. 2. During peripheral data transfer, turnoff cycles will be inserted prior to ad1 as specified by the bank configuration. Figure 83. Synchronous SRAM Write Cycle 102 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 write cycles (continued) ad1 State Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC A A B B C C Row Note 1 ad2 rl1 rcl col col col Note 2 ad1 ad c1 c1 c1 3/2 01 3/2 00 3/2 11 3/2 11 3/2 11 3/2 Col A Col B Col C Low unless Peripheral Data Transfer Notes: 1. No RAS- high time requirements are applied to these cycles. 2. During peripheral data transfer, turnoff cycles will be inserted prior to ad1 as specified by the bank configuration. Figure 84. 1 cycle/column SRAM Write Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 103 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 write cycles (continued) ad1 State ad2 rl1 rcl col col col col col col ad1 Note 2 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c2 c1 c2 c1 c2 3/2 01 3/2 00 3/2 3/2 11 3/2. 3/2. 11 3/2. 3/2. 11 3/2. Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. No RAS- high time requirements apply to these cycles. 2. During peripheral data transfer, turnoff cycles will be inserted prior to ad1 as specified by the bank configuration. Figure 85. 2 cycle/column SRAM Write Cycle 104 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 write cycles (continued) ad1 State ad2 rl1 rcl col col col col col col col col col Note 2 ad1 ad Col A Col B Col C CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINAddress / ATC Row Note 1 c1 c2 c3 c1 c2 c3 c1 c2 c3 3/2. 01 3/2. 00 3/2. 3/2. 11 3/2. 3/2. 3/2. 11 3/2. 3/2. 3/2. 11 3/2. 3/2. Col A Col B Col C A A B B C C Low unless Peripheral Data Transfer Notes: 1. No RAS- high time requirements are applied to these cycles. 2. During peripheral data transfer, turnoff cycles will be inserted prior to ad1 as specified by the bank configuration. Figure 86. 3 cycle/column SRAM Write Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 105 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM cycles The SDRAM cycles support the use of SDRAM and SGRAM devices for single-cycle memory accesses. While SDRAM cycles use the same state sequences as DRAM cycles, the memory control signal transitions are modified to perform SDRAM command cycles. The supported SDRAM commands are: * * * * * * * * DCAB Deactivate (precharge) all banks ACTV Activate the selected bank and select the row READ Input starting column address and start read operation WRT Input starting column address and start write operation MRS Set SDRAM mode register REFR Auto-refresh cycle with internal address SRS Set special register (color register) BLW Block write SDRAM cycles begin with an activate (ACTV) command followed by the requested column accesses. When a memory page change occurs, the selected bank is deactivated with a DCAB command. The TMS320C82 supports CAS latencies of 2, 3, or 4 cycles and burst lengths of 1 or 2. These are selected by the CT field read in during a bank-configuration cycle for the given bank. It should be noted that CAS latency 4 accesses are intended for use with CAS latency 3 SDRAM-like devices. The column pipelines for SDRAM accesses are shown in Figure 87. Idle cycles can occur after necessary column accesses have completed or between column accesses due to "bubbles" in the TC data flow pipeline. The pipeline diagrams show the pipeline stages for each access type and when the /CAS/DQM signal corresponding to the column access is activated. 106 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM cycles (continued) /CAS /DQM Col A Col B Col C Idle A c1 B c2 c1 C c3 c2 c1 c3 c2 ci c3 ci ci /CAS /DQM Col A Col B Col C Idle c1 A c2 c1 B c3 c2 c1 C c4 c3 c2 ci c4 c3 ci c4 ci ci Burst length 1, 2 cycle latency (CT = 1000) reads, read transfers, split-read transfers Burst length 1, 3 cycle latency (CT = 1001) reads, read transfers, split-read transfers /CAS /DQM Col A Col B Col C Col D Idle c1 A c2 c1 B c3 c2 c1 C c4 c3 c2 c1 D c5 c4 c3 c2 ci c5 c4 c3 ci c5 c4 ci c5 ci ci /CAS /DQM Col A Col B Col C Idle A c1 B C c1 c1 ci Burst length 1, 4 cycle latency (CT = 1010) reads, read transfers, split-read transfers Burst length 1 writes, block writes, SRSs /CAS /DQM Col A,B A c1 (B) c2 - C c3 c1 (D) E (F) /CAS /DQM Col A,B A c1 (B) c2 - C c3 c1 (D) c4 c2 - E (F) c2 c3 c1 c2 c3 ci ci ci Idle Col E,F Col C,D c3 c1 c4 c2 c3 ci c4 ci ci ci Col C,D Col E,F Idle Burst length 2, 2 cycle latency (CT = 1100) reads, read transfers, split-read transfers /CAS /DQM Col A,B A c1 (B) c2 Col C,D C c3 c1 (D) c4 c2 Col E,F E c5 c3 c1 c4 c2 Idle Burst length 2, 4 cycle latency (CT = 1110) reads, read transfers, split-read transfers (F) Burst length 2, 3 cycle latency (CT = 1101) reads, read transfers, split-read transfers /CAS /DQM Col A,B A c1 (B) c2 c5 c3 ci c4 ci c5 ci ci ci Idle Burst length 2 writes Col E,F Col C,D C c1 c2 c1 c2 ci ci (D) E (F) /CAS /DQM Col A A c1 - B C Col B c1 - Col C c1 - Idle Burst length 2 block writes ci Figure 87. SDRAM Column Pipelines POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 107 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 special SDRAM cycles In order to properly initialize SDRAM, the TMS320C82 provides support for two special SDRAM cycles. During the power-up refresh sequence, the first refresh cycle that receives an SDRAM bank code (/EXCEPT[1:0] = 11) will be abandoned and a power-up deactivate (DCAB) cycle is performed. Only one DCAB operation is performed, so it is expected that all SDRAM banks will be decoded for this operation. The `C82 also performs an MRS cycle immediately following a bank-configuration cycle if that cycle returned a SDRAM CT code. No further MRS cycles for that bank are performed as long as the bank configuration remains cached. ad1 State CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand DCAB ad2 dcab ad1 ad 3/2 01 00 Note 1 Low High High Address / ATC High Note 1: The row address is a don't care. Figure 88. SDRAM Power-up Deactivate 108 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 special SDRAM cycles (continued) ad1 State CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand MRS ad2 mrs ad1 ad 3/2 01 MRS Low High Address / ATC High Figure 89. SDRAM Mode Register Set POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 109 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM read cycles Read cycles begin with an activate command to activate the bank and select the row. The TC outputs the column address and activates the /TRG/CAS strobe for each read command. For burst length 1 accesses, a read command can occur on each cycle. For burst length 2 accesses, a read command may occur every two cycles. During column time, the TC places AD[63:0] into high impedance, allowing it to be driven by the memory and latches input data during the appropriate column state. The TC always reads 64 bits and extracts and aligns the appropriate bytes. Invalid bytes for bus sizes of less than 64 bits are discarded. The /CAS/DQM strobes are activated two cycles before input data is latched (three cycles before in the case of CAS latency 4 accesses). If the second column in a burst is not required, then /CAS/DQM is not activated. During peripheral device packet transfers, /DBEN remains high. For SDRAM reads, the minimum number of cycles between ad1 and the first column access is four whether exceptions are supported or not. 110 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM read cycles (continued) ad1 State ad2 ac1 ac2 col col col col dcab didle Note 2 ad1 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand ACTV Nt 1 A ii f3 l i i db t DCAB c1 c2 c1 c3 c2 c1 c3 c2 c1 c3 c2 c3 3/2. 01 3/2. 3/2. 11 3/2. 11 3/2. 11 3/2. 11 3/2. 00 3/2. 00 3/2. Row Note 1 Col A Col B Col C Col D A B C D A Address / ATC. B C A D B C D Low unless Peripheral Data Transfer READ d READ d ACTV READ d READ DCAB Notes: 1. A minimum of 3 cycles is required between a DCAB command and an ACTV command. 2. Turnoff cycles will be inserted between didle and ad1 as specified by the bank configuration. Figure 90. SDRAM Burst Length 1, 2 Cycle Latency Read POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 111 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM read cycles (continued) ad1 State ad2 ac1 ac2 col col col col idle dcab didle Note 2 ad1 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand ACTV Nt 1 A ii f3 l i i db t c1 c2 c1 c3 c2 c1 c4 c3 c2 c1 c4 c3 c2 c4 c3 c4 3/2. 01 3/2. 3/2. 11 3/2. 11 3/2. 11 3/2. 11 3/2. 00 3/2. 00 3/2. 00 3/2. Row Note 1 Col A Col B Col C Col D A B C D A Address / ATC B C A D B C D Low unless Peripheral Data Transfer READ DCAB READ d d READ ACTV READ d DCAB Notes: 1. A minimum of 3 cycles is required between a DCAB command and an ACTV command. 2. Turnoff cycles will be inserted between didle and ad1 as specified by the bank configuration. Figure 91. SDRAM Burst Length 1, 3 Cycle Latency Read 112 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM read cycles (continued) ad1 State ad2 ac1 ac2 col col col col idle idle dcab didle Note 2 ad1 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand ACTV c1 c2 c1 c3 c2 c1 c4 c3 c2 c1 c5 c4 c3 c2 c5 c4 c3 c5 c4 c5 3/2. 01 3/2. 3/2. 11 3/2. 11 3/2. 11 3/2. 11 3/2. 3/2. 00 3/2. 00 3/2. 00 3/2. Row Note 1 Col A Col B Col C Col D A B C D A Address / ATC B C D A B C D Low unless Peripheral Data Transfer READ READ READ READ DCAB Notes: 1. A minimum of 3 cycles is required between a DCAB command and an ACTV command. 2. Turnoff cycles will be inserted between didle and ad1 as specified by the bank configuration. Figure 92. SDRAM Burst Length 1, 4 Cycle Latency Read POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 113 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM read cycles (continued) ad1 State ad2 ac1 ac2 col col col col dcab didle Note 2 ad1 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand ACTV Nt 1 A ii f3 l i i db t DCAB c1 c2 c1 c3 c2 c1 c3 c2 c1 c3 c2 c3 3/2. 01 3/2. 3/2. 11 3/2. 11 3/2. 11 3/2. 11 3/2. 00 3/2. 00 3/2. Row Note 1 Col A Col B Col C Col D A,B C,D A Address / ATC. B C A D B C D Low unless Peripheral Data Transfer READ d d ACTV READ d DCAB Notes: 1. A minimum of 3 cycles is required between a DCAB command and an ACTV command. 2. Turnoff cycles will be inserted between didle and ad1 as specified by the bank configuration. Figure 93. SDRAM Burst Length 2, 2 Cycle Latency Read 114 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM read cycles (continued) ad1 State ad2 ac1 ac2 col col col col idle dcab didle Note 2 ad1 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand ACTV Nt 1 A ii f3 l i i db t c1 c2 c1 c3 c2 c1 c3 c2 c1 c3 c2 c3 3/2. 01 3/2. 3/2. 11 3/2. 11 3/2. 11 3/2. 11 3/2. 00 3/2. 00 3/2. 00 3/2. Row Note 1 Col A Col B Col C Col D A,B C,D A Address / ATC B C A D B C D Low unless Peripheral Data Transfer READ DCAB d d ACTV READ d DCAB Notes: 1. A minimum of 3 cycles is required between a DCAB command and an ACTV command. 2. Turnoff cycles will be inserted between didle and ad1 as specified by the bank configuration. Figure 94. SDRAM Burst Length 2, 3 Cycle Latency Read POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 115 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM read cycles (continued) ad1 State ad2 ac1 ac2 col col col col idle idle dcab didle Note 2 ad1 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand ACTV c1 c2 c1 c3 c2 c1 c4 c3 c2 c1 c5 c4 c3 c2 c5 c4 c3 c5 c4 c5 3/2. 01 3/2. 3/2. 11 3/2. 11 3/2. 11 3/2. 11 3/2. 3/2. 00 3/2. 00 3/2. 00 3/2. Row Note 1 Col A Col B Col C Col D A,B C,D A Address / ATC B C D A B C D Low unless Peripheral Data Transfer READ READ DCAB Notes: 1. A minimum of 3 cycles is required between a DCAB command and an ACTV command. 2. Turnoff cycles will be inserted between didle and ad1 as specified by the bank configuration. Figure 95. SDRAM Burst Length 2, 4 Cycle Latency Read 116 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM write cycles Write cycles begin with an activate command to activate the bank and select the row. The TC outputs the column address and activates the /TRG/CAS and /W strobes for each write command. For burst length 1 accesses, a write command can occur on each cycle. For burst length 2 accesses, a write command may occur every two cycles. The TC drives data out on AD[63:0] during each cycle of an active write command and indicates valid bytes by driving the appropriate /CAS/DQM strobes low. During peripheral device packet transfers, /DBEN remains high and AD[63:0] is placed in high impedance so that the peripheral may drive data into the memories. Additionally, the number of turn off cycles identified by the TO(1:0) field for the addressed bank of memory will be applied during PDT write cycles. Exceptions are not supported in Figure 96 and Figure 97. Support for exceptions increases the minimum number of cycles between ad1 and the first column state from 4 to 6. ad1 State ad2 ac1 ac2 col col col col didle dcab Note 2 ad1 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand ACTV c1 c1 c1 c1 3/2. 01 3/2. 3/2. 11 3/2. 11 3/2. 11 3/2. 11 3/2. 00 3/2. 00 3/2. Row Note 1 Col A Col B Col C Col D A B C D A Address / ATC A B B C C D D Low unless Peripheral Data Transfer WRT WRT WRT WRT DCAB Notes: 1. A minimum of 3 cycles is required between a DCAB command and an ACTV command. 2. During peripheral data transfers, turnoff cycles will be inserted prior to ad1 as specified by the bank configuration. Figure 96. SDRAM Burst Length 1 Write POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 117 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM write cycles (continued) ad1 State ad2 ac1 ac2 col col col col didle dcab Note 2 ad1 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand ACTV c1 c1 c1 c1 3/2. 01 3/2. 3/2. 11 3/2. 11 3/2. 11 3/2. 11 3/2. 00 3/2. 00 3/2. Row Note 1 Col A Col B Col C Col D A,B C,D A Address / ATC A B B C C D D Low unless Peripheral Data Transfer WRT WRT DCAB Notes: 1. A minimum of 3 cycles is required between a DCAB command and an ACTV command. 2. During peripheral data transfers, turnoff cycles will be inserted prior to ad1 as specified by the bank configuration. Figure 97. SDRAM Burst Length 2 Write 118 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 special register set cycle Special register set (SRS) cycles are used to program control registers within an SGRAM. The `C82 only supports programming of the color register for use with block writes. The cycle is similar to a single-burstlength-1 write cycle but DSF is driven high. The values output on the `C82's RCA[16:0] bus causes the color register to be selected as shown in Figure 98. The color register value is output on the AD[63:0] bus. Exception are not supported in Figure 99; support for exceptions increases the number of cycles between ad1 and the column access from 4 to 6. SDRAM Addr Pin SDRAM Function 'C82 Output Value BS A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 LC LM LS 0 1 0 0 0 Stop Reg 0 0 0 Figure 98. Special Register Set Value ad1 State Col c1 ad2 srs srsi col ad1 ad CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand SRS 3/2 01 3/2 00 3/2 11 3/2 SRS Address / ATC Color Figure 99. SDRAM SRS Cycle POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 119 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM block-write cycles Block-write cycles allow SGRAMs to write a stored color value to multiple column locations in a single access. Block-write cycles are similar to write cycles except that DSF is driven high to indicate a block-write command. Because burst is not supported for block write, burst length 2 accesses generate a single block write every other clock cycle. Exceptions are not supported in Figure 100 and Figure 101. Support for exceptions increases the minimum number of cycles between ad1 and the first column state from 4 to 6. ad1 State ad2 ac1 ac2 col col col col didle dcab ad1 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand ACTV c1 c1 c1 c1 3/2. 01 3/2. 3/2. 11 3/2. 11 3/2. 11 3/2. 11 3/2. 00 3/2. 00 3/2. Row Note 1 Col A Col B Col C Col D A B C D Address / ATC. A B C D BLKW BLKW BLKW BLKW DCAB Note 1: A minimum of 3 cycles is required between a DCAB command and an ACTV command. Figure 100. SDRAM Burst Length 1 Block Write 120 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM block-write cycles (continued) ad1 State ad2 ac1 ac2 col col col didle didle dcab ad1 ad Col A Col B Col C Col D CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand ACTV c1 c1 c1 c1 3/2. 01 3/2. 3/2. 11 3/2. 00 3/2. 11 3/2. 3/2. 00 3/2. 00 3/2. Row Note 1 Col A Col B A- B- Address / ATC. A B BLKW BLKW DCAB Note 1: A minimum of 3 cycles is required between a DCAB command and an ACTV command. Figure 101. SDRAM Burst Length 2 Block Write POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 121 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 SDRAM refresh cycle The SDRAM refresh cycle is performed when the TC receives an SDRAM cycle timing input (/EXCEPT[1:0] = 11) at the start of a refresh cycle. The /RAS and /TRG/CAS outputs are driven low for 1 cycle to strobe a refresh command (REFR) into the SDRAM. The refresh address is generated internal to the SDRAM. The `C82 outputs a 16-bit pseudo-address (used for refresh bank decode) on RCA[16:1]. The pseudo-address is decremented once for each refresh that is performed. ad1 State CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDINCommand REFR ad2 ac1 ac2 rf1 rf2 rf3 ad1 ad 3/2 11 01 (Row) Refresh pseudo-address Note 1&2 Address / ATC Notes: 1. A minimum of three cycles is required between the CLKOUT edges of a DCAB command and a subsequent ACTV command. 2. A minimum of seven cycles is required between the CLKOUT edges of a REFR command and a subsequent REFR or ACTV command. Figure 102. SDRAM Refresh 122 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 bank configuration cycle The `C82 bank configuration cycle is required each time a new bank of memory is to be accessed whose configuration is not in the memory-configuration cache. The memory cache contains six entries. Entry replacement is based on a multiple-level least-recently-used algorithm. The least-recently-used lowestpriority entry will be flushed from the cache if all six entries are used. Bank configuration cycles may occur as the result of a cache miss, packet transfer, DEA, or may be requested by the system by inputting an exception code of 00 on the /EXCEPT[1:0] inputs during the ad2 state of a memory access. This exception code forces the bank configuration to be flushed and a new configuration for that bank to be read in. This is particularly useful for systems that use "shadow mapping" to decode two different memory types to the same address. A configuration cache fill resembles a normal read cycle, with a few exceptions. Most notable are: * * Accesses are byte width only. Only four accesses are performed. In four consecutive reads, the bank configuration fields described in Figure 55 are read in over either AD[63:56] (big-endian mode) or AD[7:0] (little-endian mode). This sequence is atomic, and no pipeline bubbles will occur. The RCA bus outputs the sequence 00, 01, 02, and 03 for the four accesses. The configuration cache cycle is indicated by a row time status code of 1110 output on AD[35:32]. It is anticipated that external logic will latch that status code (using /RL) and several upper address bits (AD[31:xx]) and decode RCA[1:0] to respond with the appropriate bank configuration information. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 123 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 bank configuration cycle (continued) ad1 State CLKOUT READY EXCEPT-[1:0] STATUS[1:0] RLRCA[16:0] RASDSF TRG-/CASWCAS-/DQM[7:0] AD[63:0] DBENDDIN3/2. ad2 rl1 col col col col col col col col rto Note 2 ad1 ad 3 01 11 00 Row address Note 1 0 1 2 3 A Address / ATC. A B B C C D D Notes: 1. No RAS- high time requirements are applied to these cycles. 2. Additional turnoff cycles can be inserted by adding waitstates during the rto (turnoff) cycle. This capability is unique to this cycle. Figure 103. Bank Configuration Cycle 124 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 host interface The `C82 contains a simple three-pin mechanism by which a host or other device may gain control of the `C82 local memory bus. The /HREQ input may be driven low by the host to request the `C82's bus. Once the TC has completed the current memory access, it will place the local bus (except CLKOUT) into a highimpedance state. It will then drive the /HACK output low to indicate that the host device owns and may drive the bus. The REQ output reflects the highest-priority cycle request being received internally by the TC. The host can monitor this output to determine if It needs to relinquish the local bus back to the `C82. Table 49. REQ Output REQ 1 0 ASSOCIATED INTERNAL TC REQUEST Urgent refresh or XPT All other activity device reset The TMS320C82 is reset when the /RESET input is driven low. The `C82 outputs will immediately go into a high-impedance state with the exception of CLKOUT, /HACK, and REQ. While /RESET is low, all internal register are set to their default values and internal logic is reset. On the rising edge of /RESET, the state of READY is sampled to determine if big-endian (READY=0) or little-endian (READY=1) operation is selected. The state of /HREQ is also sampled to determine if the master processor will come up running (/HREQ=0) or halted (/HREQ=1). All other inputs and data lines are don't cares during device reset. Once /RESET is high, the `C82 will drive the high-impedance signals to their inactive values. The TC will then perform 32 refresh cycles to initialize system memory. If, during initialization refresh, the TC receives an SDRAM cycle timing code (/EXCEPT[1:0] = 11), it will perform an SDRAM DCAB cycle to initialize SDRAM and then continue with the refresh cycles. After completing initialization refresh, if the MP is running, the TC will perform a bank configuration cycle for the bank at address 0xFFFFFFC0. This is the cache subblock which contains the starting MP instruction located at 0xFFFFFFF8. If the MP comes up halted, the configuration cycle and instruction cache fills will not take place until the first occurrence of an /EINT3 interrupt to unhalt the MP. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 125 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 absolute maximum ratings Supply voltage range, VDD (see Note 1) ................................................................................... -0.3 V to 4 V Input voltage range, VI ............................................................................................................. -0.3 V to 4 V Output voltage range ................................................................................................................ -0.3 V to 4 V Operating case temperature range, TC ...................................................................................... 0C to 85C Storage temperature range ................................................................................................... -55C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage levels are with respect to ground (VSS). recommended operating conditions PARAMETER VDD VDDPLL VSS VSSPLL IOH IOL Supply voltage Phase-locked loop supply voltage (see Note 2) Supply voltage (see Note 3) Phase-locked loop supply voltage (see Note 2) High-level output current Low-level output current MIN 3.165 3.165 0 0 NOM 3.3 3.3 0 0 MAX 3.465 3.465 0 0 -400 2 UNIT V V V V A mA TC Operating case temperature 0 85 C NOTES: 2. The VDDPLL pin should be supplied through an EMI filter coupled to VSSPLL. Care should be taken to provide a minimum inductance path between VSSPLL and system ground. 3. In order to minimize noise on VSS, care should be taken to provide a minimum inductance path between the VSS pins and system ground. electrical characteristics over full ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER VIH VIL VOH VOL IO High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output current, leakage (high-impedance) (except EMU0, and EMU1) II IDD Input current (except TCK, TDI, and TMS) Supply current (See Note 4) VDD = min, IOH = max VDD = max, IOH = min VDD = max, VO = 2.8V VDD = max, VO = 0.6V VI = VSS to VDD VDD = max, 60 MHz VDD = max, 50 MHz IDDPLL CI CO PLL supply current Input capacitance Output capacitance 10 10 1.2 1.1 TEST CONDITIONS MIN 2 -0.3 2.4 0.6 20 -20 20 2.2 2.1 150 mA pF pF A A TYP MAX VDD + 0.3 0.8 UNIT V V V V A NOTE 4: Maximum supply current is derived from a test case that generates the theoretical maximum data flow using a worst casecheckerboard data pattern on a sustained cycle-by-cycle basis. Typical supply current is derived from a test case which attempts to emulate typical use conditions of the on-chip processors with random data. Typical IDD will vary from application to application based on data flow, transitions, and on-chip processor utilization. For conditions shown as MIN/MAX, use the appropriate value specified under the recommended operating conditions. All typical values are at VDD = 3.3 V, TA = 25C Typical steady state VOH will not exceed VDD 126 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 PARAMETER MEASUREMENT INFORMATION IO L T es ter P in E lec tronic s 50 CT V LO A D O utput U nder T es t IO H Where: IOL = 2.0 mA (all outputs) IOH = 400 A (all outputs) VLOAD = 1.5 V CT = 60 pF typical load circuit distributed capacitance Figure 104. Test Load Circuit signal transition levels TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V. Figure 105 shows the TTL-level outputs. 2 .4 V 2 .0 V 0 .8 V 0 .6 V Figure 105. TTL Level Outputs TTL-output transition times are specified as follows: For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no longer high is 2 V, and the level at which the output is said to be low is 0.8 V. For a low-to high transition, the level at which the output is said to be no longer low is 0.8 V, and the level at which the output is said to be high is 2 V. Figure 106 shows the LVTTL-level inputs 2 .0 V 0 .8 V Figure 106. LVTTL Level Inputs LVTTL-compatible input transition times are specified as follows: For a high-to-low transition on a input signal, the level at which the input is said to be no longer high is 2 V, and the level at which the input is said to be low is 0.8 V. For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 0.8 V, and the level at which the input is said to be high is 2 V. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 127 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 timing parameter symbology Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: A AD ADS CAS CKI CKO CMP D EIN EMU EXC HAK HRQ LIN MID AD[31:0] AD[63:0] AD[39:32] /CAS/DQM[7:0] CLKIN CLKOUT /EXCEPT[1:0], READY AD[63:0] /EINT1, /EINT2, /EINT3 EMU0, EMU1 /EXCEPT[1:0] /HACK /HREQ /LINT4 AD[63:0], RCA[16:0], STATUS[1:0] OUT AD[63:0], /CAS/DQM[7:0], /DBEN, /DDIN, DSF, /RAS, /RL, STATUS[1:0], /TRG/CAS, /W STATUS[1:0] /RAS RCA[16:0] READY /RESET REQ /RL TCK TDI TDO TMS /TRST /XPT[3:0] STS RAS RCA RDY RST REQ RL TCK TDI TDO TMS TRS XPT LOWERCASE SUBSCRIPTS AND THEIR MEANINGS ARE: a c d h su t w access time cycle time (period) delay time hold time setup time transition time pulse duration (width) THE FOLLOWING LETTERS AND SYMBOLS AND THEIR MEANINGS ARE: D H L V X Z Driven High Low Valid Unknown, changing, or don't-care level High impedance 128 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 general notes on timing parameters The period of CLKOUT may be equal to, or is twice the period of CLKIN (tc(CKI)) depending on whether or not PLL mode is selected. In PLL mode, CLKOUT is the same period as CLKIN. In non-PLL mode, the period of CLKOUT will be twice the period of CLKIN, or 2tc(CKI). The half cycle time (tH) that appears in the following tables is one-half the output clock period. All output signals from the `C82 (including CLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, refer to the appropriate cycle description section of this data sheet. CLKIN timing requirements NO. 1 2 3 4 5 tc(CKI) tw(CKIH) tw(CKIL) tt(CKI) FLOCK PARAMETER Period of CLKIN Pulse duration of CLKIN high Pulse duration of CLKIN low Transition time of CLKIN Phased-locked loop lock range 40 C82-50 MIN 10.0 4.2 4.2 1.5 80 40 MAX C82-60 MIN 8.3 3.9 3.9 1.5 80 MAX ns ns ns ns MHz UNIT This parameter is verified by computer simulation and is not tested. 1 2 4 4 C LKIN 3 Figure 107. CLKIN Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 129 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 local bus switching characteristics - CLKOUT CLKOUT may switch at either the CLKIN rate (PLL mode) or 1/2 the CLKIN rate (non-PLL mode). In either mode, no skew or phase relationship is guaranteed (function of PLL is to allow for higher processor rates with lower frequency oscillator). Each state of a memory access begins on the falling edge of CLKOUT. NO. 6 6 7 8 9 10 tc(CKO) tc(CKO) tw(CKOH) tw(CKOL) tt(CKO) tJITTER PARAMETER MIN Period of CLKOUT (non-PLL mode) Period of CLKOUT (PLL mode) Pulse duration of CLKOUT high Pulse duration of CLKOUT low Transition time of CLKOUT CLKOUT jitter (PLL mode only) 2tc(CKI) tc(CKI) tH-4.5 tH-4.5 2 1.2 C82-50 MAX MIN 2tc(CKI) tc(CKI) tH-3.7 tH-3.7 2 0.8 C82-60 MAX ns ns ns ns ns ns UNIT This is a functional minimum and is not tested. This parameter may also be specified as 2tH. This parameter is specified by computer simulation and is not tested. This parameter is characterized and is not tested. 6 7 9 9 10 10 C LKO U T 8 10 10 Figure 108. CLKOUT Timing 130 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 device reset timing requirements NO. 11 tw(RSTL) Duration of /RESET low PARAMETER Initial reset during power-up (non-PLL mode) Initial reset during power-up (PLL mode) Reset during active operation 12 13 14 15 tsu(HRQL-RSTH) th(RSTH-HRQL) tsu(RDYL-RSTH) th(RSTH-RDYL) Setup time of /HREQ low to /RESET high to configure self-bootstrap mode Hold time, /HREQ low after /RESET high to configure self-bootstrap mode Setup time of READY low to /RESET high to configure big-endian operation Hold time, READY low after /RESET high to configure big-endian operation MIN 6tH 2 6tH 4tH 0 4tH 0 ns ns ns ns MAX UNIT ns s 11 RESET 12 13 HREQ 14 15 READY Figure 109. Device Reset Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 131 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 local bus timing: memory exceptions Memory exceptions are signaled to the `C82 via the /EXCEPT[1:0] inputs. The /EXCEPT[1:0] inputs are sampled at the beginning of each row access during the ad2 state, and on each CLKOUT falling edge following rl1. The READY input is also sampled during the ad2 state and during each column access (2 and 3 cyc/col accesses only). The value n as used in the parameters represents the integral number of half-cycles between the transitions of the two signals in question. NO. 16 ta(MIDV-CMPV) PARAMETER MIN Access time, /EXCEPT[1:0] , READY valid after memory identification (address, status) valid Setup time, /EXCEPT[1:0] , READY valid to CLKOUT no longer high/low Hold time, /EXCEPT[1:0] , READY valid after CLKOUT no longer high/low Access time /EXCEPT[1:0], READY valid from /RAS low Access time, /EXCEPT[1:0], READY valid from /RL low Access time, READY valid from /CAS low 7.5 2.0 C82-50 MAX ntH-8 MIN C82-60 MAX ntH-8 ns UNIT 17 18 tsu(CMPV-CKO) th(CKO-CMPV) 7.5 2.0 ns ns 19 20 21 ta(RASL-RRV) ta(RLL-RRV) ta(CASL-RDYV) ntH-7.5 ntH-7.5 ntH-8 ntH-7.5 ntH-7.5 ntH-8 ns ns ns This parameter also applies to refresh cycles, wherein cycle timing is determined via the /EXCEPT[1:0] pin codings. 132 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 local bus timing: memory exceptions (continued) tH tH tH tH tH tH tH tH tH tH CLKOUT STATUS[1:0] AD[63:0] Address/Access Data In/Out RCA[16:0] RL RAS 20 18 16 17 19 EXCEPT[1:0] READY Figure 110. Row Time Cycle Completion Input Timing tH tH tH tH tH tH tH tH tH tH CLKOUT STATUS[1:0] RCA[16:0] CAS/DQM[7:0] 17 18 16 21 READY EXCEPT[1:0] Figure 111. Column Time Cycle Completion Input Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 133 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 general output signal characteristics The following general timing parameters apply to all TMS320C82 output signals unless otherwise specifically given. The value n as used in the parameters represents the integral number of half-cycles between the transitions of the two outputs in question. For timing purposes, outputs fall into one of three groups: the address/data bus (AD[63:0]); the other output busses (RCA[16:0], STATUS[1:0], /CAS/DQM[7:0]); and non-bus outputs (/DBEN, /DDIN, DSF, /RAS, /RL, /TRG/CAS, /W). When measuring output to output, the named group refers to the first output to transition (Output A), and the second output (Output B) refers to any output group. 134 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 general output signal characteristics (continued) NO. 22 PARAMETER MIN th(OUTV-CKOL) Hold time, CLKOUT high after output valid AD[63:0] RCA[16:0], STATUS[1:0], /CAS/DQM[7:0] (CT = 0X0X) /CAS/DQM[7:0] (CT != 0X0X) /DBEN, /DDIN, DSF, /RAS, /RL, /TRG/CAS, /W 23 th(OUTV-CKOH) Hold time, CLKOUT low after output valid AD[63:0] RCA[16:0], STATUS[1:0], /CAS/DQM[7:0] (CT = 0X0X) /CAS/DQM[7:0] (CT != 0X0X) /DBEN, /DDIN, DSF, /RAS, /RL, /TRG/CAS, /W 24 25 26 th(CKOL-OUTV) th(CKOH-OUTV) th(OUTV-OUTV) Hold time, output valid after CLKOUT low Hold time, output valid after CLKOUT high Hold time, output valid after output valid AD[63:0] RCA[16:0], STATUS[1:0], /CAS/DQM[7:0] (CT = 0X0X) /CAS/DQM[7:0] (CT != 0X0X) /DBEN, /DDIN, DSF, /RAS, /RL, /TRG/CAS, /W 27 td(CKOL-OUTV) Delay time, CLKOUT no longer high to output valid AD[63:0] RCA[16:0], STATUS[1:0], /CAS/DQM[7:0] /DBEN, /DDIN, DSF, /RAS, /RL, /TRG/CAS, /W 28 td(CKOH-OUTV) Delay time, CLKOUT no longer low to output valid AD[63:0] RCA[16:0], STATUS[1:0], /CAS/DQM[7:0] /DBEN, /DDIN, DSF, /RAS, /RL, /TRG/CAS, /W 29 td(OUTV-OUTV) Delay time, output no longer valid to output valid AD[63:0] RCA[16:0], STATUS[1:0], /CAS/DQM[7:0] (CT = 0X0X) /CAS/DQM[7:0] (CT != 0X0X) /DBEN, /DDIN, DSF, /RAS, /RL, /TRG/CAS, /W 30 31 32 td(OUTV-CKOL) td(OUTV-CKOH) tw(OUTV) Delay time, output no longer valid to CLKOUT low Delay time, output no longer valid to CLKOUT high Pulse width, output valid AD[63:0] RCA[16:0], STATUS[1:0], /CAS/DQM[7:0] (CT = 0X0X) /CAS/DQM[7:0] (CT != 0X0X) /DBEN, /DDIN, DSF, /RAS, /RL, /TRG/CAS, /W 33 34 35 36 th(CKOL-ADZ) th(CKOH-ADZ) td(CKOL-ADZ) td(CKOH-ADZ) Hold time, AD[63:0] driven after CLKOUT low Hold time, AD[63:0] driven after CLKOUT high Delay time, CLKOUT no longer high to AD[63:0] Hi-Z Delay time, CLKOUT no longer low to AD[63:0] Hi-Z ntH-6.5 ntH-5.5 ntH-5.9 ntH-5.6 ntH-5 ntH-5 ntH-5 ntH+5 ntH+5 ntH-6.3 ntH-5.5 ntH-5.6 ntH-5.5 ntH-5 ntH-5 ntH-5 ntH+5 ntH+5 ns ns ns ns ntH+6.5 ntH+5.5 ntH+5.9 ntH+5.6 ntH+5 ntH+5 ntH+5.4 ntH+6.3 ntH+5.5 ntH+5.7 ntH+5.5 ntH+4.8 ntH+5 ntH+5 ns ns ns ns ntH+6.5 ntH+5.5 ntH+5 ntH+5.9 ntH+5.5 ntH+4.7 ntH+6.5 ntH+5.5 ntH+5 ntH+5.9 ntH+5.5 ntH+4.7 ns ntH-6.5 ntH-5.5 ntH-5.9 ntH-5.5 ntH-5 ntH-6.3 ntH-5.5 ntH-5.7 ntH-5.5 ntH-4.8 ns ntH-5.5 ntH-4.5 ntH-5.0 ntH-4.6 ntH-4.1 ntH-5 ntH-5.4 ntH-5.3 ntH-4.5 ntH-4.7 ntH-4.5 ntH-4.1 ntH-5 ntH-5 ns ns ns ntH-5.3 ntH-4.5 ntH-4.8 ntH-4.4 ntH-3.9 ntH-5.3 ntH-4.4 ntH-4.7 ntH-4.4 ntH-3.9 ns C82-50 MAX MIN C82-60 MAX ns UNIT This parameter is a functional minimum specified by logic and is not tested. This parameter is specified by characterization and is not tested. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 135 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 general output signal characteristics (continued) tH tH tH tH tH tH tH tH tH tH tH tH CLKOUT 31 25 23 28 OutputA 30 29 27 24 22 26 OutputB 32 Figure 112. General Output Timing tH tH tH tH tH tH tH tH CLKOUT 34 35 36 33 AD[63:0] Hi-Z Figure 113. AD[63:0] Turnoff/Turn-Around Timing 136 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 data input signal characteristics The following general timing parameters apply to the AD[63:0] inputs unless otherwise specifically given. The value n as used in the parameters represents the integral number of half cycles between the transitions of the output and input in question. NO. 37 38 39 40 41 42 43 ta(CKOH-DV) ta(CKOL-DV) tsu(DV-CKOH) tsu(DV-CKOL) th(CKOL-DV) th(CKOH-DV) ta(OUTV-DV) PARAMETER Access time, CLKOUT high to AD[63:0] valid Access time, CLKOUT low to AD[63:0] valid Setup time, AD[63:0] valid to CLKOUT no longer low Setup time, AD[63:0] valid to CLKOUT no longer high Hold time, AD[63:0] valid after CLKOUT low Hold time, AD[63:0] valid after CLKOUT high Access time, output valid to AD[63:0] inputs valid AD[39:0] RCA[16:0], /CAS/DQM[7:0], STATUS[1:0] /DBEN, /DDIN, DSF, /RAS, /RL, /TRG/CAS, /W 44 th(OUTV-DV) Hold time, AD[63:0] valid after output valid RCA[16:0], /CAS/DQM[7:0] (CT = 00xx) RCA[16:0], /CAS/DQM[7:0] (CT = 01xx) /RAS 2.5 2 2 2.5 2 2 ns ntH-7.6 ntH-7 ntH-6.5 ntH-7.6 ntH-7 ntH-6.5 ns 6.5 6.1 2.5 2.5 C82-50 MIN MAX ntH-5.3 ntH-6.5 6.1 6.1 2.5 2.5 C82-60 MIN MAX ntH-5.3 ntH-6.5 ns ns ns ns ns ns UNIT tH tH tH tH tH tH tH tH tH tH tH tH CLKOUT 41 39 37 42 40 38 AD[63:0] 44 39 Output Figure 114. Data Input Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 137 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 external interrupt timing The following description defines the timing of the edge-triggered interrupts /EINT1 - /EINT3 and the leveltriggered interrupt /LINT4 (see Note 5). NO. 45 46 47 48 tw(EINL) tsu(EINH-CKOH) tw(EINH) tsu(LINL-CKOH) PARAMETER Pulse duration, /EINTx low Setup time, /EINTx high before CLKOUT no longer low Pulse duration, /EINTx high Setup time, /LINT4 low before CLKOUT no longer low 6 10 6 9.5 C82-50 MIN MAX 6 10 6 9.5 C82-60 MIN MAX ns ns ns ns UNIT This parameter is specified by characterization and is not tested. This parameter must only be met to ensure that the interrupt is recognized on the indicated cycle. NOTE 5: In order to ensure recognition, /LINT4 must remain low until cleared by the interrupt service routine. Interrupt Recognized CLKOUT 46 47 EINTx 45 48 LINT4 Figure 115. External Interrupt Timing 138 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 XPT input timing The following description defines the sampling of the /XPT[3:0] inputs. The value encoded on the /XPT[3:0] inputs is synchronized over multiple cycles to ensure that a stable value is present. NO. 49 50 51 52 tw(XPTV) tsu(XPTV-CKOH) th(CKOH-XPTV) th(RLL-XPTV) PARAMETER Pulse duration, /XPTx valid Setup time, /XPT[3:0] valid before CLKOUT no longer low Hold time, /XPT[3:0] valid after CLKOUT high Hold time, /XPT[3:0] valid after /RL low C82-50 MIN 12tH 12 5 6tH MAX C82-60 MIN 12tH 12 5 6tH MAX ns ns ns ns UNIT This parameter must only be met to ensure that the XPT input is recognized on the indicated cycle. This parameter must be met to ensure that a second XPT request does not occur. This parameter is a functional maximum specified by logic and is not tested. This parameter is a functional minimum specified by logic and is not tested. XPT Inputs Sampled XPT Inputs Recognized CLKOUT 50 51 49 XPT[3:0] XPTn Figure 116. XPT Input Timing - XPT Recognition CLKOUT AD[39:32] XPTn Row Status RL 52 XPT[3:0] XPTn XPTz Figure 117. XPT Input Timing - XPT Service POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 139 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 host interface timing NO. 53 54 55 56 th(REQV-CKOH) th(CKOH-REQV) th(HRQL-HAKL) td(HAKL-OUTZ) PARAMETER Hold time, CLKOUT low after REQ valid Hold time, REQ valid after CLKOUT high Hold time, /HACK high after /HREQ low Delay time, /HACK low to output Hi-Z All signals except AD[63:0] AD[63:0] 57 58 59 td(HRQH-HAKH) td(HAKH-OUTD) tsu(HRQL-CKOH) Delay time, /HREQ high to /HACK no longer low Delay time, /HACK high to outputs driven Setup time, /HREQ low to CLKOUT no longer low (see Note 6) 6tH 8.5 0 1 10 6tH 8.5 0 1 10 ns ns ns ns C82-50 MIN tH-7 tH-7 4tH-12 MAX C82-60 MIN tH-5.5 tH-5.5 4tH-12 MAX ns ns ns UNIT This parameter is specified by characterization and is not tested. This parameter is a functional minimum and is not tested. Note 6: This parameter must be met only to ensure /HREQ is sampled low on the indicated clock cycle. HREQ Sampled CLKOUT 53 54 REQ 59 HREQ 55 57 HACK 56 58 RCA[16:0] STATUS[1:0] TRG /CAS , W, DSF, RL , DBEN RAS , CAS /DQM[7:0] AD[63:0] DDIN Figure 118. Host Interface Timing 140 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 thermal resistance The following graph illustrates the maximum ambient temperature allowed for various air flow rates across the TMS320C82 to ensure that the case temperature is kept below the maximum operating temperature (85C). (See Note 7.) Maximum Ambient Temperature Versus Airflow 70 65 60 Max Ta (deg C) 55 50 45 40 35 30 25 1000 0 100 200 300 400 500 600 700 800 900 40 MHz (GGP) 50 MHz (GGP) 60 MHz (GGP) Airflow (Linear Ft/Min) Figure 119. TMS320C82 Airflow Recommendations Note 7: TMS320C82 power consumption is based on the "typical" values of IDD measured at VDD = 3.3 V. Power consumption will vary by application based on TMS320C82 processor activity and I/O pin loadings. Users must ensure that the case temperature (TC) specifications are met when defining airflow and other thermal constraints of their system. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 141 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 emulator interface connection The TMS320C82 supports emulation through a dedicated emulation port which is a superset of the IEEE 1149.1 (JTAG) standard. To support the TMS320C82 emulator, a target system must include a 14-pin header (2 rows of 7 pins) with the connections shown below. T RS T GND no pi n ( key ) GND GND GND EMU1 TMS T DI P D ( + 3.3 V ) T DO T C K RE T TCK EMU0 1 3 5 7 9 11 13 2 4 6 8 10 12 14 Pin Spacing - 0.100 in. (X, Y) Pin Width - 0.025 in. square post Pin Length - 0.318 in. nominal XDS 510TM SIGNAL TMS TDI TDO TCK /TRST EMU0 EMU1 PD (+3.3 V) TCKRET XDS 510 STATE O O I O O I I I I TARGET STATE I I O I I I/O I/O O O JTAG test mode select JTAG test data input JTAG test data output DESCRIPTION JTAG test clock - 10 MHz clock source from emulator. Can be used to drive system test clock. JTAG test reset Emulation pin 0 Emulation pin 1 Presence detect - Indicates that the target is connected and powered-up. Should be tied to +3.3 V on target system JTAG test clock return - Test clock input to the XDS510 emulator. May be buffered or unbuffered version of TCK. For best results, the emulation header should be located as close as possible to the TMS320C82. If the distance exceeds 6 inches, the emulation signals should be buffered. XDS510 is a trademark of Texas Instruments Incorporated. 142 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 emulator interface connection (continued) + 3. 3 V + 3. 3 V + 3. 3 V + 3. 3 V E M U0 E M U1 T RST TMS T DI TDO T CK C21 B21 B20 D19 C20 C22 C19 13 14 2 1 3 7 11 9 E M U0 E M U1 T RS T TMS T DI TDO T CK T CKRE T PD 5 EM U0 E M U1 C21 B21 B20 D19 TM S T DI TD O TCK C20 C22 C19 13 14 2 1 3 7 11 9 3 20 C 8 2 More than 6 in. E m ulator H e a der EM U0 E M U1 TRST T MS T DI T DO T CK T CKR E T GND GND GND GND GND 4 6 8 10 12 PD 5 GND GND GND GND GND 4 T RST 6 8 10 12 3 20 C8 2 6 in. o less r E mul ator He ad er Figure 120. Emulation Header Connections - Emulator-Driven Test Clock The target system may also generate the test clock. This allows the user to: * Set test clock frequency to match system requirements. (The emulator provides a 10-MHz test clock) * Have other devices in the system that require a test clock when the emulator is not connected. + 3.3 V + 3. 3 V E M U0 E M U1 T RS T TMS T DI TDO T CK 320 C 8 2 Syste m T est Clock C21 B21 B20 D19 C20 C22 C19 13 14 2 1 3 7 11 9 EM U0 E M U1 T RS T TMS T DI T DO T CK T CKRET PD 5 GND GND GND GND GND 4 6 8 10 12 E m ulator H eader More than 6 in. Figure 121. Emulation Header Connections - System-Driven Test Clock POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 143 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 emulator interface connection (continued) For multiprocessor applications, the following are recommended: * Buffer TMS, TDI, TDO, and TCK through the same physical package to reduce timing skew. * Buffer inputs for TMS, TDI, and TCK should be pulled high (3.3 V). A pullup resistor of 4.7 k or greater is suggested. * Buffering EMU0 and EMU1 is highly recommended to provide isolation. The buffers need not be in the same physical package as TMS, TCK, TDI, or TDO. Pullups to 3.3 V are required and should provide a signal rise time of less than 10 s. A 4.7-k resistor is suggested for most applications. * To ensure high quality signals, special PWB routing and use of termination resistors may be required. The emulator provides fixed series termination (33 ) on TMS and TDI and optional parallel terminators (180 pullup and 270 pulldown) on TCKRET and TDO. + 3. 3 V + 3. 3 V E M U0 E MU1 TRST TMS T DI TDO T CK 320 C 8 2 C21 B21 B20 D19 C20 C22 C19 13 14 2 1 3 7 11 9 EM U0 E M U1 T RST TMS T DI T DO T CK T C K R ET PD 5 GND GND GND GND GND 4 6 8 10 12 E M U0 E MU1 TRST TMS T DI TDO T CK 3 20 C 82 C21 B21 B20 D19 C20 C22 C19 E m ul at or H ea der Figure 122. Emulation Header Connections - Multiprocessor Applications 144 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 TMS320C82 DIGITAL SIGNAL PROCESSOR SPRS048 -- APRIL 1998 MECHANICAL DATA GGP (S-PBGA-N352) PLASTIC BALL GRID ARRAY (CAVITY DOWN) 31,75 TYP 35,20 SQ 34,80 1,27 0,635 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26 Heat Slug 0,91 NOM 1,70 MAX Seating Plane 0,90 0,60 0,30 M 0,15 0,50 MIN 4073223/B 11/97 NOTES: 1. All linear dimensions are in millimeters 2. This drawing is subject to change without notice. 3. Thermally enhanced plastic package with metal heat slug (HSL) 0,635 145 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 1,27 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright (c) 1998, Texas Instruments Incorporated |
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