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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
D Highest Performance Floating-Point Digital
Signal Processor (DSP) TMS320C6701 - 8.3-, 6.7-, 6-ns Instruction Cycle Time - 120-, 150-, 167-MHz Clock Rate - Eight 32-Bit Instructions/Cycle - 1 GFLOPS - TMS320C6201 Fixed-Point DSP Pin-Compatible VelociTITM Advanced Very Long Instruction Word (VLIW) 'C67x CPU Core - Eight Highly Independent Functional Units: - Four ALUs (Floating- and Fixed-Point) - Two ALUs (Fixed-Point) - Two Multipliers (Floating- and Fixed-Point) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Hardware Support for IEEE Single-Precision Instructions - Hardware Support for IEEE Double-Precision Instructions - Byte-Addressable (8-, 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization 1M-Bit On-Chip SRAM - 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) - 512K-Bit Dual-Access Internal Data (64K Bytes) 32-Bit External Memory Interface (EMIF) - Glueless Interface to Synchronous Memories: SDRAM and SBSRAM - Glueless Interface to Asynchronous Memories: SRAM and EPROM - 52M-Byte Addressable External Memory Space Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel
26
GJC (352-PIN BGA) PACKAGE (BOTTOM VIEW)
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
D
D
D 16-Bit Host-Port Interface (HPI) D
- Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching Compatible - Up to 256 Channels Each - AC97-Compatible - Serial-Peripheral-Interface (SPI) Compatible (MotorolaTM) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 352-Pin Ball Grid Array (BGA) Package (GJC Suffix) 0.18-m/5-Level Metal Process - CMOS Technology 3.3-V I/Os, 1.8-V Internal (120-, 150-MHz) 3.3-V I/Os, 1.9-V Internal (167-MHz Only)
D
D
D D D D D D D
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional block and CPU diagram . . . . . . . . . . . . . . . . . . . . . 4 CPU description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 recommended operating conditions . . . . . . . . . . . . . . . . . . . 27 electrical characteristics over recommended ranges of supply voltage and operating case temperature . . . . 28 parameter measurement information . . . . . . . . . . . . . . . 29 signal-transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 33 synchronous-burst memory timing . . . . . . . . . . . . . . . . . 35 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 39 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 46 host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 47 multichannel buffered serial port timing . . . . . . . . . . . . . 50 DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 61 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
description
The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000TM DSP platform. The TMS320C6701 ('C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a clock rate of 167 MHz, the 'C6701 offers cost-effective solutions to high-performance DSP programming challenges. The 'C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The 'C6701 can produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The 'C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The 'C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals. The 'C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a WindowsTM debugger interface for visibility into source code execution.
device characteristics
Table 1 provides an overview of the 'C6701 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. Table 1. Characteristics of the 'C6701 Processors
HARDWARE FEATURES EMIF DMA Peri herals Peripherals Host-Port Interface (HPI) McBSPs 32-Bit Timers Size (Bytes) Internal Program Memory Internal Data Memory Frequency Cycle Time Organization Size (Bytes) Organization MHz ns Core (V) I/O (V) PLL Options BGA Package Process Technology Product Status CLKIN frequency multiplier 35 x 35 mm m Product Preview (PP) Advance Information (AI) Production Data (PD) 'C6701 1 4-Channel 1 2 2 64K 64K Bytes Cache/Mapped Program 64K 2 Blocks: Eight 16-Bit Banks per Block 50/50 Split 120, 150, 167 6 ns ('6701-167); 6.7 ns ('6701-150); 8.3 ns ('6701-120) 1.8 ('6701-120, -150) Voltage 1.9 ('6701-167 only) 3.3 Bypass (x1), x4 352-pin GJC 0.18 m PD
TMS320C6000 is a trademark of Texas Instruments. Windows is a registered trademark of Microsoft Corporation.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
functional block and CPU diagram
SDRAM SBSRAM
32 Program Bus
'C6701 Digital Signal Processor
Program Access/Cache Controller Internal Program Memory 1 Block Program/Cache (64K Bytes)
SRAM ROM/FLASH I/O Devices
External Memory Interface (EMIF)
'C67x CPU Timer 0 Timer 1 Multichannel Buffered Serial Port 0 Multichannel Buffered Serial Port 1 Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File
DMA Buses
Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
HOST CONNECTION MC68360 Glueless MPC860 Glueless PCI9050 Bridge + Inverter MC68302 + PAL MPC750 + PAL MPC960 (Jx/Rx) + PAL
16
Host Port Interface (HPI)
Direct Memory Access Controller (DMA) (4 Channels) PLL (x1, x4)
Data Bus
Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs
Data Path B B Register File
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
PowerDown Logic
Data Access Controller
Internal Data Memory (64K Bytes) 2 Blocks of 8 Banks Each
These functional units execute floating-point instructions.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
CPU description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the 'C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the Functional and CPU Block diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all registers on the other side, by which the two sets of functional units can access data from the register files on opposite sides. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The 'C67x CPU executes all TMS320C62xTM DSP fixed-point instructions. In addition to the 'C62x DSP fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the 'C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The 'C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.
TMS320C62x is a trademark of Texas Instruments.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
CPU description (continued)
src1
.L1 src2
dst long dst long src
8
8
LD1 32 MSB ST1
32 32
Data Path A
long src long dst dst .S1 src1 src2
8
8
dst src1 .M1 src2
LD1 32 LSB
DA1
.D1
dst src1 src2
DA2
.D2
src2 src1 dst
LD2 32 LSB
src2
.M2 src1 dst
src2
Data Path B
.S2
src1 dst long dst long src
8
8
LD2 32 MSB ST2
32 32
long src long dst dst .L2 src2 src1
8
8
These functional units execute floating-point instructions.
Figure 1. TMS320C67x CPU Data Paths
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A AAAAA AAAAA AAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAAA AAAAAA AAAAA AAAAA AAAAA AAAAA AAAAAA AAAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA
Register File A (A0-A15) 2X 1X Register File B (B0-B15) Control Register File
A AAAAAAA AAAAAAA A AAA AAAAAAA AAAAA AAAAAAA A AAAAA AAAAA AAAAA A AAAAA AAAAAAA A AAA AAA AAAAA AAAAA AAAAAAA A AAAAAAA A AAAAA AAAAA A AAAAA A AAAAA A AAAAA A A AAAAA AAAAAAA AAAAA A AAAAAAA A A AAAAAAA A A AAAAAAA AAAAA AAAAA AAAAA A AAAAA A AAAAA A AAAAA A AAAAAAA AAA AAAAAAA AAAAAAA AAAAAAA A
AA AA AA AA AA AA
TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
signal groups description
CLKIN CLKOUT2 CLKOUT1 CLKMODE1 CLKMODE0 CLOCK/PLL PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV PLLG PLLF
Boot Mode
BOOTMODE4 BOOTMODE3 BOOTMODE2 BOOTMODE1 BOOTMODE0
Reset and Interrupts TMS TDO TDI TCK TRST EMU1 EMU0
IEEE Standard 1149.1 (JTAG) Emulation Little ENDIAN Big ENDIAN
RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0
LENDIAN
RSV9 RSV8 RSV7 RSV6 RSV5 RSV4 RSV3 RSV2 RSV1 RSV0
DMA Status Reserved Power-Down Status
DMAC3 DMAC2 DMAC1 DMAC0
PD
Control/Status
HD[15:0]
16 Data
HPI (Host-Port Interface)
HCNTL0 HCNTL1
Register Select Control
HHWIL HBE1 HBE0
Half-Word/Byte Select
HAS HR/W HCS HDS1 HDS2 HRDY HINT
Figure 2. CPU and Peripheral Signals
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
signal groups description (continued)
32 ED[31:0] CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 BE1 BE0 20 Data Asynchronous Memory Control ARE AOE AWE ARDY
Memory Map Space Select SBSRAM Control SSADS SSOE SSWE SSCLK
Word Address
Byte Enables SDRAM Control HOLD/ HOLDA EMIF (External Memory Interface)
HOLD HOLDA
SDA10 SDRAS SDCAS SDWE SDCLK
TOUT1 TINP1
Timer 1
Timer 0
TOUT0 TINP0
Timers
McBSP1
McBSP0
CLKX1 FSX1 DX1
Receive
Receive
CLKX0 FSX0 DX0
CLKR1 FSR1 DR1
Transmit
Transmit
CLKR0 FSR0 DR0
CLKS1
Clock
Clock
CLKS0
McBSPs (Multichannel Buffered Serial Ports)
Figure 3. Peripheral Signals
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
Signal Descriptions
SIGNAL NAME CLKIN CLKOUT1 CLKOUT2 CLKMODE1 CLKMODE0 PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV PLLG PLLF TMS TDO TDI TCK TRST EMU1 EMU0 RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUM0 LENDIAN NO. C10 AF22 AF20 C6 C5 A9 D11 B10 D12 C12 A11 L3 W2 R4 R3 T1 Y1 W3 K2 L2 U3 V2 W1 U4 Y2 AA1 W4 AA2 AB1 H3 I If high, LENDIAN selects little-endian byte/half-word addressing order within a word If low, LENDIAN selects big-endian addressing O Active interrupt identification number * Valid during IACK for all active interrupts (not just external) * Encoding order follows the interru t-service fetch-packet ordering interrupt-service fetch- acket O Interrupt acknowledge for all active interrupts serviced by the CPU I External interrupts interru ts * Edge-driven ( g (rising edge) g g) A A A I O/Z I I I I/O/Z I/O/Z I I PLL analog VCC connection for the low-pass filter PLL analog GND connection for the low-pass filter PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION JTAG test-port mode select (features an internal pullup) JTAG test-port data out JTAG test-port data in (features an internal pullup) JTAG test-port clock JTAG test-port reset (features an internal pulldown) Emulation pin 1, pullup with a dedicated 20-k resistor Emulation pin 0, pullup with a dedicated 20-k resistor CONTROL Device reset Nonmaskable interrupt * Edge-driven (rising edge) I PLL f frequency range (3 2 and 1) (3, 2, d * The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins. pins I TYPE CLOCK/PLL I O O Clock Input Clock output at full device speed Clock output at half of device speed Clock mode select * Selects whether the output clock frequency = input clock frequency x4 or x1 DESCRIPTION
PD D3 O Power-down mode 3 (active if high) I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these pins. A = Analog Signal (PLL Filter) For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-k resistor.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
Signal Descriptions (Continued)
SIGNAL NAME HINT HCNTL1 HCNTL0 HHWIL HBE1 HBE0 HR/W HD15 HD14 HD13 HD12 HD11 HD10 HD9 HD8 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 HAS HCS HDS1 HDS2 HRDY BOOTMODE4 BOOTMODE3 BOOTMODE2 BOOTMODE1 NO. H26 F23 D25 C26 E23 D24 C23 B13 B14 C14 B15 D15 B16 A17 B17 D16 B18 A19 C18 B19 C19 B20 B21 C22 B23 D22 A24 J24 D8 B4 A3 D5 I Boot mode I I I I O Host address strobe Host chip select Host data strobe 1 Host data strobe 2 Host ready (from DSP to host) BOOT MODE I/O/Z Host port data (used for transfer of data address and control) Host-port data, address, TYPE DESCRIPTION HOST-PORT INTERFACE (HPI) O I I I I I I Host interrupt (from DSP to host) Host control - selects between control, address, or data registers Host control - selects between control, address, or data registers Host half-word select - first or second half-word (not necessarily high or low order) Host byte select within word or half-word Host byte select within word or half-word Host read or write select
BOOTMODE0 C4 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
Signal Descriptions (Continued)
SIGNAL NAME CE3 CE2 CE1 CE0 BE3 BE2 BE1 BE0 EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 EA7 EA6 EA5 EA4 EA3 NO. AE22 AD26 AB24 AC26 AB25 AA24 Y23 AA26 J26 K25 L24 K26 M26 M25 P25 P24 R25 T26 R23 U26 U25 T23 V26 V25 W26 V24 W25 O/Z External address (word address) TYPE DESCRIPTION
EMIF - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z Memory space enables * * * * * Enabled by bits 24 and 25 of the word address Only one asserted during any external data access Decoded from the two lowest bits of the internal address Byte-write enables for most types of memory Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF - ADDRESS
Byte-enable control
EA2 Y26 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
Signal Descriptions (Continued)
SIGNAL NAME ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 ARE AOE AWE NO. AB2 AC1 AA4 AD1 AC3 AD4 AF3 AE4 AD5 AF4 AE5 AD6 AE6 AD7 AC8 AF7 AD9 AD10 AF9 AC11 AE10 AE11 AF11 AE14 AF15 AE15 AF16 AC15 AE17 AF18 AF19 AC17 EMIF - ASYNCHRONOUS MEMORY CONTROL Y24 AC24 AD23 O/Z O/Z O/Z Asynchronous memory read enable Asynchronous memory output enable Asynchronous memory write enable I/O/Z External data TYPE EMIF - DATA DESCRIPTION
ARDY W23 I Asynchronous memory ready input I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
Signal Descriptions (Continued)
SIGNAL NAME SSADS SSOE SSWE SSCLK SDA10 SDRAS SDCAS SDWE SDCLK HOLD HOLDA TOUT1 TINP1 TOUT0 TINP0 DMAC3 DMAC2 DMAC1 DMAC0 CLKS1 CLKR1 CLKX1 DR1 DX1 FSR1 NO. AC20 AF21 AD19 AD17 AD21 AF24 AD22 AF23 AE20 AA25 A7 H24 K24 M4 K4 D2 F4 D1 E2 MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) E25 H23 F26 D26 G23 E26 I I/O/Z I/O/Z I O/Z I/O/Z External clock source (as opposed to internal) Receive clock Transmit clock Receive data Transmit data Receive frame sync O DMA action complete TYPE DESCRIPTION EMIF - SYNCHRONOUS BURST SRAM CONTROL O/Z O/Z O/Z O O/Z O/Z O/Z O/Z O I O O I O I SBSRAM address strobe SBSRAM output enable SBSRAM write enable SBSRAM clock EMIF - SYNCHRONOUS DRAM CONTROL SDRAM address 10 (separate for deactivate command) SDRAM row-address strobe SDRAM column-address strobe SDRAM write enable SDRAM clock EMIF - BUS ARBITRATION Hold request from the host Hold-request-acknowledge to the host TIMERS Timer 1 or general-purpose output Timer 1 or general-purpose input Timer 0 or general-purpose output Timer 0 or general-purpose input DMA ACTION COMPLETE
FSX1 F25 I/O/Z Transmit frame sync I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
Signal Descriptions (Continued)
SIGNAL NAME CLKS0 CLKR0 CLKX0 DR0 DX0 FSR0 FSX0 RSV0 RSV1 RSV2 RSV3 RSV4 RSV5 RSV6 RSV7 RSV8 RSV9 NO. L4 M2 L1 J1 R1 P4 P3 T2 G2 C11 B9 A6 C8 C21 B22 A23 E4 A10 A15 A18 A21 A22 B7 C1 D17 F3 G24 DVDD G25 H25 J25 L25 M3 N3 N23 R26 T24 U24 W24 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground S 3.3-V supply voltage 3.3 V su ly TYPE DESCRIPTION MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) I I/O/Z I/O/Z I O/Z I/O/Z I/O/Z I I I I I O I I I O External clock source (as opposed to internal) Receive clock Transmit clock Receive data Transmit data Receive frame sync Transmit frame sync RESERVED FOR TEST Reserved for testing, pullup with a dedicated 20-k resistor Reserved for testing, pullup with a dedicated 20-k resistor Reserved for testing, pullup with a dedicated 20-k resistor Reserved for testing, pullup with a dedicated 20-k resistor Reserved for testing, pulldown with a dedicated 20-k resistor Reserved (leave unconnected, do not connect to power or ground) Reserved for testing, pullup with a dedicated 20-kW resistor Reserved for testing, pullup with a dedicated 20-kW resistor Reserved for testing, pullup with a dedicated 20-kW resistor Reserved (leave unconnected, do not connect to power or ground) SUPPLY VOLTAGE PINS
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
Signal Descriptions (Continued)
SIGNAL NAME NO. Y4 AB3 AB4 AB26 AC6 AC10 AC19 AC21 AC22 DVDD AC25 AD11 AD13 AD15 AD18 AE18 AE21 AF5 AF6 AF17 A5 A12 A16 A20 B2 B6 B11 B12 B25 C3 CVDD C15 C20 C24 D4 D6 D7 D9 D14 D18 D20 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground S 1.8 V supply 1.8-V su ly voltage (for '6701-120, -150) 6701 120, 150) 1.9-V supply voltage (for '6701-167 only) y g( y) S 3.3 V su ly 3.3-V supply voltage TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
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Signal Descriptions (Continued)
SIGNAL NAME NO. D23 E1 F1 H4 J4 J23 K1 K23 M1 M24 N4 N25 P2 P23 T3 T4 U1 CVDD V4 V23 AC4 AC9 AC12 AC13 AC18 AC23 AD3 AD8 AD14 AD24 AE2 AE8 AE12 AE25 AF12 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground S 1.8 V supply 1.8-V su ly voltage (for '6701-120, -150) 6701 120, 150) 1.9-V supply voltage (for '6701-167 only) y g( y) TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
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Signal Descriptions (Continued)
SIGNAL NAME NO. A1 A2 A4 A13 A14 A25 A26 B1 B3 B5 B24 B26 C2 C7 C13 C16 C17 C25 D13 VSS D19 E3 E24 F2 F24 G3 G4 G26 J3 L23 L26 M23 N1 N2 N24 N26 P1 P26 R24 T25 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground GND Ground pins ins TYPE GROUND PINS DESCRIPTION
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Signal Descriptions (Continued)
SIGNAL NAME NO. U2 U23 V1 V3 Y3 Y25 AA3 AA23 AB23 AC2 AC5 AC7 AC14 AC16 AD2 AD12 AD16 AD20 VSS AD25 AE1 AE3 AE7 AE9 AE13 AE16 AE19 AE23 AE24 AE26 AF1 AF2 AF8 AF10 AF13 AF14 AF25 AF26 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground GND Ground pins ins TYPE DESCRIPTION GROUND PINS (CONTINUED)
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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Signal Descriptions (Continued)
SIGNAL NAME NO. A8 B8 C9 D10 D21 NC G1 H1 H2 J2 K3 R2 I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground Unconnected pins ins TYPE DESCRIPTION REMAINING UNCONNECTED PINS
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development support
TI offers an extensive line of development tools for the TMS320C6000t DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000t DSP-based applications: Software Development Tools: Code Composer Studiot Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDSTM) Emulator (supports C6000t DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320t DSP family member devices, including documentation. See this document for further information on TMS320t DSP documentation or any TMS320t DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320t DSP-related products from other companies in the industry. To receive TMS320t DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000t DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and under "Development Tools", select "Digital Signal Processors". For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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device and development-support tool nomenclature To designate the stages in the product-development cycle, TI assigns prefixes to the part numbers of all TMS320TM DSP devices and support tools. Each TMS320TM DSP family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification Fully qualified production device
TMP
TMS
Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. Fully qualified development-support product
TMDS
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GJC), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -167 is 167 MHz). Table 2 identifies the available TMS320C6701 devices by their associated orderable part numbers (P/Ns) and gives device-specific ordering information (for example, device speeds, core and I/O supply voltage values, and device operating temperature ranges). Figure 4 provides a legend for reading the complete device name for any TMS320TM DSP family member. Table 2. TMS320C6701 Device P/Ns and Ordering Information
DEVICE ORDERABLE P/N TMSC6701GJC16719V TMS320C6701GJC150 TMS320C6701GJCA120 DEVICE SPEED 167 MHz/1 GFLOPS 150 MHz/900 MFLOPS 120 MHz/720 MFLOPS CVDD (CORE VOLTAGE) 1.9 V 1.8 V 1.8 V DVDD (I/O VOLTAGE) 3.3 V 3.3 V 3.3 V OPERATING CASE TEMPERATURE RANGE 0_C to 90_C 0_C to 90_C -40_C to 105_C
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device and development-support tool nomenclature (continued)
TMS 320 PREFIX TMX = TMP = TMS = SMJ = SM = Experimental device Prototype device Qualified device MIL-PRF-38535 (QML) Commercial processing C 6701 GJC (A) 167 DEVICE SPEED RANGE 100 MHz 200 MHz 120 MHz 233 MHz 150 MHz 250 MHz 167 MHz 300 MHz
DEVICE FAMILY 320 = TMS320TM DSP family
TEMPERATURE RANGE (DEFAULT: 0C TO 90C) Blank = 0C to 90C, commercial temperature A = -40C to 105C, extended temperature PACKAGE TYPE N = Plastic DIP J = Ceramic DIP JD = Ceramic DIP side-brazed GB = Ceramic PGA FZ = Ceramic CC FN = Plastic leaded CC FD = Ceramic leadless CC PJ = 100-pin plastic EIAJ QFP PQ = 132-pin plastic bumpered QFP PZ = 100-pin plastic TQFP PBK = 128-pin plastic TQFP PGE = 144-pin plastic TQFP GFN = 256-pin plastic BGA GGU = 144-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA GLW = 340-pin plastic BGA GHK = 288-pin plastic MicroStar BGAt DEVICE '1x DSP: 10 14 15 '2x DSP: 25 26 '2xx DSP: 203 204 '3x DSP: 30 31 32 '4x DSP: 40 44 '5x DSP: 50 51 52 53 56 57 545 546 548 6205 6211 6701 6711 206 209 240 16 17
TECHNOLOGY C = CMOS E = CMOS EPROM F = CMOS Flash EEPROM
DIP PGA CC QFP TQFP BGA
= = = = = =
Dual-In-Line Package Pin Grid Array Chip Carrier Quad Flat Package Thin Quad Flat Package Ball Grid Array
'54x DSP: 541 542 543 '6x DSP: 6201 6202 6202B 6203 6204
Figure 4. TMS320TM DSP Device Nomenclature (Including TMS320C6701)
MicroStar BGA is a trademark of Texas Instruments.
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documentation support
Extensive documentation supports all TMS320TM DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices; technical briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the 'C6x devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000TM DSP CPU architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on 'C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the 'C62x/C67x devices, associated development tools, and third-party support. The tools support documentation is electronically available within the Code Composer StudioTM Integrated Development Environment (IDE). For a complete listing of C6000TM DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
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clock PLL
All of the internal 'C67x clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3, Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. To minimize the clock jitter, a single clean power supply should power both the 'C67x device and the external clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Table 3. CLKOUT1 Frequency Ranges
PLLFREQ3 (A9) 0 0 0 PLLFREQ2 (D11) 0 0 1 PLLFREQ1 (B10) 0 1 0 CLKOUT1 Frequency Range (MHz) 50-140 65-167 130-167
Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, choose PLLFREQ value of 000b. For CLKOUT1 = 167 MHz, choose PLLFREQ value of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved.
Table 4. 'C6701 PLL Component Selection Table
CLKIN RANGE (MHz) CPU CLOCK FREQUENCY (CLKOUT1) RANGE (MHz) CLKOUT2 RANGE (MHz) R1 () C1 (nF) C2 (pF) TYPICAL LOCK TIME (s)
CLKMODE
x4 12.5-41.7 50-167 25-83.5 60.4 27 560 75 Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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clock PLL (continued)
PLLFREQ3 PLLFREQ2 PLLFREQ1 PLLV EMI Filter CLKMODE0 CLKMODE1 (see Table 3)
3.3V
PLL
PLLMULT PLLCLK
Internal to 'C6701
C3 10 mF
C4 0.1 mF
CLKIN
CLKIN LOOP FILTER
1 0
CPU CLOCK
Available Multiply Factors CLKMODE1 0 0 1 1 CLKMODE0 0 1 0 1 PLL Multiply Factors x1(BYPASS) Reserved Reserved x4 CPU Clock Frequency f(CPUCLOCK) 1 x f(CLKIN) Reserved Reserved 4 x f(CLKIN)
C2 C1
R1
NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000TM DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode
3.3V PLLV CLKMODE0 CLKMODE1
PLLFREQ3 PLLFREQ2 PLLFREQ1
PLLG
PLLF
(see Table 3)
Internal to 'C6701 PLLMULT
PLL
PLLCLK
CLKIN
CLKIN LOOP FILTER
1 0
CPU CLOCK
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal. B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only
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PLLG
PLLF
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absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Operating case temperature range, TC (Default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C (A Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40_C to 105_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55_C to 150_C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN CVDD DVDD VSS VIH VIL IOH IOL TC Supply voltage Core voltage, Supply voltage, I/O Supply ground High-level input voltage Low-level input voltage High-level output current Low-level output current Default Case temperature 0 '6701-120, -150 '6701-167 only 1.71 1.81 3.14 0 2.0 0.8 -12 12 90 NOM 1.8 1.9 3.30 0 MAX 1.89 1.99 3.46 0 UNIT V V V V V V mA mA _C
A Version -40 105 _C TI DSP's do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to these conditions can adversely affect the long term reliability of the device. System-level concerns such as bus contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. For additional power supply sequencing information, see the Power Supply Sequencing Solutions For Dual Supply Voltage DSPs application report (literature number SLVA073).
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)
PARAMETER VOH VOL II IOZ IDD2V IDD2V IDD3V Ci High-level output voltage Low-level output voltage Input current Off-state output current Supply current CPU + CPU memory access current, Supply current peripherals current, Supply current I/O pins current, Input capacitance TEST CONDITIONS DVDD = MIN, DVDD = MIN, VI = VSS to DVDD VO = DVDD or 0 V CVDD = NOM, CPU clock = 150 MHz CVDD = NOM, CPU clock = 120 MHz CVDD = NOM, CPU clock = 150 MHz CVDD = NOM, CPU clock = 120 MHz DVDD = NOM, CPU clock = 150 MHz DVDD = NOM, CPU clock = 120 MHz 470 380 250 200 85 70 10 mA pF mA mA IOH = MAX IOL = MAX MIN 2.4 0.6 10 10 TYP MAX UNIT V V uA uA
Co Output capacitance 10 pF TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown. Measured with average activity (50% high / 50% low power). For more detailed information on CPU/peripheral/I/O activity, see the TMS320C6000 Power Consumption Summary application report (literature number SPRA486).
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PARAMETER MEASUREMENT INFORMATION
IOL Tester Pin Electronics 50 Output Under Test
Vref
CT = 30 pF IOH Typical distributed load circuit capacitance.
signal-transition levels
All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.
Vref = 1.5 V
Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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INPUT AND OUTPUT CLOCKS timing requirements for CLKIN ('C6701-150, -167 devices only) (see Figure 8)
'C6701-150 NO. 1 2 3 tc(CLKIN) tw(CLKINH) tw(CLKINL) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN low CLKMODE = x4 MIN 26.7 0.4C 0.4C MAX CLKMODE = x1 MIN 6.7 0.45C 0.45C MAX MIN 24 0.4C 0.4C 5 'C6701-167 CLKMODE = x4 MAX CLKMODE = x1 MIN 6 0.45C 0.45C 0.6 MAX ns ns ns ns UNIT
4 tt(CLKIN) Transition time, CLKIN 5 0.6 The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.
timing requirements for CLKIN ('C6701-120 device only) (see Figure 8)
'C6701-120 NO. 1 2 3 4 tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN low Transition time, CLKIN CLKMODE = x4 MIN 33.3 0.4C 0.4C 5 MAX CLKMODE = x1 MIN 8.3 0.45C 0.45C 0.6 MAX ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.
1 2 CLKIN 3
4
4
Figure 8. CLKIN Timings
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INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT1 (see Figure 9)
'C6701-120 'C6701-150 'C6701-167 CLKMODE = x4 MIN 1 2 3 tc(CKO1) tw(CKO1H) tw(CKO1L) tt(CKO1) Cycle time, CLKOUT1 Pulse duration, CLKOUT1 high Pulse duration, CLKOUT1 low P - 0.7 (P/2) - 0.5 (P/2) - 0.5 MAX P + 0.7 (P/2) + 0.5 (P/2) + 0.5 0.6 CLKMODE = x1 MIN P - 0.7 PH - 0.5 PL - 0.5 MAX P + 0.7 PH + 0.5 PL + 0.5 0.6 ns ns ns ns
NO.
PARAMETER
UNIT
4 Transition time, CLKOUT1 P = 1/CPU clock frequency in nanoseconds (ns). PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
1 2 CLKOUT1 3
4
4
Figure 9. CLKOUT1 Timings
switching characteristics for CLKOUT2 (see Figure 10)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 1 2 3 4 tc(CKO2) tw(CKO2H) tw(CKO2L) tt(CKO2) Cycle time, CLKOUT2 Pulse duration, CLKOUT2 high Pulse duration, CLKOUT2 low Transition time, CLKOUT2 2P - 0.7 P - 0.7 P - 0.7 MAX 2P + 0.7 P + 0.7 P + 0.7 0.6 ns ns ns ns UNIT
P = 1/CPU clock frequency in ns. 1 2 CLKOUT2 3 4
4
Figure 10. CLKOUT2 Timings
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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INPUT AND OUTPUT CLOCKS (CONTINUED) SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters. SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK configuration.
switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1 (see Figure 11)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 1 2 3 4 td(CKO1-SSCLK) td(CKO1-SSCLK1/2) td(CKO1-CKO2) td(CKO1-SDCLK) CLKOUT1 1 SSCLK 2 SSCLK (1/2rate) 3 CLKOUT2 4 SDCLK Delay time, CLKOUT1 edge to SSCLK edge Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) Delay time, CLKOUT1 edge to CLKOUT2 edge Delay time, CLKOUT1 edge to SDCLK edge -0.8 -1.0 -1.5 -1.5 MAX 3.4 3.0 2.5 1.9 ns ns ns ns UNIT
Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
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ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles (see Figure 12 and Figure 13)
NO. 'C6701-120 'C6701-150 'C6701-167 MIN 6 7 10 11 tsu(EDV-CKO1H) th(CKO1H-EDV) tsu(ARDY-CKO1H) th(CKO1H-ARDY) Setup time, read EDx valid before CLKOUT1 high Hold time, read EDx valid after CLKOUT1 high Setup time, ARDY valid before CLKOUT1 high Hold time, ARDY valid after CLKOUT1 high 4.5 1.5 3.5 1.5 MAX ns ns ns UNIT
ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
switching characteristics for asynchronous memory cycles (see Figure 12 and Figure 13)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 1 2 3 4 5 8 9 12 13 td(CKO1H-CEV) td(CKO1H-BEV) td(CKO1H-BEIV) td(CKO1H-EAV) td(CKO1H-EAIV) td(CKO1H-AOEV) td(CKO1H-AREV) td(CKO1H-EDV) td(CKO1H-EDIV) td(CKO1H-AWEV) Delay time, CLKOUT1 high to CEx valid Delay time, CLKOUT1 high to BEx valid Delay time, CLKOUT1 high to BEx invalid Delay time, CLKOUT1 high to EAx valid Delay time, CLKOUT1 high to EAx invalid Delay time, CLKOUT1 high to AOE valid Delay time, CLKOUT1 high to ARE valid Delay time, CLKOUT1 high to EDx valid Delay time, CLKOUT1 high to EDx invalid -1.0 -1.0 4.5 -1.0 -1.0 -0.5 4.5 4.5 4.5 -1.0 4.5 -1.0 MAX 4.5 4.5 ns ns ns ns ns ns ns ns ns ns UNIT
14 Delay time, CLKOUT1 high to AWE valid The minimum delay is also the minimum output hold after CLKOUT1 high.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 CLKOUT1 1 CEx 2 BE[3:0] 4 EA[21:2]
Strobe = 5
Not ready = 2
HOLD = 1
1
3
5 7
6 ED[31:0] 8 AOE 9 ARE AWE 11 10 ARDY 10 11 9 8
Figure 12. Asynchronous Memory Read Timing
Setup = 2 CLKOUT1 1 CEx 2 BE[3:0] 4 EA[21:2] 12
Strobe = 5
Not ready = 2 HOLD = 1
1
3
5
13 ED[31:0] AOE ARE 14 AWE 11 10 ARDY 10 11 14
Figure 13. Asynchronous Memory Write Timing
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 14)
NO. 7 8 tsu(EDV-SSCLKH) th(SSCLKH-EDV) Setup time, read EDx valid before SSCLK high Hold time, read EDx valid after SSCLK high 'C6701-120 MIN 2.0 2.9 MAX 'C6701-150 'C6701-167 MIN 2.0 2.1 MAX ns ns UNIT
switching characteristics for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 14 and Figure 15)
NO. 1 2 3 4 5 6 9 10 11 12 13 14 15 tosu(CEV-SSCLKH) toh(SSCLKH-CEV) tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) tosu(OEV-SSCLKH) toh(SSCLKH-OEV) tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) tosu(WEV-SSCLKH) PARAMETER Output setup time, CEx valid before SSCLK high Output hold time, CEx valid after SSCLK high Output setup time, BEx valid before SSCLK high Output hold time, BEx invalid after SSCLK high Output setup time, EAx valid before SSCLK high Output hold time, EAx invalid after SSCLK high Output setup time, SSADS valid before SSCLK high Output hold time, SSADS valid after SSCLK high Output setup time, SSOE valid before SSCLK high Output hold time, SSOE valid after SSCLK high Output setup time, EDx valid before SSCLK high Output hold time, EDx invalid after SSCLK high Output setup time, SSWE valid before SSCLK high 'C6701-120 MIN 0.5P - 1.3 0.5P - 2.9 0.5P - 1.3 0.5P - 2.9 0.5P - 1.3 0.5P - 2.9 0.5P - 1.3 0.5P - 2.9 0.5P - 1.3 0.5P - 2.9 0.5P - 1.3 0.5P - 2.9 0.5P - 1.3 MAX 'C6701-150 'C6701-167 MIN 0.5P - 1.3 0.5P - 2.3 0.5P - 1.6 0.5P - 2.3 0.5P - 1.7 0.5P - 2.3 0.5P - 1.3 0.5P - 2.3 0.5P - 1.3 0.5P - 2.3 0.5P - 1.3 0.5P - 2.3 0.5P - 1.3 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P - 2.9 0.5P - 2.3 ns When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for all output hold times.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
SSCLK 1 CEx 3 BE[3:0] 5 EA[21:2] A1 A2 7 ED[31:0] 9 SSADS 11 SSOE SSWE 12 Q1 Q2 10 Q3 Q4 A3 8 BE1 BE2 BE3 4 BE4 6 A4 2
Figure 14. SBSRAM Read Timing (Full-Rate SSCLK)
SSCLK 1 CEx 3 BE[3:0] 5 EA[21:2] A1 A2 13 ED[31:0] D1 9 SSADS SSOE 15 SSWE 16 D2 D3 14 D4 10 A3 BE1 BE2 BE3 4 BE4 6 A4 2
Figure 15. SBSRAM Write Timing (Full-Rate SSCLK)
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16)
'C6701-120 'C6701-150 'C6701-167 MIN 7 8 tsu(EDV-SSCLKH) th(SSCLKH-EDV) Setup time, read EDx valid before SSCLK high Hold time, read EDx valid after SSCLK high 3.6 1.5 MAX ns ns
NO.
UNIT
switching characteristics for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16 and Figure 17)
NO. 1 2 3 4 5 6 9 10 11 12 13 14 15 tosu(CEV-SSCLKH) toh(SSCLKH-CEV) tosu(BEV-SSCLKH) toh(SSCLKH-BEIV) tosu(EAV-SSCLKH) toh(SSCLKH-EAIV) tosu(ADSV-SSCLKH) toh(SSCLKH-ADSV) tosu(OEV-SSCLKH) toh(SSCLKH-OEV) tosu(EDV-SSCLKH) toh(SSCLKH-EDIV) tosu(WEV-SSCLKH) PARAMETER Output setup time, CEx valid before SSCLK high Output hold time, CEx valid after SSCLK high Output setup time, BEx valid before SSCLK high Output hold time, BEx invalid after SSCLK high Output setup time, EAx valid before SSCLK high Output hold time, EAx invalid after SSCLK high Output setup time, SSADS valid before SSCLK high Output hold time, SSADS valid after SSCLK high Output setup time, SSOE valid before SSCLK high Output hold time, SSOE valid after SSCLK high Output setup time, EDx valid before SSCLK high Output hold time, EDx invalid after SSCLK high Output setup time, SSWE valid before SSCLK high 'C6701-120 MIN 1.5P - 4.5 0.5P - 2.5 1.5P - 4.5 0.5P - 2.5 1.5P - 4.5 0.5P - 2.5 1.5P - 4.5 0.5P - 2.5 1.5P - 4.5 0.5P - 2.5 1.5P - 4.5 0.5P - 2.5 1.5P - 4.5 MAX 'C6701-150 'C6701-167 MIN 1.5P - 4.5 0.5P - 2 1.5P - 4.5 0.5P - 2 1.5P - 4.5 0.5P - 2 1.5P - 4.5 0.5P - 2 1.5P - 4.5 0.5P - 2 1.5P - 4.5 0.5P - 2 1.5P - 4.5 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
16 toh(SSCLKH-WEV) Output hold time, SSWE valid after SSCLK high 0.5P - 2.5 0.5P - 2 ns When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
SSCLK 1 CEx BE[3:0] 3 BE1 5 A1 4 BE2 BE3 BE4 6 A2 A3 7 ED[31:0] 9 SSADS 11 SSOE SSWE 12 Q1 A4 8 Q2 2
EA[21:2]
Q3 10
Q4
Figure 16. SBSRAM Read Timing (1/2 Rate SSCLK)
SSCLK 1 CEx BE[3:0] 3 BE1 5 A1 4 BE2 BE3 BE4 6 A2 13 ED[31:0] Q1 9 SSADS SSOE 15 SSWE 16 Q2 Q3 Q4 10 A3 A4 14 2
EA[21:2]
Figure 17. SBSRAM Write Timing (1/2 Rate SSCLK)
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37
TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 18)
NO. 'C6701-120 'C6701-150 'C6701-167 MIN 7 8 tsu(EDV-SDCLKH) th(SDCLKH-EDV) Setup time, read EDx valid before SDCLK high Hold time, read EDx valid after SDCLK high 1.8 3 MAX ns ns UNIT
switching characteristics for synchronous DRAM cycles (see Figure 18-Figure 23)
NO. 1 2 3 4 5 6 9 10 11 12 13 14 15 16 17 tosu(CEV-SDCLKH) toh(SDCLKH-CEV) tosu(BEV-SDCLKH) toh(SDCLKH-BEIV) tosu(EAV-SDCLKH) toh(SDCLKH-EAIV) tosu(SDCAS-SDCLKH) toh(SDCLKH-SDCAS) tosu(EDV-SDCLKH) toh(SDCLKH-EDIV) tosu(SDWE-SDCLKH) toh(SDCLKH-SDWE) tosu(SDA10V-SDCLKH) toh(SDCLKH-SDA10IV) tosu(SDRAS-SDCLKH) PARAMETER Output setup time, CEx valid before SDCLK high Output hold time, CEx valid after SDCLK high Output setup time, BEx valid before SDCLK high Output hold time, BEx invalid after SDCLK high Output setup time, EAx valid before SDCLK high Output hold time, EAx invalid after SDCLK high Output setup time, SDCAS valid before SDCLK high Output hold time, SDCAS valid after SDCLK high Output setup time, EDx valid before SDCLK high Output hold time, EDx invalid after SDCLK high Output setup time, SDWE valid before SDCLK high Output hold time, SDWE valid after SDCLK high Output setup time, SDA10 valid before SDCLK high Output hold time, SDA10 invalid after SDCLK high Output setup time, SDRAS valid before SDCLK high 'C6701-120 MIN 1.5P - 4 0.5P - 1.9 1.5P - 4 0.5P - 1.9 1.5P - 4 0.5P - 1.9 1.5P - 4 0.5P - 1.9 1.5P - 4 0.5P - 1.9 1.5P - 4 0.5P - 1.9 1.5P - 4 0.5P - 1.9 1.5P - 4 MAX 'C6701-150 'C6701-167 MIN 1.5P - 4 0.5P - 1.5 1.5P - 4 0.5P - 1.5 1.5P - 4 0.5P - 1.5 1.5P - 4 0.5P - 1.5 1.5P - 4 0.5P - 1.5 1.5P - 4 0.5P - 1.5 1.5P - 4 0.5P - 1.5 1.5P - 4 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
18 toh(SDCLKH-SDRAS) Output hold time, SDRAS valid after SDCLK high 0.5P - 1.9 0.5P - 1.5 ns When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For CLKMODE x1: 1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high. 0.5P = PL, where PL = pulse duration of CLKIN low.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ SDCLK 1 CEx 3 BE[3:0] 5 EA[15:2] CA1 6 CA2 BE1
READ
READ
2
4 BE2 BE3
CA3 7 8 D1 D2 D3
ED[31:0] 15 SDA10 SDRAS 9 SDCAS SDWE 10 16
Figure 18. Three SDRAM Read Commands
WRITE SDCLK 1 CEx 3 BE[3:0] 5 EA[15:2] CA1 11 D1 15 SDA10 SDRAS 9 SDCAS 13 SDWE BE1 6 CA2 12 D2 4 BE2
WRITE
WRITE
2
BE3
CA3
ED[31:0]
D3 16
10
14
Figure 19. Three SDRAM Write Commands
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV SDCLK 1 CEx BE[3:0] 5 Bank Activate/Row Address 2
EA[15:2] ED[31:0]
15 SDA10 17 SDRAS SDCAS SDWE Row Address 18
Figure 20. SDRAM ACTV Command
DCAB SDCLK 1 CEx BE[3:0] EA[15:2] ED[31:0] 15 SDA10 17 SDRAS SDCAS 13 SDWE 14 18 16 2
Figure 21. SDRAM DCAB Command
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR SDCLK 1 CEx BE[3:0] EA[15:2] ED[31:0] SDA10 17 SDRAS 9 SDCAS SDWE 10 18 2
Figure 22. SDRAM REFR Command
MRS SDCLK 1 CEx BE[3:0] 5 EA[15:2] ED[31:0] SDA10 17 SDRAS 9 SDCAS 13 SDWE 14 10 18 MRS Value 6 2
Figure 23. SDRAM MRS Command
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41
TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
HOLD/HOLDA TIMING timing requirements for the hold/hold acknowledge cycles (see Figure 24)
NO. 'C6701-120 'C6701-150 'C6701-167 MIN 1 tsu(HOLDH-CKO1H) th(CKO1H-HOLDL) Setup time, HOLD high before CLKOUT1 high 5 MAX ns UNIT
2 Hold time, HOLD low after CLKOUT1 high 2 ns HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle. Thus, HOLD can be an asynchronous input.
switching characteristics for the hold/hold acknowledge cycles (see Figure 24)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 3 4 5 6 7 8 tR(HOLDL-EMHZ) tR(EMHZ-HOLDAL) tR(HOLDH-HOLDAH) td(CKO1H-HOLDAL) td(CKO1H-BHZ) td(CKO1H-BLZ) Response time, HOLD low to EMIF high impedance Response time, EMIF high impedance to HOLDA low Response time, HOLD high to HOLDA high Delay time, CLKOUT1 high to HOLDA valid Delay time, CLKOUT1 high to EMIF Bus high impedance Delay time, CLKOUT1 high to EMIF Bus low impedance Response time, HOLD high to EMIF Bus low impedance 4P 1 1 1 4P MAX 2P 7P 8 8 12 UNIT
ns ns ns ns ns ns
9 tR(HOLDH-BLZ) 3P 6P ns P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1. EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. DSP Owns Bus External Requester DSP Owns Bus
5 4 3 CLKOUT1 2 1 HOLD 6 HOLDA 7 8 EMIF Bus 'C6701 Ext Req 'C6701 EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE. 6 1 2 9
Figure 24. HOLD/HOLDA Timing
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
RESET TIMING timing requirements for reset (see Figure 25)
NO. 'C6701-120 'C6701-150 'C6701-167 MIN 1 tw(RESET) Width of the RESET pulse (PLL stable) 10 MAX CLKOUT1 cycles UNIT
Width of the RESET pulse (PLL needs to sync up) 250 s This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable. This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 s to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
switching characteristics during reset (see Figure 25)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 2 3 4 5 6 7 8 9 10 11 12 13 14 tR(RESET) td(CKO1H-CKO2IV) td(CKO1H-CKO2V) td(CKO1H-SDCLKIV) td(CKO1H-SDCLKV) td(CKO1H-SSCKIV) td(CKO1H-SSCKV) td(CKO1H-LOWIV) td(CKO1H-LOWV) td(CKO1H-HIGHIV) td(CKO1H-HIGHV) td(CKO1H-ZHZ) td(CKO1H-ZV) Response time to change of value in RESET signal Delay time, CLKOUT1 high to CLKOUT2 invalid Delay time, CLKOUT1 high to CLKOUT2 valid Delay time, CLKOUT1 high to SDCLK invalid Delay time, CLKOUT1 high to SDCLK valid Delay time, CLKOUT1 high to SSCLK invalid Delay time, CLKOUT1 high to SSCLK valid Delay time, CLKOUT1 high to low group invalid Delay time, CLKOUT1 high to low group valid Delay time, CLKOUT1 high to high group invalid Delay time, CLKOUT1 high to high group valid Delay time, CLKOUT1 high to Z group high impedance Delay time, CLKOUT1 high to Z group valid -1 10 -1 10 -1 10 -1 10 -1 10 1 -1 10 MAX CLKOUT1 cycles ns ns ns ns ns ns ns ns ns ns ns ns UNIT
Low group consists of: High group consists of: Z group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. HINT. EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
RESET TIMING (CONTINUED)
CLKOUT1 1 2 RESET 3 CLKOUT2 5 SDCLK 7 SSCLK 9 LOW GROUP 11 HIGH GROUP 13 Z GROUP Low group consists of: High group consists of: Z group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1. HINT. EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1. 14 12 10 8 6 4 2
HRDY is gated by input HCS. If HCS = 0 at device reset, HRDY belongs to the high group. If HCS = 1 at device reset, HRDY belongs to the low group.
Figure 25. Reset Timing
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles (see Figure 26)
NO. 'C6701-120 'C6701-150 'C6701-167 MIN 2 tw(ILOW) tw(IHIGH) Width of the interrupt pulse low 2P MAX ns UNIT
3 Width of the interrupt pulse high 2P ns Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can be connected to asynchronous inputs. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
switching characteristics during interrupt response cycles (see Figure 26)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 1 4 5 tR(EINTH-IACKH) td(CKO2L-IACKV) td(CKO2L-INUMV) Response time, EXT_INTx high to IACK high Delay time, CLKOUT2 low to IACK valid Delay time, CLKOUT2 low to INUMx valid -0.5P 9P -0.5P 13 - 0.5P 10 - 0.5P MAX ns ns ns ns UNIT
6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. When the PLL is used (CLKMODE x4), 0.5P = 1/(2 x CPU clock frequency). For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN. 1 CLKOUT2 2 EXT_INTx, NMI Intr Flag 4 IACK 5 INUMx Interrupt Number 3
4
6
Figure 26. Interrupt Timing
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles (see Figure 27, Figure 28, Figure 29, and Figure 30)
'C6701-120 'C6701-150 'C6701-167 MIN 1 2 3 4 10 11 12 13 14 18 tsu(SEL-HSTBL) th(HSTBL-SEL) tw(HSTBL) tw(HSTBH) tsu(SEL-HASL) th(HASL-SEL) tsu(HDV-HSTBH) th(HSTBH-HDV) th(HRDYL-HSTBL) tsu(HASL-HSTBL) th(HSTBL-HASL) Setup time, select signals valid before HSTROBE low Hold time, select signals valid after HSTROBE low Pulse duration, HSTROBE low Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals valid before HAS low Hold time, select signals valid after HAS low Setup time, host data valid before HSTROBE high Hold time, host data valid after HSTROBE high Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. Setup time, HAS low before HSTROBE low 4 2 2P 2P 4 2 3 2 1 2 2 MAX ns ns ns ns ns ns ns ns ns ns ns
NO.
UNIT
19 Hold time, HAS low after HSTROBE low HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
switching characteristics during host-port interface cycles (see Figure 27, Figure 28, Figure 29, and Figure 30)
'C6701-120 'C6701-150 'C6701-167 MIN 5 6 7 8 9 15 16 17 20 td(HCS-HRDY) td(HSTBL-HRDYH) td(HSTBL-HDLZ) td(HDV-HRDYL) toh(HSTBH-HDV) td(HSTBH-HDHZ) td(HSTBL-HDV) td(HSTBH-HRDYH) Delay time, HCS to HRDY Delay time, HSTROBE low to HRDY high# Delay time, HSTROBE low to HD low impedance for an HPI read Delay time, HD valid to HRDY low Output hold time, HD valid after HSTROBE high Delay time, HSTROBE high to HD high impedance Delay time, HSTROBE low to HD valid Delay time, HSTROBE high to HRDY high|| 1 1 4 P-3 3 3 3 1 P+3 12 12 12 12 MAX 12 12 ns ns ns ns ns ns ns ns
NO.
PARAMETER
UNIT
td(HASL-HRDYH) Delay time, HAS low to HRDY high 3 12 ns HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS 1 HCNTL[1:0] 1 HR/W 1 HHWIL HSTROBE HCS 7 HD[15:0] (output) 5 HRDY (case 1) 6 HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 8 17 5 1st half-word 8 2nd half-word 17 5 15 9 16 15 9 3 4 2 1 2 2 1 2 1 2 2
Figure 27. HPI Read Timing (HAS Not Used, Tied High)
HAS 10 HCNTL[1:0] 11 10 HR/W 11 10 HHWIL HSTROBE HCS 7 HD[15:0] (output) 5 HRDY (case 1) 20 HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 8 17 5 1st half-word 8 2nd half-word 17 5 18 15 9 16 9 3 4 18 15 10 11 10 11 19 11 10 19 11
Figure 28. HPI Read Timing (HAS Used)
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
1 2
1 2 12 13 12
HCNTL[1:0] 13 HBE[1:0] 1 HR/W 1 HHWIL 3 4 HSTROBE HCS 12 HD[15:0] (input) 5 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 1st half-word 2nd half-word 17 5 13 12 13 14 2 1 2 2 1 2
Figure 29. HPI Write Timing (HAS Not Used, Tied High)
HAS 19 HBE[1:0] 11 10 HCNTL[1:0] 11 10 HR/W 11 10 HHWIL 3 HSTROBE HCS HD[15:0] (input) 5 HRDY 1st half-word 18
12 13 12 19 13
11 10
11 10
11 10
14
4 18
12
13 2nd half-word
12
13
17
5
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 30. HPI Write Timing (HAS Used)
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP (see Figure 31)
'C6701-120 'C6701-150 'C6701-167 tc(CKRX) tw(CKRX) tsu(FRH-CKRL) th(CKRL-FRH) tsu(DRV-CKRL) th(CKRL-DRV) tsu(FXH-CKXL) th(CKXL-FXH) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Setup time external FSR high before CLKR low time, Hold time, external FSR high after CLKR low time Setup time DR valid before CLKR low time, Hold time, DR valid after CLKR low time Setup time, external FSX high before CLKX low time Hold time external FSX high after CLKX low time, CLKR/X ext CLKR/X ext CLKR int 5 6 7 8 10 11 CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext MIN 2P P - 1 13 4 7 4 10 1 4 4 13 4 7 3 ns ns ns ns ns ns MAX ns ns
NO.
UNIT
2 3
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the McBSP communicates to is a slave. The minimum CLKR/X pulse duration is either (P-1) or 9 ns, whichever is larger. For example, when running parts at 167 MHz (P = 6 ns), use 9 ns as the minimum CLKR/X pulse duration. When running parts at 80 MHz (P = 12.5 ns), use (P-1) = 11.5 ns as the minimum CLKR/X pulse duration.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP (see Figure 31)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 1 2 3 4 9 12 13 14 td(CKSH-CKRXH) tc(CKRX) tw(CKRX) td(CKRH-FRV) td(CKXH-FXV) tdis(CKXH-DXHZ) td(CKXH-DXV) td(FXH-DXV) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Delay time, CLKR high to internal FSR valid Delay time, CLKX high to internal FSX valid time Disable time, DX high impedance following last data bit from im edance CLKX high Delay time CLKX high to DX valid. time, valid Delay time, FSX high to DX valid. ONLY applies when in data delay 0 (XDATDLY = 00b) mode. CLKR/X int CLKR/X int CLKR int CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext 3 2P C - 1# -4 -4 3 -3 2 -2 3 -2 2 MAX 15 ns ns C + 1# 4 5 16 2 9 4 16 4 10 ns ns ns ns ns ns UNIT
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz), whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 50 MHz limit.
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS 1 3 3 CLKR 4 FSR (int) 5 FSR (ext) 7 DR 2 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) 3 Bit(n-1) 8 (n-2) (n-3) 6 4 2
Figure 31. McBSP Timings
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51
TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 32)
NO. 'C6701-120 'C6701-150 'C6701-167 MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) Setup time, FSR high before CLKS high Hold time, FSR high after CLKS high 4 4 MAX ns ns UNIT
CLKS 1 FSR external CLKR/X (no need to resync) CLKR/X(needs resync) 2
Figure 32. FSR Timing When GSYNC = 1
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 33)
'C6701-120 'C6701-150 'C6701-167 MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low 12 4 MAX SLAVE MIN 2 - 3P 5 + 6P MAX ns ns
NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 33)
'C6701-120 'C6701-150 'C6701-167 MASTER SLAVE MIN 1 2 3 6 7 th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX low Disable time, DX high impedance following last data bit from FSX high T-4 L-4 -4 L-2 MAX T+4 L+4 4 L+3 P+4 3P + 17 3P + 1 5P + 17 MIN MAX ns ns ns ns ns
NO.
PARAMETER
UNIT
8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 3 Bit(n-1) 5 (n-2) (n-3) (n-4) (n-2) (n-3) (n-4) 2
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 34)
'C6701-120 'C6701-150 'C6701-167 MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 3P 5 + 6P MAX ns ns
NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 34)
'C6701-120 'C6701-150 'C6701-167 MASTER SLAVE MIN 1 2 3 6 th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) tdis(CKXL-DXHZ) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX low L-4 T-4 -4 -2 MAX L+4 T+4 4 4 3P + 1 3P + 4 5P + 17 5P + 17 MIN MAX ns ns ns ns
NO.
PARAMETER
UNIT
7 td(FXL-DXV) Delay time, FSX low to DX valid H-2 H+3 2P + 1 4P + 13 ns P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
CLKX 1 FSX 6 Bit 0 7 Bit(n-1) 4 DR Bit 0 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
DX
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 35)
'C6701-120 'C6701-150 'C6701-167 MASTER MIN 4 5 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high Hold time, DR valid after CLKX high 12 4 MAX SLAVE MIN 2 - 3P 5 + 6P MAX ns ns
NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 35)
'C6701-120 'C6701-150 'C6701-167 MASTER SLAVE MIN 1 2 3 6 7 th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ) tdis(FXH-DXHZ) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX high Disable time, DX high impedance following last data bit from FSX high T-4 H-4 -4 H-2 MAX T+4 H+4 4 H+3 P+4 3P + 17 3P + 1 5P + 17 MIN MAX ns ns ns ns ns
NO.
PARAMETER
UNIT
8 td(FXL-DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
56
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 Bit(n-1) 5 (n-2) (n-3) (n-4) 3 (n-2) (n-3) (n-4) 2
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 36)
'C6701-120 'C6701-150 'C6701-167 MASTER MIN 4 5 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low Hold time, DR valid after CLKX low 12 4 MAX SLAVE MIN 2 - 3P 5 + 6P MAX ns ns
NO.
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 36)
'C6701-120 'C6701-150 'C6701-167 MASTER SLAVE MIN 1 2 3 6 th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX high H-4 T-4 -4 -2 MAX H+4 T+4 4 4 3P + 1 3P + 4 5P + 17 5P + 17 MIN MAX ns ns ns ns
NO.
PARAMETER
UNIT
7 td(FXL-DXV) Delay time, FSX low to DX valid L-2 L+3 2P + 1 4P + 13 ns P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
58
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX 1 FSX 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 7 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
DMAC, TIMER, POWER-DOWN TIMING switching characteristics for DMAC outputs (see Figure 37)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 1 td(CKO1H-DMACV) CLKOUT1 1 DMAC[0:3] 1 Delay time, CLKOUT1 high to DMAC valid 2 MAX 11 ns UNIT
Figure 37. DMAC Timing
timing requirements for timer inputs (see Figure 38)
NO. 'C6701-120 'C6701-150 'C6701-167 MIN tw(TINPH) Pulse duration, TINP high P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns. 1 2P MAX ns UNIT
switching characteristics for timer outputs (see Figure 38)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 2 td(CKO1H-TOUTV) CLKOUT1 1 TINP 2 TOUT 2 Delay time, CLKOUT1 high to TOUT valid 1 MAX 10 ns UNIT
Figure 38. Timer Timing
60
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics for power-down outputs (see Figure 39)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 1 td(CKO1H-PDV) CLKOUT1 1 PD 1 Delay time, CLKOUT1 high to PD valid 1 MAX 9 ns UNIT
Figure 39. Power-Down Timing
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 40)
NO. 'C6701-120 'C6701-150 'C6701-167 MIN 1 3 4 tc(TCK) tsu(TDIV-TCKH) th(TCKH-TDIV) Cycle time, TCK Setup time, TDI/TMS/TRST valid before TCK high Hold time, TDI/TMS/TRST valid after TCK high 35 10 9 MAX ns ns ns UNIT
switching characteristics for JTAG test port (see Figure 40)
NO. PARAMETER 'C6701-120 'C6701-150 'C6701-167 MIN 2 td(TCKL-TDOV) Delay time, TCK low to TDO valid -3 MAX 12 ns UNIT
1 TCK 2 TDO 4 3 TDI/TMS/TRST 2
Figure 40. JTAG Test-Port Timing
62
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TMS320C6701 FLOATING POINT DIGITAL SIGNAL PROCESSOR
SPRS067E - MAY 1998 - REVISED MAY 2000
MECHANICAL DATA
GJC (S-PBGA-N352) PLASTIC BALL GRID ARRAY
35,20 SQ 34,80 33,20 SQ 32,80 21,00 NOM 1,27
31,75 TYP
0,635
AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 13 15 17 19 21 23 25 12 14 16 18 20 22 24 26
21,00 NOM
Heat Slug
See Note E 3,50 MAX
1,00 NOM
Seating Plane 0,90 0,60 NOTES: A. B. C. D. E. F. 0,10 M 0,15 4173506-2/D 07/99
0,50 MIN
All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL). Flip chip application only Possible protrusion in this area, but within 3,50 max package height specification Falls within JEDEC MO-151/BAR-2 C/W Air Flow LFPM N/A 0 100 250 500
thermal resistance characteristics (S-PBGA package)
NO 1 2 3 4 RJC RJA RJA RJA Junction-to-case Junction-to-free air Junction-to-free air Junction-to-free air 0.74 11.31 9.60 8.34 7.30
5 RJA Junction-to-free air LFPM = Linear Feet Per Minute
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0,635 63
1,27
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Copyright (c) 2000, Texas Instruments Incorporated

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