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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
D Low-Cost, High-Performance Fixed-Point
DSP - TMS320C6411 - 3.3-ns Instruction Cycle Time - 300-MHz Clock Rate - Eight 32-Bit Instructions/Cycle - Twenty-Eight Operations/Cycle - 2400 MIPS - Fully Software-Compatible With TMS320C62x VelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core - Eight Highly Independent Functional Units With VelociTI.2 Extensions: - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle - Non-Aligned Load-Store Architecture - 64 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Byte-Addressable (8-/16-/32-/64-Bit Data) - 8-Bit Overflow Protection - Bit-Field Extract, Set, Clear - Normalization, Saturation, Bit-Counting - VelociTI.2 Increased Orthogonality L1/L2 Memory Architecture - 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) - 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) - 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) 32-Bit External Memory Interface (EMIF) - Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO) - 512M-Byte Total Addressable External Memory Space
D Enhanced Direct-Memory-Access (EDMA) D D
Controller (64 Independent Channels) Host-Port Interface (HPI) - User-Configurable Bus Width (32-/16-Bit) - Access to Entire Memory Map 32-Bit/33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2 - Access to Entire Memory Map - Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O - Four-Wire Serial EEPROM Interface - PCI Interrupt Request Under DSP Program Control - DSP Interrupt Via PCI I/O Cycle Two Multichannel Buffered Serial Ports (McBSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching Compatible - Up to 256 Channels Each - AC97-Compatible - Serial Peripheral Interface (SPI) Compatible (Motorola) Three 32-Bit General-Purpose Timers Sixteen General-Purpose I/O (GPIO) Pins - Programmable Interrupt/Event Generation Modes Flexible PLL Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 532-Pin Ball Grid Array (BGA) Package (GLZ Suffix), 0.8-mm Ball Pitch 0.12-m/6-Level Metal Process - CMOS Technology 3.3-V I/Os, 1-V Internal
D
D
D
D D D D D D D
D
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright 2002, Texas Instruments Incorporated
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PRODUCT PREVIEW
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
Table of Contents
GLZ BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . . 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional block and CPU (DSP core) diagram . . . . . . . . . . . 6 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 7 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 11 EDMA channel synchronization event . . . . . . . . . . . . . . . . . 22 interrupt sources and interrupt selector . . . . . . . . . . . . . . . . 23 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 recommended operating conditions . . . . . . . . . . . . . . . . 58 electrical characteristics over recommended ranges of supply voltage and operating case temperature . 59 parameter measurement information . . . . . . . . . . . . . . . 60 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 66 programmable synchronous interface timing . . . . . . . . 69 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 73 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 84 host-port interface (HPI) timing . . . . . . . . . . . . . . . . . . . . 85 peripheral component interconnect (PCI) timing . . . . . . 90 multichannel buffered serial port (McBSP) timing . . . . . 93 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 general-purpose input/output (GPIO) port timing . . . . 105 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
PRODUCT PREVIEW
GLZ BGA package (bottom view)
GLZ 532-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW )
AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
description
The TMS320C64x DSPs (including the TMS320C6411 device) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C6411 (C6411) device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelocTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x is a code-compatible member of the C6000 DSP platform. With performance of up to 2400 million instructions per second (MIPS) at a clock rate of 300 MHz, the C6411 device offers cost-effective solutions to high-performance DSP programming challenges. The C6411 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs)-- with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C6411 can produce two 32-bit multiply-accumulates (MACs) per cycle for a total of 600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 2400 MMACS. The C6411 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices.
The C6411 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. Other trademarks are the property of their respective owners.
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PRODUCT PREVIEW
The C6411 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a general-purpose input/output port (GPIO) with 16 GPIO pins; and a glueless external memory interface (32-bit EMIF), which is capable of interfacing to synchronous and asynchronous memories and peripherals.
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
device characteristics
Table 1 provides an overview of the C6411 DSP. The table shows significant features of the C6411 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 1. Characteristics of the C6411 Processor
HARDWARE FEATURES EMIF (32-bit bus width) EDMA (64 independent channels) HPI (32- or 16-bit user selectable) Peripherals PCI (32-bit) McBSPs (McBSP0 and McBSP1) 32-Bit Timers General-Purpose Input/Outputs (GPIOs) Size (Bytes) On-Chip Memory Organization Control Status Register (CSR.[31:16]) MHz ns Core (V) Voltage PLL Options BGA Package Process Technology Product Status I/O (V) CLKIN frequency multiplier 23 x 23 mm m Product Preview (PP) Advance Information (AI) Production Data (PD) (For more details on the C6000 DSP part numbering, see Figure 4) C6411 1 1 1 (HPI16 or HPI32) 1 2 3 16 288K 16K-Byte (16KB) L1 Program (L1P) Cache 16KB L1 Data (L1D) Cache 256KB Unified Mapped RAM/Cache (L2) 0x0C01 300 3.3 ns (C6411-300) 1 V (-300) 3.3 V Bypass (x1), x6 532-Pin BGA (GLZ) 0.12 m PP
PRODUCT PREVIEW
CPU ID + CPU Rev ID Frequency Cycle Time
Device Part Numbers
TMX320C6411GLZ
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
device compatibility
The C64x family of devices has a diverse and powerful set of peripherals. The common peripheral set that the C6411, C6414, C6415, and C6416 devices offer lead to easier system designs and faster time to market. Table 2 identifies the peripherals and coprocessors that are available on the C6414, C6415, and C6416 devices. The C6411 device is a low-cost C64x device which features significant enhancements from the C6211/C6211B devices and can be considered a subset of the C6415 device. Table 2 identifies the C6411 features in comparison with the C6211 and C6415 devices. Table 2. C6211, C6411, and C6415 Device Comparison
CPU/PERIPHERALS DSP Core L1P (Program Cache) L1D (Data Cache) L2 (Unified Mapped RAM/Cache) C6211/C6211B C62x 4 KB 4 KB 64 KB C6411 C64x 16 KB 16 KB 256 KB (1) 32-Bit programmable synchronous mode 64 32-/16-Bit 32-Bit, 33 MHz 2 Enhanced -- 3 (No TIMER2 pins) 16 300-MHz 1V x1, x6 532-pin BGA 23 x 23 mm GLZ suffix 0.12 m C6415 C64x 16 KB 16 KB 1024 KB (1) 64-Bit(1) [EMIFA] (1) 16-Bit [EMIFB] programmable synchronous mode 64 32-/16-Bit 32-Bit, 33 MHz 3 Enhanced (1) Transmit (1) Receive 3 16 400-, 500-, 600-MHz 1.2 V to 1.4 V x1, x6, x12 532-pin BGA 23 x 23 mm GLZ suffix 0.12 m
EMIF (64-, 32-, 16-bit bus width)
(1) 32-Bit
EDMA (# of independent channels) HPI (32- or 16-bit user selectable) PCI (32-bit) McBSPs (McBSP0, McBSP1, and McBSP2) UTOPIA Timers (32-bit) [TIMER0, TIMER1, TIMER2] GPIOs (GP[15:0]) Core Frequency (MHz) Core Voltage (V) PLL Modes (x1 [Bypass], x4, x6, x12) Package
16 16-Bit -- 2 -- 2 -- 150-, 167-MHz 1.8 V x1, x4 256-pin BGA 27 x 27 mm GFN suffix
Process Technology 0.18 m -- denotes peripheral/coprocessor is not available on this device.
For more detailed information on the device compatibility and similarities/differences among the C6211, C6411, C6414, C6415, and C6416 devices, see the How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718) and How To Begin Development Today With the TMS320C6411 DSP application report (literature number SPRA374).
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PRODUCT PREVIEW
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
functional block and CPU (DSP core) diagram
SDRAM SBSRAM ZBT SRAM FIFO SRAM ROM/FLASH I/O Devices Instruction Dispatch Advanced Instruction Packet Timer 2 Instruction Decode Data Path A Timer 1 A Register File A31-A16 A15-A0 Data Path B B Register File B31-B16 B15-B0 C64x DSP Core Instruction Fetch Control Registers Control Logic Test Advanced In-Circuit Emulation Interrupt Control
32
C6411 Digital Signal Processor
L1P Cache Direct-Mapped 16K Bytes Total
EMIF
Timer 0
PRODUCT PREVIEW
.L1 Enhanced DMA Controller (64-channel) L2 Memory 256K Bytes
.S1
.M1 .D1
.D2 .M2 .S2
.L2
McBSP1 McBSPs: Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs
McBSP0
L1D Cache 2-Way Set-Associative 16K Bytes Total
9 7
GPIO[8:0] GPIO[15:9]
32
HPI
or
32
Boot Configuration PLL (x1, x6) Power-Down Logic
PCI
Interrupt Selector
The PCI peripheral is muxed with the HPI peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet. Timer2 exists internally and is not pinned out externally.
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
CPU (DSP core) description
The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP VelociTI architecture. These enhancements include:
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the C64x register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram, and Figure 1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a "data cross path"--a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All functional units in the C64x CPU can access operands via the data cross path. Register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that register was updated in the previous clock cycle. In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU to operate directly on packed data to streamline data flow and increase instruction set efficiency. Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to hold the condition for conditional instructions (if the condition is not automatically "true").
TMS320C62x is a trademark of Texas Instruments.
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PRODUCT PREVIEW
D D D D D D
Register file enhancements Data path extensions Quad 8-bit and dual 16-bit extensions with data flow enhancements Additional functional unit hardware Increased orthogonality of the instruction set Additional instructions that reduce code size and increase register flexibility
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
CPU (DSP core) description (continued)
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two 16 x 16-bit multiplies or four 8 x 8-bit multiplies per clock cycle. The .M unit can also perform 16 x 32-bit multiply operations, dual 16 x 16-bit multiplies with add/subtract operations, and quad 8 x 8-bit multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies, and bidirectional variable shift hardware. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual 16-bit, and quad 8-bit operations. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable. For more details on the C64x CPU functional units enhancements, see the following documents: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) TMS320C64x Technical Overview (literature number SPRU395) How To Begin Development Today With the TMS320C6411 DSP application report (literature number SPRA374)
PRODUCT PREVIEW
TMS320C67x is a trademark of Texas Instruments.
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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CPU (DSP core) description (continued)
src1 .L1 src2 8 8
dst long dst long src ST1b (Store Data) ST1a (Store Data) 32 MSBs 32 LSBs long src long dst dst .S1 src1 Data Path A src2 long dst dst .M1 src1 src2
8 8 Register File A (A0-A31)
See Note A See Note A
DA1 (Address)
.D1
dst src1 src2 2X 1X src2
DA2 (Address) LD2a (Load Data) LD2b (Load Data) 32 LSBs 32 MSBs
.D2
src1 dst
src2 .M2 src1 dst long dst src2 Data Path B .S2 src1 dst long dst long src See Note A See Note A Register File B (B0- B31) 8 8
ST2a (Store Data) ST2b (Store Data)
32 MSBs 32 LSBs long src long dst dst .L2 src2 src1 Control Register File 8 8
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 1. TMS320C64x CPU (DSP Core) Data Paths
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PRODUCT PREVIEW
LD1b (Load Data) LD1a (Load Data)
32 MSBs 32 LSBs
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
memory map summary
Table 3 shows the memory map address ranges of the C6411 device. Internal memory is always located at address 0 and can be used as both program and data memory. The external memory address range in the C6411 device begins at the hex address location 0x8000 0000 for the EMIF. Table 3. TMS320C6411 Memory Map Summary
MEMORY BLOCK DESCRIPTION Internal RAM (L2) Reserved External Memory Interface (EMIF) Registers L2 Registers HPI Registers McBSP 0 Registers McBSP 1 Registers Timer 0 Registers Timer 1 Registers Interrupt Selector Registers EDMA RAM and EDMA Registers Reserved Timer 2 Registers GPIO Registers Reserved PCI Registers Reserved QDMA Registers Reserved McBSP 0 Data McBSP 1 Data Reserved EMIF CE0 EMIF CE1 EMIF CE2 EMIF CE3 Reserved BLOCK SIZE (BYTES) 256K 24M - 256K 256K 256K 256K 256K 256K 256K 256K 256K 256K 512K 256K 256K 768K 256K 4M - 256K 52 736M - 52 64M 64M 1G + 128M 256M 256M 256M 256M 1G HEX ADDRESS RANGE
0000 0004 0180 0184 0188 018C 0190 0194 0198 019C 01A0 01A4 01AC 01B0 01B4 01C0 01C4 0200 0200 3000 3400 3800 8000 9000 A000 B000 C000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0034 0000 0000 0000 0000 0000 0000 0000 0000
- - - - - - - - - - - - - - - - - - - - - - - - - - -
0003 017F 0183 0187 018B 018F 0193 0197 019B 019F 01A3 01AB 01AF 01B3 01BF 01C3 01FF 0200 2FFF 33FF 37FF 7FFF 8FFF 9FFF AFFF BFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0033 FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
PRODUCT PREVIEW
The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space. To get 256MB of addressable memory, an additional general-purpose output pin or external logic is required.
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
peripheral register descriptions
Table 4 through Table 18 identify the peripheral registers for the C6411 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names and their descriptions, see the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 4. EMIF Registers
HEX ADDRESS RANGE 0180 0000 0180 0004 0180 0008 0180 000C 0180 0010 0180 0014 0180 0018 0180 001C 0180 0020 0180 0024 - 0180 0040 0180 0044 0180 0048 0180 004C 0180 0050 0180 0054 0180 0058 - 0183 FFFF ACRONYM GBLCTL CECTL1 CECTL0 - CECTL2 CECTL3 SDCTL SDTIM SDEXT - CESEC1 CESEC0 - CESEC2 CESEC3 - EMIF global control EMIF CE1 space control EMIF CE0 space control Reserved EMIF CE2 space control EMIF CE3 space control EMIF SDRAM control EMIF SDRAM refresh control EMIF SDRAM extension Reserved EMIF CE1 space secondary control EMIF CE0 space secondary control Reserved EMIF CE2 space secondary control EMIF CE3 space secondary control Reserved REGISTER NAME
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PRODUCT PREVIEW
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
peripheral register descriptions (continued)
Table 5. L2 Cache Registers
HEX ADDRESS RANGE 0184 0000 0184 2000 0184 2004 0184 2008 0184 200C 0184 4000 0184 4004 0184 4010 0184 4014 0184 4020 0184 4024 0184 4030 0184 4034 0184 5000 0184 5004 ACRONYM CCFG - L2ALLOC0 L2ALLOC1 L2ALLOC2 L2ALLOC3 - L2FBAR L2FWC L2CBAR L2CWC L1PFBAR L1PFWC L1DFBAR L1DFWC - L2FLUSH L2CLEAN - 0184 8000 -0184 81FC 0184 8200 0184 8204 0184 8208 0184 820C 0184 8210 0184 8214 0184 8218 0184 821C 0184 8220 0184 8224 0184 8228 0184 822C 0184 8230 0184 8234 0184 8238 0184 823C 0184 8240 0184 8244 0184 8248 MAR0 to MAR127 MAR128 MAR129 MAR130 MAR131 MAR132 MAR133 MAR134 MAR135 MAR136 MAR137 MAR138 MAR139 MAR140 MAR141 MAR142 MAR143 MAR144 MAR145 MAR146 Reserved L2 allocation register 0 L2 allocation register 1 L2 allocation register 2 L2 allocation register 3 Reserved L2 flush base address register L2 flush word count register L2 clean base address register L2 clean word count register L1P flush base address register L1P flush word count register L1D flush base address register L1D flush word count register Reserved L2 flush register L2 clean register Reserved Reserved Controls EMIF CE0 range 8000 0000 - 80FF FFFF Controls EMIF CE0 range 8100 0000 - 81FF FFFF Controls EMIF CE0 range 8200 0000 - 82FF FFFF Controls EMIF CE0 range 8300 0000 - 83FF FFFF Controls EMIF CE0 range 8400 0000 - 84FF FFFF Controls EMIF CE0 range 8500 0000 - 85FF FFFF Controls EMIF CE0 range 8600 0000 - 86FF FFFF Controls EMIF CE0 range 8700 0000 - 87FF FFFF Controls EMIF CE0 range 8800 0000 - 88FF FFFF Controls EMIF CE0 range 8900 0000 - 89FF FFFF Controls EMIF CE0 range 8A00 0000 - 8AFF FFFF Controls EMIF CE0 range 8B00 0000 - 8BFF FFFF Controls EMIF CE0 range 8C00 0000 - 8CFF FFFF Controls EMIF CE0 range 8D00 0000 - 8DFF FFFF Controls EMIF CE0 range 8E00 0000 - 8EFF FFFF Controls EMIF CE0 range 8F00 0000 - 8FFF FFFF Controls EMIF CE1 range 9000 0000 - 90FF FFFF Controls EMIF CE1 range 9100 0000 - 91FF FFFF Controls EMIF CE1 range 9200 0000 - 92FF FFFF REGISTER NAME Cache configuration register COMMENTS
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peripheral register descriptions (continued)
Table 5. L2 Cache Registers (Continued)
HEX ADDRESS RANGE 0184 824C 0184 8250 0184 8254 0184 8258 0184 825C 0184 8260 0184 8264 0184 8268 0184 826C 0184 8270 0184 8274 0184 8278 0184 827C 0184 8280 0184 8284 0184 8288 0184 828C 0184 8290 0184 8294 0184 8298 0184 829C 0184 82A0 0184 82A4 0184 82A8 0184 82AC 0184 82B0 0184 82B4 0184 82B8 0184 82BC 0184 82C0 0184 82C4 0184 82C8 0184 82CC 0184 82D0 0184 82D4 0184 82D8 0184 82DC 0184 82E0 0184 82E4 0184 82E8 0184 82EC 0184 82F0 ACRONYM MAR147 MAR148 MAR149 MAR150 MAR151 MAR152 MAR153 MAR154 MAR155 MAR156 MAR157 MAR158 MAR159 MAR160 MAR161 MAR162 MAR163 MAR164 MAR165 MAR166 MAR167 MAR168 MAR169 MAR170 MAR171 MAR172 MAR173 MAR174 MAR175 MAR176 MAR177 MAR178 MAR179 MAR180 MAR181 MAR182 MAR183 MAR184 MAR185 MAR186 MAR187 MAR188 REGISTER NAME Controls EMIF CE1 range 9300 0000 - 93FF FFFF Controls EMIF CE1 range 9400 0000 - 94FF FFFF Controls EMIF CE1 range 9500 0000 - 95FF FFFF Controls EMIF CE1 range 9600 0000 - 96FF FFFF Controls EMIF CE1 range 9700 0000 - 97FF FFFF Controls EMIF CE1 range 9800 0000 - 98FF FFFF Controls EMIF CE1 range 9900 0000 - 99FF FFFF Controls EMIF CE1 range 9A00 0000 - 9AFF FFFF Controls EMIF CE1 range 9B00 0000 - 9BFF FFFF Controls EMIF CE1 range 9C00 0000 - 9CFF FFFF Controls EMIF CE1 range 9D00 0000 - 9DFF FFFF Controls EMIF CE1 range 9E00 0000 - 9EFF FFFF Controls EMIF CE1 range 9F00 0000 - 9FFF FFFF Controls EMIF CE2 range A000 0000 - A0FF FFFF Controls EMIF CE2 range A100 0000 - A1FF FFFF Controls EMIF CE2 range A200 0000 - A2FF FFFF Controls EMIF CE2 range A300 0000 - A3FF FFFF Controls EMIF CE2 range A400 0000 - A4FF FFFF Controls EMIF CE2 range A500 0000 - A5FF FFFF Controls EMIF CE2 range A600 0000 - A6FF FFFF Controls EMIF CE2 range A700 0000 - A7FF FFFF Controls EMIF CE2 range A800 0000 - A8FF FFFF Controls EMIF CE2 range A900 0000 - A9FF FFFF Controls EMIF CE2 range AA00 0000 - AAFF FFFF Controls EMIF CE2 range AB00 0000 - ABFF FFFF Controls EMIF CE2 range AC00 0000 - ACFF FFFF Controls EMIF CE2 range AD00 0000 - ADFF FFFF Controls EMIF CE2 range AE00 0000 - AEFF FFFF Controls EMIF CE2 range AF00 0000 - AFFF FFFF Controls EMIF CE3 range B000 0000 - B0FF FFFF Controls EMIF CE3 range B100 0000 - B1FF FFFF Controls EMIF CE3 range B200 0000 - B2FF FFFF Controls EMIF CE3 range B300 0000 - B3FF FFFF Controls EMIF CE3 range B400 0000 - B4FF FFFF Controls EMIF CE3 range B500 0000 - B5FF FFFF Controls EMIF CE3 range B600 0000 - B6FF FFFF Controls EMIF CE3 range B700 0000 - B7FF FFFF Controls EMIF CE3 range B800 0000 - B8FF FFFF Controls EMIF CE3 range B900 0000 - B9FF FFFF Controls EMIF CE3 range BA00 0000 - BAFF FFFF Controls EMIF CE3 range BB00 0000 - BBFF FFFF Controls EMIF CE3 range BC00 0000 - BCFF FFFF COMMENTS
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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peripheral register descriptions (continued)
Table 5. L2 Cache Registers (Continued)
HEX ADDRESS RANGE 0184 82F4 0184 82F8 0184 82FC 0184 8300 -0184 83FC 0184 8400 -0187 FFFF ACRONYM MAR189 MAR190 MAR191 MAR192 to MAR255 - REGISTER NAME Controls EMIF CE3 range BD00 0000 - BDFF FFFF Controls EMIF CE3 range BE00 0000 - BEFF FFFF Controls EMIF CE3 range BF00 0000 - BFFF FFFF Reserved Reserved COMMENTS
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peripheral register descriptions (continued)
Table 6. EDMA Registers
HEX ADDRESS RANGE 01A0 FF9C 01A0 FFA4 01A0 FFA8 01A0 FFAC 01A0 FFB0 01A0 FFB4 01A0 FFB8 01A0 FFBC 01A0 FFC0 01A0 FFC4 01A0 FFC8 01A0 FFCC 01A0 FFDC 01A0 FFE0 01A0 FFE4 01A0 FFE8 01A0 FFEC 01A0 FFF0 01A0 FFF4 01A0 FFF8 01A0 FFFC 01A1 0000 - 01A3 FFFF ACRONYM EPRH CIPRH CIERH CCERH ERH EERH ECRH ESRH PQAR0 PQAR1 PQAR2 PQAR3 EPRL PQSR CIPRL CIERL CCERL ERL EERL ECRL ESRL - REGISTER NAME Event polarity high register Channel interrupt pending high register Channel interrupt enable high register Channel chain enable high register Event high register Event enable high register Event clear high register Event set high register Priority queue allocation register 0 Priority queue allocation register 1 Priority queue allocation register 2 Priority queue allocation register 3 Priority queue status register Channel interrupt pending low register Channel interrupt enable low register Channel chain enable low register Event low register Event enable low register Event clear low register Event set low register Reserved Event polarity low register
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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peripheral register descriptions (continued)
Table 7. EDMA Parameter RAM
HEX ADDRESS RANGE 01A0 0000 - 01A0 0017 01A0 0018 - 01A0 002F 01A0 0030 - 01A0 0047 01A0 0048 - 01A0 005F 01A0 0060 - 01A0 0077 01A0 0078 - 01A0 008F 01A0 0090 - 01A0 00A7 01A0 00A8 - 01A0 00BF 01A0 00C0 - 01A0 00D7 01A0 00D8 - 01A0 00EF 01A0 00F0 - 01A0 00107 01A0 0108 - 01A0 011F 01A0 0120 - 01A0 0137 ACRONYM - - - - - - - - - - - - - - - - - - REGISTER NAME Parameters for Event 0 (6 words) Parameters for Event 1 (6 words) Parameters for Event 2 (6 words) Parameters for Event 3 (6 words) Parameters for Event 4 (6 words) Parameters for Event 5 (6 words) Parameters for Event 6 (6 words) Parameters for Event 7 (6 words) Parameters for Event 8 (6 words) Parameters for Event 9 (6 words) Parameters for Event 10 (6 words) Parameters for Event 11 (6 words) Parameters for Event 12 (6 words) Parameters for Event 13 (6 words) Parameters for Event 14 (6 words) Parameters for Event 15 (6 words) Parameters for Event 16 (6 words) Parameters for Event 17 (6 words) ... ... - - - - - - Parameters for Event 62 (6 words) Parameters for Event 63 (6 words) Reload/link parameters for Event M (6 words) Reload/link parameters for Event N (6 words) ... Reload/link parameters for Event Z (6 words) COMMENTS
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01A0 0138 - 01A0 014F 01A0 0150 - 01A0 0167 01A0 0168 - 01A0 017F 01A0 0150 - 01A0 0167 01A0 0168 - 01A0 017F ... ... 01A0 05D0 - 01A0 05E7 01A0 05E8 - 01A0 05FF 01A0 0600 - 01A0 0617 01A0 0618 - 01A0 062F ... 01A0 07E0 - 01A0 07F7 01A0 07F8 - 01A0 07FF
Scratch pad area (2 words) The C64x device has twenty-one parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.
Table 8. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE 0200 0000 0200 0004 0200 0008 0200 000C 0200 0010 0200 0014 - 0200 001C 0200 0020 0200 0024 0200 0028 0200 002C 0200 0030 QSOPT QSSRC QSCNT QSDST QSIDX ACRONYM QOPT QSRC QCNT QDST QIDX REGISTER NAME QDMA options parameter register QDMA source address register QDMA frame count register QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA psuedo source address register QDMA psuedo frame count register QDMA destination address register QDMA psuedo index register
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peripheral register descriptions (continued)
Table 9. Interrupt Selector Registers
HEX ADDRESS RANGE 019C 0000 019C 0004 019C 0008 019C 000C - 019C 01FF 019C 0200 019C 0204 - 019F FFFF ACRONYM MUXH MUXL EXTPOL - PDCTL - REGISTER NAME Interrupt multiplexer high Interrupt multiplexer low External interrupt polarity Reserved Peripheral power-down control register (see Table 10) Reserved COMMENTS Selects which interrupts drive CPU interrupts 10-15 (INT10-INT15) Selects which interrupts drive CPU interrupts 4-9 (INT04-INT09) Sets the polarity of the external interrupts (EXT_INT4-EXT_INT7)
Table 10. Peripheral Power-Down Control Register
HEX ADDRESS RANGE 019C 0200 ACRONYM PDCTL REGISTER NAME
Table 11. McBSP 0 Registers
HEX ADDRESS RANGE 018C 0000 0x3000 0000 - 0x33FF FFFF 018C 0004 0x3000 0000 - 0x33FF FFFF 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 018C 002C 018C 0030 018C 0034 018C 0038 018C 003C 018C 0040 - 018F FFFF ACRONYM DRR0 DRR0 DXR0 DXR0 SPCR0 RCR0 XCR0 SRGR0 MCR0 RCERE00 XCERE00 PCR0 RCERE10 XCERE10 RCERE20 XCERE20 RCERE30 XCERE30 - REGISTER NAME McBSP0 data receive register via Configuration Bus McBSP0 data receive register via Peripheral Data Bus McBSP0 data transmit register via Configuration Bus McBSP0 data transmit register via Peripheral Data Bus McBSP0 serial port control register McBSP0 receive control register McBSP0 transmit control register McBSP0 sample rate generator register McBSP0 multichannel control register McBSP0 enhanced receive channel enable register 0 McBSP0 enhanced transmit channel enable register 0 McBSP0 pin control register McBSP0 enhanced receive channel enable register 1 McBSP0 enhanced transmit channel enable register 1 McBSP0 enhanced receive channel enable register 2 McBSP0 enhanced transmit channel enable register 2 McBSP0 enhanced receive channel enable register 3 McBSP0 enhanced transmit channel enable register 3 Reserved COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it.
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Peripheral power-down control register
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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peripheral register descriptions (continued)
Table 12. McBSP 1 Registers
HEX ADDRESS RANGE 0190 0000 0x3400 0000 - 0x37FF FFFF 0190 0004 0x3400 0000 - 0x37FF FFFF 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 0190 0024 ACRONYM DRR1 DRR1 DXR1 DXR1 SPCR1 RCR1 XCR1 SRGR1 MCR1 RCERE01 XCERE01 PCR1 RCERE11 XCERE11 RCERE21 XCERE21 RCERE31 XCERE31 - REGISTER NAME Data receive register via Configuration Bus McBSP1 data receive register via Peripheral Data Bus McBSP1 data transmit register via Configuration Bus McBSP1 data transmit register via Peripheral Data Bus McBSP1 serial port control register McBSP1 receive control register McBSP1 transmit control register McBSP1 sample rate generator register McBSP1 multichannel control register McBSP1 enhanced receive channel enable register 0 McBSP1 enhanced transmit channel enable register 0 McBSP1 pin control register McBSP1 enhanced receive channel enable register 1 McBSP1 enhanced transmit channel enable register 1 McBSP1 enhanced receive channel enable register 2 McBSP1 enhanced transmit channel enable register 2 McBSP1 enhanced receive channel enable register 3 McBSP1 enhanced transmit channel enable register 3 Reserved COMMENTS The CPU and EDMA controller can only read this register; they cannot write to it.
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0190 0028 0190 002C 0190 0030 0190 0034 0190 0038 0190 003C 0190 0040 - 0193 FFFF
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peripheral register descriptions (continued)
Table 13. Timer 0 Registers
HEX ADDRESS RANGE 0194 0000 ACRONYM CTL0 REGISTER NAME Timer 0 control register COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
0194 0004
PRD0
Timer 0 period register
0194 0008 0194 000C - 0197 FFFF
CNT0 -
Timer 0 counter register Reserved
Table 14. Timer 1 Registers
HEX ADDRESS RANGE 0198 0000 ACRONYM CTL1 REGISTER NAME Timer 1 control register COMMENTS
0198 0004
PRD1
Timer 1 period register
Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
0198 0008 0198 000C - 019B FFFF
CNT1 -
Timer 1 counter register Reserved
Table 15. Timer 2 Registers
HEX ADDRESS RANGE 01AC 0000 ACRONYM CTL2 REGISTER NAME Timer 2 control register COMMENTS Determines the operating mode of the timer, monitors the timer status. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
01AC 0004
PRD2
Timer 2 period register
01AC 0008 01AC 000C - 01AF FFFF
CNT2 -
Timer 2 counter register Reserved
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Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin.
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
peripheral register descriptions (continued)
Table 16. HPI Registers
HEX ADDRESS RANGE - 0188 0000 0188 0004 0188 0008 ACRONYM HPID HPIC HPIA (HPIAW) HPIA (HPIAR) HPI data register HPI control register HPI address register (Write) HPI address register (Read) REGISTER NAME COMMENTS Host read/write access only HPIC has both Host/CPU read/write access HPIA has both Host/CPU read/write access
0188 0001 - 018B FFFF - Reserved Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
Table 17. GPIO Registers
HEX ADDRESS RANGE 01B0 0000 ACRONYM GPEN GPDIR GPVAL - GPDH GPHM GPDL GPLM GPGC GPPOL - REGISTER NAME GPIO enable register GPIO direction register GPIO value register Reserved GPIO delta high register GPIO high mask register GPIO delta low register GPIO low mask register GPIO global control register GPIO interrupt polarity register Reserved
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01B0 0004 01B0 0008 01B0 000C 01B0 0010 01B0 0014 01B0 0018 01B0 001C 01B0 0020 01B0 0024 01B0 0028 - 01B3 FFFF
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peripheral register descriptions (continued)
Table 18. PCI Peripheral Registers
HEX ADDRESS RANGE 01C0 0000 01C0 0004 01C0 0008 01C0 000C 01C0 0010 01C0 0014 01C0 0018 01C0 001C 01C0 0020 01C0 0024 01C0 0028 01C0 002C - 01C1 FFEF 0x01C1 FFF0 0x01C1 FFF4 0x01C1 FFF8 0x01C1 FFFC 01C2 0000 01C2 0004 01C2 0008 01C2 000C - 01C3 FFFF ACRONYM RSTSRC PMDCSR PCIIS PCIIEN DSPMA PCIMA PCIMC CDSPA CPCIA CCNT - - HSR HDCR DSPP - EEADD EEDAT EECTL - REGISTER NAME DSP Reset source/status register Power management DSP control/status register PCI interrupt source register PCI interrupt enable register DSP master address register PCI master address register PCI master control register Current DSP address register Current PCI address register Current byte count register Reserved Reserved Host status register Host-to-DSP control register DSP page register Reserved EEPROM address register EEPROM data register EEPROM control register Reserved
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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EDMA channel synchronization events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory. Table 19 lists the source of C64x EDMA synchronization events associated with each of the programmable EDMA channels. For the C6411 device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 19. TMS320C6411 EDMA Channel Synchronization Events
EDMA CHANNEL
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-18 19 20-47 48 49 50 51 52 53 54 55 56-63
EVENT NAME
DSP_INT TINT0 TINT1 SD_INT GPINT4/EXT_INT4 GPINT5/EXT_INT5 GPINT6/EXT_INT6 GPINT7/EXT_INT7 GPINT0 GPINT1 GPINT2 GPINT3 XEVT0 REVT0 XEVT1 REVT1 - TINT2 - GPINT8 GPINT9 GPINT10 GPINT11 GPINT12 GPINT13 GPINT14 GPINT15 - HPI/PCI-to-DSP interrupt Timer 0 interrupt Timer 1 interrupt EMIF SDRAM timer interrupt GPIO event 4/External interrupt pin 4 GPIO event 5/External interrupt pin 5 GPIO event 6/External interrupt pin 6 GPIO event 7/External interrupt pin 7 GPIO event 0 GPIO event 1 GPIO event 2 GPIO event 3 McBSP0 transmit event McBSP0 receive event McBSP1 transmit event McBSP1 receive event None Timer 2 interrupt None GPIO event 8 GPIO event 9 GPIO event 10 GPIO event 11 GPIO event 12 GPIO event 13 GPIO event 14 GPIO event 15 None
EVENT DESCRIPTION
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In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the EDMA Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
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interrupt sources and interrupt selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 20. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts (INT_00-INT_03) are non-maskable and fixed. The remaining interrupts (INT_04-INT_15) are maskable and default to the interrupt source specified in Table 20. The interrupt source for interrupts 4-15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004). Table 20. C6411 DSP Interrupts
CPU INTERRUPT NUMBER INT_00 INT_01 INT_02 INT_03 INT_04 INT_05 INT_06 INT_07 INT_08 INT_09 INT_10 INT_11 INT_12 INT_13 INT_14 INT_15 - - - - - - - - - INTERRUPT SELECTOR CONTROL REGISTER - - - - MUXL[4:0] MUXL[9:5] MUXL[14:10] MUXL[20:16] MUXL[25:21] MUXL[30:26] MUXH[4:0] MUXH[9:5] MUXH[14:10] MUXH[20:16] MUXH[25:21] MUXH[30:26] - - - - - - - - - SELECTOR VALUE (BINARY) - - - - 00100 00101 00110 00111 01000 01001 00011 01010 01011 00000 00001 00010 01100 01101 01110 01111 10000 10001 10010 10011 10100 - 11111 INTERRUPT EVENT RESET NMI Reserved Reserved GPINT4/EXT_INT4 GPINT5/EXT_INT5 GPINT6/EXT_INT6 GPINT7/EXT_INT7 EDMA_INT EMU_DTDMA SD_INT EMU_RTDXRX EMU_RTDXTX DSP_INT TINT0 TINT1 XINT0 RINT0 XINT1 RINT1 GPINT0 Reserved Reserved TINT2 Reserved Reserved. Do not use. Reserved. Do not use. GPIO interrupt 4/External interrupt pin 4 GPIO interrupt 5/External interrupt pin 5 GPIO interrupt 6/External interrupt pin 6 GPIO interrupt 7/External interrupt pin 7 EDMA channel (0 through 63) interrupt EMU DTDMA EMIF SDRAM timer interrupt EMU real-time data exchange (RTDX) receive EMU RTDX transmit HPI/PCI-to-DSP interrupt Timer 0 interrupt Timer 1 interrupt McBSP0 transmit interrupt McBSP0 receive interrupt McBSP1 transmit interrupt McBSP1 receive interrupt GPIO interrupt 0 Reserved. Do not use. Reserved. Do not use. Timer 2 interrupt Reserved. Do not use. INTERRUPT SOURCE
Interrupts INT_00 through INT_03 are non-maskable and fixed. Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields. Table 20 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see the Interrupt Selector and External Interrupts chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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signal groups description
CLKIN CLKOUT4/GP1 CLKOUT6/GP2 CLKMODE0 PLLV
Clock/PLL
Reset and Interrupts
RESET NMI GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4
PRODUCT PREVIEW
TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 EMU7 EMU8 EMU9 EMUCLK1 EMUCLK0
Reserved
RSV RSV RSV RSV RSV RSV
IEEE Standard 1149.1 (JTAG) Emulation
* * *
RSV RSV RSV
Peripheral Control and Configuration
Control/Status
PCI_EN LEND BOOTMODE [1:0] ECLKIN_SEL[1:0] EEAI HD5/AD5
GP15/PRST GP14/PCLK GP13/PINTA GP12/PGNT GP11/PREQ GP10/PCBE3 GP9/PIDSEL GP8
GPIO
GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 GP4/EXT_INT4 GP3 CLKOUT6/GP2 CLKOUT4/GP1 GP0
General-Purpose Input/Output (GPIO) Port These pins are muxed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6). To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. For more details, see the Device Configurations section of this data sheet. These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or GPIO as input-only. These GPIO pins are muxed with the PCI peripheral pins and by default these signals are set up to no function with both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 2. CPU and Peripheral Signals
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signal groups description (continued)
32 ED[31:0] CE3 CE2 CE1 CE0 20 EA[21:2] Memory Map Space Select External Memory I/F Control Data ECLKIN ECLKOUT1 ECLKOUT2 SDCKE ARE/SDCAS/SADS/SRE AOE/SDRAS/SOE AWE/SDWE/SWE ARDY SOE3 PDT
Address
BE3 BE2 BE1 BE0
Byte Enables
Bus Arbitration
HOLD HOLDA BUSREQ
EMIF (32-bit)
Figure 3. Peripheral Signals
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signal groups description (continued)
HPI (Host-Port Interface) HAS/PPAR HR/W/PCBE2 HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HINT/PFRAME
32 HD[31:0]/AD[31:0]
Data
HCNTL0/PSTOP HCNTL1/PDEVSEL
Register Select Control Half-Word Select
HHWIL/PTRDY (HPI16 ONLY)
32 HD[31:0]/AD[31:0] Data/Address Clock GP14/PCLK
PRODUCT PREVIEW
GP10/PCBE3 HR/W/PCBE2 HDS2/PCBE1 PCBE0
Command Byte Enable
Control
GP9/PIDSEL HCNTL1/PDEVSEL HINT/PFRAME GP13/PINTA HAS/PPAR GP15/PRST HRDY/PIRDY HCNTL0/PSTOP HHWIL/PTRDY
GP12/PGNT GP11/PREQ
Arbitration Error
HDS1/PSERR HCS/PPERR
Serial EEPROM PCI Interface
XSP_DO XSP_CS XSP_CLK XSP_DI
These HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For more details on these muxed pins, see the Device Configurations section of this data sheet. These PCI pins (excluding PCBE0 , XSP_DO, XSP_CLK, XSP_DI, and XSP_CS) are muxed with the HPI or GPIO peripherals. By default, these signals function as HPI and no function, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 3. Peripheral Signals (Continued)
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signal groups description (continued)
McBSP1 CLKX1 FSX1 DX1 CLKR1 FSR1 DR1 CLKS1 Transmit McBSP0 Transmit CLKX0 FSX0 DX0 CLKR0 FSR0 DR0 Clock Clock CLKS0
Receive
Receive
McBSPs (Multichannel Buffered Serial Ports)
TOUT1 TINP1
Timer 1
Timer 0
TOUT0 TINP0
Timer 2 Timers
Figure 3. Peripheral Signals (Continued)
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PRODUCT PREVIEW
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
DEVICE CONFIGURATIONS
The C6411 peripheral selections and other device configurations are determined by external pullup/pulldown resistors on the following pins (all of which are latched during device reset):
D peripherals selection
- PCI_EN
D other device configurations
- - - - - LEND BOOTMODE [1:0] ECLKIN_SEL[1:0] EEAI HD5/AD5
peripherals selection
PRODUCT PREVIEW
Some C6411 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:9], and PCI). Other C6411 peripherals (i.e., EMIF, three Timers, two McBSPs, and the GP[8:0] pins), are always available.
D HPI/GP[15:9] versus PCI
The PCI_EN pin is latched at reset. This pin determines the HPI/GP[15:9] versus the PCI peripheral selection, summarized in Table 21.
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DEVICE CONFIGURATIONS (CONTINUED)
Table 21. PCI_EN Peripheral Selection (HPI/GP[15:9] or PCI)
PCI_EN Pin PERIPHERALS SELECTED HPI GP[15:9] PCI DESCRIPTION [default] HPI is enabled, GP[15:9] pins can be programmed as GPIO, PCI is disabled. 0 This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI pins (PCBE0, XSP_DO, XSP_DI, XSP_CLK, and XSP_CS) are tied-off (Hi-Z). Also, the multiplexed GPIO/PCI pins can be used as GPIO with the proper software configuration of the GPIO enable (GPxEN) and direction (GPxDIR) registers (for more details, see Table 23). PCI is enabled, HPI/GP[15:9] are disabled. This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed GPIO/PCI pins function as PCI pins (for more details, see Table 23). Auto-initialization through PCI EEPROM or initialization via specified PCI default values is controlled by the EEAI pin, see Table 22.
1
other device configurations
Table 22 describes the C6411 device configuration pins, which are set up via external pullup/pulldown resistors through the specified pins. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section.
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PRODUCT PREVIEW
The PCI_EN pin is latched at reset and must be driven valid at all times and the user must not switch values throughout device operation.
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
DEVICE CONFIGURATIONS (CONTINUED)
Table 22. Device Configuration Pins (LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5)
CONFIGURATION PIN LEND NO. FUNCTIONAL DESCRIPTION Device Endian mode (LEND) 0 - System operates in Big Endian mode 1 - System operates in Little Endian mode (default) Bootmode [1:0]. Default is reserved. External pullup and/or pulldown resistors must be used to select a valid bootmode configuration. 00 - No boot 01 - HPI boot 10 - Reserved (default mode) 11 - EMIF 8-bit ROM boot with default timings EMIF input clock select Clock mode select for EMIF (ECLKIN_SEL[1:0]) 00 - ECLKIN (default mode) 01 - CPU/4 Clock Rate 10 - CPU/6 Clock Rate 11 - Reserved PCI EEPROM Auto-Initialization (EEAI) PCI auto-initialization via external EEPROM 0 - PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified PCI default values (default). 1 - PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1). Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. For more information on the PCI EEPROM default values, see the PCI chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). HPI configuration bus width (HPI_WIDTH) 0 - HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state.) 1 - HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
BOOTMODE[1:0]
ECLKIN_SEL[1:0]
PRODUCT PREVIEW
EEAI
HD5/AD5
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DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some of these pins are configured by software, and the others are configured by external pullup/pulldown resistors only at reset. Those muxed pins that are configured by software can be programmed to switch functionalities at any time. Those muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 23 identifies the multiplexed pins on the C6411 device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed functions.
debugging considerations
It is recommended that external connections be provided to device configuration pins, including CLKMODE0, LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0]. EEAI, HD5/AD5, and PCI_EN. Although internal pullup/pulldown resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes.
For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
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PRODUCT PREVIEW
Internal pullup/pulldown resistors also exist on specified reserved (RSV) pins. Do not oppose the internal pullup/pulldown resistors, unless otherwised noted, on these RSV pins.
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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DEVICE CONFIGURATIONS (CONTINUED)
Table 23. C6411 Device Multiplexed Pins
MULTIPLEXED PINS NAME NO. DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION These pins are software-configurable. To use these pins as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output To use GP[15:9] as GPIO pins, the PCI needs to be disabled (PCI_EN = 0), the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output
CLKOUT4/GP1
CLKOUT4
GP1EN = 0 (disabled)
CLKOUT6/GP2
CLKOUT6
GP2EN = 0 (disabled)
GP9/PIDSEL GP10/PCBE3 GP11/PREQ GP12/PGNT None GPxEN = 0 (disabled) PCI_EN = 0 (disabled) GP13/PINTA GP14/PCLK GP15/PRST HD[31:0]/AD[31:0] HAS/PPAR HCNTL1/PDEVSEL HCNTL0/PSTOP HDS1/PSERR HDS2/PCBE1 HR/W/PCBE2 HWWIL/PTRDY HINT/PFRAME HCS/PPERR HD[31:0] HAS HCNTL1 HCNTL0 HDS1 HDS2 HR/W HHWIL (HPI16 only) HINT HCS PCI_EN = 0 (disabled)
PRODUCT PREVIEW
By default, HPI is enabled upon reset (PCI is disabled). To enable the PCI peripheral an external pullup resistor (1 k) must be provided on the PCI_EN pin (setting PCI_EN = 1 at reset and keeping valid "1" after reset).
HRDY/PIRDY HRDY All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0]. For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
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Terminal Functions
SIGNAL NAME NO. TYPE IPD/ IPU CLOCK/PLL CONFIGURATION CLKIN CLKOUT4/GP1 CLKOUT6/GP2 I I/O/Z I/O/Z IPD IPD IPD Clock Input. This clock is the input to the on-chip PLL. Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z). Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). Clock mode select * Selects whether the CPU clock frequency = input clock frequency x1 (Bypass) [default] or x6. For more details on the CLKMODE0 pin and the PLL multiply factors, see the Clock PLL section of this data sheet. PLL voltage supply JTAG EMULATION TMS TDO TDI TCK TRST EMU9 EMU8 EMU7 EMU6 EMU5 EMU4 EMU3 EMU2 EMU1 EMU0 EMUCLK1 EMUCLK0 I O/Z I I I I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z IPU IPU IPU IPU IPD IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU JTAG test-port mode select JTAG test-port data out JTAG test-port clock JTAG test-port reset Emulation pin 9. Reserved for future use, leave unconnected. Emulation pin 8. Reserved for future use, leave unconnected. Emulation pin 7. Reserved for future use, leave unconnected. Emulation pin 6. Reserved for future use, leave unconnected. Emulation pin 5. Reserved for future use, leave unconnected. Emulation pin 4. Reserved for future use, leave unconnected. Emulation pin 3. Reserved for future use, leave unconnected. Emulation pin 2. Reserved for future use, leave unconnected. Emulation pin 1|| Emulation pin 0|| Emulation clock 1. Reserved for future use, leave unconnected. Emulation clock 0. Reserved for future use, leave unconnected. LITTLE/BIG ENDIAN FORMAT LEND I/O/Z IPU Device Endian mode LEND: 0 - Big Endian 1 - Little Endian (default mode) JTAG test-port data in DESCRIPTION
CLKMODE0
I
IPD
PLLV
A#
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin. # A = Analog signal (PLL Filter) || The EMU0 and EMU1 pins are internally pulled up with 30-k resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k resistor.
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PRODUCT PREVIEW
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU BOOTMODE BOOTMODE1 I/O/Z BOOTMODE0 IPD IPU Boot mode. Default is reserved. External pullup and/or pulldown resistors must be used to select a valid bootmode configuration. BOOTMODE[1:0]: 00 01 10 11 - - - - No boot HPI boot Reserved (default mode) EMIF 8-bit ROM boot with default timings DESCRIPTION
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS RESET NMI GP7/EXT_INT7 GP6/EXT_INT6 GP5/EXT_INT5 I/O/Z IPU GP4/EXT_INT4 GP15/PRST GP14/PCLK GP13/PINTA GP12/PGNT GP11/PREQ GP10/PCBE3 GP9/PIDSEL GP3 I/O/Z IPD I I IPD Device reset Nonmaskable interrupt, edge-driven (rising edge) General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The default after reset setting is GPIO enabled as input-only. * When these pins function as External Interrupts [by selecting the corresponding interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]). General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default. GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default. GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default. GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. GPIO 3 pin (I/O/Z). GPIO 0 pin. The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only) [default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT) signal (output only). This pin has no function at default [default] or this pin can be programmed as a GPIO 8 pin (I/O/Z). Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 2 pin (I/O/Z). Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a GPIO 1 pin (I/O/Z).
PRODUCT PREVIEW
GP0
IPD
GP8 CLKOUT6/GP2 CLKOUT4/GP1
I/O/Z I/O/Z I/O/Z
IPD IPD IPD
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) PCI_EN I IPD PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or PCI peripherals. For more details, see the Device Configurations section of this data sheet. PCI EEPROM Auto-Initialization (EEAI) via external EEPROM If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up. EEAI: 0 - PCI auto-initialization through EEPROM is disabled (default). 1 - PCI auto-initialization through EEPROM is enabled.
EEAI
I/O/Z
IPD
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Terminal Functions (Continued)
SIGNAL NAME HINT/ PFRAME HCNTL1/ PDEVSEL HCNTL0/ PSTOP HHWIL/ PTRDY HR/W/PCBE2 HAS/PPAR HCS/PPERR HDS1/PSERR HDS2/PCBE1 HRDY/PIRDY HD31/AD31 HD30/AD30 HD29/AD29 HD28/AD28 HD27/AD27 HD26/AD26 HD25/AD25 HD24/AD24 HD23/AD23 HD22/AD22 HD21/AD21 HD20/AD20 HD19/AD19 HD18/AD18 HD17/AD17 HD16/AD16 HD15/AD15 HD14/AD14 HD13/AD13 HD12/AD12 HD11/AD11 HD10/AD10 HD9/AD9 HD8/AD8 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet. I/O/Z Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z) As HPI data bus (PCI_EN pin = 0) * Used for transfer of data, address, and control * Host-Port bus width user-configurable at device reset via a 10-k resistor pullup/pulldown resistor on the HD5 pin: HD5 pin = 0: HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the high-impedance state.) HD5 pin = 1: HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) As PCI data-address bus (PCI_EN pin = 1) * Used for transfer of data and address NO. TYPE IPD/ IPU DESCRIPTION
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) (CONTINUED) I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z) Host control - selects between control, address, or data registers (I) [default] or PCI device select (I/O/Z). Host control - selects between control, address, or data registers (I) [default] or PCI stop (I/O/Z) Host half-word select - first or second half-word (not necessarily high or low order) [For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z) Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z) Host address strobe (I) [default] or PCI parity (I/O/Z) Host chip select (I) [default] or PCI parity error (I/O/Z) Host data strobe 1 (I) [default] or PCI system error (I/O/Z) Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z) Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z).
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) (CONTINUED) HD7/AD7 HD6/AD6 HD5/AD5 HD4/AD4 HD3/AD3 HD2/AD2 HD1/AD1 HD0/AD0 PCBE0 I/O/Z O I/O/Z IPD IPD I/O/Z Host-port data (I/O/Z) [default] or PCI data-address bus (I/O/Z) As HPI data bus (PCI_EN pin = 0) * Used for transfer of data, address, and control * Host-Port bus width user-configurable at device reset via a 10-k resistor pullup/pulldown resistor on the HD5 pin: HD5 pin = 0: HPI operates as an HPI16. (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the high-impedance state.) HD5 pin = 1: HPI operates as an HPI32. (HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.) As PCI data-address bus (PCI_EN pin = 1) * Used for transfer of data and address PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off. PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is tied-off. This pin has no function at default [default] or when PCI is enabled (PCI_EN = 0), this pin is the PCI serial interface clock (O). This pin has no function at default [default] or when PCI is enabled (PCI_EN = 0), this pin is the PCI serial interface data in (I). In PCI mode, this pin is connected to the output data pin of the serial PROM. This pin has no function at default [default] or when PCI is enabled (PCI_EN = 0), this pin is the PCI serial interface data out (O). In PCI mode, this pin is connected to the input data pin of the serial PROM. General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default. GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default. GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default. I/O/Z GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default. GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default. GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default. GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default. O/Z O/Z O/Z IPU IPU IPU EMIF memory space enables * Enabled by bits 28 through 31 of the word address * Only one pin is asserted during any external data access
PRODUCT PREVIEW
XSP_CS XSP_CLK
XSP_DI
I
IPU
XSP_DO GP15/PRST GP14/PCLK GP13/PINTA GP12/PGNT GP11/PREQ GP10/PCBE3 GP9/PIDSEL CE3 CE2 CE1
O/Z
IPU
CE0 O/Z IPU I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
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Terminal Functions (Continued)
SIGNAL NAME BE3 BE2 BE1 BE0 PDT HOLDA HOLD BUSREQ NO. TYPE IPD/ IPU DESCRIPTION
EMIF (32-bit) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY (CONTINUED) O/Z O/Z O/Z O/Z O/Z O I O IPU IPU IPU IPU IPU IPU IPU IPU EMIF byte-enable control * Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory. * Byte-write enables for most types of memory * Can be directly connected to SDRAM read and write mask signal (SDQM) EMIF peripheral data transfer, allows direct transfer between external peripherals EMIF (32-BIT) - BUS ARBITRATION EMIF hold-request-acknowledge to the host EMIF hold request from the host EMIF bus request output
EMIF (32-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL EMIF clock mode select ECLKIN_SEL1 I/O/Z ECLKIN_SEL0 IPD ECLKIN_SEL[1:0]: 00 01 10 11 - - - - ECLKIN (default mode) CPU/4 Clock Rate CPU/6 Clock Rate Reserved
ECLKIN
I
IPD
EMIF external input clock. The EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the ECLKIN_SEL[1:0] pins. ECLKIN is the default for the EMIF input clock. EMIF output clock 2. Programmable to be EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4. EMIF output clock 1 at EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) frequency. EMIF asynchronous memory read-enable/SDRAM column-address strobe/programmable synchronous interface-address strobe or read-enable * For programmable synchronous interface, the RENEN field in the CE Space Secondary Control Register (CExSEC) selects between SADS and SRE: If RENEN = 0, then the SADS/SRE signal functions as the SADS signal. If RENEN = 1, then the SADS/SRE signal functions as the SRE signal. EMIF asynchronous memory output-enable/SDRAM row-address strobe/programmable synchronous interface output-enable EMIF asynchronous memory write-enable/SDRAM write-enable/programmable synchronous interface write-enable EMIF SDRAM clock-enable (used for self-refresh mode). * If SDRAM is not in system, SDCKE can be used as a general-purpose output. EMIF synchronous memory output-enable for CE3 (for glueless FIFO interface)
ECLKOUT2 ECLKOUT1
O/Z O/Z
IPD IPD
ARE/ SDCAS/ SADS/SRE
O/Z
IPU
AOE/ SDRAS/ SOE AWE/ SDWE/ SWE SDCKE SOE3
O/Z
IPU
O/Z
IPU
O/Z O/Z
IPU IPU
ARDY I IPU Asynchronous memory ready input I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.)
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
Terminal Functions (Continued)
SIGNAL NAME EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 EA9 O/Z IPD EMIF external address (word address) NO. TYPE IPD/ IPU EMIF (32-BIT) - ADDRESS DESCRIPTION
PRODUCT PREVIEW
EA8 EA7 EA6 EA5 EA4 EA3 EA2 EMIF (32-bit) - DATA ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.) I/O/Z IPU EMIF external data
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Terminal Functions (Continued)
SIGNAL NAME ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 TIMER 1 TOUT1 TINP1 TOUT0 TINP0 CLKS1 CLKR1 CLKX1 DR1 DX1 FSR1 FSX1 CLKS0 CLKR0 CLKX0 DR0 DX0 FSR0 O/Z I O/Z I I I/O/Z I/O/Z I O/Z I/O/Z I/O/Z I I/O/Z I/O/Z I O/Z I/O/Z IPD IPD IPD IPU IPU IPD IPD IPD IPD IPD Timer 1 or general-purpose output Timer 1 or general-purpose input TIMER 0 Timer 0 or general-purpose output Timer 0 or general-purpose input McBSP1 external clock source (as opposed to internal) McBSP1 receive clock McBSP1 transmit clock McBSP1 receive data McBSP1 transmit data McBSP1 receive frame sync McBSP1 transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) McBSP0 external clock source (as opposed to internal) McBSP0 receive clock McBSP0 transmit clock McBSP0 receive data McBSP0 transmit data McBSP0 receive frame sync I/O/Z IPU EMIF external data NO. TYPE IPD/ IPU DESCRIPTION EMIF (32-bit) - DATA (CONTINUED)
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
FSX0 I/O/Z IPD McBSP0 transmit frame sync I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.)
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PRODUCT PREVIEW
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU RESERVED FOR TEST Z RSV RSV Z IPD For proper device operation, these RSV pins (AD11, AD12) must be externally pulled down to ground with a 10-k resistor. For proper device operation, this RSV pin (D15) must be externally pulled up to DVDD with a 1-k resistor. DESCRIPTION
RSV
Reserved. These pins must be connected directly to CVDD for proper device operation.
RSV IPD IPU
Reserved. This pin must be connected directly to DVDD for proper device operation.
PRODUCT PREVIEW
IPU IPU IPU IPD IPU IPU IPD IPD IPD IPD IPU RSV IPU IPU IPU IPD IPD Z IPU IPU IPU IPD Z Z Z Z I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.) Reserved (leave unconnected, do not connect to power or ground)
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION RESERVED FOR TEST (CONTINUED) IPU IPU IPU IPU IPU Z Z Z Z Z Z Z IPU IPU IPU IPU IPU Z Z RSV Z Z Z Z Z IPU IPU IPU IPU IPD Z Z Z Z Z Z IPU IPU IPU IPU I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.) Reserved (leave unconnected, do not connect to power or ground)
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION RESERVED FOR TEST (CONTINUED) IPU IPU IPU IPU IPU IPU IPU IPU IPD IPD IPU IPD IPU
PRODUCT PREVIEW
IPU IPU IPU IPU IPU IPU RSV IPD IPD IPD IPD IPU IPU IPU IPU IPD IPD IPU IPD IPD IPD IPU IPU IPU IPU IPU I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.) Reserved (leave unconnected, do not connect to power or ground)
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION RESERVED FOR TEST (CONTINUED) IPD
IPU IPU RSV IPU IPU IPU IPU IPD IPU IPU IPU IPU I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used, unless otherwise noted.) Reserved (leave unconnected, do not connect to power or ground)
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE DESCRIPTION SUPPLY VOLTAGE PINS
PRODUCT PREVIEW
DVDD
S
3.3-V supply voltage
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
DVDD
3.3-V supply voltage
S
CVDD
1-V supply voltage
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
PRODUCT PREVIEW
CVDD
S
1-V supply voltage
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE GROUND PINS DESCRIPTION
VSS
GND
Ground pins
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE DESCRIPTION GROUND PINS (CONTINUED)
PRODUCT PREVIEW
VSS
GND
Ground pins
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
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Terminal Functions (Continued)
SIGNAL NAME NO. TYPE DESCRIPTION GROUND PINS (CONTINUED)
VSS
GND
Ground pins
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
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development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 DSP family member devices, including documentation. See this document for further information on TMS320 DSP documentation or any TMS320 DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320 DSP-related products from other companies in the industry. To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
PRODUCT PREVIEW
Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.
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device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification Fully qualified production device
TMP
TMS
Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. Fully qualified development-support product
TMDS
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GLZ), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -300 is 300 MHz). Figure 4 provides a legend for reading the complete device name for any TMS320C6000 DSP platform member.
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device and development-support tool nomenclature (continued)
TMS 320 PREFIX TMX = Experimental device TMP = Prototype device TMS = Qualified device SMX= Experimental device, MIL SMJ = MIL-PRF-38535, QML SM = High Rel (non-38535)
C 6411
GLZ
()
300 DEVICE SPEED RANGE 100 MHz 120 MHz 150 MHz 167 MHz 200 MHz 233 MHz 250 MHz 300 MHz 400 MHz 500 MHz 600 MHz
DEVICE FAMILY 320 = TMS320t DSP family
TEMPERATURE RANGE (DEFAULT: 0C TO 90C) Blank = 0C to 90C, commercial temperature A = -40C to 105C, extended temperature PACKAGE TYPE GFN = 256-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA GLW = 340-pin plastic BGA GNY = 384-pin plastic BGA GNZ = 352-pin plastic BGA GLZ = 532-pin plastic BGA GHK = 288-pin plastic MicroStar BGAt DEVICE C6000 DSP: 6201 6204 6711 6414 6202 6205 6711B 6415 6202C 6211 6712 6416 6203B 6211B 6713 6203C 6701 6411
TECHNOLOGY C = CMOS
PRODUCT PREVIEW
BGA =
Ball Grid Array
Figure 4. TMS320C6000 DSP Device Nomenclature (Including the TMS320C6411 Device)
MicroStar BGA is a trademark of Texas Instruments.
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documentation support
Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on the C6000 DSP platform of devices, such as the 64-/32-/16-bit external memory interfaces (EMIFs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, multichannel buffered serial ports (McBSPs), an 8-bit Universal Test and Operations PHY Interface for ATM Slave (UTOPIA Slave) port, 32-/16-bit host-port interfaces (HPIs), a peripheral component interconnect (PCI), expansion bus (XB), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); general-purpose timers, general-purpose input/output (GPIO) port, and power-down modes. This guide also includes information on internal data and program memories.
The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x digital signal processor, and discusses the application areas that are enhanced by the C64x DSP VelociTI.2 VLIW architecture. The TMS320C6414 Fixed-Point Digital Signal Processor data sheet (literature number SPRS134) describes the features of the TMS320C6414 fixed-point DSP and provides pinouts, electrical specifications, and timings for the device. The TMS320C6416 Fixed-Point Digital Signal Processor data sheet (literature number SPRS164) describes the features of the TMS320C6416 fixed-point DSP and provides pinouts, electrical specifications, and timings for the device. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). See the Worldwide Web URL for Texas Instruments for more detailed information on the device compatibility and similarities/differences among the C6211, C6411, C6414, C6415, and C6416 devices, see the How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718) and How To Begin Development Today With the TMS320C6411 DSP application report (literature number SPRA374).
C67x is a trademark of Texas Instruments.
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PRODUCT PREVIEW
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x devices, associated development tools, and third-party support.
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clock PLL
Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes. To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended ranges of suppy voltage and operating case temperature table and the input and output clocks electricals section). Table 24 lists some examples of compatible CLKIN external clock sources: Table 24. Compatible CLKIN External Clock Sources
PRODUCT PREVIEW
COMPATIBLE PARTS FOR EXTERNAL CLOCK SOURCES (CLKIN)
PART NUMBER JITO-2 STA series, ST4100 series
MANUFACTURER Fox Electronix SaRonix Corporation Epson America Corning Frequency Control Integrated Circuit Systems
Oscillators
SG-636 342 MK1711-S, ICS525-02
PLL
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clock PLL (continued)
3.3 V CPU Clock EMI filter C1 10 F C2 0.1 F /8 PLLV /4 CLKMODE0 (See Table 25) CLKOUT4, McBSP Internal Clock CLKOUT6 Timer Internal Clock /2 Configuration Bus
PLLMULT
/6
PLL x6 00 01 10 ECLKIN_SEL[1:0]
CLKIN
PLLCLK
1 0
/4
/2 ECLKIN Internal to C6411 EMIF 00 01 10 EK2RATE (GBLCTL.[19,18])
(For the PLL Options, CLKMODE0 Pin Setup, and PLL Clock Frequency Ranges, see Table 25.)
ECLKOUT1
ECLKOUT2
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000 DSP device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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clock PLL (continued)
Table 25. TMS320C6411 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time
GLZ PACKAGE - 23 x 23 mm BGA CLKMODE0 0 1 CLKMODE (PLL MULTIPLY FACTORS) Bypass (x1) [default] x6 CLKIN RANGE (MHz) 30-75 30-50 CPU CLOCK FREQUENCY RANGE (MHz) 30-75 180-300 CLKOUT4 RANGE (MHz) 7.5-18.8 45-75 CLKOUT6 RANGE (MHz) 5-12.5 30-50 TYPICAL LOCK TIME (s) N/A
75 These clock frequency range values are applicable to a C6411-300 speed device. Use an external pullup resistor on the CLKMODE0 pin to set the C6411 device to the valid PLL multiply clock mode (x6). With an internal pulldown resistor on the CLKMODE0 pin, the default clock mode is x1 (bypass). Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s.
PRODUCT PREVIEW
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power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. system-level design considerations System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board. power-supply design considerations A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail. Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
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absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage ranges: CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 2.3 V DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage ranges: (except PCI), VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V (PCI), VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Output voltage ranges: (except PCI), VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V (PCI), VOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to DVDD + 0.5 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65_C to 150_C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN CVDD DVDD Supply voltage, Core Supply voltage, I/O Supply ground High-level input voltage (except PCI) Low-level input voltage (except PCI) Input voltage (PCI) High-level input voltage (PCI) Low-level input voltage (PCI) except CLKOUT4 and CLKOUT6 IOH IOL High-level output current Low-level output current CLKOUT4 and CLKOUT6 except CLKOUT4 and CLKOUT6 CLKOUT4 and CLKOUT6 -0.5 0.5DVDD -0.5 0.97 3.14 0 2 0.8 DVDD + 0.5 DVDD + 0.5 0.3DVDD -8 -16 8 16 NOM 1 3.3 0 MAX 1.03 3.46 0 UNIT V V V V V V V V mA mA mA mA
PRODUCT PREVIEW
VSS VIH VIL VIP VIHP VILP
TC Operating case temperature 0 90 _C Future variants of the C6411 DSP may operate at voltages ranging from 1.0 V to 1.4 V to provide a range of system power/performance options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.1 V, 1.2 V, 1.3 V, 1.4 V with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of C641x devices.
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electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)
PARAMETER VOH VOHP VOL VOLP II IIP IOZ ICDD IDDD Ci High-level output voltage (except PCI) High-level output voltage (PCI) Low-level output voltage (except PCI) Low-level output voltage (PCI) Input current (except PCI) Input leakage current (PCI) Off-state output current Core supply current I/O supply current Input capacitance TEST CONDITIONS DVDD = MIN, IOHP = -0.5 mA, DVDD = MIN, IOLP = 1.5 mA, VI = VSS to DVDD 0 < VIP < DVDD, IOH = MAX 3.3 V IOL = MAX 3.3 V 3.3 V TBD 125 10 MIN 2.4 0.9DVDD 0.4 0.1DVDD 150 10 10 TYP MAX UNIT V V V V uA uA uA mA mA pF
VO = DVDD or 0 V CVDD = 1 V, CPU clock = 300 MHz DVDD = 3.3 V, CPU clock = 300 MHz
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PRODUCT PREVIEW
Co Output capacitance 10 pF For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs. Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6411 Power Consumption Summary application report (literature number SPRA373).
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PARAMETER MEASUREMENT INFORMATION
IOL Tester Pin Electronics 50 Output Under Test
Vcomm
CT IOH Where: IOL IOH Vcomm CT = = = = 1 A 1 A 0.5 V 6.35-pF typical load-circuit capacitance
Figure 6. Test Load Circuit for AC Timing Measurements
PRODUCT PREVIEW
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.
Vref = 1.5 V
Figure 7. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks, VILP MAX and VIHP MIN for PCI input clocks, and VOLP MAX and VOHP MIN for PCI output clocks.
Vref = VIH MIN (or VOH MIN or VIHP MIN or VOHP MIN) Vref = VIL MAX (or VOL MAX or VILP MAX or VOLP MAX)
Figure 8. Rise and Fall Transition Time Voltage Reference Levels
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PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 26 and Figure 9). Figure 9 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device. Table 26. IBIS Timing Parameters Example (see Figure 9)
NO. 1 2 3 4 5 6 7 8 9 10 11 ECLKOUTx (Output from DSP) 1 ECLKOUTx (Input to External Device) Control Signals (Output from DSP) 4 5 Control Signals (Input to External Device) Data Signals (Output from External Device) Data Signals (Input to DSP) Control signals include data for Writes. Data signals are generated during Reads from an external device. 6 7 8 3 2 DESCRIPTION Clock route delay Minimum DSP setup time External device hold time requirement External device setup time requirement Control signal route delay External device hold time External device access time DSP hold time requirement DSP setup time requirement Data route delay Minimum DSP hold time
10 11
9
Figure 9. IBIS Input/Output Timings
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PRODUCT PREVIEW
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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INPUT AND OUTPUT CLOCKS timing requirements for CLKIN (see Figure 10)
-300 NO. 1 2 3 tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN low PLL MODE x6 MIN MAX x1 (BYPASS) MIN MAX ns ns ns ns UNIT
4 Transition time, CLKIN The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. For more details on the PLL multiplier factor (x6), see the Clock PLL section of this data sheet. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
1 2
4
PRODUCT PREVIEW
CLKIN 3 4
Figure 10. CLKIN Timing
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INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT4 (see Figure 11)
-300 NO. 1 2 3 4 tc(CKO4) tw(CKO4H) tw(CKO4L) tt(CKO4) Cycle time, CLKOUT4 Pulse duration, CLKOUT4 high Pulse duration, CLKOUT4 low Transition time, CLKOUT4 PARAMETER CLKMODE = x1, x6 MIN MAX ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. P = 1/CPU clock frequency in nanoseconds (ns)
1 2 CLKOUT4 3
4
4
Figure 11. CLKOUT4 Timing
switching characteristics over recommended operating conditions for CLKOUT6 (see Figure 12)
-300 NO. 1 2 3 4 tc(CKO6) tw(CKO6H) tw(CKO6L) tt(CKO6) Cycle time, CLKOUT6 Pulse duration, CLKOUT6 high Pulse duration, CLKOUT6 low Transition time, CLKOUT6 PARAMETER CLKMODE = x1, x6 MIN MAX ns ns ns ns UNIT
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. P = 1/CPU clock frequency in nanoseconds (ns) 1 2 CLKOUT6 3 4
4
Figure 12. CLKOUT6 Timing
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
INPUT AND OUTPUT CLOCKS (CONTINUED) timing requirements for ECLKIN (see Figure 13)
-300 NO. 1 2 3 4 tc(EKI) tw(EKIH) tw(EKIL) tt(EKI) Cycle time, ECLKIN Pulse duration, ECLKIN high Pulse duration, ECLKIN low Transition time, ECLKIN MIN MAX UNIT ns ns ns ns
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 1 2 ECLKIN 3 4
PRODUCT PREVIEW
4
Figure 13. ECLKIN Timing
switching characteristics over recommended operating conditions for ECLKOUT1# (see Figure 14)
-300 NO. 1 2 3 4 5 6 tc(EKO1) tw(EKO1H) tw(EKO1L) tt(EKO1) td(EKIH-EKO1H) td(EKIL-EKO1L) PARAMETER Cycle time, ECLKOUT1 Pulse duration, ECLKOUT1 high Pulse duration, ECLKOUT1 low Transition time, ECLKOUT1 Delay time, ECLKIN high to ECLKOUT1 high Delay time, ECLKIN low to ECLKOUT1 low MIN MAX UNIT ns ns ns ns ns ns
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns. # EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns.
ECLKIN 6 5 ECLKOUT1 2 1 3
4
4
Figure 14. ECLKOUT1 Timing
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INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for ECLKOUT2 (see Figure 15)
-300 NO. 1 2 3 4 5 tc(EKO2) tw(EKO2H) tw(EKO2L) tt(EKO2) td(EKIH-EKO2H) td(EKIH-EKO2L) PARAMETER Cycle time, ECLKOUT2 Pulse duration, ECLKOUT2 high Pulse duration, ECLKOUT2 low Transition time, ECLKOUT2 Delay time, ECLKIN high to ECLKOUT2 high MIN MAX UNIT ns ns ns ns ns ns
6 Delay time, ECLKIN high to ECLKOUT2 low The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns. N = the EMIF input clock divider; N = 1, 2, or 4.
6
ECLKIN 1 2 ECLKOUT2 3 4 4
Figure 15. ECLKOUT2 Timing
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PRODUCT PREVIEW
5
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles (see Figure 16 and Figure 17)
-300 NO. 3 4 6 tsu(EDV-AREH) th(AREH-EDV) tsu(ARDY-EKO1H) th(EKO1H-ARDY) Setup time, EDx valid before ARE high Hold time, EDx valid after ARE high Setup time, ARDY valid before ECLKOUT1 high MIN MAX UNIT ns ns ns
7 Hold time, ARDY valid after ECLKOUT1 high ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers.
switching characteristics over recommended operating conditions for asynchronous memory cycles (see Figure 16 and Figure 17)
PRODUCT PREVIEW
-300 NO. 1 2 5 8 9 10 11 12 13 14 tosu(SELV-AREL) toh(AREH-SELIV) td(EKO1H-AREV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKO1H-AWEV) tosu(PDTV-AREL) toh(AREH-PDTIV) tosu(PDTV-AWEV) toh(AWEH-PDTIV) PARAMETER Output setup time, select signals valid to ARE low Output hold time, ARE high to select signals invalid Delay time, ECLKOUT1 high to ARE vaild Output setup time, select signals valid to AWE low Output hold time, AWE high to select signals invalid Delay time, ECLKOUT1 high to AWE vaild Output setup time, PDT valid to ARE low Output hold time, ARE high to PDT invalid Output setup time, PDT valid to AWE valid Output hold time, AWE high to PDT invalid MIN MAX UNIT ns ns ns ns ns ns ns ns ns
ns RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT1 period in ns Select signals for EMIF include: CEx, BE[3:0], EA[21:2], AOE; and for EMIF writes, include ED[31:0].
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 ECLKOUT1 1 CEx 1 BE[3:0] 1 EA[21:2] Address 3 4 ED[31:0] 1 AOE/SDRAS/SOE 5 ARE/SDCAS/SADS/SRE AWE/SDWE/SWE 6 ARDY 11 PDT AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data is not latched into EMIF. 12 Read Data 2 5 BE 2 2 2 Strobe = 3 Not Ready Hold = 2
7 6
7
Figure 16. Asynchronous Memory Read Timing
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 ECLKOUT1 8 CEx 8 BE[3:0] 8 EA[21:2] 8 ED[31:0] AOE/SDRAS/SOE ARE/SDCAS/SADS/SRE Write Data Address 9 BE 9 9 9 Strobe = 3 Not Ready Hold = 2
PRODUCT PREVIEW
10 AWE/SDWE/SWE 7 6 ARDY 13 PDT 6
10
7
14
AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z).
Figure 17. Asynchronous Memory Write Timing
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING timing requirements for programmable synchronous interface cycles (see Figure 18)
-300 NO. 6 7 tsu(EDV-EKOxH) th(EKOxH-EDV) Setup time, read EDx valid before ECLKOUTx high Hold time, read EDx valid after ECLKOUTx high MIN MAX UNIT ns ns
switching characteristics over recommended operating synchronous interface cycles (see Figure 18-Figure 20)
NO. 1 2 3 4 5 8 9 10 11 12 td(EKOxH-CEV) td(EKOxH-BEV) td(EKOxH-BEIV) td(EKOxH-EAV) td(EKOxH-EAIV) td(EKOxH-ADSV) td(EKOxH-OEV) td(EKOxH-EDV) td(EKOxH-EDIV) td(EKOxH-WEV) PARAMETER Delay time, ECLKOUTx high to CEx valid Delay time, ECLKOUTx high to BEx valid Delay time, ECLKOUTx high to BEx invalid Delay time, ECLKOUTx high to EAx valid Delay time, ECLKOUTx high to EAx invalid Delay time, ECLKOUTx high to SADS/SRE valid Delay time, ECLKOUTx high to, SOE valid Delay time, ECLKOUTx high to EDx valid Delay time, ECLKOUTx high to EDx invalid Delay time, ECLKOUTx high to SWE valid
conditions
for
programmable
-300 MIN MAX UNIT ns ns ns ns ns ns ns ns ns ns
13 td(EKOxH-PDTV) Delay time, ECLKOUTx high to PDT valid ns The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
READ latency = 2 ECLKOUTx 1 CEx BE[3:0] EA[21:2] 2 BE1 4 EA1 EA2 6 ED[31:0] 8 ARE/SDCAS/SADS/SRE 9 9 AOE/SDRAS/SOE AWE/SDWE/SWE PDT The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIF CE Space Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data is not latched into EMIF. 13 13 Q1 EA3 EA3 7 Q2 Q3 Q4 8 3 BE2 BE3 BE4 5 EA4 1
PRODUCT PREVIEW
Figure 18. Programmable Synchronous Interface Read Timing (With Read Latency = 2)
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
ECLKOUTx 1 CEx 2 BE1 4 EA1 10 ED[31:0] ARE/SDCAS/SADS/SRE AOE/SDRAS/SOE 12 AWE/SDWE/SWE PDT 13 13 12 10 Q1 8 3 BE2 BE3 BE4 5 EA2 EA3 EA4 11 Q2 Q3 Q4 8 1
BE[3:0]
EA[21:2]
The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z).
Figure 19. Programmable Synchronous Interface Write Timing (With Write Latency = 0)
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
Write Latency = 1 ECLKOUTx 1 CEx BE[3:0] EA[21:2] ED[31:0] 8 ARE/SDCAS/SADS/SRE AOE/SDRAS/SOE 2 BE1 4 EA1 10 EA2 10 Q1 EA3 Q2 EA4 11 Q3 Q4 8 3 BE2 BE3 BE4 5 1
PRODUCT PREVIEW
12 AWE/SDWE/SWE 13 PDT
12 13
The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIF CE Space Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0. The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC): - Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency - Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency - CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued (CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1). - Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles (RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1). - Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2 ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during programmable synchronous interface accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z).
Figure 20. Programmable Synchronous Interface Write Timing (With Write Latency = 1)
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 21)
-300 NO. 6 7 tsu(EDV-EKO1H) th(EKO1H-EDV) Setup time, read EDx valid before ECLKOUT1 high Hold time, read EDx valid after ECLKOUT1 high MIN MAX UNIT ns ns
switching characteristics over recommended operating conditions for synchronous DRAM cycles (see Figure 21-Figure 28)
-300 NO. 1 2 3 4 5 8 9 10 11 12 13 14 td(EKO1H-CEV) td(EKO1H-BEV) td(EKO1H-BEIV) td(EKO1H-EAV) td(EKO1H-EAIV) td(EKO1H-CASV) td(EKO1H-EDV) td(EKO1H-EDIV) td(EKO1H-WEV) td(EKO1H-RAS) td(EKO1H-ACKEV) td(EKO1H-PDTV) PARAMETER Delay time, ECLKOUT1 high to CEx valid Delay time, ECLKOUT1 high to BEx valid Delay time, ECLKOUT1 high to BEx invalid Delay time, ECLKOUT1 high to EAx valid Delay time, ECLKOUT1 high to EAx invalid Delay time, ECLKOUT1 high to SDCAS valid Delay time, ECLKOUT1 high to EDx valid Delay time, ECLKOUT1 high to EDx invalid Delay time, ECLKOUT1 high to SDWE valid Delay time, ECLKOUT1 high to SDRAS valid Delay time, ECLKOUT1 high to SDCKE valid Delay time, ECLKOUT1 high to PDT valid MIN MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ ECLKOUT1 1 CEx BE[3:0] 4 Bank 4 Column 4 EA12 6 ED[31:0] D1 7 D2 D3 D4 2 BE1 5 3 BE2 BE3 BE4 1
EA[21:13] EA[11:2]
5
5
PRODUCT PREVIEW
AOE/SDRAS/SOE 8 ARE/SDCAS/SADS/SRE AWE/SDWE/SWE 14 PDT ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data is not latched into EMIF. 14 8
Figure 21. SDRAM Read Command (CAS Latency 3)
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
SYNCHRONOUS DRAM TIMING (CONTINUED)
WRITE ECLKOUT1 1 CEx 2 BE[3:0] 4 EA[21:13] 4 EA[11:2] 4 EA12 9 ED[31:0] AOE/SDRAS/SOE 8 ARE/SDCAS/SADS/SRE 11 AWE/SDWE/SWE 14 PDT ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z). 14 11 8 D1 9 D2 D3 D4 10 Column 5 Bank 5 BE1 5 4 BE2 BE3 BE4 3 2
Figure 22. SDRAM Write Command
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV ECLKOUT1 1 CEx BE[3:0] 4 Bank Activate 4 Row Address 4 Row Address 5 1
EA[21:13] EA[11:2]
5
5
EA12 ED[31:0]
12
12
PRODUCT PREVIEW
AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
Figure 23. SDRAM ACTV Command
DCAB ECLKOUT1 1 CEx BE[3:0] EA[21:13, 11:2] 4 EA12 ED[31:0] 12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS 11 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 11 12 5 1
Figure 24. SDRAM DCAB Command
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
SYNCHRONOUS DRAM TIMING (CONTINUED)
DEAC ECLKOUT1 1 CEx BE[3:0] 4 EA[21:13] EA[11:2] 4 EA12 ED[31:0] 12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS 11 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 11 12 5 Bank 5 1
Figure 25. SDRAM DEAC Command
REFR ECLKOUT1 1 CEx BE[3:0] EA[21:13, 11:2] EA12 ED[31:0] 12 AOE/SDRAS/SSOE 8 ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 8 12 1
Figure 26. SDRAM REFR Command
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
SYNCHRONOUS DRAM TIMING (CONTINUED)
MRS ECLKOUT1 1 CEx BE[3:0] 4 MRS value 5 1
EA[21:2] ED[31:0]
12 AOE/SDRAS/SSOE 8 ARE/SDCAS/SSADS 11
12
8
11
PRODUCT PREVIEW
AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
Figure 27. SDRAM MRS Command
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SYNCHRONOUS DRAM TIMING (CONTINUED)
TRAS cycles Self Refresh ECLKOUT1 ACEx BE[3:0] EA[21:13, 11:2] EA12 ED[31:0] AOE/SDRAS/SOE ARE/SDCAS/SADS/ SRE AWE/SDWE/SWE 13 SDCKE ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 13 End Self-Refresh
Figure 28. SDRAM Self-Refresh Timing
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles (see Figure 29)
-300 NO. 3 toh(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns. MIN MAX UNIT ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles (see Figure 29)
-300 NO. 1 2 4 5 6 7 td(HOLDL-EMHZ) td(EMHZ-HOLDAL) td(HOLDH-EMLZ) td(EMLZ-HOLDAH) td(HOLDL-EKOHZ) td(HOLDH-EKOLZ) PARAMETER Delay time, HOLD low to EMIF Bus high impedance Delay time, EMIF Bus high impedance to HOLDA low Delay time, HOLD high to EMIF Bus low impedance Delay time, EMIF Bus low impedance to HOLDA high Delay time, HOLD low to ECLKOUTx high impedance Delay time, HOLD high to ECLKOUTx low impedance MIN MAX UNIT ns ns ns ns ns
PRODUCT PREVIEW
ns E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns. EMIF Bus consists of: CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE , SDCKE, SOE3, and PDT. The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0, ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 29. All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. DSP Owns Bus External Requestor Owns Bus 3 HOLD 2 HOLDA EMIF Bus 1 C6411 4 C6411 5 DSP Owns Bus
ECLKOUTx 6 ECLKOUTx EMIF Bus consists of: CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE, SDCKE, SOE3, and PDT. 7
Figure 29. HOLD/HOLDA Timing
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
BUSREQ TIMING switching characteristics over recommended operating conditions for the BUSREQ cycles (see Figure 30)
-300 NO. 1 td(AEKO1H-ABUSRV) ECLKOUT1 PARAMETER Delay time, AECLKOUT1 high to ABUSREQ valid MIN MAX UNIT ns
1 BUSREQ
1
Figure 30. BUSREQ Timing
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
RESET TIMING timing requirements for reset (see Figure 31)
-300 NO. Width of the RESET pulse (PLL stable) 1 16 17 tw(RST) tsu(boot) th(boot) Width of the RESET pulse (PLL needs to sync up) Setup time, boot configuration bits valid before RESET high Hold time, boot configuration bits valid after RESET high MIN MAX UNIT ns s ns
ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6 when CLKIN and PLL are stable. This parameter applies to CLKMODE x6 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 s to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5 are the boot configuration pins during device reset.
switching characteristics over recommended operating conditions during reset#|| (see Figure 31)
-300
PRODUCT PREVIEW
NO. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 td(RSTL-ECKI) td(RSTH-ECKI) td(RSTL-ECKO1HZ) td(RSTH-ECKO1V) td(RSTL-EMIFZHZ) td(RSTH-EMIFZV) td(RSTL-EMIFHIV) td(RSTH-EMIFHV) td(RSTL-EMIFLIV) td(RSTH-EMIFLV) td(RSTL-LOWIV) td(RSTH-LOWV) td(RSTL-ZHZ) td(RSTH-ZV)
PARAMETER Delay time, RESET low to ECLKIN synchronized internally Delay time, RESET high to ECLKIN synchronized internally Delay time, RESET low to ECLKOUT1 high impedance Delay time, RESET high to ECLKOUT1 valid Delay time, RESET low to EMIF Z high impedance Delay time, RESET high to EMIF Z valid Delay time, RESET low to EMIF high group invalid Delay time, RESET high to EMIF high group valid Delay time, RESET low to EMIF low group invalid Delay time, RESET high to EMIF low group valid Delay time, RESET low to low group invalid Delay time, RESET high to low group valid Delay time, RESET low to Z group high impedance Delay time, RESET high to Z group valid
MIN
MAX
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. # E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns. || EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, SDCKE, and PDT. EMIF high group consists of: HOLDA (when the corresponding HOLD input is high) EMIF low group consists of: BUSREQ; HOLDA (when the corresponding HOLD input is low) Low group consists of: XSP_CS, XSP_CLK, and XSP_DO; all of which apply only when PCI EEPROM (EEAI) is enabled (with PCI_EN = 1). Otherwise, the XSP_CLK and XSP_DO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet. Z group consists of: HD[31:0]/AD[31:0], CLKX0, CLKX1, XSP_CLK, FSX0, FSX1, DX0, DX1, XSP_DO, CLKR0, CLKR1, FSR0, FSR1, TOUT0, TOUT1, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, and HINT/PFRAME.
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RESET TIMING (CONTINUED)
CLKOUT4 CLKOUT6 1 RESET 2 ECLKIN 4 ECLKOUT1 ECLKOUT2 6 EMIF Z Group 8 EMIF High Group 10 EMIF Low Group 12 Low Group 14 Z Group 17 Boot and Device Configuration Inputs EMIF Z group consists of: 16 13 11 9 7 5 3
15
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, SDCKE, and PDT. EMIF high group consists of: HOLDA (when the corresponding HOLD input is high) EMIF low group consists of: BUSREQ; HOLDA (when the corresponding HOLD input is low) Low group consists of: XSP_CS, XSP_CLK, and XSP_DO; all of which apply only when PCI EEPROM (EEAI) is enabled (with PCI_EN = 1). Otherwise, the XSP_CLK and XSP_DO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section of this data sheet. Z group consists of: HD[31:0]/AD[31:0], CLKX0, CLKX1, XSP_CLK, FSX0, FSX1, DX0, DX1, XSP_DO, CLKR0, CLKR1, FSR0, FSR1, TOUT0, TOUT1, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, and HINT/PFRAME. If LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5 pins are actively driven, care must be taken to ensure no timing contention between parameters 6, 7, 14, 15, 16, and 17. Boot and Device Configurations Inputs (during reset) include: LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5. The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.
Figure 31. Reset Timing
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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EXTERNAL INTERRUPT TIMING timing requirements for external interrupts (see Figure 32)
-300 NO. 1 tw(ILOW) tw(IHIGH) Width of the interrupt pulse low MIN MAX UNIT ns ns
2 Width of the interrupt pulse high P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. 2
1 EXT_INTx/GPx, NMI
Figure 32. External/NMI Interrupt Timing
PRODUCT PREVIEW
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HOST-PORT INTERFACE (HPI) TIMING timing requirements for host-port interface cycles (see Figure 33 through Figure 40)
-300 NO. 1 2 3 4 10 11 12 13 14 18 tsu(SELV-HSTBL) th(HSTBL-SELV) tw(HSTBL) tw(HSTBH) tsu(SELV-HASL) th(HASL-SELV) tsu(HDV-HSTBH) th(HSTBH-HDV) th(HRDYL-HSTBL) tsu(HASL-HSTBL) th(HSTBL-HASL) Setup time, select signals valid before HSTROBE low Hold time, select signals valid after HSTROBE low Pulse duration, HSTROBE low Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals valid before HAS low Hold time, select signals valid after HAS low Setup time, host data valid before HSTROBE high Hold time, host data valid after HSTROBE high Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. Setup time, HAS low before HSTROBE low MIN MAX UNIT ns ns ns ns ns ns ns ns ns ns ns
19 Hold time, HAS low after HSTROBE low HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL. Select the parameter value of 4P or 12.5 ns, whichever is greater.
switching characteristics over recommended operating conditions during host-port interface cycles (see Figure 33 through Figure 40)
-300 NO. 5 6 7 8 9 15 16 17 td(HCS-HRDY) td(HSTBL-HRDYH) td(HSTBL-HDLZ) td(HDV-HRDYL) toh(HSTBH-HDV) td(HSTBH-HDHZ) td(HSTBL-HDV) PARAMETER Delay time, HCS to HRDY# Delay time, HSTROBE low to HRDY high|| Delay time, HSTROBE low to HD low impedance for an HPI read Delay time, HD valid to HRDY low Output hold time, HD valid after HSTROBE high Delay time, HSTROBE high to HD high impedance Delay time, HSTROBE low to HD valid (HPI16 only) MIN MAX UNIT ns ns ns ns ns ns ns
td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY highk ns HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. # HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. || This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is full. kThis parameter is used after a word (HPI32) or the second half-word (HPI16) of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS 1 HCNTL[1:0] 1 HR/W 1 HHWIL HSTROBE HCS 7 HD[15:0] (output) 5 1st halfword 8 2nd halfword 17 5 15 9 16 15 9 3 4 3 2 1 2 2 1 2 1 2 2
PRODUCT PREVIEW
HRDY (case 1) 6 HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 8 17 5
Figure 33. HPI16 Read Timing (HAS Not Used, Tied High)
HAS 10 HCNTL[1:0] 11 10 HR/W 11 10 HHWIL HSTROBE HCS 7 HD[15:0] (output) 5 HRDY (case 1) 6 HRDY (case 2) For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 8 17 5 1st half-word 8 2nd half-word 17 5 18 15 9 16 9 3 4 18 15 10 11 10 11 19 11 10 19 11
Figure 34. HPI16 Read Timing (HAS Used)
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HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS 1 2 HCNTL[1:0] 1 HR/W 1 HHWIL 3 4 HSTROBE HCS 12 HD[15:0] (input) 5 HRDY (case 1) 6 HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 17 5 1st halfword 2nd halfword 17 5 13 12 13 14 3 2 1 2 2 1 2
1 2
Figure 35. HPI16 Write Timing (HAS Not Used, Tied High)
19 HAS 10 HCNTL[1:0] 11 10 HR/W 11 10 HHWIL 3 HSTROBE HCS HD[15:0] (input) 5 HRDY (case 1) 6 HRDY (case 2) 1st half-word 18 12 14 4 10 10 11 10
19 11
11
11
18 13 2nd half-word 12 13
17 17
5 5
For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 36. HPI16 Write Timing (HAS Used)
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS 1 HCNTL[1:0] 1 HR/W HSTROBE HCS 7 HD[31:0] (output) 5 HRDY (case 1) 6 HRDY (case 2) 8 17 5 8 17 5 9 15 3 2 2
PRODUCT PREVIEW
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 37. HPI32 Read Timing (HAS Not Used, Tied High)
19 HAS 11 10 HCNTL[1:0] 11 10 HR/W 18 HSTROBE HCS 7 HD[31:0] (output) 5 HRDY (case 1) 6 HRDY (case 2) For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 8 17 5 8 17 5 9 15 3
Figure 38. HPI32 Read Timing (HAS Used)
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HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS 1 HCNTL[1:0] 1 HR/W 3 14 HSTROBE HCS 12 HD[31:0] (input) 5 HRDY (case 1) 6 17 5 17 5 13 2 2
HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 39. HPI32 Write Timing (HAS Not Used, Tied High)
19 HAS 11 10 HCNTL[1:0] 11 10 HR/W 3 18 HSTROBE HCS 12 HD[31:0] (input) 5 HRDY (case 1) 6 HRDY (case 2) For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 17 5 17 5 13 14
Figure 40. HPI32 Write Timing (HAS Used)
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING timing requirements for PCLK (see Figure 41)
-300 NO. 1 2 3 4 tc(PCLK) tw(PCLKH) tw(PCLKL) tsr(PCLK) Cycle time, PCLK Pulse duration, PCLK high Pulse duration, PCLK low v/t slew rate, PCLK MIN MAX UNIT ns ns ns V/ns
For 3.3 V operation, the reference points for the rise and fall transitions are measured at VILP MAX and VIHP MIN. 0.4 DVDD V MIN Peak to Peak for 3.3V signaling
1 2 PCLK 3
4
PRODUCT PREVIEW
4
Figure 41. PCLK Timing
timing requirements for PCI reset (see Figure 42)
-300 NO. 1 2 tw(PRST) tsu(PCLKA-PRSTH) Pulse duration, PRST Setup time, PCLK active before PRST high PCLK 1 PRST 2 MIN MAX UNIT ms s
Figure 42. PCI Reset (PRST) Timing
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PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING (CONTINUED) timing requirements for PCI inputs (see Figure 43)
-300 NO. 5 6 tsu(IV-PCLKH) th(IV-PCLKH) Setup time, input valid before PCLK high Hold time, input valid after PCLK high MIN MAX UNIT ns ns
switching characteristics over recommended operating conditions for PCI outputs (see Figure 43)
-300 NO. 1 2 3 4 td(PCLKH-OV) td(PCLKH-OIV) td(PCLKH-OLZ) td(PCLKH-OHZ) PARAMETER Delay time, PCLK high to output valid Delay time, PCLK high to output invalid Delay time, PCLK high to output low impedance Delay time, PCLK high to output high impedance PCLK 1 2 PCI Output 3 4 PCI Input 5 6 Valid Valid MIN MAX UNIT ns ns ns ns
Figure 43. PCI Intput/Output Timing
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING (CONTINUED) timing requirements for serial EEPROM interface (see Figure 44)
-300 NO. 8 9 tsu(DIV-CLKH) th(CLKH-DIV) Setup time, XSP_DI valid before XSP_CLK high Hold time, XSP_DI valid after XSP_CLK high MIN MAX UNIT ns ns
switching characteristics over recommended operating conditions for serial EEPROM interface (see Figure 44)
-300 NO. 1 2 3 4 tw(CSL) td(CLKL-CSL) td(CSH-CLKH) tw(CLKH) tw(CLKL) tosu(DOV-CLKH) PARAMETER Pulse duration, XSP_CS low Delay time, XSP_CLK low to XSP_CS low Delay time, XSP_CS high to XSP_CLK high Pulse duration, XSP_CLK high Pulse duration, XSP_CLK low Output setup time, XSP_DO valid after XSP_CLK high MIN NOM MAX UNIT ns ns ns ns ns ns ns
PRODUCT PREVIEW
5 6
7 toh(CLKH-DOV) Output hold time, XSP_DO valid after XSP_CLK high P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. 2 1 XSP_CS 3 XSP_CLK 6 XSP_DO 8 XSP_DI 9 7 4 5
Figure 44. PCI Serial EEPROM Interface Timing
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MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING timing requirements for McBSP (see Figure 45)
-300 NO. 2 3 5 6 7 8 10 11 tc(CKRX) tw(CKRX) tsu(FRH-CKRL) th(CKRL-FRH) tsu(DRV-CKRL) th(CKRL-DRV) tsu(FXH-CKXL) th(CKXL-FXH) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Setup time, external FSR high before CLKR low Hold time, external FSR high after CLKR low Setup time, DR valid before CLKR low Hold time, DR valid after CLKR low Setup time, external FSX high before CLKX low Hold time, external FSX high after CLKX low CLKR/X ext CLKR/X ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKX int CLKX int CLKX ext ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. The maximum bit rate for McBSP-to-McBSP communications is 75 MHz; therefore, the minimum CLKR/X clock cycle is either four times the CPU cycle time (4P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 300 MHz (P = 3.33 ns), use 13.33 ns (75 MHz) as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 200 MHz (P = 5 ns), use 4P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a Master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a Slave. CLKX ext ns ns ns ns ns MIN MAX UNIT ns ns
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP (see Figure 45)
-300 NO. 1 2 3 4 9 12 13 td(CKSH-CKRXH) tc(CKRX) tw(CKRX) td(CKRH-FRV) td(CKXH-FXV) tdis(CKXH-DXHZ) td(CKXH-DXV) PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Delay time, CLKR high to internal FSR valid Delay time, CLKX high to internal FSX valid Disable time, DX high impedance following last data bit from CLKX high Delay time, CLKX high to DX valid Delay time, FSX high to DX valid 14 td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode CLKR/X int CLKR/X int CLKR int CLKX int CLKX ext CLKX int CLKX ext CLKX int CLKX ext FSX int ns FSX ext || || || || ns ns ns # # MIN MAX UNIT ns ns ns ns
PRODUCT PREVIEW
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. The maximum bit rate for McBSP-to-McBSP communications is 75 MHz; therefore, the minimum CLKR/X clock cycle is either four times the CPU cycle time (4P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 300 MHz (P = 3.33 ns), use 13.33 ns (75 MHz) as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 200 MHz (P = 5 ns), use 4P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies to the following hardware configuration: the serial port is a Master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a Slave. # C = H or L S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see footnote above). || Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P
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MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKS 1 3 3 CLKR 4 FSR (int) 5 FSR (ext) 7 DR 2 3 CLKX 9 3 Bit(n-1) 8 (n-2) (n-3) 6 4 2
11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3)
Figure 45. McBSP Timing
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FSX (int)
TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 46)
-300 NO. 1 2 tsu(FRH-CKSH) th(CKSH-FRH) Setup time, FSR high before CLKS high Hold time, FSR high after CLKS high MIN MAX UNIT ns ns
CLKS 1 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) 2
Figure 46. FSR Timing When GSYNC = 1
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MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 47)
-300 NO. 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low MASTER MIN MAX SLAVE MIN MAX ns ns UNIT
5 Hold time, DR valid after CLKX low P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 47)
-300 NO. 1 2 3 6 7 th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ) PARAMETER Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX low Disable time, DX high impedance following last data bit from FSX high MASTER MIN MAX SLAVE MIN MAX ns ns ns ns UNIT ns
8 td(FXL-DXV) Delay time, FSX low to DX valid ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 3 Bit(n-1) 5 (n-2) (n-3) (n-4) (n-2) (n-3) (n-4) 2
Figure 47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 48)
-300 NO. 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MASTER MIN MAX SLAVE MIN MAX ns ns UNIT
5 Hold time, DR valid after CLKX high P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 48)
-300 NO. 1 2 3 6 th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) tdis(CKXL-DXHZ) PARAMETER Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX low MASTER MIN MAX SLAVE MIN MAX ns ns ns UNIT ns
7 td(FXL-DXV) Delay time, FSX low to DX valid ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
CLKX 1 FSX 6 Bit 0 7 Bit(n-1) 4 DR Bit 0 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
DX
Figure 48. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 49)
-300 NO. 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MASTER MIN MAX SLAVE MIN MAX ns ns UNIT
5 Hold time, DR valid after CLKX high P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 49)
-300 NO. 1 2 3 6 7 th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ) tdis(FXH-DXHZ) PARAMETER Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX high Disable time, DX high impedance following last data bit from FSX high MASTER MIN MAX SLAVE MIN MAX ns ns ns ns ns UNIT
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8 td(FXL-DXV) Delay time, FSX low to DX valid ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
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MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 Bit(n-1) 5 (n-2) (n-3) (n-4) 3 (n-2) (n-3) (n-4) 2
Figure 49. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
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MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED) timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 50)
-300 NO. 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MASTER MIN MAX SLAVE MIN MAX ns ns UNIT
5 Hold time, DR valid after CLKX high P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 50)
-300 NO. 1 2 3 6 th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) PARAMETER Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX high MASTER MIN MAX SLAVE MIN MAX ns ns ns ns UNIT
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7 td(FXL-DXV) Delay time, FSX low to DX valid ns P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP # FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).
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MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKX 1 FSX 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 7 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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TIMER TIMING timing requirements for timer inputs (see Figure 51)
-300 NO. 1 tw(TINPH) tw(TINPL) Pulse duration, TINP high MIN MAX UNIT ns ns
2 Pulse duration, TINP low P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
switching characteristics over recommended operating conditions for timer outputs (see Figure 51)
-300 NO. 3 4 tw(TOUTH) tw(TOUTL) Pulse duration, TOUT high Pulse duration, TOUT low PARAMETER MIN MAX UNIT ns ns
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
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2 1 TINPx 3 TOUTx 4
Figure 51. Timer Timing
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING timing requirements for GPIO inputs (see Figure 52)
-300 NO. 1 tw(GPIH) tw(GPIL) Pulse duration, GPIx high MIN MAX UNIT ns ns
2 Pulse duration, GPIx low P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
switching characteristics over recommended operating conditions for GPIO outputs (see Figure 52)
-300 NO. 3 4 tw(GPOH) tw(GPOL) Pulse duration, GPOx high Pulse duration, GPOx low PARAMETER MIN MAX UNIT ns ns
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns. 2 1 GPIx 3 GPOx 4
Figure 52. GPIO Port Timing
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TMS320C6411 FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS196 - MARCH 2002
JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 53)
-300 NO. 1 3 4 tc(TCK) tsu(TDIV-TCKH) th(TCKH-TDIV) Cycle time, TCK Setup time, TDI/TMS/TRST valid before TCK high Hold time, TDI/TMS/TRST valid after TCK high MIN MAX UNIT ns ns ns
switching characteristics over recommended operating conditions for JTAG test port (see Figure 53)
-300 NO. 2 td(TCKL-TDOV) PARAMETER Delay time, TCK low to TDO valid MIN MAX UNIT ns
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1 TCK 2 TDO 4 3 TDI/TMS/TRST 2
Figure 53. JTAG Test-Port Timing
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MECHANICAL DATA
GLZ (S-PBGA-N532)
23,10 22,90 SQ 0,80 0,40
AF AE AD AC AB AA Y V U T R P
PLASTIC BALL GRID ARRAY
20,00 TYP
A1 Corner
N M K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26
0,40
L
0,80
W
Heat Slug 3,30 MAX 1,00 NOM
Bottom View
Seating Plane 0,55 0,45 0,10 M
0,45 0,35
0,12 4201884/C 11/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Thermally enhanced plastic package with heat slug (HSL) Flip chip application only
thermal resistance characteristics (S-PBGA package)
NO 1 2 3 4 5 6 7 RJC RJB RJA RJA RJA RJA PsiJT Junction-to-case Junction-to-board Junction-to-free air Junction-to-free air Junction-to-free air Junction-to-free air Junction-to-package top C/W 1.4 4.9 17.5 14.5 12.5 10.4 0.7 4.5 Air Flow (m/s) N/A 0.00 0.00 0.75 1.25 2.00 N/A N/A
8 PsiJB Junction-to-board m/s = meters per second
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