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TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996
D D D D D D D D
10-Bit Resolution A/D Converter Microprocessor Peripheral or Standalone Operation On-Chip 12-Channel Analog Multiplexer Built-In Self-Test Mode Software-Controllable Sample-and-Hold Function Total Unadjusted Error . . . 1 LSB Max Pinout and Control Signals Compatible With TLC540 and TLC549 Families of 8-Bit A/D Converters CMOS Technology
PARAMETER Channel Acquisition Sample Time Conversion Time (Max) Samples Per Second (Max) Power Dissipation (Max) VALUE 5.5 s 21 s 32 x 103 6 mW
DW OR N PACKAGE (TOP VIEW)
INPUT A0 INPUT A1 INPUT A2 INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7 INPUT A8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC SYSTEM CLOCK I/O CLOCK ADDRESS INPUT DATA OUT CS REF + REF - INPUT A10 INPUT A9
FN PACKAGE (TOP VIEW)
description
The TLC1541 is a CMOS A/D converter built around a 10-bit switched-capacitor successiveapproximation A/D converter. The device is designed for serial interface to a microprocessor or peripheral using a 3-state output with up to four control inputs ( including independent SYSTEM CLOCK, I/O CLOCK, chip select [CS], and ADDRESS INPUT ). A 2.1-MHz system clock for the TLC1541, with a design that includes simultaneous read/write operation, allows highspeed data transfers and sample rates up to 32 258 samples per second. In addition to the high-speed converter and versatile control logic, there is an on-chip, 12-channel analog multiplexer that can be used to sample any one of 11 inputs or an internal self-test voltage and a sample-andhold function that operates automatically.
INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
INPUT A2 INPUT A1 INPUT A0 VCC SYSTEM CLOCK I/O CLOCK ADDRESS INPUT DATA OUT CS REF +
PACKAGE PLASTIC CHIP CARRIER (FN) TLC1541CFN TLC1541IFN PLASTIC DIP (N) TLC1541CN TLC1541IN
Copyright (c) 1996, Texas Instruments Incorporated
AVAILABLE OPTIONS SMALL OUTLINE (DW) TLC1541CDW TLC1541IDW
TA
0C to 70C - 40C to 85C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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INPUT A8 GND INPUT A9 INPUT A10 REF-
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TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996
description (continued)
The converters incorporated in the TLC1541 feature differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally switched-capacitor design allows low-error conversion in 21 s over the full operating temperature range. The TLC1541 is available in DW, FN, and N packages. The C-suffix versions are characterized for operation from 0C to 70C. The I-suffix versions are characterized for operation from - 40C to 85C.
functional block diagram
REF+ 14 1 2 3 4 5 6 7 8 9 11 12 REF- 13
Sample and Hold
10-Bit Switched-Capacitors Analog-to-Digital Converter 10 Output Data Register 10-to-1 Data Selector and Driver
ANALOG INPUTS
12-Channel Analog Multiplexer
10
16
4
Input Address Register
DATA OUT
4 4 Self-Test Reference ADDRESS INPUT 17 Input Multiplexer 2 Control Logic and I/O Counters
I/O CLOCK CS SYSTEM CLOCK
18 15 19
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE 1 k TYP INPUT A0 - A10 Ci = 60 pF TYP (equivalent input capacitance) INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
INPUT A0 - A10 5 M TYP
2
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TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996
operating sequence
1 2 3 4 5 6 7 8 9 10 Don't Access Cycle B Sample Cycle B Care Access Cycle C Sample Cycle C 1 2 3 4 5 6 7 8 9 10
I/O CLOCK
tconv See Note A
CS
See Note C MSB LSB Don't Care twH(CS) MSB LSB Don't Care HI-Z State B9 A9 LSB MSB MSB B8 B7 B6 B5 B4 B3 Conversion Data B B2 B1 B0 B9 LSB MSB C3 C2 C1 C0 HI-Z State
ADDRESS INPUT DATA OUT
B3 B2 B1 B0
A9
A8 A7
A6 A5
A4 A3 A2 A1
A0
Previous Conversion Data A MSB (see Note B)
NOTES: A. The conversion cycle, which requires 44 system clock periods, initiates on the tenth falling edge of the I/O clock after CS goes low for the channel whose address exists in memory at that time. When CS is kept low during conversion, the I/O clock must remain low for at least 44 system clock cycles to allow the conversion to complete. B. The most significant bit (MSB) is automatically placed on the DATA OUT bus after CS is brought low. The remaining nine bits (A8-A0) clock out on the first nine I/O clock falling edges. C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a chip-select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the minimum chip-select setup time elapses.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Peak input current (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: DW or N package . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to digital ground with REF - and GND wired together (unless otherwise noted).
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TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996
recommended operating conditions
MIN Supply voltage, VCC Positive reference voltage, Vref + (see Note 2) Negative reference voltage, Vref - (see Note 2) Differential reference voltage, Vref + - Vref - (see Note 2) Analog input voltage (see Note 2) High-level control input voltage, VIH Low-level control input voltage, VIL Input/output clock frequency, fclock(I/O) System clock frequency, fclock(SYS) Setup time, address bits before I/O CLOCK, tsu(A) Hold time, address bits after I/O CLOCK, th(A) Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Operating Sequence) 0 fclock(I/O) 400 0 3 4.75 2.5 - 0.1 1 0 2 0.8 1.1 2.1 NOM 5 VCC 0 VCC MAX 5.5 VCC + 0.1 2.5 VCC + 0.2 VCC UNIT V V V V V V V MHz MHz ns ns System clock cycles System clock cycles ns ns ns ns 30 20 100 40 0 - 40 70 85 ns ns C
Pulse duration, CS high during conversion, twH(CS) (see Operating Sequence) Pulse duration, SYSTEM CLOCK high, twH(SYS) Pulse duration, SYSTEM CLOCK low, twL(SYS) Pulse duration, I/O CLOCK high, twH(I/O) Pulse duration, I/O CLOCK low, twL(I/O) System Clock transition time (see Note 4) I/O O erating Operating free-air tem erature, TA temperature C suffix I suffix fclock(SYS) 1048 kHz fclock(SYS) > 1048 kHz fclock(I/O) 525 kHz fclock(I/O) > 525 kHz
44 210 190 404 404
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied to REF - convert as all zeros (0000000000). For proper operation, REF + voltage must be at least 1 V higher than REF - voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V. 3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three system clock cycles (or less) after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum chip select setup time elapses. 4. The amount of time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 s for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996
electrical characteristics over recommended operating temperature range, VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 1.1 MHz, fclock(SYS) = 2.1 MHz (unless otherwise noted)
PARAMETER VOH VOL IOZ IIH IIL ICC High-level output voltage (terminal 16) Low-level output voltage High-impedance-state High impedance state output current High-level input current Low-level input current Operating supply current TEST CONDITIONS VCC = 4.75 V, VCC = 4.75 V, VO = VCC, VO = 0, VI = VCC VI = 0 CS at 0 V Selected channel at VCC, Unselected channel at 0 V Selected channel at 0 V, Unselected channel at VCC Vref+ = VCC, Analog inputs Control inputs CS at 0 V IOH = 360 A IOL = 3.2 mA CS at VCC CS at VCC 0.005 - 0.005 1.2 0.4 - 0.4 1.3 7 5 MIN 2.4 0.4 10 - 10 2.5 - 2.5 2.5 1 A -1 3 55 15 mA pF TYP MAX UNIT V V A A A mA
Selected channel leakage current
ICC + Iref Ci
Supply and reference current Input capacitance
All typical values are at VCC = 5 V and TA = 25C.
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TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996
operating characteristics over recommended operating temperature range, VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 1.1 MHz, fclock(SYS) = 2.1 MHz
PARAMETER EL EZS EFS ET Linearity error Zero-scale error Full-scale error Total unadjusted error Self-test output code tconv Conversion time Total access and conversion time Channel acquisition time (sample cycle) Time output data remains valid after I/O CLOCK Delay time, I/O CLOCK to DATA OUT valid Output enable time Output disable time Data bus rise time See Figure 1 See Operating Sequence TEST CONDITIONS See Note 5 See Notes 2 and 6 See Notes 2 and 6 See Note 7 Input A11 address = 1011 (see Note 8) 0111110100 (500) MIN MAX 1 1 1 1 1000001100 (524) 21 31 6 s s I/O clock cycles ns 400 150 150 300 ns ns ns ns UNIT LSB LSB LSB LSB
tv td ten tdis tr(bus)
10
tf(bus) Data bus fall time 300 ns NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied to REF - convert as all zeros (0000000000). For proper operation, REF + voltage must be at least 1 V higher than REF - voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V. 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. 6. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference between 1111111111 and the converted output for full-scale input voltage. 7. Total unadjusted error includes linearity, zero-scale, and full-scale errors. 8. Both the input address and the output codes are expressed in positive logic. The A11 analog input signal is internally generated and used for test purposes.
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SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
1.4 V 3 k Output Under Test CL (see Note A) Test Point Output Under Test CL (see Note A) Test Point 3 k Output Under Test CL (see Note A) See Note B LOAD CIRCUIT FOR tPZL AND tPLZ VCC CS 50% 0V VCC 3 k Test Point
LOAD CIRCUIT FOR td, tr, AND tf
See Note B LOAD CIRCUIT FOR tPZH AND tPHZ
SYSTEM CLOCK tPZL Output Waveform 1 (see Note C) See Note B tPZH Output Waveform 2 (see Note C) 50% 10% tPHZ 90% 50% 0V VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES VOH 0V tPLZ VCC
I/O CLOCK td
0.4 V
Output
2.4 V 0.4 V
DATA OUT
2.4 V 0.4 V
tr(bus)
tf(bus)
VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES
VOLTAGE WAVEFORMS FOR DELAY TIME NOTES: A. CL = 50 pF B. ten = tPZH or tPZL and tdis = tPHZ or tPLZ. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
Figure 1. Load Circuits and Voltage Waveforms
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TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996
APPLICATION INFORMATION simplified analog input analysis
Using the equivalent circuit in Figure 2, the time required to charge the analog input capacitance from 0 V to VS within 1/2 LSB can be derived as follows: The capacitance charging voltage is given by VC = VS 1- e where Rt = Rs + ri The final voltage to 1/2 LSB is given by VC (1/2 LSB) = VS - (VS /2048) Equating equation 1 to equation 2 and solving for time (tc) gives - t /R C VS - (VS/2048) = VS 1- e c t i (2)
(
- tc /RtCi
)
(1)
(
)
(3) (4)
and tc (1/2 LSB) = Rt x Ci x ln(2048) Therefore, with the values given, the time for the analog input signal to settle is tc (1/2 LSB) = (Rs + 1 k) x 55 pF x ln(2048) This time must be less than the converter sample time shown in the timing diagrams.
Driving Source Rs VS ri VC 1 k MAX Ci 55 pF MAX TLC1541
(5)
VI
VI = Input Voltage at INPUT A0 - A10 VS = External Driving Source Voltage Rs = Source Resistance ri = Input Resistance Ci = Input Capacitance Driving source requirements: * Noise and distortion levels for the source must be at least equivalent to the resolution of the converter. * Rs must be real at the input frequency.
Figure 2. Equivalent Input Circuit Including the Driving Source
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TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996
PRINCIPLES OF OPERATION
The TLC1541 is a complete data acquisition system on a single chip. The device includes such functions as sample and hold, 10-bit A/D converter, data and control registers, and control logic. For flexibility and access speed, there are four control inputs: chip select (CS), address input, I/O clock, and system clock. These control inputs and a TTL-compatible, 3-state output are intended for serial communications with a microprocessor or microcomputer. The TLC1541 can complete conversions in a maximum of 21 s, while complete input-conversion output cycles can be repeated at a maximum of 31 s. The system and I/O clocks are normally used independently and do not require any special speed or phase relationships between them. This independence simplifies the hardware and software control tasks for the device. Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and software need only be concerned with addressing the desired analog channel, reading the previous conversion result, and starting the conversion by using I/O CLOCK. SYSTEM CLOCK drives the conversion-crunching circuitry so that the control hardware and software need not be concerned with this task. When CS is high, DATA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature allows each of these terminals, with the exception of the CS terminal, to share a control logic point with its counterpart terminals on additional A/D devices when using additional TLC1541 devices. In this way, the above feature serves to minimize the required control logic terminals when using multiple A/D devices. The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain the conversion result. A normal control sequence is: 1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and then a falling edge of SYSTEM CLOCK after a low CS transition before recognizing the low transition. This technique protects the device against noise when the device is used in a noisy environment. The MSB of the previous conversion result automatically appears on DATA OUT. 2. A new positive-logic multiplexer address shifts in on the first four rising edges of I/O CLOCK. The MSB of the address shifts in first. The negative edges of these four I/O clock pulses shift out the second, third, fourth, and fifth most-significant bits of the previous conversion result. The on-chip sample-and-hold begins sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically involves the charging of internal capacitors to the level of the analog input voltage. 3. Five clock cycles are then applied to the I/O CLOCK, and the sixth, seventh, eighth, ninth, and tenth conversion bits shift out on the negative edges of these clock cycles. 4. The final tenth-clock cycle is applied to the I/O CLOCK. The falling edge of this clock cycle completes the analog sampling process and initiates the hold function. Conversion is then performed during the next 44 system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low for at least 44 system-clock cycles to allow for the conversion function. CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise glitches on I/O CLOCK. When glitches occur on I/O CLOCK, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also, when CS goes high, it must remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion in progress. A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through 4 before the 44 system-clock cycles occur. Such action yields the conversion result of the previous conversion and not the ongoing conversion.
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TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS
SLAS073C - DECEMBER 1995 - REVISED AUGUST 1996
PRINCIPLES OF OPERATION
It is possible to connect SYSTEM CLOCK and I/O CLOCK together in special situations in which controlling-circuitry points must be minimized. In this case, the following special points must be considered in addition to the requirements of the normal control sequence previously described. 1. This device requires the first two clocks to recognize that CS is at a valid low level when the common clock signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock signal is used for the conversion clock also. 2. A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address. Also, upon shifting in the address, CS must be raised after the tenth valid (12 total) I/O CLOCK. Otherwise, additional common-clock cycles are recognized as I/O CLOCK cycles and shift in an erroneous address. For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time. This device accommodates these applications. Although the on-chip sample-and-hold begins sampling upon the negative edge of the fourth valid I/O CLOCK cycle, the hold function does not initiate until the negative edge of the tenth valid I/O CLOCK cycle. Thus, the control circuitry can leave the I/O CLOCK signal in its high state during the tenth valid I/O CLOCK cycle until the moment at which the analog signal must be converted. The TLC1541 continues sampling the analog input until the eighth valid falling edge of the I/O CLOCK. The control circuitry or software then immediately lowers the I/O CLOCK signal and holds the analog signal at the desired point in time and starts the conversion.
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Copyright (c) 1998, Texas Instruments Incorporated
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