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| THS7530 www.ti.com SLOS405A - DECEMBER 2002- REVISED APRIL 2003 HIGH SPEED, FULLY DIFFERENTIAL, CONTINUOUSLY VARIABLE GAIN AMPLIFIER FEATURES D Low Noise: Vn = 1.1 nV/ Hz, D D D Noise Figure = 9 dB Low Distortion: - HD2 = -65 dBc, HD3 = -61 dBc at 32 MHz - IMD3 = -62 dBc, OIP3 = 21 dBm at 70 MHz 300 MHz Bandwidth Continuously Variable Gain Range: 11.6 dB to 46.5 dB Gain Slope: 38.8 dB/V Fully Differential Input and Output DESCRIPTION The THS7530 is fabricated using Texas Instruments' state-of-the-art BiCom III SiGe complementary bipolar process. The THS7530 is a dc-coupled wide bandwidth amplifier with voltage-controlled gain. The amplifier has high impedance differential inputs and low impedance differential outputs with high bandwidth gain control, output common mode control, and output voltage clamping. Signal channel performance is exceptional with 300-MHz bandwidth, and third harmonic distortion of -61 dBc at 32 MHz with 1 VPP output into 400 . Gain control is linear in dB with 0 V to 0.9 V varying the gain from 11.6 dB to 46.5 dB with 38.8-dB/V gain slope. Output voltage limiting is provided to limit the output voltage swing, and prevent saturating following stages. The device is characterized for operation over the industrial temperature range: -40C to 85C. D D D Output Common-Mode Voltage Control D Output Voltage Limiting APPLICATIONS D Time Gain Amplifiers in Ultra Sound, Sonar, D D D and Radar Automatic Gain Control in Communication and Video System Gain Calibration in Communications Variable Gain in Instrumentation AGC APPLICATION 1 k 0.1 F 24.9 0.1 F VIN+ VIN- VOCM 0.1 F 0.1 F VS- PD VG- THS7530 24.9 VCL+ VCL- 1 k VS+ = 5 V 0.1 F 33 pF 24.9 6.8 F 0.1 F VOUT+ VOUT- 24.9 33 pF 0.1 F VG+ AGC detect VREF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002 - 2003, Texas Instruments Incorporated THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGING/ORDERING INFORMATION PRODUCT THS7530 PACKAGE TSSOP PowerPAD PACKAGE DESIGNATOR PWP-14 PWP 14 SYMBOL THS7530 TEMPERATURE RANGE, TA -40C to 85C 40C ORDERING NUMBER THS7530PWP THS7530PWPR TRANSPORT MEDIA Tube Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) THS7530 Supply voltage, VS+ - Vs- Input voltage, VI Output current, IO (2) Differential input voltage, VID Continuous power dissipation Maximum junction temperature, TJ Maximum junction temperature for long term stability, TJ Operating free-air temperature range, TA Storage temperature range, Tstg Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds HBM ESD CDM MM 5.5 V VS 65 mA 4 V See Dissipation Rating Table 150C 125C -40C to 85C -65C to 150C 300C 3000 V 1500 V 200 V (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The THS7530 incorporates a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package. RECOMMENDED OPERATING CONDITIONS TEST CONDITIONS Supply voltage, [VS- to VS+] Operating free-air temperature, TA Input common mode voltage Output common mode voltage [VS- to VS+] = 5 V [VS- to VS+] = 5 V MIN 4.5 -40 2.5 2.5 TYP 5 MAX 5.5 85 UNIT V C V V PACKAGE THERMAL DATA PACKAGE 14PWP PCB See Layout Considerations in the application section of this data sheet. JA ( C/W) 37.5 JC ( C/W) 2.07 TA = 25C POWER RATING 3W PowerPAD is a trademark of Texas Instruments. 2 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 SPECIFICATIONS: MAIN AMPLIFIER VS+ = 5 V, VS- = 0 V, VOCM = 2.5 V, VICM = 2.5 V, VG- = 0 V, VG+ = 1 V (maximum gain), TA = 25C, ac performance measured using the ac test circuit shown in Figure 1 (unless otherwise noted). DC performance is measured using the dc test circuit shown in Figure 2 (unless otherwise noted) TYP PARAMETER AC PERFORMANCE (See Figure 1) Small-signal bandwidth Slew rate(1) Settling time to 1%(1) Harmonic distortion 2nd Harmonic 3rd Harmonic Third-order intermodulation distortion All gains, PIN = -45 dBm 1 VPP Step, 25% to 75%, minimum gain 1 VPP Step, minimum gain VO(PP) = 1 V, RL(diff)= 400 f = 32 MHz f = 32 MHz PO = -10 dBm each tone, fC=70 MHz, 200 kHz tone spacing fC=70 MHz, 200 kHz tone spacing Source impedance: 50 f > 100 kHz 300 1250 11 -65 -61 -62 MHz V/s ns dBc dBc dBc Typ Typ Typ Typ Typ Typ TEST CONDITIONS 25 C 25 C OVER TEMPERATURE -40 C to 85 C UNITS MIN/ MAX Third-order output intercept point Noise figure (with input termination) Total input voltage noise DC PERFORMANCE--INPUTS (See Figure 2) Input bias current Input bias current offset Minimum input voltage Maximum input voltage Common-mode rejection ratio Differential input impedance DC PERFORMANCE--OUTPUTS (See Figure 2) Output offset voltage Maximum output voltage high Minimum output voltage low Output current Output impedance 21 9 1.1 20 <150 39 1.6 3.35 56 40 1.7 3.2 44 dBm dB nV/Hz A pA V V dB k || pF 340 3.275 1.7 16 480 3.25 1.8 16 mV V V mA MHz V/V 12 13.8 mV V V k || pF V A Typ Typ Typ Max Typ Max Min Min Typ Max Min Max Min Typ Typ Typ Max Typ Typ Typ Typ Typ Minimum gain Minimum gain 1.5 3.5 114 8.5 || 3.0 All gains 100 3.5 1.5 37 15 32 1.00 4.5 1.75 3.25 25 || 1 2.5 <1 OUTPUT COMMON-MODE VOLTAGE CONTROL (See Figure 2) Small-signal bandwidth Gain Common-mode offset voltage Minimum input voltage Maximum input voltage Input impedance Default voltage, with no connect Input bias current (1) Slew rate and settling time measured at amplifier output. 3 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 SPECIFICATIONS: MAIN AMPLIFIER (CONTINUED) VS+ = 5 V, VS- = 0 V, VOCM = 2.5 V, VICM = 2.5 V, VG- = 0 V, VG+ = 1 V (maximum gain), TA = 25C, ac performance measured using the ac test circuit shown in Figure 1 (unless otherwise noted). DC performance is measured using the dc test circuit shown in Figure 2 (unless otherwise noted) TYP PARAMETER GAIN CONTROL (See Figure 2) Gain control differential voltage range Minus gain control voltage Minimum gain Maximum gain Gain slope Gain slope variation Gain G i error Gain control input bias current Gain control input resistance Gain control bandwith VOLTAGE CLAMPING (See Figure 2) Output voltages (VOUT) relative to clamp voltages (VCL) VCL input resistance VCL voltage limits POWER SUPPLY (See Figure 2) Specified operating voltage Maximum quiescent current Power supply rejection (PSRR) POWERDOWN (See Figure 2) Enable voltage threshold Disable voltage threshold Power-down quiescent current Input current high Input current low Input impedance Turnon time delay Turnoff time delay Forward isolation in power down Input resistance in power down Output resistance in power down Measured to 50% quiescent current TTL low = normal operation TTL high = shut down 1.4 1.4 0.35 9 109 50 || 1 820 500 80 >1 16 0.4 16 116 1.0 1.65 0.45 19 119 V V mA A A k || pF ns ns dB M k Min Max Max Max Max Typ Typ Typ Typ Typ Typ 5 40 77 5.5 48 70 5.5 49 45 V mA dB Max Max Min In voltage limiting mode 25 3.3 Vs- to Vs+ 38 60 mV k V Max Typ Typ Small signal -3 dB VG+ VG- - VS- VG+ = 0 V VG+ = 0.9 V VG+ = 0 V to 0.9 V VG+ = 0 V to 0.9 V VG+ = 0 V to 0.15 V VG+ = 0.15 V to 0.9 V 0 to 1 -0.6 to 0.8 11.6 46.5 38.8 1.5 4 2.25 <1 40 15 V V dB dB dB/V dB/V dB dB A k MHz Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ Typ TEST CONDITIONS 25 C 25 C OVER TEMPERATURE -40 C to 85 C UNITS MIN/ MAX 4 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 VS+ = 5 V 1 k 0.1 F VCL+ VCL- 1 k 0.1 F 33 pF 24.9 VOCM PD 0.1 F VS- VG- VG+ THS7530 24.9 33 pF 1:1 VOUT Coax 50 Load 50 6.8 F 50 Source Coax VIN 1:1 Figure 1. AC Test Circuit VS+ = 5 V VCL+ VCL- VIN+ VOCM VIN- 0.1 F VS- VG+ 0.1 F 6.8 F VOUT+ THS7530 PD VG- 800 VOUT- Figure 2. DC Test Circuit 5 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 PIN ASSIGNMENTS THD7530PWP (TOP VIEW) NC NC VIN+ VIN- VG+ VG- PD 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCL+ VCL- VOCM VOUT- VOUT + VS+ VS- NC - No internal connection Terminal Functions TERMINAL NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME NC NC VIN+ VIN- VG+ VG- PD VS- VS+ VOUT+ VOUT- VOCM VCL- VCL+ No internal connection No internal connection Noninverting amplifier input Inverting amplifier input Gain setting positive input Gain setting negative input Powerdown, PD = logic low puts part into low power mode, PD = logic high or open for normal operation Negative amplifier power supply input Positive amplifier power supply input Noninverted amplifier output Inverted amplifier output Output common-mode voltage input Output negative clamp voltage input Output positive clamp voltage input DESCRIPTION 6 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 TYPICAL CHARACTERISTICS TABLE OF GRAPHS Measured using the ac test circuit shown in Figure 1 (unless otherwise noted). FIGURE Voltage Gain to Load Gain and Gain Error Noise Figure Output Intercept Point 1-dB Compression Point Total Input Voltage Noise Intermodulation Distortion Harmonic Distortion S-Parameters Differential Input Impedance of Main Amplifier Differential Output Impedance of Main Amplifier VG+ Input Impedance VOCM Input Impedance Common-Mode Rejection Ratio Step Response - 2 VPP Step Response - Rising Edge Step Response - Falling Edge vs Frequency (Input at 45 dBm) vs VG+ vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Time vs Time vs Time 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VOLTAGE GAIN TO LOAD vs FREQUENCY (PIN = -45 dBm) 50 Maximum Gain 40 Voltage Gain to Load - dB 45 40 GAIN AND GAIN ERROR vs VG+ 0.4 0.2 35 Gain Gain Error - dB 30 Gain - dB 25 -0.2 20 15 Minimum Gain 10 -0.6 5 0 1000 0 200 400 600 800 -0.8 1000 Gain Error -0.4 0 30 20 10 0 -10 1 Gain is taken at load. Add 6 dB to refer to amplifier output. 10 100 f - Frequency - MHz V - VG+ - mV Figure 3 Figure 4 7 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 NOISE FIGURE vs FREQUENCY 35 Gain = 20 dB Output Intercept Point - dBm 30 NF - Noise Figure - dB 25 Gain = 30 dB 20 15 Gain = 40 dB 10 Terminated Input 5 0 50 100 150 200 250 300 f - Frequency - MHz 60 55 50 45 40 35 30 25 20 15 10 0 OUTPUT INTERCEPT POINT vs FREQUENCY 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 dB COMPRESSION POINT vs FREQUENCY Taken at load. Add 3 dB to refer to amplifier output OIP2 OIP3 Taken at load. Add 3 dB to refer to amplifier output 50 100 150 200 250 300 1 dB Compression Point - dBm 50 100 150 200 250 300 f - Frequency - MHz f - Frequency - MHz Figure 5 TOTAL INPUT VOLTAGE NOISE vs FREQUENCY Hz 100 Figure 6 INTERMODULATION DISTORTION vs FREQUENCY -45 -50 IMD 2 and IMD 3 - dBc IMD2 HD2 and HD3 - dBc -55 -60 IMD3 -65 -70 -75 VG+ = 1 V, VO = 1 VPP (Composite), RL = 400 0 50 100 150 200 -54 -56 -58 -60 -62 -64 -66 -68 -70 0 10 -50 -52 Figure 7 HARMONIC DISTORTION vs FREQUENCY RL = 400 VO = 1 Vpp, VG+ = 1 V V n - Total Input Voltage Noise - nV / 10 HD3 HD2 1 -80 10 100 1k 10 k 100 k 1 M 10 M 100 M f - Frequency - Hz f - Frequency - MHz 20 30 40 50 60 70 f - Frequency - MHz Figure 8 S-PARAMETERS vs FREQUENCY 0 Differential Input Impedance - k Differential Input Impedance - k -10 -20 -30 -40 -50 S12 -60 -70 Figure 9 DIFFERENTIAL INPUT IMPEDANCE OF MAIN AMPLIFIER vs FREQUENCY 10 9 8 7 6 5 4 3 2 1 0 100 300 0.1 1 10 100 1000 f - Frequency - MHz Differential Output Impedance - Figure 10 DIFFERENTIAL OUTPUT IMPEDANCE OF MAIN AMPLIFIER vs FREQUENCY 50 45 40 35 30 25 20 15 10 5 0 1 10 100 1000 S22 S11 0.1 10 f - Frequency - MHz 1 f - Frequency - MHz Figure 11 Figure 12 Figure 13 8 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 VG+ INPUT INPEDANCE vs FREQUENCY 100 90 V G+ - Input Inpedance - k V OCM - Input Impedance - k 80 70 60 50 40 30 20 10 0 0.1 1 f - Frequency - MHz 10 20 25 VOCM INPUT IMPEDANCE vs FREQUENCY CMRR - Common-Mode Rejection Ratio - dB COMMON-MODE REJECTION RATIO vs FREQUENCY -10 -20 15 -30 10 -40 5 -50 0 0.1 -60 0.1 1 10 100 1000 f - Frequency - MHz 1 10 100 f - Frequency - MHz Figure 14 Figure 15 Figure 16 STEP RESPONSE 1.5 1 0.5 0 -0.5 -1 -1.5 0 200 400 600 800 1000 t - Time - ns At Amplifier Output and Minimum Gain RL = 400 V O - Output Voltage - V STEP RESPONSE - RISING EDGE 1.5 STEP RESPONSE - FALLING EDGE 1.5 Amplifier Output at Minimum Gain RL = 400 0.5 V O - Output Voltage - V Amplifier Output at Minimum Gain RL = 400 0 2 4 6 8 10 12 Step Response - 2VPP 1 1 0.5 0 -0.5 -1 -1.5 0 -0.5 -1 -1.5 0 2 4 6 8 10 12 t - Time - ns t - Time - ns Figure 17 Figure 18 Figure 19 9 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 APPLICATION INFORMATION The THS7530 is designed for nominal 5-V power supply from VS+ to VS-. The amplifier has fully differential inputs, VIN+ and VIN-, and fully differential outputs, VOUT+ and VOUT- The inputs are high impedance and outputs are low impedance. External resistors are recommended for impedance matching and termination purposes. The inputs and outputs can be dc-coupled, but for best performance, the input and output common-mode voltage should be maintained at the midpoint between the two supply pins. The output common-mode voltage is controlled by the voltage applied to VOCM. Left unterminated, VOCM is set to midsupply by internal resistors. A 0.1-F bypass capacitor should be placed between VOCM and ground to reduce common-mode noise. The input common-mode voltage defaults to midrail when left unconnected. For voltages other than midrail, VOCM must be biased by external means. VIN+ and VIN- both require a nominal 30-A bias current for proper operation. Therefore, insure equal input impedance at each input to avoid generating an offset voltage that varies with gain. Voltage applied from VG- to VG+ controls the gain of the part with 38.8-dB/V gain slope. The input can be differential or single ended. VG- must be maintained within -0.6 V and +0.8 V of VS- for proper operation. The negative gain input should typically be tied directly to the negative power supply. VCL+ and VCL- are inputs that limit the output voltage swing of the amplifier. The voltages applied set an absolute limit on the voltages at the output. Input voltages at VCL+ and VCL- clamp the output insuring that neither output exceeds those values. The power-down input is a TTL compatible input, referenced to the negative supply voltage. A logic low puts the THS7530 in power savings mode. In power-down mode the part consumes less than 1-mA current, the output goes high impedance, and a high amount of isolation is maintained between the input and output. Power supply bypass capacitors are required for proper operation. A 6.8-F tantalum bulk capacitor is recommended if the amplifier is located far from the power supply and may be shared among other devices. A ceramic 0.1-F capacitor is recommended within 0.1" of the device power pin. The ceramic capacitors should be located on the same layer as the amplifier to eliminate the use of vias between the capacitors and the power pin. The following circuits show some basic circuit configurations. VS+ = 5 V 1 k 0.1 F VCL+ 50 1:1 VIN VOCM PD 0.1 F VS- VG- VG+ 33 pF THS7530 24.9 VCL- 24.9 1 k 0.1 F 33 pF 1:1 VOUT 6.8 F Figure 20. EVM Schematic: Designed for Use With Typical 50- RF Test Equipment 10 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 VS+ = 5 V 1 k 0.1 F 49.9 49.9 VCL+ VCL- 24.9 VIN VOCM PD 0.1 F VS- VG- VG+ 33 pF THS7530 24.9 0.1 F VOUT- 0.1 F VOUT+ 1 k 0.1 F 33 pF 6.8 F Figure 21. AC-Coupled Single-Ended Input With AC-Coupled Differential Output VS+ = 5 V 1 k 0.1 F 24.9 0.1 F VIN+ VIN- 0.1 F 0.1 F VS- VOCM PD VG- VG+ 33 pF THS7530 24.9 0.1 F VOUT- 24.9 VCL+ VCL- 24.9 0.1 F VOUT+ 1 k 0.1 F 33 pF 6.8 F Figure 22. AC-Coupled Diferential Input With AC-Coupled Differential Output VS+ = 5 V 1 k 0.1 F 49.9 49.9 VCL+ VCL- 24.9 VIN VOCM PD 0.1 F VS- VG+ VG- 33 pF THS7530 VOUT- 24.9 VOUT+ 1 k 0.1 F 33 pF 6.8 F Figure 23. DC-Coupled Single-Ended Input With DC-Coupled Differential Output 11 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 VS+ = 5 V 1 k 0.1 F 24.9 24.9 VCL+ VCL- 24.9 VIN+ VIN- VOCM PD 0.1 F VS- VG- VG+ 33 pF THS7530 24.9 VOUT- VOUT+ 1 k 0.1 F 33 pF 6.8 F Figure 24. DC-Coupled Differential Input With DC-Coupled Differential Output LAYOUT CONSIDERATIONS The THS7530 comes in a thermally enhance PowerPADt package. Figure 25 shows the recommended number of vias and thermal land size recommended for best performance. Thermal vias connect the thermal land to internal or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the interface between the package body and the thermal land on the surface of the board during solder reflow. The experiments conducted jointly with Solectron Texas indicate that a via drill diameter of 0.33mm (13 mils) or smaller works well when 1 ounce copper is plated at the surface of the board and simultaneously plating the barrel of the via. If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a dimension equal to the via diameter + 0,1 mm minimum. This prevents the solder from being wicked through the thermal via and potentially creating a solder void in the region between the package bottom and the thermal land on the surface of the PCB. TSSOP 14 Pin PWP 2X3 3.4 5 Figure 25. Recommended Thermal Land Size and Thermal Via Patterns (dimensions in mm) See TI's Technical Brief titled PowerPADt Thermally Enhanced Package (SLMA002) for a detailed discussion of the PowerPADt package, its dimensions, and recommended use. 12 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 THEORY OF OPERATION Figure 26 shows a simplified schematic of the THS7530. The input architecture is a modified Gilbert Cell. The output from the Gilbert Cell is converted to a voltage and buffered to the output as a fully-differential signal. A summing node between the outputs is used to compare the output common-mode voltage to the VOCM input. The VOCM error amplifier then servos the output common-mode voltage to maintain it equal to the VOCM input. Left unterminated, VOCM is set to midsupply by internal resistors. The gain control input is conditioned to give linear in dB gain control (block H). The gain control input is a differential signal from 0 V to 0.9 V which varies the gain from 11.6 dB to 46.5 dB. VCL+ and VCL- provide inputs that limit the output voltage swing of the amplifier. VCL+ VS+ x1 Output Buffer VCL- VOUT+ VOCM Error Amplifier VIN+ VIN- Power Control VOUT- VOCM PD VS- VG+ VG- H THS7530 Figure 26. THS7530 Simplified Schematic 13 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 SPICE MODEL * [Disclaimer] (C) Copyright Texas Instruments Incorporated 1999-2002 All rights reserved * Texas Instruments Incorporated hereby grants the user of this SPICE Macro-model a * non-exclusive, nontransferable license to use this SPICE Macro-model under the following * terms. Before using this SPICE Macro-model, the user should read this license. If the * user does not accept these terms, the SPICE Macro-model should be returned to Texas * Instruments within 30 days. The user is granted this license only to use the SPICE * Macro-model and is not granted rights to sell, load, rent, lease or license the SPICE * Macro-model in whole or in part, or in modified form to anyone other than user. User may * modify the SPICE Macro-model to suit its specific applications but rights to derivative * works and such modifications shall belong to Texas Instruments. This SPICE Macro-model is * provided on an "AS IS" basis and Texas Instruments makes absolutely no warranty with * respect to the information contained herein. TEXAS INSTRUMENTS DISCLAIMS AND CUSTOMER * WAIVES ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY * OR FITNESS FOR A PARTICULAR PURPOSE. The entire risk as to quality and performance is with * the Customer. ACCORDINGLY, IN NO EVENT SHALL THE COMPANY BE LIABLE FOR ANY DAMAGES, * WHETHER IN CONTRACT OR TORT,INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, CONSEQUENTIAL, * EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR APPLICATION OF THE SPICE * Macro-model provided in this package. Further, Texas Instruments reserves the right to * discontinue or make changes without notice to any product herein to improve reliability, * function, or design. Texas Instruments does not convey any license under patent rights or * any other intellectual property rights, including those of third parties. * * THS7530 SUBCIRCUIT * HIGH SPEED FULLY DIFFERENTIAL VARIABLE AMPLIFIER * WRITTEN 11/26/02 * VG- is tied to VS- and output clamping is not modeled * CONNECTIONS: * * * * * * * * .SUBCKT THS7530 * *INPUT* Q1 Q2 R1 I1 I2 14 IN+ | | | | | | | | 1 IN- | | | | | | | 2 VS+ | | | | | | 3 VS- | | | | | 4 OUT- | | | | 5 OUT+ | | | 6 VOCM | | 7 VG+ | 8 122 1 101 NPN_IN 123 2 102 NPN_IN 102 101 25 16 16 101 4 DC 4.85e-3 102 4 DC 4.85e-3 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 *QUAD* Q3 Q4 Q5 Q6 R2 R3 132 120 122 NPN 121 119 122 NPN 132 119 123 NPN 121 120 123 NPN 132 3 121 3 250 250 16 16 16 16 *CURRENT AMP* F1 VF1 *Z NODE* R4 I3 I4 V9 V10 128 129 2k 128 129 VF1 6 132 121 0V 129 4 DC 0.75e-3 128 4 DC 0.75e-3 128 328 0.7 129 329 0.7 *FREQUENCY SHAPING* E3 R5 L3 C6 E4 R9 L4 C7 131 0 329 0 1 131 140 140 133 133 0 30 7.5n 24p 130 0 328 0 1 130 141 141 125 125 0 30 10n 27p *OUTPUT BUFFER* Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 R6 R7 R10 R11 I5 I6 I7 I8 4 133 117 PNP 3 133 127 NPN 3 117 134 NPN 4 127 135 PNP 4 125 116 PNP 3 125 126 NPN 3 116 136 NPN 4 126 137 PNP 138 134 135 138 139 136 137 139 5 5.12 5.12 81.92 81.92 5.12 5.12 81.92 81.92 5 5 5 3 117 DC 0.4e-3 127 4 DC 0.4e-3 3 116 DC 0.4e-3 126 4 DC 0.4e-3 15 THS7530 www.ti.com SLOS405A DECEMBER 2002- REVISED APRIL 2003 *OUTPUT Z* R8 R12 L1 L2 C1 *VOCM Rcm1 Ccm1 Rcm2 Ccm2 E1 Rtop Rbot Q7 Q8 *GAIN CONTROL* V8 E5 E6 E7 E8 E9 V7 235 8 0.454 231 0 235 4 0.51 232 0 POLY(1) 231 0 0.0 1 1 0.5 3.5 233 0 232 0 0.115 234 0 POLY(1) 233 0 0.0 0 1 0 0.333 120 119 234 0 0.42 3 120 1.6 115 114 115 114 114 113 114 113 8k 0.1p 8k 0.1p 113 138 115 139 113 5 115 6 65 4n 4n 2p 2 2 118 0 114 7 1e3 37 47 50k 50k 16 16 128 118 3 PNP 129 118 3 PNP Rsupply 3 4 310 .MODEL NPN_IN NPN + KF=1E-12 .MODEL NPN NPN .MODEL PNP PNP .ENDS 16 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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