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| THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 LOW POWER DISSIPATION ADSL LINE DRIVER FEATURES D Low Power Dissipation Increases ADSL Line D D D D D D D Card Density Low THD of -88 dBc (100-, 1 MHz) Low MTPR Driving +20 dBm on the Line - -76 dBc With High Bias Setting - -74 dBc With Low Bias Setting Wide Output Swing of 44VPP Differential Into a 200 Differential Load (VCC = 12 V) High Output Current of 600 mA (Typ) Wide Supply Voltage Range of 5 V to 15 V Pin Compatible With EL1503C and EL1508C - Multiple Package Options Multiple Power Control Modes - 11 mA/ch Full Bias Mode - 7.5 mA/ch Mid Bias Mode - 4 mA/ch Low Bias Mode - 0.25 mA/ch Shutdown Mode - IADJ Pin for User Controlled Bias Current - Stable Operation Down to 2 mA/ch Low Noise for Increased Receiver Sensitivity - 3.2 nV/Hz Voltage Noise - 1.5 pA/Hz Noninverting Current Noise - 10 pA/Hz Inverting Current Noise 1 k +12V - CODEC VIN+ + THS6182a -12V APPLICATIONS D Ideal for Full Rate ADSL Applications DESCRIPTION The THS6182 is a current feedback differential line driver ideal for full rate ADSL systems. Its extremely low power dissipation is ideal for ADSL systems that must achieve high densities in ADSL central office rack applications. The unique architecture of the THS6182 allows the quiescent current to be much lower than existing line drivers while still achieving very high linearity without the need for excess open loop gain. Fixed multiple bias settings of the amplifiers allow for enhanced power savings for line lengths where the full performance of the amplifier is not required. To allow for even more flexibility and power savings, an IADJ pin is available to further lower the bias currents while maintaining stable operation with as little as 2 mA per channel. The wide output swing of 44 Vpp differentially with 12V power supplies allows for more dynamic headroom, keeping distortion at a minimum. With a low 3.2 nV/Hz voltage noise coupled with a low 10 pA/Hz inverting current noise, the THS6182 increases the sensitivity of the receive signals, allowing for better margins and reach. D Typical ADSL CO Line Driver Circuit Utilizing Active Impedance 8.68 1.33 k 953 1.33 k 1:1.2 +20 dBm Line Power 100 1 k +12V - CODEC VIN- + THS6182b -12V 8.68 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002 - 2003, Texas Instruments Incorporated THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage. ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE SYMBOL TA ORDER NUMBER THS6182RHFR THS6182RHF Leadless 24 in 4 mm x 24-pin 5 mm PowerPAD RHF-24 6182 THS6182RHFT -40C to 85C THS6182D THS6182DR THS6182DW THS6182DW SOIC-20 DW-20 THS6182 THS6182DWR Tape and reel (250 devices) Tube (40 devices) Tape and reel (2500 devices) Tube (25 devices) Tape and reel (2000 devices) TRANSPORT MEDIA Tape and reel (3000 devices) THS6182D SOIC-16 D-16 THS6182 PACKAGE DISSIPATION RATINGS(1) PACKAGE RHF-24 D-16 PowerPAD SOLDERED(2) JA 32C/W - PowerPAD NOT SOLDERED(3) JA 74C/W 62.9C/W JC 1.7C/W 25.7C/W DW-20 - 45.4C/W 16.4C/W (1) JA values shown are typical for standard test PCBs only. (2) For high power dissipation applications, use of the PowerPAD package and soldering the PowerPAD to the PCB is required. Failure to do so may result in reduced reliability and/or lifetime of the device. See TI technical brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package. (3) Use of packages without the PowerPAD or not soldering the PowerPAD to the PCB, should be limited to low-power dissipation applications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) ELECTRICAL Supply voltage, VCC(2) Input voltage, VI Output current, IO (2) Differential input voltage, VIO THERMAL Maximum junction temperature, any condition(3), TJ Maximum junction temperature, continuous operation, long term reliability(4), TJ Operating free-air temperature, TA Storage temperature, Tsgt 150C 125C -40C to 85C -65C to 150C THS6182 16.5 V VCC 1000 mA 2 V Lead temperature, 1,6 mm (1/16-inch) from case for 10 seconds 300C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The THS6182 may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature that could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package. (3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process. (4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. 2 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 ABSOLUTE MAXIMUM RATINGS ESD HBM ESD ratings CDM MM 500 V 1500 V 200 V RECOMMENDED OPERATING CONDITIONS MIN Dual supply Supply voltage VCC+ to VCC- voltage, Operating free-air temperature, TA Operating junction temperature, continuous operation TJ Normal storage temperature, Tstg Single supply 5 10 -40 -40 -40 NOM 12 24 MAX UNIT 15 30 85 125 85 V C C C ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, TA = 25C,VCC = 12 V, RF = 2 k, Gain = +5, IADJ = Bias1 = Bias2 = 0 V, RL = 50 (unless otherwise noted) NOISE/DISTORTION PERFORMANCE PARAMETER MTPR Multitone power ratio Receive band spillover TEST CONDITIONS Gain =+9.5, 163 kHz to 1.1 MHz DMT, +20 dBm Line Power, See Figure 1 for circuit Gain =+5, 25 kHz to 138 kHz with MTPR signal applied, See Figure 1 for circuit 2nd harmonic HD Harmonic distortion, VO(PP) = 2 V f = 1 MHz Input voltage noise In ut Input current noise Crosstalk +Input -Input 3rd harmonic Differential load = 200 Differential load = 50 Differential load = 200 Differential load = 50 MIN TYP -76 -95 -88 -70 -107 -84 3.2 1.5 10 -65 -60 3.9 3.7 10.7 10.0 13.5 12.7 350 450 450 4.1 3.9 11.0 10.6 13.9 13.4 400 600 600 1000 6 Gain = +10 Open-loop 0.05 8.5 mA k mA MAX UNIT dBc dBc dBc dBc nV/Hz pA/Hz dBc dBc Vn In VCC = 5 V, 12 V, 15 V, f = 100 kHz VCC = 5 V, 12 V 15 V, f = 100 kHz V V, V f = 1 MHz, VO(PP) = 2 V, VCC = 5 V, 12 V, 15 V RL = 100 RL = 25 RL = 100 RL = 25 RL = 100 RL = 25 RL = 100 RL = 25 VCC = 5 V VCC = 12 V VCC = 15 V VCC = 12 V OUTPUT CHARACTERISTICS VCC = 5 V VO Single-ended Single ended output voltage swing VCC = 12 V VCC = 15 V RL = 5 V V V IO I(SC) () Output Out ut current (1) Short-circuit current (1) Output resistance Output resistance--terminate mode Output resistance--shutdown mode RL = 10 RL = 1 Open-loop f = 1 MHz, f = 1 MHz, (1) A heatsink is rsequired to keep the junction temperature below absoulte maximum rating when an output is heavily loaded or shorted. See Absolute Maximum Ratings section for more information. 3 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range, TA = 25C,VCC = 12 V, RF = 2 k, Gain = +5, IADJ = Bias1 = Bias2 = 0 V, RL = 50 (unless otherwise noted) POWER SUPPLY PARAMETER VCC Operating range Dual supply Single supply VCC = 5 V Quiescent current (each driver)(1) Full-bias mode ( (Bias-1 = 0, Bias-2 = 0) , ) (Trimmed with VCC = 15 V at 25C) (T i d ith t VCC = 12 V VCC = 15 V TA = 25C TA = full range TA = 25C TA = full range TA = 25C TA = full range TEST CONDITIONS MIN TYP 12 24 9.7 11 11.5 7.5 4 0.25 -50 -47 -56 -53 -60 -56 dB MAX 16.5 33 10.7 11.7 12 12.5 12.5 13 8.5 5 0.9 mA UNIT V mA mA mA 4 8 ICC Mid; Bias-1 = 1, Bias-2 = 0 Quiescent current ( Qi t t (each d i ) h driver) Variable bias modes, VCC = 12 V modes Low; Bias-1 = 0, Bias-2 = 1 Shutdown; Bias-1 = 1, Bias-2 = 1 VCC = 5 V, VCC = 0.5 V VCC = 12 V, 15 V, VCC = 1 V TA = 25C TA = full range TA = 25C TA = full range PSRR Power su ly rejection ratio supply ( (VCC = 1 V) ) (1) Approximately 0.5 mA (total) flows from VCC+ to GND for internal logic control bias. DYNAMIC PERFORMANCE PARAMETER TEST CONDITIONS Gain = +1, RF = 1.2 k RL = 100 BW Single ended small-signal Single-ended small signal bandwidth (3 (-3 dB), VO = 0.1 Vrms RL = 25 Single-ended slew-rate(2) Gain = +2, RF = 1 k Gain = +5, RF = 1 k Gain = +10, RF = 1 k Gain = +1, RF = 1.5k Gain = +2, RF = 1 k Gain = +5, RF = 1 k Gain = +10, RF = 1 k SR VO = 10 VPP, Gain =+5 (2) Slew-rate is defined from the 25% to the 75% output levels MIN TYP 100 80 35 20 65 60 40 22 450 V/s MHz MHz MAX UNIT DC PERFORMANCE PARAMETER Input offset voltage TEST CONDITIONS TA = 25C TA = full range VCC = 5 V, 12 V, 15 V TA = 25C TA = full range TA = full range TA = 25C VCC = 5 V, 12 V 15 V V V, + Input bias current TA = full range TA = 25C MIN TYP 1 0.5 50 8 8 900 15 20 15 20 k A MAX 20 25 10 15 V/C mV UNIT VOS Differential offset voltage Offset drift -Input bias current Input IIB ZOL Open loop transimpedance TA = full range RL = 1 k, VCC = 12 V, 15 V, 4 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 ELECTRICAL CHARACTERISTICS (CONTINUED) over recommended operating free-air temperature range, TA = 25C,VCC = 12 V, RF = 2 k, Gain = +5, IADJ = Bias1 = Bias2 = 0 V, RL = 50 (unless otherwise noted) INPUT CHARACTERISTICS PARAMETER VCC = 5 V TEST CONDITIONS TA = 25C TA = full range TA = 25C TA = full range TA = 25C TA = full range TA = 25C TA = full range MIN 2.7 2.6 9.5 9.3 12.4 12.1 48 44 800 30 1.7 54 12.7 9.8 TYP 3.0 MAX UNIT V V V dB k pF VICR Input common mode voltage range common-mode VCC = 12 V VCC = 15 V CMRR Common-mode Common mode rejection ratio Input resistance Input capacitance VCC = 5 V 12 V 15 V V, V, + Input - Input RI CI LOCIC CONTROL CHARACTERISTICS PARAMETER VIH VIL IIH IIL Bias pin voltage for logic 1 Bias pin voltage for logic 0 Bias pin current for logic 1 Bias pin current for logic 0 Transition time--logic 0 to logic 1(1) Transition time--logic 1 to logic 0(1) TEST CONDITIONS Relative to GND pin voltage Relative to GND pin voltage VIH = 3.3 V, GND = 0 V VIL = 0.5 V, GND = 0 V 4 1 1 1 MIN 2.0 0.8 30 10 TYP MAX UNIT V V A A s s (1) Transition time is defined as the time from when the logic signal is applied to the time when the supply current has reached half its final value. LOGIC TABLE BIAS-1 0 1 0 BIAS-2 0 0 1 FUNCTION Full bias mode Mid bias mode Low bias mode DESCRIPTION Amplifiers ON with lowest distortion possible (default state) Amplifiers ON with power savings with a reduction in distortion performance Amplifiers ON with enhanced power savings and a reduction of distortion performance 1 1 Shutdown mode Amplifiers OFF and output has high impedance NOTE: The default state for all logic pins is a logic zero (0). 5 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 750 +18V - CODEC 4.87 THS6182a +20 dBm Line Power 100 V IN+ + 1k 1.33 k 1k 1:1.6 750 +18V - CODEC 4.87 THS6182b V IN- + Figure 1. Single-Supply ADSL CO Line Driver Circuit Utilizing Active Impedance (SF = 4) 6 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 PIN ASSIGNMENTS THS6182 SOIC-20 (DW) PACKAGE (TOP VIEW) D1 IN- 1 D1 OUT 2 VCC - 3 GND 4 GND GND GND D1 IN+ BIAS-2 BIAS-1 THS6182 SOIC-16 (D) PACKAGE (TOP VIEW) D1 IN- 1 D1 OUT V CC - GND GND D1 IN+ BIAS-2 BIAS-1 20 19 D2 IN- D2 OUT 16 15 14 13 12 11 10 9 D2 IN- D2 OUT VCC + GND GND D2 IN+ I ADJ N/C 2 3 4 5 6 7 8 18 VCC + 17 GND 16 15 14 13 12 11 GND GND GND D2 IN+ I ADJ N/C 5 6 7 8 9 10 THS6182 Leadless 24-pin PowerPAD 4 mm X 5 mm (RHF) PACKAGE (TOP VIEW) D1 OUT D2 OUT D2 IN- D1 IN- N/C N/C N/C VCC- N/C N/C N/C GND Power PAD TM N/C N/C V CC+ N/C N/C N/C GND D1IN+ BIAS-2 BIAS-1 IADJ D2IN+ 7 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Output voltage headroom Common-mode rejection ratio Crosstalk Total quiescent current Large signal output amplitude Voltage and current noise Overdrive recovery Power supply rejection ratio Output amplitude Slew rate Closed-loop output impedance Quiescent current Quiescent current Common-mode rejection ratio Input bias current Input offset voltage 2nd Harmonic distribution 3rd Harmonic distribution 2nd Harmonic distribution 3rd Harmonic distribution vs Frequency vs Frequency vs Output voltage vs Frequency vs Supply voltage vs Temperature vs Common-mode voltage vs Temperature vs Temperature vs Frequency vs Frequency vs Output voltage vs Output voltage vs Frequency vs Frequency vs Output current vs Frequency vs Frequency 2 3 4 5 6-8 9 10 11 12 - 37 38 39 40 41 42 43 44 45 - 52 53 - 60 61 - 64 65 - 68 8 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE HEADROOM vs OUTPUT CURRENT 2.5 Output Voltage Headroom -(VCC- out) V COMMON-MODE REJECTION RATIO vs FREQUENCY 80 70 VCC= 12 V Gain = 2 RL= 25 Crosstalk -dB CROSSTALK vs FREQUENCY 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 Gain = +1 Gain = +5 VCC= 12 V RL= 100 2 VCC= 12 V 1.5 VCC= 5 V CMRR -dB 60 50 40 30 20 1 0.5 10 0 0 2 00 400 600 800 O ut p ut C ur r ent - mA 0 10 k 100 k 1M 10 M 100 M 100 k 1M 10 M 100 M f - Frequency - Hz f - Frequency - Hz Figure 2 Figure 3 Figure 4 TOTAL QUIESCENT CURRENT 25 Full Bias M ode VCC= 12 V LARGE SIGNAL OUTPUT AMPLITUDE vs FREQUENCY 24 Large Signal Output Amplitude -dB(VPP ) Vo = 8 Vp p 18 Vo = 4 Vp p 12 Vo =2 Vp p 6 Vo = 1Vp p 0 Vo =0 .5Vp p -6 -12 Vo = 0 .2 5Vp p -18 100 k 1M 10 M 100 M f - Frequency - Hz 1G VCC= 12 V Gain = 5 RF = 500 RL= 100 Full Bias LARGE SIGNAL OUTPUT AMPLITUDE vs FREQUENCY 30 Large Signal Output Amplitude -dB(VPP) Vo = 16 Vp p 24 Vo = 8 Vp p 18 Vo = 4 Vp p 12 Vo =2 Vp p 6 Vo = 1Vp p 0 Vo =0 .5Vp p -6 Vo = 0 .2 5Vp p -12 -18 100 k 1M 10 M 100 M f f - Frequency - Hz 1G VCC= 12 V Gain = 10 RF = 500 RL= 100 Full Bias Total Quiescent Current (mA) 20 15 M id Bias Mo de 10 Lo w Bias Mo de 5 0 0.01 0.1 1 R s et t o G N D - k 10 100 Figure 5 Figure 6 Figure 7 LARGE SIGNAL OUTPUT AMPLITUDE vs FREQUENCY 18 Large Signal Output Amplitude -dB(VPP) Vo = 4 Vp p 12 Vo =2 Vpp 6 Vo = 1Vpp 0 Vo =0 .5Vp p -6 Vo = 0 .25Vp p -12 VCC= 5V Gain = 5 RF = 750 RL= 25 Full Bias Hz VOLTAGE AND CURRENT NOISE vs FREQUENCY 10 0 0 10 0 0 3 2 Hz I n - Current Noise - pA/ Input Voltage -V In+ 1 OVERDRIVE RECOVERY VCC= 12V Gain = 5 RL= 100 15 10 5 Output Voltage -V Vn - Voltage Noise - nV/ 10 0 100 0 -1 -2 -3 Vin 0 -5 -10 -15 0 .0 0 .5 Time ( S) 1.0 10 In- Vn 10 Vo ut -18 100 k 1M 10 M 100 M f - Frequency - Hz 1G 1 10 100 1k 10 k f - Frequency - Hz 1 100 k Figure 8 Figure 9 Figure 10 9 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 POWER SUPPLY REJECTION RATIO vs FREQUENCY 80 70 60 50 40 30 20 10 0 -10 1k VCC = 12V Gain = 5 RF = 500 RL = 100 10k 100k 1M f - Frequency -Hz 10M 100M Vcc- Vcc+ Output Amplitude -dB PSSR -Power Supply Rejection Ratio -dB 2 1 0 -1 -2 -3 -4 -5 -6 OUTPUT AMPLITUDE vs FREQUENCY RF = 1 k RF = 1.2 k 2 1 0 Output Amplitude -dB OUTPUT AMPLITUDE vs FREQUENCY RF = 1 k RF = 1.2 k RF = 2 k -1 RF = 2 k -2 -3 -4 -5 -6 -7 VCC = 15V Gain = 1 RL = 100 VO = 0.1 Vrms Full Bias 1M 10 M 100 M f - Frequency - Hz 1G VCC = 15V Gain = 1 RL = 25 VO = 0.1 Vrms Full Bias 1M 10 M 100 M 1G -7 100 k 100 k f - Frequency - Hz Figure 11 OUTPUT AMPLITUDE vs FREQUENCY RF = 750 RF = 500 14 Output Amplitude -dB 13 12 11 10 9 8 Figure 12 OUTPUT AMPLITUDE vs FREQUENCY RF = 750 RF = 500 Output Amplitude -dB Figure 13 OUTPUT AMPLITUDE vs FREQUENCY RF = 500 16 15 14 Output Amplitude -dB 13 12 11 10 9 8 16 15 21 20 19 18 17 RF = 1 k RF = 1 k 16 15 14 13 12 100 k VCC = 15V Gain = 10 RL = 25 VO = 0.1 Vrms Full Bias 1M RF = 2 k VCC = 15V Gain = 5 RL = 25 VO = 0.1 Vrms Full Bias 1M 10 M 100 M f - Frequency - Hz 1G VCC = 15V Gain = 5 RL = 100 VO = 0.1 Vrms Full Bias 1M RF = 1 k RF = 2 k RF = 2 k 7 100 k 7 100 k 10 M 100 M 10 M 100 M f - Frequency - Hz f - Frequency - Hz Figure 14 OUTPUT AMPLITUDE vs FREQUENCY RF = 500 0 Output Amplitude -dB -1 -2 -3 -4 -5 -6 Figure 15 OUTPUT AMPLITUDE vs FREQUENCY RF = 1.2 k 1 RF = 1 k Output Amplitude -dB Figure 16 OUTPUT AMPLITUDE vs FREQUENCY RF = 1.2 k RF = 1 k 0 -1 -2 RF = 2 k -3 -4 -5 -6 VCC = 12V Gain = 1 RL = 100 VO= 0.1 Vrms Full Bias 1M 10 M 100 M f - Frequency - Hz 1G 21 20 19 Output Amplitude -dB 18 17 16 15 14 13 2 2 1 RF = 2 k RF = 1 k VCC = 15V Gain = 10 RL = 100 VO = 0.1 Vrms Full Bias RF = 2 k VCC = 12V Gain = 1 RL = 25 VlO = 0.1 Vrms Full Bias 1M 10 M 100 M 1G 12 100 k 1M 10 M f - Frequency - Hz 100 M -7 100 k -7 100 k f - Frequency - Hz Figure 17 Figure 18 Figure 19 10 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 10 9 8 Output Amplitude -dB 7 6 5 4 3 2 1 100 k OUTPUT AMPLITUDE vs FREQUENCY 12 9 OUTPUT AMPLITUDE vs FREQUENCY 16 RF = 825 15 RF = 500 14 Output Amplitude -dB 13 12 11 10 9 8 10 M 100 M 1G 7 100 k OUTPUT AMPLITUDE vs FREQUENCY RF = 750 RF = 500 RF = 500 Output Amplitude -dB 6 3 0 -3 -6 RF = 1 k RF = 2 k RF = 1 k RF = 2 k VCC = 12V Gain = 2 RL = 25 VO = 0.1 Vrms Full Bias 1M 10 M 100 M f - Frequency - Hz 1G RF = 2 k VCC = 12V Gain = 5 RL = 25 VO = 0.1 Vrms Full Bias 1M 10 M f - Frequency - Hz 100 M VCC = 12V Gain = 2 RL = 100 VO = 0.1 Vrms Full Bias 1M -9 100 k f - Frequency - Hz Figure 20 OUTPUT AMPLITUDE vs FREQUENCY RF = 750 RF = 500 Figure 21 OUTPUT AMPLITUDE vs FREQUENCY RF = 750 RF = 500 Figure 22 OUTPUT AMPLITUDE vs FREQUENCY RF = 750 RF = 500 16 15 14 Output Amplitude -dB 16 15 14 Output Amplitude -dB 16 15 14 Output Amplitude -dB 13 12 11 10 9 8 RF = 1 k RF = 2 k VCC = 12V Gain = 5 RL = 25 VO = 0.1 Vrms Mid Bias 1M 10 M f - Frequency - Hz 100 M 13 12 RF = 1 k RF = 2 k 13 12 11 10 9 8 VCC = 12V Gain = 5 RL = 100 VO = 0.1 Vrms Full Bias 1M RF = 2 k RF = 1 k 11 10 9 8 7 100 k VCC = 12V Gain = 5 RL = 25 VO = 0.1 Vrms Low Bias 1M 10 M f - Frequency - Hz 100 M 7 100 k 7 100 k 10 M 100 M f - Frequency - Hz Figure 23 OUTPUT AMPLITUDE vs FREQUENCY RF = 750 RF = 500 14 Output Amplitude -dB Figure 24 OUTPUT AMPLITUDE vs FREQUENCY RF = 750 15 Figure 25 OUTPUT AMPLITUDE vs FREQUENCY RF = 500 16 15 14 Output Amplitude -dB 13 12 11 10 9 8 16 21 20 19 Output Amplitude -dB 13 12 11 10 9 8 7 100 k RF = 1 k RF = 500 RF = 2 k VCC = 12V Gain = 5 RL = 100 VO = 0.1 Vrms Low Bias 1M 10 M f - Frequency - Hz 100 M 18 17 16 15 14 13 12 100 k RF = 1 k RF = 1 k RF = 2 k VCC = 12V Gain = 5 RL = 100 VO = 0.1 Vrms Mid Bias 1M 10 M f - Frequency - Hz 100 M RF = 2 k VCC = 12V Gain = 10 RL = 25 VO = 0.1 Vrms Full Bias 1M 10 M 100 M 7 100 k f - Frequency - Hz Figure 26 Figure 27 Figure 28 11 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 21 20 OUTPUT AMPLITUDE vs FREQUENCY RF = 500 OUTPUT AMPLITUDE vs FREQUENCY 16 15 RF = 500 14 Output Amplitude -dB Output Amplitude -dB 13 12 11 10 9 8 7 100 k VCC= 12V Gain = -5 RL = 25 VO = 0.1 Vrms Full Bias 1M 10 M f - Frequency - Hz 100 M RF = 1 k 14 13 16 15 OUTPUT AMPLITUDE vs FREQUENCY 19 Output Amplitude -dB 18 17 16 15 14 13 VCC = 12V Gain = 10 RL = 100 VO = 0.1 Vrms Full Bias 1M 10 M f - Frequency - Hz 100 M RF = 1 k RF = 2 k RF = 500 RF = 1 k 12 11 10 9 8 VCC = 12V Gain = -5 RL = 100 VO = 0.1 Vrms Full Bias 1M 10 M f - Frequency - Hz 100 M 12 100 k 7 100 k Figure 29 OUTPUT AMPLITUDE vs FREQUENCY RF = 1.2 k 2 RF = 1 k Output Amplitude -dB 1 0 -1 -2 -3 -4 -5 Figure 30 OUTPUT AMPLITUDE vs FREQUENCY 16 RF = 1 k 15 RF = 1.2 k 14 Output Amplitude -dB 13 Figure 31 OUTPUT AMPLITUDE vs FREQUENCY RF = 500 RF = 750 3 2 1 Output Amplitude -dB 0 -1 3 RF = 2 k 12 11 10 9 8 VCC = 5V Gain = 5 RL = 25 VO = 0.1 Vrms Full Bias 1M 10 M 100 M RF = 2 k -2 -3 -4 -5 -6 100 k VCC = 5V Gain = 1 RL = 25 VO = 0.1 Vrms Full Bias 1M 10 M 100 M f - Frequency - Hz 1G RF = 2 k VCC = 5V Gain = 1 RL = 100 VO = 0.1 Vrms Full Bias 1M 10 M 100 M 1G -6 100 k 7 100 k f - Frequency - Hz f - Frequency - Hz Figure 32 OUTPUT AMPLITUDE vs FREQUENCY RF = 500 RF = 750 14 Output Amplitude -dB Output Amplitude -dB 13 12 11 10 9 8 VCC = 5V Gain = 5 RL = 100 VO = 0.1 Vrms Full Bias 1M 10 M 100 M RF = 1 k RF = 2 k Figure 33 OUTPUT AMPLITUDE vs FREQUENCY 21 RF = 500 20 19 Output Amplitude -dB RF = 1 k RF = 2 k VCC = 5V Gain = 10 RL = 25 VO = 0.1 Vrms Full Bias 1M 10 M 100 M 18 17 16 15 14 13 Figure 34 OUTPUT AMPLITUDE vs FREQUENCY RF = 500 16 15 21 20 19 18 17 16 15 14 13 12 100 k RF = 1 k RF = 2 k VCC = 5V Gain = 10 RL = 25 VlO = 0.1 Vrms Full Bias 1M 10 M 100 M 7 100 k 12 100 k f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure 35 Figure 36 Figure 37 12 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 SLEW RATE vs OUTPUT VOLTAGE 500 SR+ 400 SR- Slew-Raie (V/us) 300 Zo -Closed Loop Output Impedance -Ohms CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY 1000 Shutdown 100 Mid Bias 10 Low Bias 1 VCC = 12V Gain = 10 RL = 500 Total Quiescent Current -mA 25 QUIESCENT CURRENT vs SUPPLY VOLTAGE Ta = 25 deg.C Icc+ (Full) Icc- (Full) Icc+ (Mid) 20 15 A 10 Icc+ (Low) 5 Icc- (Low) Icc+ (SD) Icc- (SD) Icc- (Mid) 200 Full Bias 100 0.1 0 0 5 10 15 Output Voltage - Vp-p 20 0.01 100 k 1M 10 M 100 M 3 5 f - Frequency - Hz 7 11 9 13 Supply Voltage - +/-Vcc 15 Figure 38 QUIESCENT CURRENT vs TEMPERATURE Vcc = +/-12V 20 Icc+ (Mid) 15 Icc- (Mid) 10 Icc+ (Low) Icc- (Low) 5 Icc+ (SD) 0 -40 -20 0 20 40 60 Temperature - Deg.C 80 100 Icc- (SD) Icc+ (Full) Common Mode Rejection Ratio -dB 80 70 Icc- (Full) Figure 39 COMMON-MODE REJECTION RATIO vs COMMON-MODE VOLTAGE 90 Vcc = +/-15V -40 Deg C Input Bias Current -uA 12 11 Figure 40 INPUT BIAS CURRENT vs TEMPERATURE 25 13 Total Quiescent Current -mA 85 Deg C 60 25 Deg C 50 40 30 20 -14 -10 -6 -2 2 6 10 Common Mode Voltage - V 14 Iib- 10 9 8 7 6 -40 Iib+ -20 0 20 40 60 Temperature - Deg C 80 100 Figure 41 INPUT OFFSET VOLTAGE vs TEMPERATURE 5.5 Figure 42 2ND HARMONIC DISTORTION vs FREQUENCY -40 Differential configuration -40 Figure 43 2ND HARMONIC DISTORTION vs FREQUENCY Differential configuration -50 Low Bias Input Offset Voltage -mV 5 Vio - Channel A -50 Low Bias -60 2nd HD -dBc 4.5 2nd HD -dBc -60 Mid Bias Full Bias -70 Mid Bias Full Bias VCC = 12V Gain = 10 RL = 200 RF = 1 k VO= 2 VPP 1M 10 M f - Frequency - Hz 100 M -70 4 Vio - Channel B 3.5 -80 -80 -90 -90 3 -40 -20 0 20 40 60 Temperature - Deg C 80 100 -100 100 k VCC = 5V Gain = 10 RL = 200 RF = 1 k VO = 2 VPP 1M 10 M f - Frequency - Hz 100 M -100 100 k Figure 44 Figure 45 Figure 46 13 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 -45 -50 2ND HARMONIC DISTORTION vs FREQUENCY -45 Differential configuration -50 2ND HARMONIC DISTORTION vs FREQUENCY Differential configuration -40 2ND HARMONIC DISTORTION vs FREQUENCY Differential configuration -50 Low Bias -55 2nd HD -dBc -60 -65 -70 -75 -80 100 k Full Bias Mid Bias 2nd HD -dBc -55 Mid Bias -60 -65 -70 -75 -80 100 k Low Bias VCC = 5V Gain = 10 RL = 50 RF = 1 k VO = 2 VPP 100 M 2nd HD -dBc -60 -70 Low Bias VCC = 12V Gain = 10 RL = 50 RF = 1 k VO = 2 VPP 10 M 100 M Mid Bias Full Bias VCC = 12V Gain = 5 RL = 200 RF = 1 k VO = 2 VPP 1M 10 M 100 M -80 Full Bias -90 1M f - Frequency - Hz 1M 10 M f - Frequency - Hz -100 100 k f - Frequency - Hz Figure 47 2ND HARMONIC DISTORTION vs FREQUENCY -40 Differential configuration -50 -50 Low Bias -55 Figure 48 2ND HARMONIC DISTORTION vs FREQUENCY Differential configuration Figure 49 2ND HARMONIC DISTORTION vs FREQUENCY -45 Differential configuration -50 -55 2nd HD -dBc -60 -65 Low Bias -70 -75 Full Bias -80 -85 100 k VCC = 5V Gain = 5 RL = 50 RF = 1 k VO = 2 VPP 100 M Mid Bias -45 -60 2nd HD -dBc 2nd HD -dBc -60 Mid Bias -65 -70 -75 -80 -85 100 k Full Bias Low Bias VCC = 12V Gain = 5 RL = 50 RF = 1 k VO = 2 VPP 10 M 100 M -70 Mid Bias Full Bias VCC = 5V Gain = 5 RL = 200 RF = 1 k VO = 2 VPP -80 -90 -100 100 k 1M 10 M f - Frequency - Hz 100 M 1M f - Frequency - Hz 1M 10 M f - Frequency - Hz Figure 50 3RD HARMONIC DISTORTION vs FREQUENCY -30 -40 -50 3rd HD -dBc -60 Low Bias -70 -80 -90 Differential configuration -100 100 k 1M 10 M f - Frequency - Hz 100 M -100 100 k Mid Bias Full Bias -80 -90 VCC = 12V Gain = 10 RL = 200 RF = 1 k VO = 2 VPP 3rd HD -dBc -30 Figure 51 3RD HARMONIC DISTORTION vs FREQUENCY Differential configuration -40 -50 3rd HD -dBc -60 Mid Bias -70 VCC = 5V Gain = 10 RL = 200 RF = 1 k VO = 2 VPP 1M 10 M f - Frequency - Hz 100 M Full Bias Low Bias -40 Figure 52 3RD HARMONIC DISTORTION vs FREQUENCY -30 Differential configuration Low Bias -50 -60 Mid Bias -70 -80 -90 -100 100 k Full Bias VCC = 5V Gain = 10 RL = 50 RF = 1 k VO = 2 VPP 1M 10 M f - Frequency - Hz 100 M Figure 53 Figure 54 Figure 55 14 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 3RD HARMONIC DISTORTION vs FREQUENCY -30 Differential configuration -40 -50 3rd HD -dBc 3rd HD -dBc -60 -70 -80 -90 -100 100 k Mid Bias Full Bias VCC = 12V Gain = 10 RL = 50 RF = 1 k VO = 2 VPP 1M 10 M f - Frequency - Hz 100 M Low Bias -30 -40 3RD HARMONIC DISTORTION vs FREQUENCY Differential configuration Low Bias -30 -40 3RD HARMONIC DISTORTION vs FREQUENCY VCC = 5V Gain = 5 RL = 200 RF = 1 k VO = 2 VPP Low Bias -50 -60 -70 -80 -90 -100 100 k Mid Bias Full Bias VCC = 12V Gain = 5 RL = 200 RF = 1 k VO = 2 VPP 1M 10 M f - Frequency - Hz 100 M 3rd HD -dBc -50 -60 -70 Mid Bias -80 Full Bias -90 Differential configuration -100 100 k 1M 10 M f - Frequency - Hz 100 M Figure 56 3RD HARMONIC DISTORTION vs FREQUENCY Low Bias -40 -50 3rd HD -dBc -60 -70 -80 -90 Differential configuration -100 100 k 1M 10 M 100 M -100 100 k Full Bias VCC = 12V Gain = 5 RL = 50 RF = 1 k VO = 2 VPP Mid Bias -40 Figure 57 3RD HARMONIC DISTORTION vs FREQUENCY -30 Differential configuration -80 -75 Low Bias Figure 58 2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE Differential configuration -30 Low Bias -50 3rd HD -dBc 2nd HD -dBc -60 -70 -80 -90 Mid Bias Full Bias VCC = 5V Gain = 5 RL 50 RF = 1 k VO = 2 VPP 1M 10 M f - Frequency - Hz 100 M -85 Mid Bias -90 Full Bias VCC = 12V Gain = 5 RL = 200 RF = 1 k f = 1 MHz 0 5 10 15 20 25 30 Output Voltage - Vpp 35 40 -95 -100 f - Frequency - Hz Figure 59 2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE -75 Low Bias -80 -70 Figure 60 2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE -65 Low Bias Figure 61 2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE -65 Low Bias Differential configuration 2nd HD -dBc 2nd HD -dBc -70 Mid Bias 2nd HD -dBc Mid Bias -85 Mid Bias -90 Full Bias -95 VCC = 5V Gain = 5 RL = 200 RF = 1 k f = 1 MHz 10 Full Bias -75 VCC = 12V Gain = 5 RL = 50 RF = 1 k f = 1 MHz 0 5 10 15 20 Output Voltage - Vpp 25 30 Full Bias -75 VCC = 5V Gain = 5 RL = 50 RF = 1 k f = 1 MHz 0 2 4 6 8 10 -100 0 5 Output Voltage - Vpp -80 -80 Output Voltage - Vpp Figure 62 Figure 63 Figure 64 15 THS6182 www.ti.com SLLS544E - SEPTEMBER 2002 - REVISED JULY 2003 -70 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE Differential configuration -70 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE Differential configuration 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE -65 -70 VCC = 12 V Gain = 5 RL = 50 RF = 1 k f = 1 MHz -75 Low Bias 3rd HD -dBc -80 3rd HD -dBc -75 Low Bias 3rd HD -dBc Low Bias -75 -80 -85 -90 Full Bias -95 -80 -85 Mid Bias -85 Mid Bias Mid Bias -90 Full Bias -95 VCC = 5V Gain = 5 RL = 200 RF = 1 k f = 1 MHz 6 8 10 -90 Full Bias -95 VCC = 12V Gain = 5 RL = 200 RF = 1 k f = 1 MHz 35 40 -100 0 2 4 Output Voltage - Vpp Differential configuration -100 0 5 10 15 20 25 30 -100 0 5 10 15 20 25 30 Output Voltage - Vpp Output Voltage - Vpp Figure 65 Figure 66 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE -65 Differential configuration -70 Mid Bias -75 3rd HD -dBc -80 -85 -90 Full Bias -95 -100 0 2 4 6 Output Voltage - Vpp 8 10 VCC = 5V Gain = 5 RL = 50 RF = 1 k f = 1 MHz Low Bias Figure 67 Figure 68 16 MECHANICAL DATA MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001 D (R-PDSO-G**) 8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25) PLASTIC SMALL-OUTLINE PACKAGE 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.008 (0,20) NOM Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40) 0.010 (0,25) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX A MIN 8 0.197 (5,00) 0.189 (4,80) 14 0.344 (8,75) 0.337 (8,55) 16 0.394 (10,00) 0.386 (9,80) 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI003E - JANUARY 1995 - REVISED SEPTEMBER 2001 DW (R-PDSO-G**) 16 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 9 PLASTIC SMALL-OUTLINE PACKAGE 0.050 (1,27) 16 0.010 (0,25) 0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.291 (7,39) 0.010 (0,25) NOM Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** DIM A MAX 0.004 (0,10) 16 0.410 (10,41) 0.400 (10,16) 18 0.462 (11,73) 0.453 (11,51) 20 0.510 (12,95) 0.500 (12,70) 24 0.610 (15,49) 0.600 (15,24) 28 0.710 (18,03) 0.700 (17,78) 4040000/E 08/01 A MIN NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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