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TAS5112
SLES048B - JULY 2003
DIGITAL AMPLIFIER POWER STAGE
FEATURES D 50 W per Channel (BTL) Into 6 (Stereo) D 95 dB Dynamic Range With TAS5026 D Less Than 0.1% THD+N (TDAA System - 1 W
RMS Into 6 ) RMS into 6 )
D Less Than 0.2% THD+N (TDAA System - 50 W D Power Efficiency Typically 90% Into 6- Load D Self-Protecting Design (Undervoltage,
Overtemperature and Short Conditions) With Error Reporting
APPLICATIONS D DVD Receiver D Home Theatre D Mini/Micro Component Systems D Internet Music Appliance DESCRIPTION
The TAS5112 is a high-performance, integrated stereo digital amplifier power stage designed to drive 6- speakers at up to 50 W per channel. The device incorporates TI's PurePath Digitalt technology and is used in conjunction with a digital audio PWM processor (TAS50XX) and a simple passive demodulation filter to deliver high-quality, high-efficiency, true-digital audio amplification. The efficiency of this digital amplifier is typically 90%, reducing the size of both the power supplies and heat sinks needed. Overcurrent protection, overtemperature protection, and undervoltage protection are built into the TAS5112, safeguarding the device and speakers against fault conditions that could damage the system.
D Internal Gate Drive Supply Voltage Regulator D EMI Compliant When Used With
Recommended System Design
THD + NOISE vs OUTPUT POWER
1 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % RL = 6 TC = 75C 1
THD + NOISE vs FREQUENCY
RL = 6 TC = 75C PO = 50 W 0.1 PO = 10 W PO = 1 W 0.01
0.1
0.01 100m
1
10
100
0.001 20
100
1k f - Frequency - Hz
10k 20k
PO - Output Power - W
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Digital and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
TAS5112
SLES048B - JULY 2003
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
Terminal Assignment
The TAS5112 is offered in a thermally enhanced 56-pin TSSOP DFD (thermal pad is on the top), shown as follows.
DFD PACKAGE (TOP VIEW)
ABSOLUTE MAXIMUM RATINGS
TAS5112 DVDD TO DGND GVDD TO GND PVDD_X TO GND (dc voltage) PVDD_X TO GND (spike voltage(2)) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OUT_X TO GND (dc voltage) OUT_X TO GND (spike voltage(2)) BST_X TO GND (dc voltage) BST_X TO GND (spike voltage(2)) GREG TO GND (3) PWM_XP, RESET, M1, M2, M3, SD, OTW Maximum operating junction temperature, TJ Storage temperature
over operating free-air temperature range unless otherwise noted(1) UNITS -0.3 V to 4.2 V 33.5 V 33.5 V 48 V 33.5 V 48 V 48 V 53 V 14.2 V -0.3 V to DVDD + 0.3 V -40C to 150C -40C to 125C
GND GND GREG OTW SD_CD SD_AB PWM_DP PWM_DM RESET_CD PWM_CM PWM_CP DREG_RTN M3 M2 M1 DREG PWM_BP PWM_BM RESET_AB PWM_AM PWM_AP GND DGND GND DVDD GREG GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
GND GVDD BST_D PVDD_D PVDD_D OUT_D OUT_D GND GND OUT_C OUT_C PVDD_C PVDD_C BST_C BST_B PVDD_B PVDD_B OUT_B OUT_B GND GND OUT_A OUT_A PVDD_A PVDD_A BST_A GVDD GND
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolutemaximum-ratedconditions for extended periods may affect device reliability. (2) The duration of voltage spike should be less than 100 ns. (3) GREG is treated as an input when the GREG pin is overdriven by GVDD of 12 V.
ORDERING INFORMATION
TA PACKAGE DESCRIPTION 0C to 70C TAS5112DFD 56-pin small TSSOP (1) For the most current specification and package information, refer to our web site at www.ti.com.
PACKAGE DISSIPATION RATINGS
PACKAGE RJC (C/W) RJA (C/W)
56-pin DAD TSSOP 1.14 See Note 1 (1) The TAS5112 package is thermally enhanced for conductive cooling using an exposed metal pad area. It is impractical to use the device with the pad exposed to ambient air as the only heat sinking of the device. For this reason, RJA a system parameter that characterizes the thermal treatment provided in the application. An example and discussion of typical system RJA values are provided in the Thermal Information section. This example provides additional information regarding the power dissipation ratings. This example should be used as a reference to calculate the heat dissipation ratings for a specific application. TI application engineering provides technical support to design heat sinks if needed.
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TAS5112
SLES048B - JULY 2003
Terminal Functions
TERMINAL NAME BST_A BST_B BST_C BST_D DGND DREG DREG_RTN DVDD GND NO. 31 42 43 54 23 16 12 25 1, 2, 22, 24, 28, 29, 27, 36, 37, 48, 49, 56 3, 26 30, 55 15 14 13 4 34, 35 38, 39 46, 47 50, 51 32, 33 40, 41 44, 45 52, 53 20 21 18 17 10 11 8 7 19 9 6 FUNCTION(1) P P P P P P P P P DESCRIPTION High side bootstrap supply (BST), external capacitor to OUT_A required High side bootstrap supply (BST), external capacitor to OUT_B required HS bootstrap supply (BST), external capacitor to OUT_C required HS bootstrap supply (BST), external capacitor to OUT_D required Digital I/O reference ground Digital supply voltage regulator decoupling pin, capacitor connected to GND Digital supply voltage regulator decoupling return pin I/O reference supply input (3.3V) Power ground
GREG GVDD M1 (TST0) M2 M3 OTW OUT_A OUT_B OUT_C OUT_D PVDD_A PVDD_B PVDD_C PVDD_D PWM_AM PWM_AP PWM_BM PWM_BP PWM_CM PWM_CP PWM_DM PWM_DP RESET_AB RESET_CD SD_AB
P P I I I O O O O O P P P P I I I I I I I I I I O O
Gate drive voltage regulator decoupling pin, capacitor to REG_GND Voltage supply to on-chip gate drive and digital supply voltage regulators Mode selection pin Mode selection pin Mode selection pin Overtemperature warning output, open drain with internal pullup Output, half-bridge A Output, half-bridge B Output, half-bridge C Output, half-bridge D Power supply input for half-bridge A Power supply input for half-bridge B Power supply input for half-bridge C Power supply input for half-bridge D Input signal (negative), half-bridge A Input signal (positive), half-bridge A Input signal (negative), half-bridge B Input signal (positive), half-bridge B Input signal (negative), half-bridge C Input signal (positive), half-bridge C Input signal (negative), half-bridge D Input signal (positive), half-bridge D Reset signal, active low Reset signal, active low Shutdown signal for half-bridges A and B Shutdown signal for half-bridges C and D
SD_CD 5 (1) I = input, O = Output, P = Power
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TAS5112
SLES048B - JULY 2003
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FUNCTIONAL BLOCK DIAGRAM
BST_A GREG PVDD_A Gate Drive PWM_AP PWM Receiver Timing Control Gate Drive GND Protection A RESET GREG PVDD_B Protection B Gate Drive PWM_BP PWM Receiver Timing Control Gate Drive To Protection Blocks GND DREG DREG GVDD OTW OT Protection SD UVP DREG_RTN DREG_RTN GREG GREG DREG GREG GREG OUT_B BST_B OUT_A
This diagram shows one channel.
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TAS5112
SLES048B - JULY 2003
RECOMMENDED OPERATING CONDITIONS
MIN DVDD GVDD PVDD_x Digital supply (1) Supply for internal gate drive and logic regulators Half-bridge supply Relative to DGND Relative to GND Relative to GND, RL= 6 to 8 3 16 0 0 TYP 3.3 29.5 29.5 MAX 3.6 30.5 30.5 125 UNIT V V V _C
TJ Junction temperature (1) It is recommended for DVDD to be connected to DREG via a 100- resistor.
ELECTRICAL CHARACTERISTICS
PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100- resistor, RL = 6 , 8X fs = 384 kHz, unless otherwise noted TYPICAL SYMBOL PARAMETER TEST CONDITIONS TA=25C TA=25C OVER TEMPERATURE TCase= 75C TA=40C TO 85C UNITS MIN/TYP/ MAX
AC PERFORMANCE, BTL Mode, 1 kHz RL = 8 , THD = 0.2%, AES17 filter, 1 kHz RL = 8 , THD = 10%, AES17 filter, 1 kHz Po Output power RL = 6 , THD = 0.2%, AES17 filter, 1 kHz RL = 6 , THD = 10%, AES17 filter, 1 kHz Po = 1 W/ channel, RL = 6 , AES17 filter THD+N Total harmonic distortion + noise Po = 10 W/channel, RL = 6 , AES17 filter Po = 50 W/channel, RL = 6 , AES17 filter Vn SNR DR Output integrated voltage noise Signal-to-noise ratio Dynamic range A-weighted, mute, RL = 6 ,, 20 Hz to 20 kHz, AES17 filter A-weighted, AES17 filter f = 1 kHz, A-weighted, AES17 filter 40 50 50 62 0.03% 0.04% 0.2% 260 96 96 V dB dB W W W W Typ Typ Typ Typ Typ Typ Typ Max Typ Typ
INTERNAL VOLTAGE REGULATOR DREG GREG IVGDD IDVDD Voltage regulator Voltage regulator GVDD supply current, operating DVDD supply current, operating Io = 1 mA, PVDD = 18 V-30.5 V Io = 1.2 mA, PVDD = 18 V-30.5 V fS = 384 kHz, no load, 50% duty cycle fS = 384 kHz, no load 1 3.1 13.4 24 5 V V mA mA Typ Typ Max Max
OUTPUT STAGE MOSFETs Ron,LS Ron,HS Forward on-resistance, low side Forward on-resistance, high side TJ = 25C TJ = 25C 155 155 m m Typ Typ
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ELECTRICAL CHARACTERISTICS
PVDD_x = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100- resistor, RL = 6 , 8X fs = 384 kHz, unless otherwise noted TYPICAL SYMBOL PARAMETER TEST CONDITIONS TA=25C TA=25C OVER TEMPERATURE TCase= 75C TA=40C TO 85C UNITS MIN/TYP/ MAX
INPUT/OUTPUT PROTECTION Set the DUT in normal operation mode with all the protections enabled. Sweep GVDD up and down Monitor down. SD output. Record the GREG reading when SD is triggered. 6.9 7.4 74 7.9 V Max V Min
Vuvp,G
Undervoltage protection rotection limit, GVDD
OTW OTE OC
Overtemperature warning, junction temperature Overtemperature error, junction temperature Overcurrent protection PWM_AP, PWM_BP, M1, M2, M3, SD, OTW See Note 1.
125 150 5.8
C C A
Typ Typ Typ
STATIC DIGITAL SPECIFICATION
2 VIH VIL Leakage Lk High-level High level input voltage Low-level input voltage Input l k I t leakage current t DVDD 0.8 -10 10 OTW/SHUTDOWN (SD) Internally pull up R from OTW/SD to DVDD 30 22.5
V V V A A
Min Max Max Min Max
k
Min
VOL Low level output voltage IO = 4 mA 0.4 V Max (1) To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care. See DemodulationFilter Design in the ApplicationInformation section of the data sheet and consider the recommended inductors and capacitors for optimalperformance. It is also important to consider PCB design and layout for optimum performance of the TAS5112. It is recommended to follow the TAS5112F2EVM (S/N 112) design and layout guidelines for best performance.
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TAS5112
SLES048B - JULY 2003
SYSTEM CONFIGURATION USED FOR CHARACTERIZATION
Gate-Drive Power Supply External Power Supply H-Bridge Power Supply
TAS5112DFD 1 1 F GND 2 GND 3 GREG 4 OTW 5 SD_CD ERR_RCVY PWM_AP_1 PWM_AM_1 VALID_1 6 SD_AB 7 PWM_DP 8 PWM_DM 9 RESET_CD 10 11 12 100 nF PWM PROCESSOR TAS5026 13 14 15 M1 16 PWM_AP_2 PWM_AM_2 VALID_2 17 PWM_BP 18 PWM_BM 19 RESET_AB 20 PWM_AM 21 PWM_AP 100 100 nF 22 23 DGND 24 GND 25 DVDD 26 1 F 27 28 GND GND GVDD GND GREG OUT_A 33 PVDD_A 32 PVDD_A 31 BST_A 30 1.5 29 100 nF 33 nF LPCB 1000 F GND GND 35 OUT_A 34 1.5 10 H 100 nF 4.7 k GND OUT_B 37 36 OUT_B 38 1.5 PVDD_B 39 DREG BST_B 41 PVDD_B 40 100 nF 10 H 470 nF 100 nF 4.7 k 33 nF LPCB PWM_CM PWM_CP DREG_RTN M3 M2 GND 47 OUT_C 46 OUT_C 45 PVDD_C PVDD_C BST_C 44 43 42 1.5 33 nF LPCB 1000 F 1.5 10 H 100 nF 4.7 k GND 48 OUT_D 49 OUT_D 50 1.5 PVDD_D PVDD_D 52 51 100 nF 10 H 470 nF 100 nF 4.7 k BST_D 53 33 nF LPCB GVDD GND 55 54 1.5 100 nF 56
{
{
100 nF
{
{
100 nF
LPCB : TRACK IN THE PCB (1.0 mm wide and 50 mm long)
{Voltage Suppressor Diode: 1SMA33CAT
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TAS5112
SLES048B - JULY 2003
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TYPICAL CHARACTERISTICS AND SYSTEM PERFORMANCE OF TAS5112 EVM WITH TAS5026 PWM PROCESSOR
TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY
1 THD+N - Total Harmonic Distortion + Noise - % RL = 6 TC = 75C PO = 50 W 0.1 PO = 10 W PO = 1 W 0.01 Noise Amplitude - dBr 0 -20 -40 -60 -80 -100 -120 -140 0.001 20 -160 100 1k f - Frequency - Hz 10k 20k 0 2 4 6
NOISE AMPLITUDE vs FREQUENCY
RL = 6 FFT = -60 dB TC = 75C TAS5026 Front End Device
8
10
12
14
16
18
20
22
f - Frequency - kHz
Figure 1
Figure 2
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
10 THD+N - Total Harmonic Distortion + Noise - % RL = 6 TC = 75C 50 PO - Output Power - W 60 TA = 75C
OUTPUT POWER vs H-BRIDGE VOLTAGE
1
40 RL = 6 30 RL = 8
0.1
20
10
0.01 100m
0 1 10 100 0 4 8 12 16 20 24 28 32 PO - Output Power - W VDD - Supply Voltage - V
Figure 3
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Figure 4
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TAS5112
SLES048B - JULY 2003
SYSTEM OUTPUT STAGE EFFICIENCY vs OUTPUT POWER
100 - System Output Stage Efficiency - % 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 PO - Output Power - W f = 1 kHz RL = 6 TC = 75C Ptot - Power Loss - W 11 10 9 8 7 6 5 4 3 2 1 0 0 5 f = 1 kHz RL = 6 TC = 75C
POWER LOSS vs OUTPUT POWER
10 15 20 25 30 35 40 45 50 55 60 65 PO - Output Power - W
Figure 5
Figure 6
OUTPUT POWER vs CASE TEMPERATURE
60 58 56 PO - Output Power - W 54 52 50 48 46 44 42 40 0 20 40 60 80 100 120 140 TC - Case Temperature - C Channel 2 Channel 1 Amplitude - dBr PVDD = 29.5 V RL = 6 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 10 100
AMPLITUDE vs FREQUENCY
RL = 6
RL = 8
1k f - Frequency - Hz
10k
50k
Figure 7
Figure 8
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TAS5112
SLES048B - JULY 2003
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ON-STATE RESISTANCE vs JUNCTION TEMPERATURE
200 190 ron - On-State Resistance - m 180 170 160 150 140 130 120 0 10 20 30 40 50 60 70 80 90 100 TJ - Junction Temperature - C
Figure 9
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TAS5112
SLES048B - JULY 2003
THEORY OF OPERATION
POWER SUPPLIES
The power device only requires two supply voltages, GVDD and PVDD_X. GVDD is the gate drive supply for the device, regulated internally down to approximately 12 V, and decoupled with regards to board GND on the GREG pins through an external capacitor. GREG powers both the low side and high side via a bootstrap step-up conversion. The bootstrap supply is charged after the first low-side turn-on pulse. Internal digital core voltage DREG is also derived from GVDD and regulated down by internal circuitry to 3.3 V. The gate-driver regulator can be bypassed for reducing idle loss in the device by shorting GREG to GVDD and directly feeding in 12.0 V. This can be useful in an application where thermal conduction of heat from the device is difficult. PVDD_X is the H-bridge power supply pin. Two power pins exists for each half-bridge to handle the current density. It is very important that the circuitry recommendations around the PVDD_X pins are followed very carefully both topologyand layout-wise. For topology recommendations, see the Typical System Configuration section. Following these recommendations is important for parameters like EMI, reliability, and performance.
ground. This precharges the bootstrap supply capacitors and discharges the output filter capacitor (see the Typical TAS5112 Application Configuration section). After GVDD has been applied, it takes approximately 800 s to fully charge the BST capacitor. Within this time, RESET must be kept low. After approximately 1 ms, the back-end bootstrap capacitor is charged. RESET can now be released if the modulator is powered up and streaming valid PWM signals to the back-end PWM_xP. Valid means a switching PWM signal which complies with the frequency and duty cycle ranges stated in the Recommended Operating Conditions. A constant HIGH dc level on the PWM_xP is not permitted, because it would force the high-side MOSFET ON until it eventually ran out of BST capacitor energy and might damage the device. An unknown state of the PWM output signals from the modulator is illegal and should be avoided, which in practice means that the PWM processor must be powered up and initialized before RESET is de-asserted HIGH to the back end.
POWERING DOWN
For power down of the back end, an opposite approach is necessary. The RESET must be asserted LOW before the valid PWM signal is removed. When PWM processors are used in conjunction with TI TDAA back ends, the correct timing control of RESET and PWM_xP is performed by the modulator.
POWERING UP
> 1 ms > 1 ms
PRECAUTION
The TAS5112 must always start up in the high-impedance (Hi-Z) state. In this state, the bootstrap (BST) capacitor is precharged by a resistor on each PWM output node to ground. See the system configuration. This ensures that the back end is ready for receiving PWM pulses, indicating either HIGH- or LOW-side turnon after RESET is deasserted to the back end. With the following pulldown and BST capacitor size the charge time is:
RESET
GVDD
PVDD_X
C = 33 nF, R = 4.7 k R x C x 5 = 775.5 s
After GVDD has been applied, it takes approximately 800 s to fully charge the BST capacitor. During this time, RESET must be kept low. After approximately 1 ms the back end BST is charged and ready. RESET can now be released if the PWM modulator is ready and is streaming valid PWM signals to the back end. Valid PWM signals are switching PWM signals with a frequency between 350-400 kHz. A constant HIGH level on the PWM+ would force the high side MOSFET ON until it eventually ran out of BST capacitor energy. Putting the device in this condition should be avoided.
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PWM_xP
During power up when RESET is asserted LOW, all MOSFETs are turned off and the two internal half-bridges are in the high-impedance state (Hi-Z). The bootstrap capacitors supplying high-side gate drive are at this point not charged. To comply with the click and pop scheme and use of non-TI TDAA modulators it is recommended to use a 4-k pulldown resistor on each PWM output node to
TAS5112
SLES048B - JULY 2003
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In practice this means that the DVDD-to-PWM processor (front-end) should be stable and initialization should be completed before RESET is deasserted to the back end.
The device can be recovered by toggling RESET low and then high, after all errors are cleared.
Overcurrent (OC) Protection
The device has individual forward current protection on both high-side and low-side power stage FETs. The OC protection works only with the demodulation filter present at the output. See Demodulation Filter Design in the Application Information section of the data sheet for design constraints.
CONTROL I/O
Shutdown Pin: SD
The SD pin functions as an output pin and is intended for protection-mode signaling to, for example, a controller or other front-end device. The pin is open-drain with an internal pullup to DVDD. The logic output is, as shown in the following table, a combination of the device state and RESET input:
SD 0 0 1(1) 1 RESET 0 1 0 1 Not used Device in protection mode, i.e., UVP and/or OC and/or OT error Device set high-impedance (Hi-Z), SD forced high DESCRIPTION
Overtemperature (OT) Protection
A dual temperature protection system asserts a warning signal when the device junction temperature exceeds 125C. The OT protection circuit is shared by all half-bridges.
Undervoltage (UV) Protection
Undervoltage lockout occurs when GVDD is insufficient for proper device operation. The UV protection system protects the device under power-up and power-down situations. The UV protection circuits are shared by all half-bridges.
Normal operation (1) SD is pulled high when RESET is asserted low independent of chip state (i.e., protection mode). This is desirable to maintain compatibility with some TI PWM front ends.
Reset Function
The function of the reset input is twofold:
Temperature Warning Pin: OTW
The OTW pin gives a temperature warning signal when temperature exceeds the set limit. The pin is of the open-drain type with an internal pullup to DVDD.
OTW 0 1 DESCRIPTION Junction temperature higher than 125C Junction temperature lower than 125C
D D
Reset is used for re-enabling operation after a latching error event. Reset is used for disabling output stage switching (mute function).
The error latch is cleared on the falling edge of reset and normal operation is resumed when reset goes high.
Overall Reporting
The SD pin, together with the OTW pin, gives chip state information as described in Table 1.
PROTECTION MODE
Latching Shutdown on All Errors
In latching shutdown mode, all error situations result in a permanent shutdown (output stage Hi-Z). Re-enabling can be done by toggling the RESET pin.
Table 1. Error Signal Decoding
OTW 0 0 1 1 SD 0 1 0 1 DESCRIPTION Overtemperature error (OTE) Overtemperature warning (OTW) Overcurrent (OC) or undervoltage (UVP) error Normal operation, no errors/warnings
MODE Pins Selection
The protection mode is selected by shorting M1/M2 to DREG or DGND according to Table 2.
Table 2. Protection Mode Selection
M1 0 0 1 1 _ 0 1 0 1 Reserved Latching shutdown on all errors Reserved Reserved PROTECTION MODE
Chip Protection
The TAS5112 protection function is implemented in a closed loop with, for example, a system controller and TI PWM processor. The TAS5112 contains three individual systems protecting the device against error conditions. All of the error events covered result in the output stage being set in a high-impedance state (Hi-Z) for maximum protection of the device and connected equipment.
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The output configuration mode is selected by shorting the M3 pin to DREG or DGND according to Table 3.
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TAS5112
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Table 3. Output Mode Selection
M3 0 1 Reserved OUTPUT MODE Bridge-tied load output stage (BTL)
If this rule is observed, the TAS5112 will not have distortion issues due to the output inductors and overcurrent conditions will not occur due to inductor saturation in the output filter. Another parameter to be considered is the idle current loss in the inductor. This can be measured or specified as inductor dissipation (D). The target specification for dissipation is less than 0.05. In general, 10-H inductors suffice for most applications. The frequency response of the amplifier is slightly altered by the change in output load resistance; however, unless very tight control of frequency response is necessary (better than 0.5 dB), it is not necessary to deviate from 10 H. The graphs in Figure 11 display the inductance vs current characteristics of two inductors that are recommended for use with the TAS5112.
INDUCTANCE vs CURRENT
11 DFB1310A 10
APPLICATION INFORMATION
DEMODULATION FILTER DESIGN
The TDAA amplifier outputs are driven by heavy-duty DMOS transistors in an H-bridge configuration. These transistors are either off or fully on, which reduces the DMOS transistor on-state resistance, R(DMOSon), and the power dissipated in the device, thereby increasing efficiency. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio signal. It is recommended that a second-order LC filter be used to recover the audio signal. For this application, EMI is considered important; therefore, the selected filter is the full-output type shown in Figure 10.
TAS51xx
L - Inductance - H
Output A
L R(Load)
9 DASL983XX-1023 8 7 6 5 4
C1A C2 C1B Output B L
Figure 10. Demodulation Filter
The main purpose of the output filter is to attenuate the high-frequency switching component of the PurePath Digital amplifier while preserving the signals in the audio band. Design of the demodulation filter affects the performance of the power amplifier significantly. As a result, to ensure proper operation of the overcurrent (OC) protection circuit and meet the device THD+N specifications, the selection of the inductors used in the output filter must be considered according to the following. The rule is that the inductance should remain stable within the range of peak current seen at maximum output power and deliver at least 5 H of inductance at 15 A.
0
5
10 I - Current - A
15
Figure 11. Inductance Saturation
The selection of the capacitor that is placed across the output of each inductor (C2 in Figure 10) is very simple. To complete the output filter, use a 0.47-F capacitor with a voltage rating at least twice the voltage applied to the output stage (PVDD). This capacitor should be a good quality polyester dielectric such as a Wima MKS2-047ufd/100/10 or equivalent. In order to minimize the EMI effect of unbalanced ripple loss in the inductors, 0.1-F 50-V SMD capacitors (X7R or better) (C1A and C1B in Figure 10) should be added from the output of each inductor to ground.
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THERMAL INFORMATION
The thermally augmented package provided with the TAS5112 is designed to be interfaced directly to heat sinks using a thermal interface compound (for example, Wakefield Engineering type 126 thermal grease.) The heat sink then absorbs heat from the ICs and couples it to the local air. If the heatsink is carefully designed, this process can reach equilibrium and heat can be continually removed from the ICs. Because of the efficiency of the TAS5112, heat sinks can be smaller than those required for linear amplifiers of equivalent performance. RJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with roughly the following components:
Thus, for a single monaural IC, the system RJA = RJC + thermal grease resistance + heat sink resistance. Table 4, Table 5, and Table 6 indicate modeled parameters for one or two TAS5112 ICs on a single heat sink. The final junction temperature is set at 110C in all cases. It is assumed that the thermal grease is 0.002 inch thick and that it is similar in performance to Wakefield Type 126 thermal grease. It is important that the thermal grease layer is 0.002 inches thick and that thermal pads or tape are not used in the pad-to-heat sink interface due to the high power density that results in these extreme power cases.
Table 4. Case 1 (2 x 50 W Unclipped Into 6 , Both Channels in Same IC) (1)
56-Pin HTSSOP Ambient temperature Power to load (per channel) Power dissipation Delta T inside package Delta T through thermal grease Required heat sink thermal resistance Junction temperature System RJA 25C 50 W (unclipped) 4.5 W 10.2C, note 2 x channel dissipation 37.1C, note 2 x channel dissipation 4.2C/W 110C 19C/W
D D D
RJC (the thermal resistance from junction to case, or in this case the metal pad) Thermal grease thermal resistance Heat sink thermal resistance
RJC has been provided in the General Information section. The thermal grease thermal resistance can be calculated from the exposed pad area and the thermal grease manufacturer's area thermal resistance (expressed in C-in2/W). The area thermal resistance of the example thermal grease with a 0.002 inch thick layer is about 0.1 C-in2/W. The approximate exposed pad area is as follows: 56-pin HTSSOP 0.045 in2
RJA * power dissipation 85C Junction temperature 85C + 25C = 110C (1) This case represents a stereo system with only one package. See Case 2 and Case 2A if doing a full-power, 2-channel test in a multichannel system.
Dividing the example thermal grease area resistance by the surface area gives the actual resistance through the thermal grease for both ICs inside the package: 56-pin HTSSOP 2.27 C/W
Table 5. Case 2 (2 x 50 W Unclipped Into 6 , Channels in Separate Packages) (1)
56-Pin HTSSOP Ambient temperature Power to load (per channel) Power dissipation Delta T inside package Delta T through thermal grease Required heat sink thermal resistance Junction temperature System RJA RJA * power dissipation Junction temperature 25C 50 W (unclipped) 4.5 W 5.1C 18.6C 6.9C/W 110C 19C/W 85C 85C + 25C = 110C
The thermal resistance of thermal pads is generally considerably higher than a thin thermal grease layer. Thermal tape has an even higher thermal resistance. Neither pads nor tape should be used with either of these two packages. A thin layer of thermal grease with careful clamping of the heat sink is recommended. It may be difficult to achieve a layer 0.001 inch thick or less, so the modeling below is done with a 0.002 inch thick layer, which may be more representative of production thermal grease thickness. Heat sink thermal resistance is generally predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD) model, or measured.
14
(1) In this case, the power is separated into two packages. Note that this allows a considerably smaller heat sink because twice as much area is available for heat transfer through the thermal grease. For this reason, separating the stereo channels into two ICs is recommended in full-power stereo tests made on multichannel systems.
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TAS5112
SLES048B - JULY 2003
Table 6. Case 2A (2 x 60 W Unclipped Into 6 , Channels in Separate IC Packages) (1)
56-Pin HTSSOP Ambient temperature Power to load (per channel) Power dissipation per channel Delta T inside package Delta T through thermal grease Required heat sink thermal resistance Junction temperature System RJA RJA * power dissipation Junction temperature 25C 60 W (10% THD) 5.4 W 6.1C, note 2 x channel dissipation 22.3C, note 2 x channel dissipation 5.3C/W 110C 15.9C/W 85C 85C + 25C = 110C
CLICK AND POP REDUCTION
TI modulators feature a pop and click reduction system that controls the timing when switching starts and stops. Going from non-switching to switching operation causes a spectral energy burst to occur within the audio bandwidth, which is heard in the speaker as an audible click, for instance, after having asserted RESET LH during a system start-up. To make this system work properly, the following design rules must be followed when using the TAS5112 back end:
D
(1) In this case, the power is also separated into two packages, but overdriving causes clipping to 10% THD. In this case, the high power requires extreme care in attachment of the heat sink to ensure that the thermal grease layer is 0.002 inches thick. Note that this power level should not be attempted with both channels in a single IC because of the high power density through the thermal grease layer.
The relative timing between the PWM_AP/M_x signals and their corresponding VALID_x signal should not be skewed by inserting delays, because this increases the audible amplitude level of the click. The output stage must start switching from a fully discharged output filter capacitor. Because the output stage prior to operation is in the high-impedance state, this is done by having a passive pulldown resistor on each speaker output to GND (see Typical System Configuration).
D
Other things that can affect the audible click level:
D
The spectrum of the click seems to follow the speaker impedance vs. frequency curve--the higher the impedance, the higher the click energy. Crossover filters used between woofer and tweeter in a speaker can have high impedance in the audio band, which should be avoided if possible.
D
Thermal Pad 8,20 mm 7,20 mm
Another way to look at it is that the speaker impulse response is a major contributor to how the click energy is shaped in the audio band and how audible the click will be. The following mode transitions feature click and pop reduction.
STATE Normal(1) Mute 3,90 mm 2,98 mm Normal(1) Error recovery Normal(1) Hard Reset Mute Normal(1) Error recovery (ERRCVY) Normal(1) Hard Reset Normal(1) CLICK AND POP REDUCED Yes Yes Yes Yes No Yes
(1) Normal = switching 15
TAS5112
SLES048B - JULY 2003
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REFERENCES
1. 2. 3. 4. 5. TAS5000 Digital Audio PWM Processor data manual - TI (SLAS270) True Digital Audio Amplifier TAS5001 Digital Audio PWM Processor data sheet - TI (SLES009) True Digital Audio Amplifier TAS5010 Digital Audio PWM Processor data sheet - TI (SLAS328) True Digital Audio Amplifier TAS5012 Digital Audio PWM Processor data sheet - TI (SLES006) TAS5026 Six-Channel Digital Audio Processor data manual - TI (SLES041) PWM
6. 7. 8. 9.
TAS5036A Six-Channel Digital Audio Processor data manual - TI (SLES061)
PWM
TAS3103 Digital Audio Processor With 3D Effects data manual - TI - TI (SLES038) Digital Audio Measurements application report - TI (SLAA114) PowerPAD Thermally Enhanced technical brief - TI (SLMA002) Package
10. System Design Considerations for True Digital Audio Power Amplifiers application report - TI (SLAA117)
16
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TAS5112
SLES048B - JULY 2003
DFD (R-PDSO-G**)
48 PINS SHOWN
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE (DIE DOWN)
0,50 48
0,27 0,17 25
0,08 M
Thermal Pad (See Note D)
6,20 6,00
8,30 7,90 0,15 NOM
Gage Plane 1 A 24 0- 8 0,75 0,50 0,25
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX A MIN 48 12,60 12,40 56 14,10 13,90 64 17,10 16,90 4073260/A 02/98 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. The package thermal performance may be enhanced by attaching an external heatsink to the thermal pad. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments. 17
MECHANICAL DATA
MPDS044 - JANUARY 1998
DCA (R-PDSO-G**)
48 PINS SHOWN
PowerPADTM PLASTIC SMALL-OUTLINE PACKAGE
0,50 48
0,27 0,17 25
0,08 M
Thermal Pad (See Note D)
6,20 6,00
8,30 7,90 0,15 NOM
Gage Plane 1 A 24 0- 8 0,25 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX A MIN
48 12,60 12,40
56 14,10 13,90
64 17,10 16,90 4073259/A 01/98
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
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