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Features
* * * * * * * * * * * * *
Supply voltage up to 40 V RDSon typ. 0.5 @ 25C, max. 1 @ 150C Up to 1.5 A output current Three half-bridge outputs formed by three high-side and three low-side drivers Capable to switch all kinds of loads such as DC motors, bulbs, resistors, capacitors and inductors No crossover current Very low quiescent current Is < 10 A in stand-by mode vs. total temperature range Outputs short-circuit protected Overtemperature protection for each switch and overtemperature prewarning Undervoltage protection Various diagnosis functions such as shorted output, open load, overtemperature and power-supply fail Serial data interface, daisy chain capable, up to 2 MHz clock frequency SO14 power package
Description
T6818 / T6828 are fully protected driver interfaces designed in 0.8-m BCDMOS technology. It is used to control up to 3 different loads by a microcontroller i n a u t o m o t i v e a n d i n d u s t r i a l applications. Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 A. The drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial data interface. Therefore all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. Protection is guaranteed in terms of s h o r t - c i r c u i t c o n d i t i o n s , o v e r temperature and undervoltage. Various diagnosis functions and a very low quiescent current in stand-by-mode opens a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for demanding up-market applications.
Triple Half Bridge DMOS Output Driver with Serial Input Control T6818 T6828
Ordering Information
Extended Type Number T6818-TBS T6818-TBQ T6828-TBS T6828-TBQ Package SO14 SO14 SO14 SO14 Remarks Power package, tubed Power package with head slug, taped and reeled Power package, tubed Power package with head slug, taped and reeled
Rev. A1, 07-Nov-01
Preliminary Information
1 (16)
Preliminary Information
Block Diagram
Figure 1.
n. u.
n. u.
O C S
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
H S 3
L S 3
H S 2
L S 2
H S 1
L S 1
S R R
3
VS
Input register Output register
DI 5 P S F O P L S C D n. u. n. u. n. u. n. u. n. u. n. u. H S 3
Serial interface
L S 3 H S 2 L S 2 H S 1 L S 1 T P
Charge pump
CLK 6
CS 4 Fault detect INH 10 Fault detect Fault detect
UV protection
11
Control logic
VCC
DO 9
Power-on reset
1 7
GND GND GND GND
Fault detect
Fault detect
Fault detect
Thermal protection
13 OUT1
8 14
2 OUT3
12 OUT2
2 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Pin Configuration
Figure 2.
GND OUT3 VS CS DI CLK GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND OUT1 OUT2 VCC INH DO GND
Pin Description
Pin 1 Symbol GND Function T6818: Ground; reference potential; internal connection to Pin 7, 8 and 14; cooling tab T6828: Additional connection to heat slug Half bridge-output 3; formed by internally connected Power-MOS high-side switch 3 and low-side switch 3 with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load Power supply for output stages OUT1, OUT2 and OUT3, internal supply Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) Ground; see Pin 1 Ground; see Pin 1 Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit status information to the C (LSB is transferred first); output will remain tristated, unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. Inhibit input; 5-V logic input with internal pull down; low = stand-by, high = normal operating Logic supply voltage (5V) Half bridge-output 2; see Pin 2 Half bridge-output 1; see Pin 2 Ground; see Pin 1
2 3 4 5 6 7 8 9
OUT3 VS CS DI CLK GND GND DO
10 11 12 13 14
INH VCC OUT2 OUT1 GND
Preliminary Information
Rev. A1, 07-Nov-01
3 (16)
Preliminary Information
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3. Data transfer
CS
DI
SRR
0
LS1
1
HS1
2
LS2
3
HS2
4
LS3
5
HS3
6
n. u.
7
n. u.
8
n. u.
9
n. u.
10
n. u.
11
n. u.
12
OCS
13
n. u.
14
n. u.
15
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
SCD
OPL
PSF
Input Data Protocol
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. n. u. n. u. n. u. OCS n. u. n. u. Function Status register reset (high = reset; the bits PSF, OPL and SCD in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 Not used Not used Not used Not used Not used Not used Overcurrent shutdown (high = overcurrent shutdown is active) Not used Not used
4 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Output Data Protocol
Output (Status) Register TP Status LS1 Status HS1 Status LS2 Status HS2 Status LS3 Status HS3 n. u. n. u. n. u. n. u. n. u. n. u. SCD
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13
Function Temperature prewarning: high = warning high = output is on, low = output is off; not affected by SRR high = output is on, low = output is off; not affected by SRR Description see LS1 Description see HS1 Description see LS1 Description see HS1 Not used Not used Not used Not used Not used Not used Short circuit detected: set high, when at least one high-side or low-side switch is switched off by a short circuit condition. Bits 1 to 6 can be used to detect the shorted switch. Open load detected: set high, when at least one active high sideor low side-switch sinks/sources a current below the open load threshold current. Power-supply fail: undervoltage at Pin VS detected
14 15
OPL PSF
After power-on reset, the input register has the following status
Bit 15 Bit 14 Bit 13 (OCS) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 (HS1) Bit 1 (LS1) Bit 0 (SRR)
x
x
H
x
x
x
x
x
x
L
L
L
L
L
L
L
Power-Supply Fail
In case of undervoltage at Pin VS the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. An undervoltage condition is only detected if it occurs over the undervoltage detection delay time tdUV. After the undervoltage occurred the outputs are enabled immediately. The PSF bit keeps high until it is reset by the SRR bit in the input register. If the current through a high side or low side switch in ON-state does not reach the open load detection threshold, the open load detection bit (OPL) in the output register is set. The OPL bit keeps high until it is reset by the SRR bit in the input register. An open load condition is only detected if it occurs over the open load detection delay time tdSd.
Open-Load Detection
Overtemperature Protection
If the junction temperature at one or more switches exceeds the thermal prewarning threshold TjPW set, the temperature prewarning bit (TP) in the output register is set. When
Preliminary Information
Rev. A1, 07-Nov-01
5 (16)
Preliminary Information
temperature falls below the thermal prewarning threshold TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low the state of TP appears at Pin DO. After the C has read this information CS is set high and the data transfer is interrupted without affecting the state of input and output registers. If the junction temperature at one or more switches exceeds the thermal shutdown threshold Tj switch off, all outputs are disabled and the corresponding bits in the output register are set to low. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold Tjswitchon and writing a high to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis.
Short-Circuit Protection
The output currents are limited by a current regulator. If the overcurrent shutdown bit (OCS) in the input register is set, the concerned output is switched off after a short delay time (tdSd ) when the current exceeds the overcurrent limitation and shutdown threshold. In this case the short-circuit detection bit (SCD) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inactive. In this case the SCD bit is set also if the current exceeds the overcurrent limitation and shutdown threshold, but the outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset and the disabled outputs are enabled. To inhibit the T6818 / T6828, switch Pin 10 (INH) to 0 V. In this case all output switches are turned off and the data in the output register are deleted. The current consumption is reduced to less than 10 A out of VS and less than 20 A out of VCC. The outputs are switched to tristate. The output switches can be activated again by switching Pin 10 (INH) to 5 V which initiates an internal power-on reset.
Inhibit
6 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Absolute Maximum Ratings
All values refer to GND pins
Parameter Supply voltage Supply voltage t<0.5s; IS>-2A Logic supply voltage Logic input voltage Logic output voltage Input current Output current Output current Reverse conducting current (tpulse = 150 s) Junction-temperature range Storage-temperature range Pin 3 Pin 3 Pin 11 Pins 4 to 6, 10 Pin 9 Pins 4 to 6, 10 Pin 9 Pins 2, 12 and 13 Pins 2, 12 and 13 towards Pin 3 Symbol VVS VVS VVCC VCS,VDI, VCLK, VINH VDO ICS,IDI, ICLK, IINH IDO IOut3, IOut2, IOut1 IOut3, IOut2, IOut1 TJ TSTG Value -0.3 to 40 -1 -0.3 to 7 -0.3 to VVCC+0.3 -0.3 to VVCC+0.3 -10 to +10 -10 to +10 Internal limited, see output specification 17 -40 to 150 -55 to 150 A C C Unit V V V V V mA mA
Thermal Resistance
Parameter T6818 Junction - pin Junction - ambient T6828 Junction - pin Junction - ambient Measured to heat slug, GND Pins 1, 7, 8, 14 RthJP RthJA 5 30 K/W K/W Measured to GND Pins 1, 7, 8, 14 RthJP RthJA 30 65 K/W K/W Test Conditions Symbol Value Unit
Operating Range
Parameter Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction-temperature range Symbol VVS VVCC VCS,VDI, VCLK, VINH fCLK Tj Value VUV
1)
Unit V V V MHz C
to 40
4.75 to 5.25 -0.3 to VVCC 2 -40 to 150
Preliminary Information
Rev. A1, 07-Nov-01
7 (16)
Preliminary Information
Noise and Surge Immunity
Parameter Conducted interferences Interference suppression ESD (Human Body Model) ESD (Machine Model) ISO 7637-1 VDE 0879 Part 3 ESD S 5.1 JEDEC A115A Test Conditions Value Level 4 1) Level 6 2 kV 200 V
Electrical Characteristics
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 1 1.1 1.2 Parameters Current Consumption Quiescent current (VS ) Quiescent current (VCC) Supply current (VS) VVS < 16 V, INH = low 4.75 V < VVCC < 5.25 V INH = low , VVS <16 V normal operating, all outputs off 4.75 V < VVCC < 5.25 V, normal operating 3 11 IVS IVCC IVS 1 15 5 25 A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1.3
3
4
6
mA
A
1.4 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.3 3.4 3.5 3.6
Supply current (VCC)
11
IVCC
350
500
A
A
Undervoltage Detection, Power-On Reset Power-on reset threshold Powe-on reset delay time Undervoltagedetection threshold Undervoltagedetection hysteresis Undervoltagedetection delay time Thermal Prewarning and Shutdown Thermal prewarning Thermal prewarning Thermal prewarning hysteresis Thermal shutdown Thermal shutdown Thermal shutdown hysteresis TjPW set TjPW reset TjPW Tj switch off Tj switch on Tj switch off 150 135 120 105 145 130 15 175 160 15 200 185 170 155 C C C C C C B B B B B B After switching on VCC VCC = 5 V VCC = 5 V 3 3 11 VVCC tdPor VUv VUv tdUV 10 3.4 30 5.5 0.6 40 3.9 95 4.4 160 7.0 V s V V s A A A B A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
8 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Electrical Characteristics
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 3.7 Parameters Ratio thermal shutdown / thermal prewarning Ratio thermal shutdown / thermal prewarning Output Specification (OUT1-OUT3) On resistance On resistance Source output leakage current Sink output leakage current High-side switch reverse diode forward voltage Low-side switch reverse diode forward voltage Source overcurrent limitation and shutdown threshold Sink overcurrent limitation and shutdown threshold Overcurrent shutdown delay time Source open-load detection threshold Sink open-load detection threshold Open-load detection delay time Source output switch on delay 1) Sink output switch on delay 1) Source output switch off delay 1) Sink output switch off delay 1) VVS = 13 V, RLoad = 30 VVS = 13 V, RLoad = 30 VVS = 13 V, RLoad = 30 VVS = 13 V, RLoad = 30 2, 12, 13 2, 12, 13 IOut = 1.5 A IOut = -1.5 A VOut1-3 = 0 V, output stages off VOut1-3 = VVS, output stages off IOut = 1.5 A 2, 12, 13 2, 12, 13 2, 12, 13 2, 12, 13 2, 12, 13 2, 12, 13 2, 12, 13 2, 12, 13 RDS On L RDS On H IOut1-3 IOut1-3 VOut1-3 -VVS -15 300 1 1 A A B B A A Test Conditions Pin Symbol Tj switch off / TjPW set Tj switch on / TjPW reset Min. 1.05 Typ. 1.2 Max. Unit Type* B
3.8 4 4.1 4.2 4.3 4.4 4.5
1.05
1.2
B
1.3
V
A
4.6
IOut = -1.5 A
VOut1-3
-1.3
V
A
4.7
IOut1-3
-2.5
-2
-1.5
A
A
4.8
IOut1-3 tdSd IOut1-3 IOut1-3 tdSd tdon tdon tdoff tdoff
1.5
2
2.5
A
A
4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16
10 -45 15 200 5 15 5 1 -30 30
40 -15 45 600 15 25 15 2
s mA mA s s s s s
A A A A A A A A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Preliminary Information
Rev. A1, 07-Nov-01
9 (16)
Preliminary Information
Electrical Characteristics
7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. 4.17 5 5.1 5.2 5.3 5.4 5.5 6 6.2 6.3 7 7.1 7.2 Note: Parameters Dead time between corresponding highand low-side switches Input voltage lowlevel threshold Input voltage highlevel threshold Hysteresis of input voltage Pull-down current Pin DI, CLK, INH Pull-up current Pin CS Output-voltage high level Leakage current (tristate) Inhibit Input - Timing Standby setup time Standby setup time tIINHsethl tIINHsetlh 100 100 s s A A VDI, VCLK, VINH = VCC VCS = 0 V Test Conditions VVS = 13 V, RLoad = 30 Pin Symbol tdon -tdoff Min. 1 Typ. Max. Unit s Type* B
Logic Inputs DI, CLK, CS, INH 4-6, 10 4-6, 10 4-6, 10 5, 6, 10 4 VIL VIH VI IPD IPU 50 10 -50 0.3 x VVCC
0.7rVVC
C
V V mV A A
A A B A A
500 60 -10
Serial Interface - Logic Output DO IOL = -2 mA VCS = VCC 0V < VDO < VVCC 9 9 VDOH IDO VVCC0.7 V -10 10 V A A A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level. Device not in stand-by for t >1ms
10 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Serial Interface - Timing
Parameters DO enable after CS falling edge DO disable after CS rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CLK high time CLK low time CLK period time CLK setup time CLK setup time DI setup time DI hold time Test Conditions CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF Timing Chart No. 1 2 10 4 8 9 5 6 7 3 11 12 Symbol tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold 225 225 500 225 225 500 225 225 40 40 Min. Typ. Max. 200 200 100 100 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Preliminary Information
Rev. A1, 07-Nov-01
11 (16)
Preliminary Information
Figure 4. Serial interface timing with chart numbers
1
2
CS
DO
9
CS
4
7
CLK
5 3 6 8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
12 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
Application Circuit
Figure 5.
Vcc
U5021M Watchdog
Trigger Reset
Enable
Vs
n. u. O n. C u. S n. u. n. u. n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R
BYT41D 3
VS
V Batt
13 V +
Input register Output register
DI
Serial interface
n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 LT SP 1
Charge pump
5
P S F
O P L
S C D
n. u.
n. u.
CLK
6
C
CS
4
Fault detect Fault detect Fault detect
UV protection
11
Vcc Vcc
VCC
INH
10
Control logic
5V 1 GND 7 GND +
DO
9
Power-on reset
Fault detect
Fault detect
Fault detect
Thermal protection
2
OUT3
8 14
GND GND
12
OUT2
13
OUT1
Vcc
M
M
Application Notes
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolytic capacitor C > 22 F in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOutzx (see Absolute Maximum Ratings). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10 F in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins.
Preliminary Information
Rev. A1, 07-Nov-01
13 (16)
Preliminary Information
Package Information
Package SO14
Dimensions in mm
8.75
5.2 4.8 3.7
1.4 0.4 1.27 7.62 14 8 0.25 0.10 0.2 3.8 6.15 5.85
technical drawings according to DIN specifications
1
7
14 (16)
T6818 / T6828
Rev. A1, 07-Nov-01
T6818 / T6828
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It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
Preliminary Information
Rev. A1, 07-Nov-01
15 (16)
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Web Site
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(c) Atmel Germany GmbH 2001. Atmel Germany GmbH makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel Germany GmbH's Terms and Conditions. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel Germany GmbH are granted by the Company in connection with the sale of AtmelGermany GmbH products, expressly or by implication. Atmel Germany GmbH's products are not authorized for use as critical components in life support devices or systems. Data sheets can also be retrieved fron the Internet: http://www.atmel-wm.com
Rev. A1, 07-Nov-01

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