View T5761_1004709.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* Frequency Receiving Range of f0 = 868 MHz to 870 MHz or f0 = 902 MHz to 928 MHz * 30 dB Image Rejection * Receiving Bandwidth BIF = 600 kHz for Low Cost 90-ppm Crystals * Fully Integrated LC-VCO and PLL Loop Filter * Very High Sensitivity with Power Matched LNA * High System IIP3 (-16 dBm), System 1-dB Compression Point (-25 dBm) * High Large-signal Capability at GSM Band * * * * * * * *
(Blocking -30 dBm at +20 MHz, IIP3 = -12 dBm at +20 MHz) 5 V to 20 V Automotive Compatible Data Interface Data Clock Available for Manchester- and Bi-phase-coded Signals Programmable Digital Noise Suppression Low Power Consumption Due to Configurable Polling Temperature Range -40C to +105C ESD Protection 2 kV HBM, All Pins Communication to Microcontroller Possible Via a Single Bi-directional Data Line Low-cost Solution Due to High Integration Level with Minimum External Circuitry Requirements
UHF ASK/FSK Receiver T5760/T5761 Preliminary
Description
The T5760/T5761 is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with the Atmel's PLL RF transmitter T5750. Its main applications are in the areas of telemetering, security technology and keylessentry systems. It can be used in the frequency receiving range of f0 = 868 MHz to 870 MHz or f0 = 902 MHz to 928 MHz for ASK or FSK data transmission. All the statements made below refer to 868.3 MHz and 915.0 MHz applications. Figure 1. System Block Diagram
UHF ASK/FSK Remote control transmitter UHF ASK/FSK Remote control receiver
T5750
T5760/ T5761
PLL
Demod.
Control
1...5
C
XTO
IF Amp
Antenna VCO
Antenna PLL XTO
Power amp.
LNA
VCO
Rev. 4561B-RKE-10/02
1
Figure 2. Block Diagram
CDEM
FSK/ASKdemodulator and data filter Rssi Limiter out RSSI IF
Dem_out
Data interface
DATA
SENS AVCC AGND DGND DVCC
POLLING/_ON
Sensitivityreduction Polling circuit and control logic
Amp.
DATA_CLK
4. Order f0 = 950 kHz/ 1 MHz
FE
CLK
IC_ACTIVE
LPF fg = 2.2 MHz Standby logic
IF Amp.
Loopfilter
Poly-LPF fg = 7 MHz LC-VCO XTO
XTAL
LNAREF
f f :2 :256
LNA_IN LNAGND
LNA
2
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Pin Configuration
Figure 3. Pinning SO20
SENS 1 20 DATA
IC_ACTIVE
2
19
POLLING/_ON
CDEM
3
18
DGND
AVCC
4
17
DATA_CLK
TEST 1 5 6
16
TEST 4
AGND
T5760/ T5761
15
DVCC
n.c.
7
14
XTAL
LNAREF
8
13
n.c.
LNA_IN
9
12
TEST 3
LNAGND
10
11
TEST 2
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol SENS IC_ACTIVE CDEM AVCC TEST 1 AGND n.c. LNAREF LNA_IN LNAGND TEST 2 TEST 3 n.c. XTAL DVCC TEST 4 DATA_CLK DGND POLLING/_ON DATA Function Sensitivity-control resistor IC condition indicator: Low = sleep mode, High = active mode Lower cut-off frequency data filter Analog power supply Test pin, during operation at GND Analog ground Not connected, connect to GND High-frequency reference node LNA and mixer RF input DC ground LNA and mixer Do not connect during operating Test pin, during operation at GND Not connected, connect to GND Crystal oscillator XTAL connection Digital power supply Test pin, during operation at DVCC Bit clock of data stream Digital ground Selects polling or receiving mode; Low: receiving mode, High: polling mode Data output/configuration input
3
4561B-RKE-10/02
RF Front End
The RF front end of the receiver is a low-IF heterodyne configuration that converts the input signal into a 950 kHz/1 MHz IF signal with an image rejection of typical 30 dB. According to Figure 3 the front end consists of an LNA (Low Noise Amplifier), LO (Local Oscillator), I/Q mixer, polyphase lowpass filter and an IF amplifier. The PLL generates the carrier frequency for the mixer via a full integrated synthesizer with integrated low noise LC-VCO (Voltage Controlled Oscillator) and PLL-loop filter. The XTO (crystal oscillator) generates the reference frequency fXTO. The integrated LCVCO generates two times the mixer drive frequency fVCO. The I/Q signals for the mixer are generated with a divide by two circuit (fLO = fVCO/2). fVCO is divided by a factor of 256 and feeds into a phase frequency detector and compared with fXTO. The output of the phase frequency detector is fed into an integrated loop filter and thereby generates the control voltage for the VCO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/128 The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal with high current but low voltage signal, so that there is only a small voltage at the crystal oscillator frequency at Pin XTAL. According to Figure 4, the crystal should be connected to GND with a series capacitor CL . The value of that capacitor is recommended by the crystal supplier. Due to a somewhat inductive impedance at steady state oscillation and some PCB parasitics a lower value of CL is normally necessary. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO (the best way is to use a crystal with known load resonance frequency to find the right value for this capacitor) and hereby of fLO. When designing the system in terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the XTO must be considered. If a crystal with 30 ppm adjustment tolerance at 25C, 50 ppm over temperature -40C to +105C, 10 ppm of total aging and a CM (motional capacitance) of 7 fF is used, an additional XTO pulling of 30 ppm has to be added. The resulting total LO tolerance of 120 ppm agrees with the receiving bandwidth specification of the T5760/T5761 if the T5750 has also a total LO tolerance of 120 ppm. Figure 4. XTO Peripherals
VS DVCC CL XTAL n.c. TEST 3 TEST 2
The nominal frequency f LO is determined by the RF input frequency f RF and the IF frequency fIF using the following formula (low side injection): fLO = fRF - fIF
4
T5760/T5761
4561B-RKE-10/02
T5760/T5761
To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 950 kHz. To achieve a good accuracy of the filter corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO. fIF = fLO/915 The relation is designed to achieve the nominal IF frequency of fIF = 950 kHz for the 868.3 MHz version. For the 915 MHz version an IF frequency of fIF = 1.0 MHz results. The RF input either from an antenna or from an RF generator must be transformed to the RF input Pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances influence the input matching. The RF receiver T5760/T5761 exhibits its highest sensitivity if the LNA is power matched. This makes the matching to an SAW filter as well as to 50 W or an antenna easier. Figure 33 shows a typical input matching network for fRF = 868.3 MHz to 50 W. Figure 34 illustrates an according input matching for 868.3 MHz to an SAW. The input matching network shown in Figure 33 is the reference network for the parameters given in the electrical characteristics.
Analog Signal Processing
IF Filter
The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 950 kHz for applications where fRF = 868.3 MHz and fIF =1.0 MHz for fRF = 915 MHz. The nominal bandwidth is 600 kHz. The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DRRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity. In FSK mode the S/N ratio is not affected by the dynamic range of the RSSI amplifier, because only the hard limited signal from a high gain limiting amplifier is used by the demodulator. The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red. VTh_red is determined by the value of the external resistor RSens. RSens is connected between Pin SENS and GND or VS. The output of the comparator is fed into the digital control logic. By this means it is possible to operate the receiver at a lower sensitivity. If RSens is connected to GND, the receiver switches to full sensitivity. It is also possible to connect the Pin SENS directly to GND to get the maximum sensitivity. If RSens is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of RSens, the maximum sensitivity by the signal-tonoise ratio of the LNA input. The reduced sensitivity depends on the signal strength at the output of the RSSI amplifier.
Limiting RSSI Amplifier
5
4561B-RKE-10/02
Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 33 and exhibits the best possible sensitivity and at the same time power matching at RF_IN. R Sens can be connected to V S or GND via a microcontroller. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at Pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to Figure 5 is issued at Pin DATA to indicate that the receiver is still active (see Figure 32). Figure 5. Steady L State Limited DATA Output Pattern
DATA
t DATA_min t DATA_L_max
FSK/ASK Demodulator and Data Filter
The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via the bit ASK/_FSK in the OPMODE register. Logic `L' sets the demodulator to FSK, applying `H' to ASK mode. In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal to noise ratio is achieved. This circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. If the S/N (ratio to suppress in-band noise signals) exceeds about 10 dB the data signal can be detected properly, but better values are found for many modulation schemes of the competing transmitter. The FSK demodulator is intended to be used for an FSK deviation of 10 kHz Df 100 kHz. In FSK mode the data signal can be detected if the S/N (ratio to suppress inband noise signals) exceeds about 2 dB. This value is valid for all modulation schemes of a disturber signal. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its passband can be adopted to the characteristics of the data signal. The data filter consists of a 1storder high pass and a 2nd-order lowpass filter. The highpass filter cut-off frequency is defined by an external capacitor connected to Pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula: 1 fcu_DF = ---------------------------------------------------------2 p 30 kW CDEM In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the lowpass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is defined in the OPMODE register (refer to chapter `Configuration of the Receiver'). The BR_Range must be set in accordance to the used baud-rate.
6
T5760/T5761
4561B-RKE-10/02
T5760/T5761
The T5760/T5761 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 2 dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver.
Receiving Characteristics
The RF receiver T5760/T5761 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity and large signal capability. The receiving frequency response without a SAW front-end filter is illustrated in Figure 6 and Figure 7. This example relates to ASK mode. FSK mode exhibits a similar behavior. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 3 dB must be considered, but the overall selectivity is much better. When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated, to be the sum of the deviation of the crystal and the XTO deviation of the T5760/T5761. Low-cost crystals are specified to be within 90 ppm over tolerance, temperature and aging. The XTO deviation of the T5760/T5761 is an additional deviation due to the XTO circuit. This deviation is specified to be 30 ppm worst case for a crystal with CM = 7 fF. If a crystal of 90 ppm is used, the total deviation is 120 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode. Figure 6. Narrow Band Receiving Frequency Response
0.0
-10.0
-20.0
dP (dB)
-30.0
-40.0
-50.0
-60.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0
df (MHz)
7
4561B-RKE-10/02
Figure 7. Wide Band Receiving Frequency Response
0.0 -10.0 -20.0 -30.0 -40.0
dP (dB)
-50.0 -60.0 -70.0 -80.0 -90.0 -100.0 -12.0
-9.0
-6.0
-3.0
0.0
3.0
6.0
9.0
12.0
df (MHz)
Polling Circuit and Control Logic
The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected, the receiver remains active and transfers the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc. Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected microcontroller or it can be operated by up to five uni-directional ports.
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the analog filtering is derived from one clock. This clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divide by 14 circuit. According to chapter `RF Front End', the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin) which also defines the operating frequency of the local oscillator (fLO). The basic clock cycle is TClk = 14/fXTO giving TClk = 2.066 s for fRF = 868.3 MHz and TClk = 1.961 s for fRF = 915 MHz. TClk controls the following application-relevant parameters: * * * * * Timing of the polling circuit including bit check Timing of the analog and digital signal processing Timing of the register programming Frequency of the reset marker IF filter center frequency (fIF0)
Most applications are dominated by two transmission frequencies: fTransmit = 915 MHz is mainly used in USA, fTransmit = 868.3 MHz in Europe. In order to ease the usage of all TClk-dependent parameters on this electrical characteristics display three conditions for each parameter.
8
T5760/T5761
4561B-RKE-10/02
T5760/T5761
* * * Application USA (fXTO = 7.14063 MHz, TClk = 1.961 s) Application Europe (fXTO = 6.77617 MHz, TClk = 2.066 s) Other applications The electrical characteristic is given as a function of TClk.
The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range) which is defined in the OPMODE register. This clock cycle TXClk is defined by the following formulas for further reference: BR_Range = BR_Range0: BR_Range1: BR_Range2: BR_Range3: TXClk = 8 TClk TXClk = 4 TClk TXClk = 2 TClk TXClk = 1 TClk
Polling Mode
According to Figure 11, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode the signal processing circuitry is disabled for the time period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period TBit-check. This period varies check by check as it is a statistical process. An average value for TBit-check is given in the electrical characteristics. During TStartup and TBit-check the current consumption is IS = ISon. The condition of the receiver is indicated on Pin IC_ACTIVE. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: I Soff T Sleep + I Son ( T Startup + T Bit-check ) I Spoll = ------------------------------------------------------------------------------------------------------------T Sleep + T Startup + T Bit-check During TSleep and TStartup the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command the transmitter must start the telegram with an adequate preburst. The required length of the preburst depends on the polling parameters TSleep, TStartup, TBit-check and the start-up time of a connected microcontroller (TStart_microcontroller). Thus, TBit-check depends on the actual bit rate and the number of bits (NBit-check) to be tested. The following formula indicates how to calculate the preburst length. TPreburst TSleep + TStartup + TBit-check + TStart_microcontroller
Sleep Mode
The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor XSleep (according to Table 8), and the basic clock cycle TClk. It is calculated to be: TSleep = Sleep XSleep 1024 TClk In US- and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd to'1'. According to Table 7, the highest register value of sleep sets the receiver into a permanent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line and may also be used for microcontroller polling - via Pin POLLING/_ON, the receiver can be switched on and off.
9
4561B-RKE-10/02
Figure 8. Polling Mode Flow Chart
Sleep mode: All circuits for signal processing are disabled. Only XTO and Polling logic is enabled. Output level on Pin IC_ACTIVE => low IS = ISoff TSleep = Sleep x XSleep x 1024 x TClk
Sleep: XSleep: TClk:
Start-up mode: The signal processing circuits are enabled. After the start-up time (TStartup) all circuits are in stable condition and ready to receive. Output level on Pin IC_ACTIVE => high IS = ISon TStartup
5-bit word defined by Sleep0 to Sleep4 in OPMODE register Extension factor defined by XSleepStd according to Table 9 Basic clock cycle defined by fXTO and Pin MODE Is defined by the selected baud rate range and TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register.
TStartup:
Bit-check mode: The incomming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. Output level on Pin IC_ACTIVE => high IS = ISon TBit-check NO Bit check OK ?
T Bit-check :
Depends on the result of the bit check If the bit check is ok, TBit-check depends on the number of bits to be checked (NBit-check) and on the utilized data rate. If the bit check fails, the average time period for that check depends on the selected baud-rate range and on TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register.
YES Receiving mode: The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via Pin DATA or POLLING/_ON. Output level on Pin IC_ACTIVE => high IS = ISon OFF command
Figure 9. Timing Diagram for Complete Successful Bit Check
( Number of checked Bits: 3 ) Bit check ok
IC_ACTIVE Bit check Dem_out Data_out (DATA) 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
TStart-up Start-up mode
T Bit-check Bit-check mode Receiving mode
10
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Bit-check Mode
In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge tests before the receiver switches to receiving mode is also programmable. Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBit-check in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If NBit-check is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if NBit-check is set to a lower value. In polling mode, the bit-check time is not dependent on NBit-check. Figure 9 shows an example where 3 bits are tested successfully and the data signal is transferred to Pin DATA. According to Figure 10, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time tee is in between the lower bit-check limit TLim_min and the upper bit-check limit TLim_max, the check will be continued. If tee is smaller than T Lim_min or t ee exceeds T Lim_max , the bit check will be terminated and the receiver switches to sleep mode. Figure 10. Valid Time Window for Bit Check
1/fSig tee TLim_min TLim_max
Configuring the Bit Check
Dem_out
For best noise immunity it is recommended to use a low span between TLim_min and TLim_max. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A `11111...' or a `10101...' sequence in Manchester or Bi-phase is a good choice concerning that advice. A good compromise between receiver sensitivity and susceptibility to noise is a time window of 30% regarding the expected edge-to-edge time tee. Using pre-burst patterns that contain various edge-to-edge time periods, the bitcheck limits must be programmed according to the required span. The bit-check limits are determined by means of the formula below. TLim_min = Lim_min TXClk TLim_max = (Lim_max -1) TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using above formulas, Lim_min and Lim_max can be determined according to the required TLim_min, TLim_max and TXClk. The time resolution defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to the chapter `Receiving Mode'. The lower limit should be set to Lim_min 10. The maximum value of the upper limit is Lim_max = 63. If the calculated value for Lim_min is <19, it is recommended to check 6 or 9 bits (NBit-check) to prevent switching to receiving mode due to noise.
11
4561B-RKE-10/02
Figure 14, Figure 15 and Figure 16 illustrate the bit check for the bit-check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during TStartup. The output of the ASK/FSK demodulator (Dem_out) is undefined during that period. When the bit check becomes active, the bit-check counter is clocked with the cycle TXClk. Figure 14 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 15 the bit check fails as the value CV_Lim is lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 16. Figure 11. Timing Diagram During Bit Check
( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check 1/2 Bit Dem_out Bit-checkcounter
0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4
Bit check ok
Bit check ok
1/2 Bit
1/2 Bit
TStart-up Start-up mode
TXClk
TBit-check Bit-check mode
Figure 12. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check 1/2 Bit Dem_out Bit-checkcounter
0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12 0
Bit check failed ( CV_Lim < Lim_min )
TStart-up Start-up mode
TBit-check Bit-check mode
TSleep Sleep mode
Figure 13. Timing Diagram for Failed Bit Check (Condition: CV_Lim >= Lim_max)
( Lim_min = 14, Lim_max = 24 ) IC_ACTIVE Bit check 1/2 Bit Dem_out Bit-checkcounter
0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0
Bit check failed ( CV_Lim >= Lim_max )
TStart-up Start-up mode
TBit-check Bit-check mode
TSleep Sleep mode
12
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Duration of the Bit Check If no transmitter signal is present during the bit check, the output of the ASK/FSK
demodulator delivers random signals. The bit check is a statistical process and TBit-check varies for each check. Therefore, an average value for TBit-check is given in the electrical characteristics. TBit-check depends on the selected baud-rate range and on TClk. A higher baud-rate range causes a lower value for TBit-check resulting in a lower current consumption in polling mode. In the presence of a valid transmitter signal, TBit-check is dependent on the frequency of that signal, fSig, and the count of the checked bits, NBit-check. A higher value for NBit-check thereby results in a longer period for TBit-check requiring a higher value for the transmitter pre-burst TPreburst.
Receiving Mode
If the bit check was successful for all bits specified by NBit-check, the receiver switches to receiving mode. According to Figure 9, the internal data signal is switched to Pin DATA in that case and the data clock is available after the start bit has been detected (see Figure 20). A connected microcontroller can be woken up by the negative edge at Pin DATA or by the data clock at Pin DATA_CLK. The receiver stays in that condition until it is switched back to polling mode explicitly.
Digital Signal Processing The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different
ways and as a result converted into the output signal data. This processing depends on the selected baud-rate range (BR_Range). Figure 14 illustrates how Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the bit-check counter. Data can change its state only after TXClk has elapsed. The edge-to-edge time period tee of the Data signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to tee TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. The maximum time period for DATA to stay Low is limited to TDATA_L_max. This function is employed to ensure a finite response time in programming or switching off the receiver via Pin DATA. TDATA_L_max is thereby longer than the maximum time period indicated by the transmitter data stream. Figure 16 gives an example where Dem_out remains Low after the receiver has switched to receiving mode. Figure 14. Synchronization of the Demodulator Output
T XClk Clock bit-check counter Dem_out Data_out (DATA)
t ee
13
4561B-RKE-10/02
Figure 15. Debouncing of the Demodulator Output
Dem_out Data_out (DATA) t DATA_min tDATA_min t DATA_min
tee
t ee
t ee
Figure 16. Steady L State Limited DATA Output Pattern After Transmission
IC_ACTIVE
Bit check Dem_out Data_out (DATA) tDATA_min Start-up mode Bit-check mode Receiving mode
tDATA_L_max
After the end of a data transmission, the receiver remains active. Depending of the bit Noise_Disable in the OPMODE register, the output signal at Pin DATA is high or random noise pulses appear at Pin DATA (see chapter 'Digital Noise Suppression'). The edge-to-edge time period tee of the majority of these noise pulses is equal or slightly higher than TDATA_min.
Switching the Receiver Back to Sleep Mode
The receiver can be set back to polling mode via Pin DATA or via Pin POLLING/_ON. When using Pin DATA, this pin must be pulled to Low for the period t1 by the connected microcontroller. Figure 17 illustrates the timing of the OFF command (see Figure 32). The minimum value of t1 depends on BR_Range. The maximum value for t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. Note also that an internal reset for the OPMODE and the LIMIT register will be generated if t1 exceeds the specified values. This item is explained in more detail in the chapter `Configuration of the Receiver'. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 to be `1' during the register configuration. Only one sync pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF command the sleep time TSleep elapses. Note that the capacitive load at Pin DATA is limited (see chapter 'Data Interface').
14
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Figure 17. Timing Diagram of the OFF Command via Pin DATA
IC_ACTIVE
t1 t2 t3 t4 t10 t7 t5
Out1 (microcontroller)
Data_out (DATA)
X
Serial bi-directional data line
X
Bit 1 ("1") (Start bit) OFF-command Receiving mode TSleep Sleep mode TStart-up Start-up mode
Figure 18. Timing Diagram of the OFF Command via Pin POLLING/_ON
IC_ACTIVE ton2 ton3 Bit check ok
POLLING/_ON X
Data_out (DATA)
X
Serial bi-directional data line
X Receiving mode Sleep mode Start-up mode Bit-check mode
X
Receiving mode
Figure 19. Activating the Receiving Mode via Pin POLLING/_ON
IC_ACTIVE t on1
POLLING/_ON X
Data_out (DATA)
Serial bi-directional data line Sleep mode Start-up mode
X
Receiving mode
15
4561B-RKE-10/02
Figure 18 illustrates how to set the receiver back to polling mode via Pin POLLING/_ON. The Pin POLLING/_ON must be held to low for the time period ton2. After the positive edge on Pin POLLING/_ON and the delay ton3, the polling mode is active and the sleep time TSleep elapses. This command is faster than using Pin DATA at the cost of an additional connection to the microcontroller. Figure 19 illustrates how to set the receiver to receiving mode via the Pin POLLING/_ON. The Pin POLLING/_ON must be held to Low. After the delay ton1, the receiver changes from sleep mode to start-up mode regardless the programmed values for TSleep and NBit-check. As long as POLLING/_ON is held to Low, the values for TSleep and NBit-check will be ignored, but not deleted (see chapter 'Digital Noise Suppression'). If the receiver is polled exclusively by a microcontroller, TSleep must be programmed to 31 (permanent sleep mode). In this case the receiver remains in sleep mode as long as POLLING/_ON is held to High.
Data Clock
The Pin DATA_CLK makes a data shift clock available to sample the data stream into a shift register. Using this data clock, a microcontroller can easily synchronize the data stream. This clock can only be used for Manchester and Bi-phase coded signals. After a successful bit check, the receiver switches from polling mode to receiving mode and the data stream is available at Pin DATA. In receiving mode, the data clock control logic (Manchester/Bi-phase demodulator) is active and examines the incoming data stream. This is done, like in the bit check, by subsequent time frame checks where the distance between two edges is continuously compared to a programmable time window. As illustrated in Figure 20, only two distances between two edges in Manchester and Bi-phase coded signals are valid (T and 2T). The limits for T are the same as used for the bit check. They can be programmed in the LIMIT-register (Lim_min and Lim_max, see Table 10 and Table 11). The limits for 2T are calculated as follows: Lower limit of 2T: Lim_min_2T = (Lim_min + Lim_max) - (Lim_max - Lim_min)/2 Upper limit of 2T: Lim_max_2T= (Lim_min + Lim_max) + (Lim_max - Lim_min)/2 (If the result for 'Lim_min_2T' or 'Lim_max_2T' is not an integer value, it will be round up) The data clock is available, after the data clock control logic has detected the distance 2T (Start bit) and is issued with the delay tDelay after the edge on Pin DATA (see Figure 20). If the data clock control logic detects a timing or logical error (Manchester code violation), like illustrated in Figure 21 and Figure 22, it stops the output of the data clock. The receiver remains in receiving mode and starts with the bit check. If the bit check was successful and the start bit has been detected, the data clock control logic starts again with the generation of the data clock (see Figure 23). It is recommended to use the function of the data clock only in conjunction with the bit check 3, 6 or 9. If the bit check is set to 0 or the receiver is set to receiving mode via the Pin POLLING/_ON, the data clock is available if the data clock control logic has detected the distance 2T (Start bit). Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit.
Generation of the Data Clock
16
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Figure 20. Timing Diagram of the Data Clock
Preburst Bit check ok T '1' Dem_out '1' '1' '1' '1' 2T '0' '1' '1' '0' '1' '0' Data
Data_out (DATA)
DATA_CLK Start bit Bit-check mode tDelay Receiving mode, data clock control logic active tP_Data_Clk
Figure 21. Data Clock Disappears Because of a Timing Error
Data
Timing error (T ee < T Lim_min OR T Lim_max T Lim_max_2T) T ee
'1' Dem_out
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Data_out (DATA)
DATA_CLK Receiving mode, data clock control logic active Receiving mode, bit check active
Figure 22. Data Clock Disappears Because of a Logical Error
Data Logical error (Manchester code violation)
'1' Dem_out
'1'
'1'
'0'
'1'
'1'
'?'
'0'
'0'
'1'
'0'
Data_out (DATA)
DATA_CLK Receiving mode, data clock control logic active Receiving mode, bit check aktive
17
4561B-RKE-10/02
Figure 23. Output of the Data Clock After a Successful Bit Check
Data Bit check ok
'1' Dem_out
'1'
'1'
'1'
'1'
'0'
'1'
'1'
'0'
'1'
'0'
Data_out (DATA)
DATA_CLK Receiving mode, bit check active
Start bit
Receiving mode, data clock control logic active
The delay of the data clock is calculated as follows: tDelay = tDelay1 + tDelay2 tDelay1 is the delay between the internal signals Data_Out and Data_In. For the rising edge, tDelay1 depends on the capacitive load CL at Pin DATA and the external pull-up resistor Rpup. For the falling edge, tDelay1 depends additionally on the external voltage VX (see Figure 24, Figure 25 and Figure 32). When the level of Data_In is equal to the level of Data_Out, the data clock is issued after an additional delay tDelay2. Note that the capacitive load at Pin DATA is limited. If the maximum tolerated capacitive load at Pin DATA is exceeded, the data clock disappears (see chapter 'Data Interface'). Figure 24. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA)
Data_Out
V X V Ih = 0,65 * V S V Il = 0,35 * V S
Serial bi-directional data line Data_In DATA_CLK
tDelay1 tDelay
tDelay2 tP_Data_Clk
Figure 25. Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA)
Data_Out
VX V Ih = 0,65 * V S V Il = 0,35 * V S
Serial bi-directional data line Data_In DATA_CLK t Delay1 t Delay t Delay2 tP_Data_Clk
18
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Digital Noise Suppression
Automatic Noise Suppression
After a data transmission, digital noise appears on the data output (see Figure 26). Preventing that digital noise keeps the connected microcontroller busy. It can be suppressed in two different ways. If the bit Noise_Disable (Table 9) in the OPMODE register is set to 1 (default), the receiver changes to bit-check mode at the end of a valid data stream. The digital noise is suppressed and the level at Pin DATA is High in that case. The receiver changes back to receiving mode, if the bit check was successful. This way to suppress the noise is recommended if the data stream is Manchester or Bi-phase coded and is active after power on. Figure 28 illustrates the behavior of the data output at the end of a data stream. Note that if the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on Pin DATA. The length of the pulse depends on the selected baud-rate range. Figure 26. Output of Digital Noise at the End of the Data Stream
Bit check ok Data_out (DATA) DATA_CLK Bit-check mode Receiving mode, data clock control logic active Receiving mode, bit check aktive Receiving mode, data clock control logic active Receiving mode, bit check aktive Preburst Data Digital Noise Bit check ok Digital Noise Preburst Data Digital Noise
Figure 27. Automatic Noise Suppression
Bit check ok Data_out (DATA) DATA_CLK Bit-check mode Receiving mode, data clock control logic active Bit-check mode Receiving mode, data clock control logic active Bit-check mode Preburst Data Bit check ok Preburst Data
Figure 28. Occurrence of a Pulse at the End of the Data Stream
Timing error
(tee < TLim_min OR TLim_max < tee < TLim_min_2T OR tee > TLim_max2T
T ee Data stream Digital noise
'1' Dem_out
'1'
'1'
Data_out (DATA)
T Pulse
DATA_CLK Receiving mode, data clock control logic active Bit-check mode
19
4561B-RKE-10/02
Controlled Noise Suppression by the Microcontroller
Figure 29. Controlled Noise Suppression
Bit check ok Serial bi-directional data line (DATA_CLK) POLLING/_ON Bit-check mode Receiving mode Start-up Bit-check mode mode Receiving mode Sleep mode Preburst Data OFF-command Digital Noise Bit check ok Preburst Data Digital Noise
If the bit Noise_Disable (see Table 9) in the OPMODE register is set to 0, digital noise appears at the end of a valid data stream. To suppress the noise, the Pin POLLING/_ON must be set to Low. The receiver remains in receiving mode. Then, the OFF command causes the change to the start-up mode. The programmed sleep time (see Table 7) will not be executed because the level at Pin POLLING/_ON is low, but the bit check is active in that case. The OFF command activates the bit check also if the Pin POLLING/_ON is held to Low. The receiver changes back to receiving mode if the bit check was successful. To activate the polling mode at the end of the data transmission, the Pin POLLING/_ON must be set to High. This way of suppressing the noise is recommended if the data stream is not Manchester or Bi-phase coded.
Configuration of the Receiver
The T5760/T5761 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a Power-On Reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 3 shows the structure of the registers. According to Table 2, bit 1 defines if the receiver is set back to polling mode via the OFF command (see chapter 'Receiving Mode') or if it is programmed. Bit 2 represents the register address. It selects the appropriate register to be programmed. To get a high programming reliability, Bit 15 (Stop bit), at the end of the programming operation, must be set to 0. Table 1. Effect of Bit 1 and Bit 2 on Programming the Registers
Bit 1 1 0 0 Bit 2 x 1 0 Action The receiver is set back to polling mode (OFF command) The OPMODE register is programmed The LIMIT register is programmed
Table 2. Effect of Bit 15 on Programming the Register
Bit 15 0 1 Action The values will be written into the register (OPMODE or LIMIT) The values will not be written into the register
20
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Table 3. Effect of the Configuration Words within the Registers
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 OFF command 1 - BR_Range 0 1 Baud1 Default values of Bit 3...14 - Lim_min 0 0 Lim_ min5 0 Lim_ min4 1 Lim_ min3 0 Lim_ min2 1 Lim_ min1 0 Lim_ min0 1 Lim_ max5 1 Lim_ max4 0 Baud0 BitChk1 BitChk0 NBit-check Modulation ASK/ _FSK 0 Sleep4 Sleep3 - - - - - - - - - - - - - - - Sleep X Sleep Sleep1 Sleep0 XSleep
Std
OPMODE register Noise Suppres sion Noise_ Disable 1
0
Sleep2
0
0
0
1
0
0
1
1
0
0
- -
LIMIT register Lim_max Lim_ max3 1 Lim_ max2 0 Lim_ max1 0 Lim_ max0 1
- 0
Default values of Bit 3...14
-
The following tables illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits TLim_min and TLim_max as shown in Table 10 and Table 11. Table 4. Effect of the configuration word BR_Range
BR_Range Baud1 0 Baud0 0 Baud-rate Range/Extension Factor for Bit-check Limits (XLim) BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) XLim = 8 (default) BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4 BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 BR_Range3 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1
0
1
1
0
1
1
Table 5. Effect of the Configuration word NBit-check
NBit-check BitChk1 0 0 1 1 BitChk0 0 1 0 1 Number of Bits to be Checked 0 3 (default) 6 9
21
4561B-RKE-10/02
Table 6. Effect of the Configuration Bit Modulation
Modulation ASK/_FSK 0 1 Selected Modulation - FSK (default) ASK
Table 7. Effect of the Configuration Word Sleep
Sleep Sleep4 0 Sleep3 0 Sleep2 0 Sleep1 0 Sleep0 0 Start Value for Sleep Counter (TSleep = Sleep x Xsleep x 1024 x TClk) 0 (Receiver is continuously polling until a valid signal occurs) 1 (TSleep 2.1 ms for XSleep = 1 and fRF = 868.3 ms, 2.0 ms for fRF = 915 MHz) 2 3 ... 6 (TSleep = 12.695 ms for fRF = 868.3 MHz, 12.047 ms for fRF = 915 MHz) (default) ... 29 30 31 (permanent sleep mode)
0 0 0 ... 0 ... 1 1 1
0 0 0 ... 0 ... 1 1 1
0 0 0 ... 1 ... 1 1 1
0 1 1 ... 1 ... 0 1 1
1 0 1 ... 0 ... 1 0 1
Table 8. Effect of the Configuration Bit XSleep
XSleep XSleepStd 0 1 Extension Factor for Sleep Time (TSleep = Sleep x Xsleep x 1024 x TClk) 1 (default) 8
Table 9. Effect of the Configuration Bit Noise Suppression
Noise Suppression Noise_Disable
0 1
Suppression of the Digital Noise at Pin DATA
Noise suppression is inactive Noise suppression is active (default)
22
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Table 10. Effect of the Configuration Word Lim_min
Lim_min (1) (Lim_min < 10 is not Applicable) Lim_min5 0 0 0 .. Lim_min4 0 0 0 .. Lim_min3 1 1 1 .. Lim_min2 0 0 1 .. Lim_min1 1 1 0 .. Lim_min0 0 1 0 .. 21 (default) (TLim_min = 347 s for fRF = 868.3 MHz and BR_Range0 TLim_min = 329 s for fRF = 915 MHz and BR_Range0) 61 62 63 Lower Limit Value for Bit Check (TLim_min = Lim_min x XLim x TClk) 10 11 12
0
1
0
1
0
1
.. 1 1 1 Note:
.. 1 1 1
.. 1 1 1
.. 1 1 1
.. 0 1 1
.. 1 0 1
1. Lim_min is also used to determine the margins of the data clock control logic (see chapter 'Data Clock').
Table 11. Effect of the Configuration Word Lim_max
Lim_max (1) (Lim_max < 12 is not applicable) Lim_max5 0 0 0 .. Lim_max4 0 0 0 .. Lim_max3 1 1 1 .. Lim_max2 1 1 1 .. Lim_max1 0 0 1 .. Lim_max0 0 1 0 .. 41 (default) (TLim_max = 661 s for fRF = 868.3 MHz and BR_Range0, TLim_max = 627 s for fRF = 915 MHz and BR_Range0) 61 62 63 Upper Limit Value for Bit Check (TLim_max = (Lim_max - 1) x XLim x TClk) 12 13 14
1
0
1
0
0
1
.. 1 1 1 Note:
.. 1 1 1
.. 1 1 1
.. 1 1 1
.. 0 1 1
.. 1 0 1
1. Lim_max is also used to determine the margins of the data clock control logic (see chapter 'Data Clock').
23
4561B-RKE-10/02
Conservation of the Register Information
The T5760/T5761 implies an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to Figure 30, a power-on reset (POR) is generated if the supply voltage VS drops below the threshold voltage VThReset. The default parameters are programmed into the configuration registers in that condition. Once V S exceeds V ThReset the POR is canceled after the minimum reset period tRst. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at Pin DATA after a reset. The RM is represented by the fixed frequency fRM at a 50% duty-cycle. RM can be canceled via a Low pulse t1 at Pin DATA. The RM implies the following characteristics: * * fRM is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be misinterpreted by the connected microcontroller. If the receiver is set back to polling mode via Pin DATA, RM cannot be canceled by accident if t1 is applied according to the proposal in the section "Programming the Configuration Registers".
By means of that mechanism the receiver cannot lose its register information without communicating that condition via the reset marker RM. Figure 30. Generation of the Power-on Reset
VS POR tRst Data_out (DATA) X
V ThReset
1 / f RM
24
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Programming the Configuration Register
Figure 31. Timing of the Register Programming
IC_ACTIVE t1 t2 t3 t4 Out1 (microcontroller) t5 t6 t7 t9 t8
Data_out (DATA) Serial bi-directional data line
X
X Bit 1 ("0") (Start bit) Bit 2 ("1") (Registerselect) Programming frame Receiving mode Bit 14 ("0") (Poll8) Bit 15 ("0") (Stop bit) TSleep TStart-up SleepStart-up mode mode
Figure 32. Data Interface
V X = 5 V to 20 V V S = 4.5 V to 5.5 V
T5760/ T5761
Rpup DATA I/O
Serial bi-directional data line
Microcontroller
0V/5V
Data_In
Input Interface
0 ... 20 V
ID
CL
Data_out
Out1 (microcontroller )
The configuration registers are programmed serially via the bi-directional data line according to Figure 31 and Figure 32. To start programming, the serial data line DATA is pulled to Low for the time period t1 by the microcontroller. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 15 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the programming window, the individual bits are set. If the microcontroller pulls down Pin DATA for the time period t7 during t5, the according bit is set to '0'. If no programming pulse t7 is issued, this bit is set to '1'. All 15 bits are subsequently programmed this way. The time frame to program a bit is defined by t6.
25
4561B-RKE-10/02
Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. Programming of a register is possible both in sleep-mode and in active-mode of the receiver. During programming, the LNA, LO, lowpass filter IF-amplifier and the FSK/ASK Manchester demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to '1', it represents the OFF command to set the receiver back to polling mode at the same time. For the length of the programming start pulse t1, the following convention should be considered: * t1(min) < t1 < 5632 TClk: t1(min) is the minimum specified value for the relevant BR_Range
Programming respectively OFF command is initiated if the receiver is not in reset mode. If the receiver is in reset mode, programming respectively Off command is not initiated and the reset marker RM is still present at Pin DATA. This period is generally used to switch the receiver to polling mode or to start the programming of a register. In reset condition, RM is not cancelled by accident. * t1 > 7936 x TClk Programming respectively OFF command is initiated in any case. The registers OPMODE and LIMIT are set to the default values. RM is cancelled if present. This period is used if the connected microcontroller detected RM. If the receiver operates in default mode, this time period for t1 can generally be used. Note that the capacitive load at Pin DATA is limited.
Data Interface
The data interface (see Figure 32) is designed for automotive requirements. It can be connected via the pull-up resistor Rpup up to 20 V and is short-circuit-protected. The applicable pull-up resistor Rpup depends on the load capacity CL at Pin DATA and the selected BR_range (see Table 12). Table 12. Applicable Rpup
BR_range Applicable Rpup
B0 CL 1nF B1 B2 B3 B0 CL 100pF B1 B2 B3
1.6 kW to 47 kW 1.6 kW to 22 kW 1.6 kW to 12 kW 1.6 kW to 5.6 kW 1.6 kW to 470 kW 1.6 kW to 220 kW 1.6 kW to 120 kW 1.6 kW to 56 kW
26
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Figure 33. Application Circuit: fRF = 868.3 MHz without SAW Filter
VS C7 4.7u 10% GND R3 >= 1.6k C14 39n 5% C13 10n 10%
1 SENS 2 IC_ACTIVE 3 CDEM 4 AVCC 5 TEST1 6 AGND 7 n.c. DATA POLLING/_ON DGND DATA_CLK TEST4 DVCC XTAL 20 19 18 17 16 15
IC_ACTIVE R2 Sensitivity reduction 56k to 150k VX = 5 V to 20 V
DATA POLLING/_ON DATA_CLK C12 10n 10% C11 12p 2% np0
T5760/ T5761
Q1
14
8 LNAREF 9 LNA_IN 10 LNAGND
n.c. 13 12 TEST3 11 TEST2
6.77617 MHz
RF_IN
C17 1.5p 0.1p np0
C16 18p 5% np0 Toko LL1608-FS4N7S 4.7nH, 0.3nH
Figure 34. Application Circuit: fRF = 868.3 MHz with SAW Filter
VS IC_ACTIVE C7 4.7u 10% GND
1 SENS 2 IC_ACTIVE 3 CDEM 4 AVCC 5 TEST1 6 AGND 7 n.c. DATA POLLING/_ON DGND DATA_CLK TEST4 DVCC XTAL 20 19 18 17 16 15
R2 Sensitivity reduction 56k to 150k R3 >= 1.6k C14 39n 5% C13 10n 10% VX = 5 V to 20 V
DATA POLLING/_ON DATA_CLK C12 10n 10% C11 12p 2% np0
T5760/ T5761
Q1
14
8 LNAREF 9 LNA_IN 10 LNAGND
n.c. 13 12 TEST3 11 TEST2
6.77617 MHz
C16 18p 5% np0
C17 5.6p 0.1p np0 Toko LL1608-FS4N7S 4.7nH, 0.3nH
RF_IN
Toko LL1608-FS12NJ 12nH, 5% 1 C2 3.3p 0.1p np0
EPCOS B3570 IN OUT OUT_GND CASE_GND CASE_GND 5 6 7 8
2 IN_GND 3 CASE_GND 4 CASE_GND
27
4561B-RKE-10/02
Absolute Maximum Ratings
Parameters
Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Maximum input level, input matched to 50 W
Symbol
VS Ptot Tj Tstg Tamb Pin_max
Min.
Max.
6 1000 150
Unit
V mW
C C C
-55 -40
+125 +105 10
dBm
Thermal Resistance
Parameters
Junction ambient
Symbol
RthJA
Value
100
Unit
K/W
Electrical Characteristics
All parameters refer to GND, T amb = -40C to +105C, V S = 4.5 V to 5.5 V, f 0 = 868.3 MHz and f 0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C)
fRF = 868.3 MHz 6.77617 MHz Oscillator Parameter Test Conditions Symbol Min. Typ. Max. Min. fRF = 915 MHz 7.14063 MHz Oscillator Typ. Max. Min. Variable Oscillator Typ. Max. Unit
Basic Clock Cycle of the Digital Circuitry Basic clock cycle Extended basic clock cycle Polling Mode Sleep time (see Figure 11, Figure 20 and Figure 33) Start-up time (see Figure 11 and Figure 12) Time for bit check (see Figure 11) Sleep and XSleep are defined in the OPMODE register Sleep XSleep 1024 2.0662 1852 1059 1059 662 Sleep XSleep 1024 2.0662 1852 1059 1059 662 Sleep XSleep 1024 1.9607 1758 1049 1049 628 Sleep XSleep 1024 1.9607 1758 1049 1049 628 Sleep XSleep 1024 TClk Sleep XSleep 1024 TClk BR_Range0 BR_Range1 BR_Range2 BR_Range3 TClk 2.0662 16.53 8.26 4.13 2.07 2.0662 16.53 8.26 4.13 2.07 1.9607 15.69 7.84 3.92 1.96 1.9607 15.69 7.84 3.92 1.96 14/fXTO 8 TClk 4 TClk 2 TClk 1 TClk 14/fXTO 8 TClk 4 TClk 2 TClk 1 TClk s s s s s
TXClk
TSleep
ms
BR_Range0 BR_Range1 BR_Range2 BR_Range3 Average bit-check time while polling, no RF applied (see Figure 15 and Figure 16) BR_Range0 BR_Range1 BR_Range2 BR_Range3
TStartup
896.5 512.5 512.5 320.5 TClk
896.5 512.5 512.5 320.5 TClk
s s s s s
TBit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms
28
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Electrical Characteristics (Continued)
All parameters refer to GND, T amb = -40C to +105C, V S = 4.5 V to 5.5 V, f 0 = 868.3 MHz and f 0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C)
fRF = 868.3 MHz 6.77617 MHz Oscillator Parameter Time for bit check (see Figure 11) Test Conditions Bit-check time for a valid input signal fSig (see Figure 12) NBit-check = 0 NBit-check = 3 NBit-check = 6 NBit-check = 9 Symbol Min. Typ. Max. Min. fRF = 915 MHz 7.14063 MHz Oscillator Typ. Max. Min. Variable Oscillator Typ. Max. Unit
TBit-check 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig
1 TXClk 3/fSig 6/fSig 9/fSig
1 TClk 3.5/fSig 6.5/fSig 9.5/fSig
ms ms ms ms
Receiving Mode Intermediate frequency Baud-rate range BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 165.3 82.6 41.3 20.7 165.3 82.6 41.3 20.7 156.8 78.4 39.2 19.6 156.8 78.4 39.2 19.6 10 TXClk 10 TXClk 10 TXClk 10 TXClk 10 TXClk 10 TXClk 10 TXClk 10 TXClk s s s s fIF 1.0 1.8 3.2 5.6 0.95 1.8 3.2 5.6 10.0 1.054 1.89 3.38 5.9 1.00 1.89 3.38 5.9 10.5 fRF/915 BR_Range0 2 s/TClk BR_Range1 2 s/TClk BR_Range2 2 s/TClk BR_Range3 2 s/TClk MHz kBaud kBaud kBaud kBaud
BR_Range
Minimum time period between edges at Pin DATA (see Figure 18 and Figure 19) (With the exception of parameter TPulse) Maximum Low period at Pin DATA (see Figure 16) Delay to activate the start-up mode (see Figure 22) OFF command at Pin POLLING/_ON (see Figure 21) Delay to activate the sleep mode (see Figure 21) Pulse on Pin DATA at the end of a data stream (see Figure 30)
tDATA_min
BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3
tDATA_L_max
2149 1074 537 269
2149 1074 537 269
2139 1020 510 255
2139 1020 510 255
130 TXClk 130 TXClk 130 TXClk 130 TXClk
130 TXClk 130 TXClk 130 TXClk 130 TXClk
s s s s
Ton1
19.6
21.7
18.6
20.6
9.5 TClk
10.5 TClk
s
Ton2
16.5
15.6
8 TClk
s
Ton3
17.6
19.6
16.6
18.6
8.5 TClk
9.5 TClk
s
BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3
TPulse
16.5 8.3 4.1 2.1
16.5 8.3 4.1 2.1
15.69 7.84 3.92 1.96
15.69 7.84 3.92 1.96
8 TClk 4 TClk 2 TClk 1 TClk
8 TClk 4 TClk 2 TClk 1 TClk
s s s s
29
4561B-RKE-10/02
Electrical Characteristics (Continued)
All parameters refer to GND, T amb = -40C to +105C, V S = 4.5 V to 5.5 V, f 0 = 868.3 MHz and f 0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C)
fRF = 868.3 MHz 6.77617 MHz Oscillator Parameter Test Conditions Symbol Min. Typ. Max. Min. fRF = 915 MHz 7.14063 MHz Oscillator Typ. Max. Min. Variable Oscillator Typ. Max. Unit
Configuration of the Receiver (see Figure 17 and Figure 33) Frequency of the reset marker Programming start pulse Frequency is stable within 50 ms after POR BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR Programming delay period Synchronization pulse Delay until of the program window starts Programming window Time frame of a bit Programming pulse Equivalent acknowledge pulse: E_Ack Equivalent time window OFF-bit programming window t2 t3 fRM 118.2 118.2 124.5 124.5 1/ (4096 TClk) 1/ (4096 TClk) Hz
t1
3355 2273 1731 1461 16397 795 264
11637 11637 11637 11637
3184 2168 1643 1386 15560 754 251
11043 11043 11043 11043
1624 TClk 1100 TClk 838 TClk 707 TClk 7936 TClk
5632 TClk 5632 TClk 5632 TClk 5632 TClk
s s s s s s s
797 264
756 251
384.5 TClk 128 TClk
385.5 TClk 128 TClk
t4
131
131
125
125
63.5 TClk
63.5 TClk
s
t5 t6 t7
529 1058 132
529 1058 529
502 1004 125
502 1004 502
256 TClk 512 TClk 64 TClk
256 TClk 512 TClk 256 TClk
s s s
t8
264
264
251
251
128 TClk
128 TClk
s
t9
533
533
506
506
258 TClk
258 TClk
s
t10
929
929
881
881
449.5 TClk
449.5 TClk
s
Data Clock (see Figure 27 and Figure 28) Minimum delay time between edge at DATA and DATA_CLK Pulse width of negative pulse at Pin DATA_CLK BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 0 0 0 0 66.1 33.0 16.5 8.3 16.5 8.3 4.1 2.1 66.1 33.0 16.5 8.3 0 0 0 0 63 31 15.7 7.8 16.7 7.8 3.9 1.96 63 31 15.7 7.8 0 0 0 0 4 TXClk 4 TXClk 4 TXClk 4 TXClk 1 TXClk 1 TXClk 1 TXClk 1 TXClk 4 TXClk 4 TXClk 4 TXClk 4 TXClk s s s s s s s s
tDelay2
tP_DATA_CLK
30
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Electrical Characteristics (continued)
All parameters refer to GND, T amb = -40C to +105C, V S = 4.5 V to 5.5 V, f 0 = 868.3 MHz and f 0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C)
Parameters
Current consumption
Test Conditions
Sleep mode (XTO and polling logic active) IC active (start-up-, bit-check-, receiving mode) Pin DATA = H FSK ASK
Symbol
ISoff
Min.
Typ.
170
Max.
276
Unit
A
ISon
7.8 7.4 -16 -70 5 200 || 3.2 200 || 3.2 -25 20 30
9.9 9.6
mA mA dBm
LNA, Mixer, Polyphase Lowpass and IF Amplifier (Input Matched According to Figure 33 Referred to RFIN)
Third-order intercept point LO spurious emission System noise figure LNA_IN input impedance 1 dB compression point Image rejection Maximum input level Within the complete image band BER 10-3, FSK mode ASK mode T5760 T5761 fosc = 867.3 MHz at 10 MHz at fXTO XTO pulling, appropriate load capacitance must be connected to XTAL, crystal CM = 7 fF fXTAL = 6.77617 MHz (EU) fXTAL = 7.14063 MHz (US) Parameter of the supplied crystal Parameter of the supplied crystal and board parasitics ASK (level of carrier) BER 10-3, 100% Mod fin = 868.3 MHz/915 MHz VS = 5 V, Tamb = 25C fIF = 950 kHz/1 MHz BR_Range0 BR_Range1 BR_Range2 BR_Range3 Pin_max LNA/mixer/IF amplifier Required according to I-ETS 300220 With power matching |S11| < -10 dB at 868.3 MHz at 915 MHz IIP3 ISLORF NF ZiLNA_IN IP1db -57 dBm dB
W || pF W || pF
dBm dB -10 -10 dBm dBm MHz MHz dBC/Hz dBC
Local Oscillator
Operating frequency range VCO Phase noise local oscillator Spurious of the VCO XTO pulling fVCO fVCO L (fm) 866 900 -140 -55 871 929 -130 -45
fXTO RS C0
-30ppm
fXTAL
+30ppm
MHz
W
Series resonance resistor of the crystal Static capacitance at Pin XTAL to GND Input sensitivity ASK
120 6.5
pF
Analog Signal Processing (Input Matched According to Figure 33 Referred to RFIN)
PRef_ASK
-110 -108.5 -108 -106
-112 -110.5 -110 -108
-114 -112.5 -112 -110
dBm dBm dBm dBm
31
4561B-RKE-10/02
Electrical Characteristics (continued)
All parameters refer to GND, T amb = -40C to +105C, V S = 4.5 V to 5.5 V, f 0 = 868.3 MHz and f 0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C)
Parameters
Sensitivity variation ASK for the full operating range compared to Tamb = 25C, VS = 5 V Sensitivity variation ASK for full operating range including IF filter compared to Tamb = 25C, VS = 5 V
Test Conditions
fin = 868.3 MHz/915 MHz fIF = 950 kHz/1 MHz PASK = PRef_ASK + DPRef fin = 868.3 MHz/915 MHz fIF = 950 kHz/1 MHz fIF -210 kHz to +210 kHz fIF -270 kHz to +270 kHz PASK = PRef_ASK + DPRef BER 10-3 fin = 868.3 MHz/915 MHz VS = 5 V, Tamb = 25C fIF = 950 kHz/1 MHz BR_Range0 df = 16 kHz to 28 kHz df = 10 kHz to 100 kHz BR_Range1 df = 16 kHz to 28 kHz df = 10 kHz to 100 kHz BR_Range2 df = 18 kHz to 31 kHz df = 13 kHz to 100 kHz BR_Range3 df = 25 kHz to 44 kHz df = 20 kHz to 100 kHz
Symbol
DPRef
Min.
+2.5
Typ.
Max.
-1.0
Unit
dB
DPRef
+5.5 +7.5
-1.5 -1.5
dB dB
Input sensitivity FSK
PRef_FSK
-103 -101 -101 -99 -99.5 -97.5 -97.5 -95.5 +3
-106
-107.5 -107.5 -105.5 -105.5 -104
dBm dBm dBm dBm dBm dBm dBm dBm dB
PRef_FSK
-104
PRef_FSK
-102.5
PRef_FSK
-100.5
-102
Sensitivity variation FSK for the full operating range compared to
Tamb = 25C, VS = 5 V
Sensitivity variation FSK for the full operating range including IF filter compared to Tamb = 25C,
fin = 868.3 MHz/915 MHz fIF = 950 kHz/1 MHz PFSK = PRef_FSK + DPRef fin = 868.3 MHz/915 MHz fIF = 950 kHz/1 MHz fIF -150 kHz to +150 kHz fIF -200 kHz to +200 kHz fIF -260 kHz to +260 kHz PFSK = PRef_FSK + DPRef ASK mode FSK mode
DPRef
-1.5
VS = 5 V
DPRef
+6 +8 +11 10 2 60 0.11 0.16 39 22 12 8.2
-2 -2 -2 12 3
dB dB dB dB dB dB
S/N ratio to suppress inband noise signals. Noise signals may have any modulation scheme Dynamic range RSSI amplifier Lower cut-off frequency of the data filter Recommended CDEM for best performance
SNRASK SNRFSK DRRSSI
1 f cu_DF = ---------------------------------------------------------2 p 30 kW CDEM CDEM = 33 nF BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3
fcu_DF
0.20
kHz nF nF nF nF
CDEM
32
T5760/T5761
4561B-RKE-10/02
T5760/T5761
Electrical Characteristics (continued)
All parameters refer to GND, T amb = -40C to +105C, V S = 4.5 V to 5.5 V, f 0 = 868.3 MHz and f 0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C)
Parameters
Edge-to-edge time period of the input data signal for full sensitivity
Test Conditions
BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 RSense connected from Pin Sens to VS, input matched according to Figure 33, fIN = 868.3 MHz/915 MHz, VS = 5 V, Tamb = +25C RSense = 56 kW RSense = 100 kW
Symbol
Min.
270 156 89 50
Typ.
Max.
1000 560 320 180
Unit
ms ms ms ms
tee_sig
Upper cut-off frequency data filter
fu
2.8 4.8 8.0 15.0
3.4 6.0 10.0 19.0
4.0 7.2 12.0 23.0
kHz kHz kHz kHz dBm (peak level)
Reduced sensitivity
PRef_Red PRef_Red
DPRed
-63 -72 5 5
-68 -77 0 0
-73 -82 0 0
dBm dBm dB dB
Reduced sensitivity variation over full operating range Reduced sensitivity variation for different values of RSense
RSense = 56 kW RSense = 100 kW PRed = PRef_Red + DPRed Values relative to RSense = 56 kW RSense = 56 kW RSense = 68 kW RSense = 82 kW RSense = 100 kW RSense = 120 kW RSense = 150 kW PRed = PRef_Red + DPRed
DPRed
0 -3.5 -6.0 -9.0 -11.0 -13.5 1.95 2.8 3.75
dB dB dB dB dB dB V
Threshold voltage for reset
VThRESET
Digital Ports
Data output - Saturation voltage Low - max voltage at Pin DATA - quiescent current - short-circuit current - ambient temp. in case of permanent short-circuit Data input - Input voltage Low - Input voltage High DATA_CLK output - Saturation voltage Low - Saturation voltage High IC_ACTIVE output - Saturation voltage Low - Saturation voltage High Iol 12 mA Iol = 2 mA Voh = 20 V Vol = 0.8 V to 20 V Voh = 0 V to 20 V Vol Vol Voh Iqu Iol_lim tamb_sc 13 0.35 0.08 0.8 0.3 20 20 45 85 V V V A mA C
30
VIl Vich IDATA_CLK = 1mA IDATA_CLK = -1mA IIC_ACTIVE = 1 mA IIC_ACTIVE = -1 mA Vol Voh Vol Voh
0.35 VS 0.65VS 0.1 VS-0.15 V 0.1 VS-0.15 V
V V V V V V
0.4
VS-0.4 V
0.4
VS-0.4 V
33
4561B-RKE-10/02
Electrical Characteristics (continued)
All parameters refer to GND, T amb = -40C to +105C, V S = 4.5 V to 5.5 V, f 0 = 868.3 MHz and f 0 = 915 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25C)
Parameters
POLLING/_ON input - Low level input voltage - High level input voltage TEST 4 pin - High level input voltage TEST 1 pin - Low level input voltage
Test Conditions
Receiving mode Polling mode Test input must always be set to High Test input must always be set to Low
Symbol
VIl VIh VIh VIl
Min.
Typ.
Max.
0.2 VS
Unit
V V V
0.8VS 0.8VS 0.2 VS
V
Ordering Information
Extended Type Number
T5760-TGS T5760-TGQ T5761-TGS T5761-TGQ
Package
SO20 SO20 SO20 SO20
Remarks
Tube, for 868 MHz ISM band Taped and reeled, for 868 MHz ISM band Tube, for 915 MHz ISM band Taped and reeled, for 915 MHz ISM band
Package Information
Package SO20
Dimensions in mm
12.95 12.70 9.15 8.65 7.5 7.3
2.35 0.25 10.50 10.20 11
0.4 1.27 11.43 20
0.25 0.10
technical drawings according to DIN specifications
1
10
34
T5760/T5761
4561B-RKE-10/02
Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
Atmel (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
4561B-RKE-10/02 xM

▲Up To Search▲

Price & Availability of T5761

	To Download T5761 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .