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TRF6900
Evaluation Board
User's Guide
August 2000
Mixed-Signal RF Products
SWRU001
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Information About Cautions and Warnings
Preface
Read This First
About This Manual
This document is intended to introduce the TRF6900 evaluation module (EVM) and familiarize the reader with setting up and testing the TRF6900 EVM using the evaluation software in a typical laboratory environment.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 - Overview - Chapter 2 - Evaluation Board - Chapter 3 - Software User's Guide
Information About Cautions and Warnings
This user's guide may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you.
The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.
Read This First
iii
iv
Running Title--Attribute Reference
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 EVM Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-2 1-3
2
Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 Top Side Silkscreen and Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.1.2 Bottom Side Silkscreen and Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 EVM DC Voltage Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.4 Serial Interface and PC Port Pin Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.5 Standard PC Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.6 Jumper Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.6.1 Jumper Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.6.2 Jumper Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.7 Connectors and Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.7.1 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.7.2 Test Points (TP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.7.3 Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.7.4 LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Software User's Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Main Program Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.1 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.2 Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.3 Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.4 PLL and MM Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.5 LPT Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.6 Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.7 Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.8 Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.9 Changing Values on the Main Program Screen . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3 Chip Layout Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4 PLL/Modulation Options Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.5 Testing of Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.6 Testing of the Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.6.1 Test Equipment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3
Chapter Title--Attribute Reference
v
Running Title--Attribute Reference
3.6.2 3.6.3 3.6.4
Software Programming for Receiver Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Learning and Hold Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Measured Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Figures
1-1 2-1 2-2 2-3 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 TRF6900 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 TRF6900 EVM DC Voltage Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 TRF6900 EVM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 EVM Jumper Locations and Default Configuration of the EVM . . . . . . . . . . . . . . . . . . . . . 2-12 Main Program Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Chip Layout Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 PLL/Modulation Options Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Block Diagram for Testing of the TRF6900 EVM Transmitter Section . . . . . . . . . . . . . . . . . 3-9 Main Program Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Chip Layout Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Spectrum Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Input of Frequency Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Main Panel Display After Clock Offset Is Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 PLL/Modulation Options View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 PLL/Modulation Options Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 FSK Output From Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Block Diagram for Testing of the TRF6900 EVM Transmitter Section With an External Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 FSK Output From Transmitter With an External Modulation . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Test Setup for TRF6900 Receiver Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Main Program Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Chip Layout Screen for Receiver Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 Measured Data With -50 dBm Input Signal at AMP_OUT and RXDATA Test Points . . . 3-21 Measured Data With -90 dBm Input Signal at AMP_OUT and RXDATA Test Points . . . 3-21
vi
Chapter 1
Overview
This chapter gives an overview of the TRF6900 evaluation module (EVM).
Topic
1.1 1.2 1.3
Page
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 EVM Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1-1
Purpose
1.1 Purpose
The TRF6900 evaluation module (EVM) provides a platform for lab prototype evaluation of the Texas Instruments TRF6900.
1.2 EVM Setup
The 3.5-inch diskette supplied with the TRF6900 contains the software required to demonstrate the TRF6900. Complete the following steps to set up the TRF6900 for evaluation. Step 1: Place the 3.5-inch diskette into the floppy disk drive of the computer being used to evaluate the TRF6900. Step 2: Copy the TRF6900.exe file to the hard drive. Step 3: Connect a DB25 female to DB25 male cable between the TRF6900 evaluation board and the PC parallel port. The DB25 female end of the cable is connected to the TRF6900. The DB25 male end of the cable is connected to the desired LPT port of the PC. (LPT1 or LPT2). Step 4: Connect a dc power supply capable of 10 V 200 mA between the red power supply pin and ground on the TRF6900 evaluation board. Step 5: Verify that the power supply output is set to 8 V. Turn the power supply on. Step 6: If jumper at JP8 is installed, verify that LED3 (the red power on LED) is illuminated. Step 7: Run the TRF6900.exe file on the PC. Step 8: Press the Send Words Now (F12) button located on the program screen. Step 9: Verify that LED1 (the green lock detect LED) is illuminated. When the lock detect LED is illuminated, the PLL is locked on frequency. Note: The actual icons/windows on the computer screen may differ from those shown in the user's guide, due to software version upgrades. The schematics shown in this user's guide may not match the current revision due to PCB and component upgrades. Always check the TI website for the latest schematics and software.
1-2
Block Diagram
1.3 Block Diagram
Figure 1-1 shows the block diagram for the TRF6900.
Figure 1-1. TRF6900 Block Diagram
DEM_GND
38
LNA_OUT
LNA_VCC
MIX_GND
MIX_OUT
MIX_VCC
IF1_OUT
IF_GND
MIX_IN
IF1_IN
IF2_IN
48 1
47
46
45
44
43
42
41
40
39
37 36
VREF
LNA_GND LNA_IN LNA_GND PA_VCC PA_OUT PA_GND PLL_GND PD_SET PD_OUT2 PD_OUT1 LOCKDET PLL_VCC
2 LNA 3
RF Buffer Amplifier RF Mixer 1st IF Amplifier RSSI
2nd IF Amplifier/ Limiter
DEM_VCC DEM_TANK DEM_TANK RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CA DATA_OUT DATA CLOCK STROBE
35
FM/FSK Demodulator
34
4
LO Buffer Amplifier Data Switch
33
5 Power Amplifier 6 LPF Amplifier/ Post-Detection Amplifier
Buffer Amplifier 32
31
TRF6900
7
30
8
Data Slicer
29
9 PLL 10 Direct Digital Synthesizer and Power-Down Logic Serial Interface
28
27
11
26 25
12 VCO 13 14 15 16 17 18 19 20 21 22 23 24
VCO_TANK1
VCO_TANK2
DDS_GND
DDS_VCC
DIG_GND
STDBY
MODE
DIG_VCC
XOSC1
TX_DATA
XOSC2
GND
Overview
1-3
1-4
Chapter 2
Evaluation Board
This chapter describes the EVM and its operation.
Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7
Page
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 EVM Voltage Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Serial Interface and PC Port Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Standard PC Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Jumper Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Connectors and Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Evaluation Board
2-1
Schematics
VCC1
J4 C16 100pF R8 VCC1 C23
4
RX_IN C18 1000pF L7 4.7nH 10 R10 R11 6.2 k VCC1 10 C28 C29 4700pF 470pF 0.8V L8 C31 10nH TP1 R19 10 k R21 1 V2 2 SMV1247-079 R22 TBD R25 DNP R26 TBD TBD DNP DNP R24 J7 EX_VCO_INPUT EX_VCO_INPUT TBD DNP 10 k 1 V1 SMV1247-079 2 C33 3.3pF 120pF C34 3.3pF SELECT L8 FOR CENTER FREQUENCY. SELECT C33, C34 FOR TUNING RANGE. TYPICAL TUNING RANGE (Vcc=3.3V) Vt: 0.5 TO 3.0V f: 845-965MHz C30 1000pF C35 0.1 F R23 10 VCC1 R18 100 CQ1 25.6 MHz R20 1M C36 10pF C37 10pF R13 0 R12 100 k IC1 TRF6900 PG2.3 C19 0.1 F
RX_IN
C17 4.7pF
L6 10nH DNP C20 1000pF DNP 3.3pF 4 C24 3.3pF DNP
4
J5
TX_OUT
TX_OUT
C26 10pF DNP TRANSMISSION LINE LENGTH = 618 mils FR4, Er = 4.3 C27 13 14 15 16 17 18 19 20 21 22 23 24 0.1 F
4
1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 C25 0.1 - 10 F
VCC2
3
FUNDAMENTAL MODE INITIAL TOLERANCE +/- 7 PPM STAB OVER TEMP +/- 20 PPM TEMP RANGE -40 TO +85 DEG C
C38 1.5 - 10pF DNP SAT
ADJUST FOR OUTPUT FREQUENCY AT J5
0
0
2-2
C1
1
C2 J1 MIX_OUT/1IF_INPUT MIX_OUT/1IF_INPUT 120pF L1 2.2 H
DNP
2
DNP
3
1000pF
C3 0.1 F
5
R52 0 BPF1 SFECV10.7MJ-A-TC BW=150 kHz DNP 1 3 2 C7 C8 J3 IF_OUT/2IF_INPUT DNP
3 1 2
J2 C5
1
2.1 Schematics
LNA_OUT/MIX_IN 1000pF DNP R51 1.0pF DNP 1000pF R53 0 L4 18nH R4 2 FOR 110KHz: SFECV10.7MH-A-TC 10 C10 0.1 F 1.25V TYPICAL R5 10 C13 0.1 F R7 10k L5 2.2 H C14 100pF C15 DNP VCC1 BPF2 SFECV10.7MJ-A-TC BW=150 kHz 1 3 VCC1 L3 120pF 2.2 H C9 10pF
3 2
LNA_OUT/MIX_IN DNP C6
C4 L2 8.2nH 0.1 F
IF_OUT/2IF_INPUT
R6 VCC1 10 48 47 46 45 44 43 42 41 40 39 38 37 TYPICAL C12 0.1 F
C11 0.1 F
RSSI_OUT R9, C21, C22 SET FOR BANDWIDTH. AS SHOWN, 1dB BW = 20KHz
1 2
C21 R9 C22 39 k 330pF 100pF
RSSI/RXDATA_OUT R54
J6 RSSI/RXDATA_OUT
R1 510
AMP_OUT RXDATA DATA CLOCK STROBE MODE STDBY TXDATA LOCKDET
LDET R15 5.6k
LED1 LDET LN1371SG-(TR) Q1 FMMT2222ATA
AMP_OUT VCC2 AMP_OUT CLOCK R27 100 R28 DATA STROBE R29 IC2 RXDATA R30 10 k R31 10 k R32 10 k 20 100 STROBE VCC2 R2 510 R33 TXDATA LL4148 CR2 LL4148 0 STDBY R36 5.6 k RSSI_O CR3 MODE LL4148 MODE R37 100 STDBY VCC2 VCC2 JP6 3 3 2 1 2 JP7 1 R38 100 TXDATA CR4 LL4148 R39 10 k R40 10 k R41 10 k C40 1000pF DNP RXD Q2 FMMT2222ATA LED2 ENABLE LN1471SY-(TR) 100 CLOCK
C39 0.1 F
DATA
P1
RXDATA RSSI 11 13 15 17 R35 10 k CR1 TXDATA1 TX DATA FILTER
1 1OE 2 1A1 1Y1 18 4 1A2 1Y2 16 6 1A3 1Y3 14 8 1A4 1Y4 12 19 2OE
RSSI_OUT R50 10 k R49 10 k R46 10 k R17 10 k R14 10 k R3 10 k
1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
9 2A1 2Y1 7 2A2 2Y2 5 2A3 2Y3 2A4 2Y4 3 10 SN74LVT244BDW
DB25M
POWER 8.0V RED CR5 3 VIN VOUT ADJ 1 R43 360 C43 1 F C45 0.01 F C44 0.1 F JP8 0 S1JB ZR1 SMBJ8.5CA 1 2 R44 500 3 C41 10 F C42 0.1 F 2 VR1 LM317MDT 2.2 - 3.6V (3.0V TYP)
VCC1
LED3 VCC LN1271R-(TR) R45 220
R34 220
VR2 3.3V VCC2 R47 220 1 2 3 4 VI VO VO ADJ LM317LBD NC VO VO NC 8 7 6 5
Evaluation Board
R48 360
C46 1 F
C47 0.1 F
C48 0.01 F
GROUND CLIPS
Schematics
GND1 GND2 GND3 GND4 GND5
2-3
Top Side Silkscreen and Drawing
2.1.1
Top Side Silkscreen and Drawing
2-4
Top Side Silkscreen and Drawing
2.1.2
Bottom Side Silkscreen and Drawing
Evaluation Board
2-5
2-6
Parts List
2.2 Parts List
Count 2 2 1 1 13 RefDes BPF1, BPF2 C45, C48 C28 C25 C3, C4, C10-C13, C19, C27, C35, C39, C42, C44, C47 C32 C5, C20 C29 C1, C7, C18, C30 C6 C43, C46 C38 C9, C26 C41 C24 C36, C37 C33, C34 C17, C23 C14, C18, C22 C2, C8, C31 C21 C40 C15 CQ1 CQ1_A Value BW = 150 kHz 0.01 F 0.022 F 0.1 F - 10 F 0.1 F Pattern Name SFECV10.7 0603 0603 1206 0603 0603 Description Band pass filter MFG. Murata Part No. SFECV10.7MJ-A-TC Distributor/Part No.
Evaluation Board
1 2 1 4 1 2 1 2 1 1 2 2 2 3 3 1 1 1 1 1
0.5 pF 1 nF 1.0 nF 1 nF 1.0 pF 1 F 1.5 pF - 10 pF 10 pF 10 F 12 pF 47 pF 3.3 pF 4.7 pF 100 pF 120 pF 330 pF 1000 pF DNP 25.6 MHz
0603 0603 0603 0603 0603 1208 tantalum 9341 Series 0603 1206 tantalum 0603 0603 0603 0603 0603 0603 0603 0603 AT0300 0603 HC45/U gull wing CX-1-SM Surface-mount ceramic trimmer capacitor Resistance weld miniature crystal Surface-mount quartz crystal Temex Internation Crystal Mfg. CFP (CMAC Frequency Products) AT0300 88542 18 MHZ CX-1 SMI Tantalum capacitor Tantalum capacitor Trimmer Capacitor Johnson 9341-3Sl Newark - 95F9901
Count 1 4 1 1 1 7 5 2 1 3 2 2 1 1 1 1
RefDes CQ1_B CR1, CR2, CR3, CR4 CR5 IC1 IC2 J1, J2, J3, J4, J5, J6, J7 JP1, JP2, JP3, JP4, JP5 JP6, JP7, JP8 L1, L3, L5 L2, L8 L6, L7 L4 LED1 LED2 LED3 P1 Q1, Q2
Value
Pattern Name ATS-SM series MELF3 (MINIMELF) SMB TQFP48 SO20WB SMA_H
Description Crystal Fast switching diode Rectifier Single chip transceiver Octal Buffers and line drivers with 3-state outputs SMA brass connector - horizontal/PC mount 0603 SMD resistor Breakaway headers Breakaway headers Surface-mount inductor Surface-mount inductor Surface-mount inductor Surface-mount inductor Surface-mount LED-gull wing-S type - green Surface-mount LED-gull wing-S type - amber Surface-mount LED-gull wing-S type - red Subminiature D connector NPN silicon planar switching transistor - 330 mW
MFG. CTS Reeves Diode Inc Diode Inc Texas Instruments Texas Instruments Johnson Components
Part No. ATS256SM-T LL4148 S1JBT TRF6900 SN74LVT244BDW 142-0701-801
Distributor/Part No. Digi-Key - CTX51?TR-ND Digi-Key - LL4148BCT-ND Digi-Key - S1HBDUCT-ND
Digi-Key - 296-1707-5-ND Newark - 90F2624
0
0603 Jumper-3 pin Jumper-2 pin
AMP AMP Murata Murata Murata Murata Panasonic Panasonic Panasonic AMP Zetex
4-103239-0 4-103239-0 LQS33N2R2G04M00 LQW1608 LQW1608 LQW1608 LN1371SG-(TR) LN1471SY-(TR) LN1271SR-(TR) 745783-4 FMMT2222A
Newark - 90F7725 Newark - 90F7725
2.2 H 8.2 nH 10 nH 18 nH LDET ENABLE VCC
1214 0603 0603 0603 LED, S type LED, S type LED, S type DB25M SOT23
Digi-Key - P516CT-ND Digi-Key - P517CT-ND Digi-Key - P490CT-ND Newark - 90F5485
Evaluation Board
2-7
1 2
7 1 1 1
R1, R2, R3, R12, R33, R42, R46 R20 R16 R11
0 1M 2M 3.9K
0603
Parts List
0603 0603 0603
2-8
Parts List
Count 6 13
RefDes R4-R6, R8, R13, R23 R7, R15, R17, R19, R21, R30-R32, R35, R36, R39-R41 R9 R18, R27, R28, R29, R37, R38 R10 R45, R47 R14, R34, R43 R48 R44 R22, R24-R26
Value 10 10K
Pattern Name 0603 0603
Description
MFG.
Part No.
Distributor/Part No.
Evaluation Board
1 6 1 2 3 1 1 4
39K 100 100K 220 270 360 500 TBD
0603 0603 0603 0603 0603 0603 P1S Panasonic 0603 0603 0603 0603 Surface mount trimmer potentiometer Panasonic EVM-1SSX50BXX
2 1
V1, V2 VR1
SOD323
Hyperabrupt tuning varactor DPAK CADE369A-13
Alpha Industries, Inc. Three-terminal adjustable output positive voltage regulator Three-terminal adjustable output positive voltage regulator Transient voltage suppressor Color coded PC test point (any color)
SMV1129-011 ON Semiconductor LM317MDT Newark - 06F9320
1
VR2
SO6NB
ON Semiconductor
LM317LBD
Newark - 06F9304
1 11
ZR1 AMP_OUT, CLOCK, DATA, F_TXDATA, LDET, MODE, RSSI, RXDATA, STDY, STROBE, TXDATA GND 8.0 V TP2-TP6 BLK RED
SMBK-BI PC test point
Vishay/Liteon Components Corp.
SMBJ8.5CA TP-105-01-??
Digi-Key - SMBJ8.5AGICT-ND Newark - 98B32??
1 1 5
PC test point PC test point SMD test point
Color coded PC test point (black) Color coded PC test point (red) Surface mlunt test point
Components Corp. Components Corp. Components Corp.
TP-105-01-00 TP-105-01-02 TP-107-01
Newark - 97B3259 Newark - 97B3257 Newark - 97B2647
EVM DC Voltage Setup
2.3 EVM DC Voltage Setup
The evaluation board should be used with a dc power supply voltage of 8 V nominal. Figure 2-1 details the dc voltage supply setup for the TRF6900 EVM.
Figure 2-1. TRF6900 EVM DC Voltage Setup
V out for LM317 voltage regulator is equal to: V out= 1.25(1+(R44/R43)) V at terminal 3 of LM317 should be 2 to 3 volts higher than Vout With V inequal to 8 volts , V= 7.2 volts
POWER 8.0V RED
Connect JP8 For Power ON LED
VR1 LM317MDT 3 VIN VOUT ADJ 1 2 JP8 0 2.2 - 3.6V (3.0V TYP) VCC1
CR5 S1JB ZR1 SMBJ8.5CA
C41 10 F
C42 0.1 F
R43 360
C43 1 F
C44 0.1 F
C45 0.01 F
1 2 R44 500 3
LED3 VCC LN1271R-(TR) R45 220
V in is equal to 8.0 volts min. to 10 volts max.
R34 220
Vadj Used to Change Vout From 2.2 V to 3.6 V
3.3V VCC2 R47 220 C46 1 F C47 0.1 F C48 0.01 F
VR2 1 2 3 4 VI VO VO ADJ NC VO VO NC 8 7 6 5
LM317LBD GROUND CLIPS GND1 GND2 GND3 GND4 GND5 R48 360
Evaluation Board
2-9
VCC2
P1-5 TX_Data from PC P1-6 Enable from PC P1-7, Mode from PC P1-11 RSSI_Out to PC P1-12 RX_Data to PC
DB25M
RXDATA RSSI
2 4 6 8 19
1A1 1A2 1A3 1A4 2OE
18 1Y1 16 1Y2 14 1Y3 12 1Y4 CR1 LL4148 CR2 LL4148 TXDATA1
TX DATA FILTER R33 TXDATA 0 STDBY R36 5.6 k
VCC2
VCC2
JP6 3 2 1
JP7 3 2 1
VCC2
2-10
Serial Interface and PC Port Pin Out
2.4 Serial Interface and PC Port Pin Out
Figure 2-2 details the serial interface portion of the TRF6900 EVM.
Evaluation Board
Figure 2-2. TRF6900 EVM Serial Interface
AMP_OUT AMP_OUT CLOCK R27 CLOCK C39 0.1 F DATA 100 R28 DATA STROBE 100 R29 P1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 RXDATA 1 IC2 1OE STROBE 20 100 R30 10 k R31 10 k R32 10 k
P1-2: Clock Input from PC P1-3: Data Input from PC P1-4 Strobe Input from PC
R2 510
RSSI_OUT R35 10 k
9 11 2A1 2Y1 13 7 2A2 2Y2 5 15 2A3 2Y3 17 3 2A4 2Y4 10 SN74LVT244BDW
LED2 ENABLE LN1471SY-(TR)
Q2 FMMT2222ATA
RSSI_O RXD
CR3 MODE LL4148 MODE R37 100 STDBY R38 100 TXDATA CR4 LL4148 R39 10 k R40 10 k R41 10 k C40 1000pF DNP
Standard PC Parallel Port
2.5 Standard PC Parallel Port
A standard PC parallel port is configured as follows:
1 14 13 25
View Is Looking at Connector Side of DB-25 Male Connector
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Description Strobe Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 ACK Busy Paper Empty Select Auto Feed Error Initialize Printer Select Input PC Output PC Output PC Output PC Output PC Output PC Output PC Output PC Output PC Output PC Input PC Input PC Input PC Input PC Output PC Input PC Output PC Output
Pin Assignments Note: 8 Data Outputs 4 Misc Other Outputs 5 Data Inputs Note: Pins 18 - 25 are Ground
Note:
The TRF6900 EVM uses pins 2 - 7 for signals from the PC to the EVM. Pins 11 and 12 are used for signals from the EVM to the PC.
Evaluation Board
2-11
Jumper Connections
2.6 Jumper Connections
Figure 2-3 shows the default position of the jumpers on the TRF6900 EVM.
Figure 2-3. EVM Jumper Locations and Default Configuration of the EVM
J1 MIX_OUT 1 JP1 2 3 MIX_OUT BPF1 Input 1 BPF1 BPF1 Output 2 IF2_IN DEM_GND 1 IF1_OUT 2 3 BPF2 Input BPF2 3 JP2 J2 LNA_OUT/MIX_OUT 2 1 MIX_IN LNA_OUT LNA_VCC LNA_OUT MIX_GND MIX_VCC MIX_OUT IF1_OUT MIX_IN IF1_IN IF_GND IF2_IN VREF BPF2 Output J3 IF Out
JP3
JP1 default is NO Connection
48
47
46
45
44
43
42
41
40
39
38
37
J4 RX_IN LNA_GND LNA_IN LNA_GND PA_VCC PA_OUT PA_GND PLL_GND
1
RF Buffer Amplifier
2
2nd IF Amplifier/ Limiter 1st IF Amplifier RSSI FM/FSK Demodulator
36
DEM_VCC DEM_TANK
LNA
35
RF Mixer
3
34
DEM_TANK RSSI_OUT
4
J5 TX_Out
LO Buffer Amplifier Data Switch Buffer Amplifier
33
5
32
AMP_IN 1 AMP_CAP AMP_OUT S&H_CA DATA_OUT JP4 2 3 RSSI/RXDATA_Out J6
Power Amplifier
6
LPF Amplifier/ Post-Detection Amplifier
31
7
TRF6900 (Top View)
Data Slicer
30
PD_SET PD_OUT2
8
29
9
28
PLL PD_OUT1 LOCKDET PLL_VCC
10
11
Direct Digital Synthesizer and Power-Down Logic
27
Serial Interface
26
DATA CLOCK STROBE Default connection
12
VCO
13 14 15 16 17 18 19 20 21 22 23 24
25
VCO_TANK2
DDS_GND
DIG_VCC
DIG_GND
VCO_Tank1
DDS_VCC
2-12
TX_DATA
STDBY
XOSC1
XOSC2
MODE
GND
Jumper Connections
2.6.1
Jumper Connections
JP1 1 2 3 To J1 MIX_OUT To IC1-44 MIX_OUT, JP9-1 To BPF1 Input JP2 1 2 3 To J2 LNA_OUT/MIX_IN To IC1-47 LNA_OUT To IC1-46 MIX_IN
JP1 Default is no connection JP3 1 2 3 JP4 To J3 IF_OUT (IF Out 1) To IC1-41 IF1_OUT To BPF2 Input 1 2 3 To IC1-33 RSSI_OUT To J6 RSSI/RXDATA_OUT To IC1-28 RXDATA
JP5 1 2
JP6 To R11 and C29 (Loop Filter) To R19 and R21 (VCO Tank) 1 2 3 To VCC2 To Mode Test Point To Ground
JP6 Default is no connection JP7 1 2 3 To VCC2 To STDBY Test Point To Ground JP8 1 2 VR1 output (VCC1) To LED3 anode (Power on LED)
JP7 Default is no connection BPF1 Bypass Capacitor 1 2 To IC1-44 MIX_OUT To IC1- 42 IF1_IN Denotes Default Connection
Default is a 0.1 F-Capacitor (C3)
2.6.2
Jumper Description
The jumpers on the TRF6900 EVM, as shown in Figure 2-3, are used for the following purposes:
- JP1
Jumper JP1 is used for testing of the mixer circuit of the TRF6900. Testing of the mixer stage by itself is accomplished by connecting JP1-1 to JP1-2, JP2-1 to JP2-3, and removing the 0.1-F capacitor (C3) connecting terminal 44 (MIX_OUT) and terminal 42 (IF1_IN). Jumpers JP1-2 and JP1-3 would be connected if the BPF1 filter were installed. The default state for jumper JP1 is no connection.
Evaluation Board
2-13
Jumper Connections
- JP2
Jumper JP2 is used for testing of the mixer circuit of the TRF6900. Testing of the mixer stage by itself is accomplished by connecting JP1-1 to JP1-2, JP2-1 to JP2-3, and removing the 0.1-F capacitor connecting terminal 44 (MIX_OUT) and terminal 42 (IF1_IN). The IF mixer and LNA stages may be tested together by connecting JP1-1 to JP1-2, JP2-2 to JP2-3 (default) and removing the 0.1-F capacitor (C3) connecting terminal 44 (MIX_OUT) and terminal 42 (IF1_IN). The LNA stage is tested by itself by connecting JP2-1 to JP2-2. The default state for jumper JP2 is JP2-2 to JP2-3.
- JP3
Jumper JP3 is used to observe the output of IF1, the first IF amplifier, by connecting JP3-1 to JP3-2. The default configuration of JP3-2 to JP3-3 connects the output of the first IF amplifier to the input of the second IF amplifier.
- JP4
Jumper JP4 is used to monitor RXDATA_OUT when connected as JP4-2 to JP4-3. Jumper JP4 is used to monitor RSSI_OUT when connected as JP4-1 to JP4-2. The default state for jumper JP4 is JP4-2 to JP4-3.
- JP5
Jumper JP5 is used to connect the VCO tank circuit to the loop filter of the PLL circuit. The only reason to remove jumper JP5 is to test the tuning range of the VCO tank circuit with an external power supply. The default state for jumper JP5 is JP5-1 to JP5-2.
- JP6
Jumper JP6 can be used to pull the MODE line up to VCC (JP6-1 to JP6-2) or pull down to ground (JP6-2 to JP6-3), if a computer connection is not installed. The primary purpose for JP6 is as a test point to monitor the state of the MODE line. The default state for jumper JP6 is not connected.
- JP7
Jumper JP7 can be used to pull the STDBY line up to VCC (JP7-1 to JP7-2) or pull down to ground (JP7-2 to JP7-3), if a computer connection is not installed. The primary purpose for JP7 is as a test point to monitor the state of the STDBY line. The default state for jumper JP7 is not connected.
- JP8
Jumper JP8 is used to connect the Power On LED to the output of the IC1 voltage regulator. The default state for jumper JP8 is JP8-1 to JP8-2.
- BPF1 Bypass Capacitor
A 0.1-F capacitor (C3) is used to bypass BPF1 and connect the mixer output directly to the first IF amplifier. BPF1 is not installed on the TRF6900 evaluation board. If the user requires BPF1 to be installed, then remove the capacitor (C3) connecting terminal 44 (MIX_OUT) and terminal 42 (IF1_IN) and connect JP1-2 to JP1-3.
2-14
Connectors and Test Points
2.7 Connectors and Test Points
The following are descriptions of the TRF6900 EVM connectors and test points.
2.7.1
Connectors
- P1
P1 is the PC parallel port interface and is a male DB25 connector. P1 is connected to the LPT1 or LPT2 port of the computer on which the TRF6900 software is running.
- J1 MIX_OUT
MIX_OUT is an SMA female connector used with jumpers JP1 and JP2 to test the mixer circuit of the TRF6900.
- J2 LNA_OUT/MIX IN
LNA_OUT/MIX_IN is an SMA female connector used with jumpers JP1 and JP2 to test the mixer and LNA circuits of the TRF6900.
- J3 IF_OUT
IF_OUT is an SMA female connector used with jumper JP3 to monitor the IF output circuit of the TRF6900.
- J4 RX_IN
RX_IN is an SMA female connector which is connected to the input of the LNA. The LNA is the input to the receiver section of the TRF6900.
- J5 TX_OUT
TX_OUT is an SMA female connector which is connected to the transmitter output of the TRF6900.
- J6 RSSI/RXDATA_OUT
This is a SMA female connector used with jumper JP4 to monitor the RXDATA output or RSSI output of the TRF6900.
- J7 VCO_TANK
VCO_TANK is an SMA female connector used with resistors R22, R24, R25, R26, and capacitor C31 to directly feed in an external VCO signal. Resistors R22, R24, R25, and R26 are used to form a T attenuator. The components for this option are not installed on the EVM.
2.7.2
Test Points (TP)
- TP1
Test point TP1 is used to monitor the tuning voltage applied to the VCO circuit by the PLL circuit.
- AMP_OUT TP
The AMP_OUT test point is used to monitor the output of the LPF amplifier/post-detection amplifier.
- LDET TP
The LDET test point is used to monitor the lock detect line of the TRF6900.
Evaluation Board
2-15
Connectors and Test Points
- RSSI TP
The RSSI test point is used to monitor the RSSI level from IC1-33 RSSI_OUT.
- RXDATA TP
The RXDATA test point is used to monitor the RXDATA from IC1-28 DATA_OUT. This is the demodulated signal.
- MODE TP
The MODE test point is used to monitor the MODE line.
- STDBY TP
The STDBY test point is used to monitor the STDBY line.
- CLOCK TP
The CLOCK test point is used to monitor the CLOCK signal from the PC.
- DATA TP
The DATA test point is used to monitor the DATA signal from the PC.
- STROBE TP
The STROBE test point is used to monitor the STROBE signal from the PC.
- TXDATA TP
The TXDATA test point is used to monitor the transmitted data. Transmit data from an external source can also be applied at this point.
2.7.3
Adjustments
Resistor R44 is varied to adjust the VCC1 voltage applied to IC1 (TRF6900).
2.7.4
LED Indicators
- VCC LED
If JP8 is installed, the VCC LED is illuminated when voltage is applied to IC1.
- LDET LED
The LDET LED is illuminated when the lock detect line IC1-11 (TRF6900) is high, indicating that the PLL circuit is locked.
- ENABLE LED
The ENABLE LED is illuminated when the STDBY line from computer is in the high state.
2-16
Chapter 3
Software User's Guide
This chapter describes the Windows-based software application that accompanies the EVM.
Topic
3.1 3.2 3.3 3.4 3.5 3.6
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Main Program Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Chip Layout Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 PLL/Modulation Options Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Testing of Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Testing of Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Software User's Guide
3-1
Introduction
3.1 Introduction
A Windows-based software application accompanies the evaluation board. The software is intended for use in either a Windows 95/98 or Windows NT environment. If the Windows NT environment is used, the Windows NT driver software must accompany the software. However, if the operating system is Windows 95/98, the software application can run on its own. Both the Windows NT Driver and the TRF6900 software are provided on diskette. Your system administrator must install the Windows NT Driver if you do not have administrative privileges on your computer. The TRF6900 software can run from the floppy disk by following these steps: 1) Click on the Start button on the desktop 2) Click on the Run button 3) Type - A:\ TRF6900.exe and press OK
3-2
Main Program Screen
3.2 Main Program Screen
The screen shown in Figure 3-1 will appear on your monitor.
Figure 3-1. Main Program Screen
Transmit Frequency for Transmit Mode or LO Frequency for Receive Mode Crystal or Clock Frequency Double Click Here With the Left Mouse Button to Obtain Chip Layout View
Computer Printer Port LPT1 or LPT2
Press to Program the TRF6900
NOTE: When word bits are displayed in RED, the Send Words Now (F12) button on the main program screen, must be pressed for changes to be updated.
The main program screen is divided into eight main sections as follows:
3.2.1
Synthesizer
This section is used to set the crystal/clock (CLK) frequency, the Desired Freq., and the PreScaler value of the divided-by-N of the PLL. From these inputs, the actual frequency and bit values of Words A and B are calculated.
Software User's Guide
3-3
Main Program Screen
3.2.2
Mode Options
This section allows the user to control various features of the TRF6900. The following is a brief summary of the 12 controls. 1) PLL: 2) VCO: 3) Pwr Amp: 4) Slicer: 5) SLCTL: 6) LPF: 7) DSW: 8) RSSI: 9) LIM: 10) IF: 11) MIX: 12) LNA: Turns the phase-locked loop on or off. Turns the voltage controlled oscillator on or off. Allows the power amp to be set to off, 20-dB attenuation, 10-dB attenuation, or 0-dB attenuation states. Turns the data slicer on or off. If the data slicer is on, this selects either the Learn or Hold mode for the data slicer. Turns the low pass filter (LPF) on or off. Data switch. Selecting LIM sets LPF input to the demodulator. Selecting RSSI sets the LPF input to the RSSI. Turns the radio strength signal indicator (RSSI) on or off. Turns the limiter (LIM) on or off. Turns the intermediate frequency (IF) amplifier on or off. Turns the mixer on or off. Allows the low-noise amplifier (LNA) to be set to off, low gain, or high gain modes.
3.2.3
Output Parameters
This section allows the user to turn the TRF6900 Enable, TXData, and Mode control lines on and off. When the mode control line is off, Mode 0 is defaulted. When the mode control line is on, Mode 1 is defaulted. Mode 0 initializes using Words A and D, Mode 1 initializes using Words B and C. Clock Width and Strobe Width allow the clock and strobe pulse widths to be increased or decreased.
3.2.4
PLL and MM Options
Allows the change of the APLL value (0, 20, 40...140), the NPLL value (256, 512), and the modulation mode (FSK).
3.2.5
LPT Port
Allows the user to change between the LPT1 and LPT2 ports of the controlling computer.
3-4
Main Program Screen
3.2.6
Help
Gives a brief description of each control box. For example, clicking on the PLL box in the Mode Options section on the main program screen, the Help box will read: Phase-Lock Loop 0: Off 1: On Valid in Mode 0 or 1. Most of the other control boxes follow this format. The first line indicates what portion of the TRF6900 is being controlled. The next two lines indicate the bit value. If the PLL is off, bit 12 of Words C and D are equal to 0. If it is on, bit 12 is equal to 1. The last line indicates this control works in both Mode 0 and Mode 1. Double clicking in the Help box on the main program screen, activates the chip layout screen.
3.2.7
Words
This section updates the binary words after changes are made to the control options. Clicking on the box next to the word can individually send each word. Clicking on the Send Words Now (F12) button on the main program screen or by pressing F12 on the keyboard, sends all the words to the TRF6900.
3.2.8
Operation Mode
Operation Mode shows if the TRF6900 is enabled, which mode (0 or 1) is selected, and if the transmit (TX) data line is on or off.
3.2.9
Changing Values on the Main Program Screen
- Synthesizer Section
CLK:
Type the desired clock frequency inside the box or use the arrows located at the right side of the box.
Desired Freq.: Type the desired transmit or LO receive frequency inside the box or use the arrows located at the right side of the box. PreScaler: Click inside the box to change divide-by-N value between 256 and 512. The value of NPLL under PLL and MM Options changes when the PreScaler value changes.
- Mode Options
PLL: VCO: Pwr Amp:
Click inside the box to turn the PLL on or off. (Turn on for transmit or receive.) The VCO is always on. Clicking has no effect. Use the arrow at the side of the box to select the desired power amplifier attenuation.
Software User's Guide
3-5
Main Program Screen
Slicer: SLCTL: LPF: DSW:
Click inside the box to turn the data slicer on or off. Click inside the box to select between Learn and Hold modes. This will only work when the data slicer is on. Click inside the box to turn LPF on or off. Click inside the box to select between LIM and RSSI. This changes the position of the data switch inside the TRF6900. The data switch selects between the output of RSSI and FM/FSK demodulator (LIM) as the input to the LPF amplifier. (See block diagram in Figure 1-1) Click inside the box to turn RSSI on or off. Click inside the box to turn LIM (second IF amp/limiter) on or off. Click inside the box to turn the first IF amplifier on or off. Click inside the box to turn the RF mixer on or off. Click the arrow beside the box to turn LNA off, set to High Gain mode, or set to Low Gain mode.
RSSI: LIM: IF: MIX: LNA:
- Output Parameters
Enable: TXData: Mode: Clock Width:
Click inside the box to turn the TRF6900 on or off. Click inside the box to switch the TXData line between high or low. Click inside the box to switch the mode line between 0 and 1. Type inside the box to increase or decrease the clock pulse width. (This should not be changed during normal use) Type inside the box to increase or decrease the strobe pulse width. (This should not be changed during normal use)
Strobe Width:
- PLL and MM Options
APLL: NPLL:
Use arrows on side of box to select between values of 0, 20, 40, 60, 80, 100, 120, and 140. Click inside of the box to change the divide-by-N value between 256 and 512. The value of PreScaler under Synthesizer changes when the NPLL value changes. Modulation mode is fixed to FSK modulation mode.
MM:
- LPT Port
LPT_x:
Click inside the box to chose between PC parallel ports LPT 1 or LPT 2.
3-6
Chip Layout Screen
- Help
Help:
When any box on the main program screen is selected, (clicked inside of box with mouse) the Help screen displays the valid selections for that box. Double clicking inside the Help box will cause the chip layout screen to be displayed as shown if Figure 3-2.
3.3 Chip Layout Screen
The chip layout screen can be accessed by double clicking on the left mouse button in the Help section of the main program screen. The chip layout screen appears as a simplified internal schematic of the TRF6900 as shown in Figure 3-2:
Figure 3-2. Chip Layout Screen
Clicking Here Will Turn LNA On or Off or Select High Gain or Low Gain Mode
Selecting Icon Will Turn Function On or Off
Enable or Standby. IC is Disabled in Standby Mode. Clicking Here Will Set Power Amp Attenuation (0 dB, 10 dB, 20 dB) or Turn the Power Amp Off
Select Icon to Change Position of Data Switch Between RSSI and FSK DEMOD Selecting Icon Will Turn LPF (Video Amp) On or Off Selecting Icon Will Turn Data Slicer On or Off. Data Slicer Must be On to Select Between Learning and Hold Modes Press to Select Learning or Hold Mode Press to Select PLL/Modulation Options Screen Note: PLL Must be On
VCO On or Off
Mode Select 0 or 1 Turn TX Data On or Off Press to Program the TRF6900 Press to Start FSK Test
- The 12 Mode Options (e.g., the PLL, VCO, LNA, etc.) are controlled from
the chip layout screen, as well as the main program screen. Changes made in either the main program screen or the chip layout screen simultaneously update both screens. The user can also control the chip enable, TXData, and mode control lines from the chip layout screen.
Software User's Guide
3-7
PLL/Modulation Options Screen
- The user can select FSK Modulation. The FSK Test button, located on the
chip layout screen, will allow the user to transmit data using the TRF6900. Options for use with the FSK Test button are the pulse repetition frequency (PRF), which is defaulted to 100 Hz, and the Run Time (Min), which can be set in minutes. For example, if you want the test to run for five minutes, set Run Time (Min) to 5.
- The PLL/Modulation Options button brings up the PLL/Modulation Op-
tions screen as shown in Figure 3-3. This button is activated only when the PLL is on.
3.4 PLL/Modulation Options Screen
The PLL/Modulation Options screen is accessed by pressing the PLL/Modulation Option button, located on the chip layout screen, and is displayed as shown in Figure 3-3:
Figure 3-3. PLL/Modulation Options Screen
DV6 Display Set to 1 by Double Clicking
f1 Frequency 915 MHz f2 Frequency 915.10 MHz FSK Deviation of 100 kHz
Send Bits Button
The PLL/Modulations Options screen is divided into four sections:
- APLL
Controls the acceleration factor for the PLL. The values are 0, 20, 40, 60, 80, 100, 120, and 140. Any changes are automatically updated in the PLL and MM Options section of the main program screen, after pressing the Send Bits button located on the PLL screen.
- NPLL
Controls the N-Divider of the PLL. The NPLL can be set to either 256 or 512. Any changes are automatically updated in the NPLL box on the main program screen, after pressing the Send Bits button located on the PLL screen.
3-8
Testing of Transmitter
- Modulation Mode
Allows the user to select FSK modulation. Any changes are automatically updated in the MM box on the main program screen, after pressing the Send Bits button located on the PLL screen.
- FSK Frequency Register
This section acts as a calculator, and sets bits 20-13 of Word D to the user defined bits. The bits of the FSK deviation register (DV7-DV0) can be set individually by double clicking inside each DVx box. After setting all bits, press the Send Bits button located on the PLL screen. The bits of the frequency register will be mapped to Word D on the main program screen, and highlighted in green. Furthermore, Fout: TX_Data High (MHz), Fout: TX_Data Low (MHz) frequencies, and their difference (Delta Fout kHz), are calculated and displayed. Press the Send Bits button located on the PLL/Modulation Options screen to program the TRF6900. Press the Close button to return to the chip layout screen.
3.5 Testing of Transmitter
To perform tests of the transmitter section of the TRF6900, perform the following steps: Step 1: Test Setup: Set up the test bench as shown in Figure 3-4:
Figure 3-4. Block Diagram for Testing of the TRF6900 EVM Transmitter Section
PC with TRF6900 software installed PC Printer port (LPT1 or LPT2)
Frequency Counter
Spectrum Analyzer
Cable DB25M to DB25F
Coupled Port
J5 P1 DB25M (Male) TRF6900 Evaluation Board
Directional Coupler
Software User's Guide
3-9
Testing of Transmitter
Step 2: Software Programming: For testing the TRF6900 transmitter section, set the main program screen and the chip layout screen as shown in Figure 3-5 and Figure 3-6:
Figure 3-5. Main Program Screen
Transmit Frequency Double Clicking Here With Left Mouse Button to Obtain Chip Layout View
3-10
Testing of Transmitter
Chip Layout Screen of TRF6900 Software for Transmitter Testing
Figure 3-6. Chip Layout Screen
Clicking Here Will Set Power Amp Attenuation (0 dB, 10 dB, 20 dB) or Turn the Power Amp Off
After setup is complete, press the Send Words button on the chip layout screen or the Send Words Now (F12) button on the main program screen to send the programming words to the TRF6900.
Software User's Guide
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Testing of Transmitter
Step 3: Spectrum Analyzer Setup and Clock Offset Procedure Set-up the spectrum analyzer to observe the following:
Figure 3-7. Spectrum Analyzer
Clock Offset Procedure
1) Use the test setup of Figure 3-4 and transmitter software setup as shown in Figure 3-5. 2) Observe the frequency reading on the frequency counter. 3) Subtract 915.000000 MHz from the frequency counter reading. 4) Enter the difference value in the Freq. Error box in the main program screen as shown in Figure 3-8. 5) If difference value is negative, enter - sign, followed by the difference value Example: Frequency Counter reading is 914.996000 MHz. Subtracting 915.000 MHz from 914.996 MHz will yield a difference of -4000 Hz. This difference is entered in the Freq. Error block as -0.004 MHz (see Figure 3-8). 6) Press the Update CLK button on the main program screen. 7) Observe that clock frequency is updated as shown in Figure 3-9. 8) Pressing the Update CLK button twice will cause the frequency offset to be cleared.
3-12
Testing of Transmitter
Figure 3-8. Input of Frequency Error
Figure 3-9. Main Panel Display After Clock Offset Is Applied
Software User's Guide
3-13
Testing of Transmitter
Step 4: FSK Modulation Output Test On the chip layout screen press the PLL/Modulation Options button.
The PLL/Modulation Options View Is Set Up as Shown in Figure 3-10:
Figure 3-10. PLL/Modulation Options View
Select This Button to Start the FSK Modulation Test Select This Button With Mouse to Set FSK Frequency
Select to Program the TRF6900 - Set the DVx bits, as shown in Figure 3-11, by double clicking inside each
DVx box to set the value to either a 1 or 0. For this example only DV6 is set to a 1.
- Press the Send Bits button located on the PLL/Modulations Options
screen, to obtain the results shown in Figure 3-11.
- Press the Close button located on the PLL/Modulations Options screen.
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Testing of Transmitter
Figure 3-11. PLL/Modulation Options Screen
DV6 Display Set to 1
f1 Frequency 915 MHz f2 Frequency 915.10 MHz FSK Deviation of 100 kHz Send Bits Button - Press the Send Words button on the chip layout screen or the Send Words
Now (F12) on the main program screen.
- Press the FSK Test button on the chip layout screen, as shown in Figure
3-10, to start the FSK test.
- Set up the spectrum analyzer to observe the spectrum analyzer display
as shown in Figure 3-12.
Software User's Guide
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Testing of Transmitter
Figure 3-12. FSK Output From Transmitter
Note:
This is FSK modulation with f1 equal to 915.0 MHz, f2 equal to 915.10 MHz and 100 Hz data rate. The f1 frequency is the 0 frequency. The f2 frequency is the 1 frequency.
Figure 3-13. Block Diagram for Testing of the TRF6900 EVM Transmitter Section With an External Pulse Generator
PC With TRF6900 Software Installed
PC Printer (LPT1 or LPT2) Power Supply
Cable DB25M to DB25F
P1 DB25M (Male) 3V 1 kHz
TRF6900 Evaluation Board
J5 Spectrum Analyzer TXDATA TP GND TP Coaxial Cable With Clip Lead Ends
Pulse Generator Pulse Generator Output Waveform
3-16
Testing of Transmitter
To use an external pulse generator to supply transmit data, set up the test bench as shown in Figure 3-13.
- Perform the FSK modulation output test as described in the previous sec-
tion. In this new setup, an external pulse generator is providing the modulation. The FSK Test button on the chip layout screen, does not need to be pressed to start the FSK test.
Figure 3-14. FSK Output From Transmitter With an External Modulation
Note:
This is FSK modulation with f1 equal to 915.0 MHz, f2 equal to 915.10 MHz and 1000 Hz data rate. The f1 frequency is the 0 frequency. The f2 frequency is the 1 frequency.
Software User's Guide
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Testing of the Receiver
3.6 Testing of the Receiver
Figure 3-15. Test Setup for TRF6900 Receiver Testing
10 kHz Pulse Generator Pulse Generator Output Waveform Power Supply Voltage = 8 V Power Supply Cable DB25M to DB25F External Modulation Input Signal Generator
PC With TRF6900 Software Installed
P1 DB25M (Male)
TRF6900 Evaluation Board
RX_IN J4
RSSI TP
+ Ground - Voltmeter
PC Printer Port (LPT1 or LPT2)
AMP_OUT TP Channel 1
RXDATA TP Channel 2 Oscilloscope
Ground TP
3.6.1
Test Equipment Setup
Set the external signal generator and oscilloscope according to the following:
Signal Generator Center frequency FM frequency deviation from carrier External modulation input 915.000 MHz 50 kHz 10 kHz
Oscilloscope Channel 1 2 Volts/Division 1 2 Time/Division 20 s 20 s
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Testing of the Receiver
3.6.2
Software Programming for Receiver Testing
Set up the main program screen and the chip layout screen as shown in Figure 3-16 and Figure 3-17.
Figure 3-16. Main Program Screen
Transmit Frequency for Transmit Mode or LO Frequency for Receive Mode
When Word Bits are Displayed in Red, the Send Words Now (F12) Button Must Be Pressed for Changes to Be Updated
Note: The receiver frequency of the TRF6900 is 915.000 MHz. The TRF6900 is using a 10.7-MHz IF frequency. Therefore, the local oscillator (LO) is set to a frequency of 904.30 MHz. LO frequency = RF frequency - IF Frequency (904.30 = 915.000 - 10.7) The desired frequency block of the TRF6900 software control program is used to set the internal VCO frequency of the TRF6900. (See block diagram)
Software User's Guide
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Testing of the Receiver
Figure 3-17. Chip Layout Screen for Receiver Testing
Press to Program The TRF6900
Press to Select Learning or Hold Modes
3.6.3
Learning and Hold Modes
During the Learning Mode, the data slicer is constantly integrating the incoming signal and charging capacitor C25 (see schematic diagram) to a dc voltage level (Vref) that is proportional to the average demodulation dc level. Capacitor C25 is connected to terminal 29 of the TRF6900 (S&H_CA terminal). During the Hold Mode, the data slicer stops integrating and uses the dc voltage level stored on capacitor C25 as the decision threshold between a logic 1 and logic 0 as measured on terminal 28 DATA_OUT. For receiver measurements, the output of terminal 28 DATA_OUT is measured at the RXDATA test point.
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Testing of the Receiver
3.6.4
Measured Receive Data
The data plots in Figure 3-18 and Figure 3-19, show the measured receive data at the AMP_OUT and RXDATA test points for input signals at -50 dBm and -90 dBm, respectively.
Figure 3-18. Measured Data With -50 dBm Input Signal at AMP_OUT and RXDATA Test Points
AMP_OUT Test Point
RXDATA Test Point
Figure 3-19. Measured Data With -90 dBm Input Signal at AMP_OUT and RXDATA Test Points
AMP_OUT Test Point
RXDATA Test Point
Software User's Guide
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