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SPT7883
10-BIT, 70 MSPS A/D CONVERTER PRELIMINARY INFORMATION
FEATURES
* 2.5 V power supply * SNR: 60 dB @IN = 10 MHz, S = 70 MHz; 58 dB @IN = 30 MHz * Low power dissipation: 145 mW @2.5 V; Sleep mode: 2.6 mW * Sample rate: 10-115 MSPS * Frequency-dependent biasing * Internal sample-and-hold * Differential input * Low input capacitance * 9.67 ENOBs @ IN = 10 MHz, S = 70 MHz * SFDR: 73 dB * IP core available NOVEMBER 21, 2001
APPLICATIONS
* * * * * * * Imaging Computer scanners Communications Set top boxes Video products Battery-operated equipment Portable test equipment
GENERAL DESCRIPTION
The SPT7883 is a compact, high-speed, low-power 10-bit monolithic analog-to-digital converter, implemented in a 0.25 m CMOS process. It has 10-bit resolution with 9.67 effective bits and spurious-free dynamic range (SFDR) of 73 dB for video frequency signals. The converter includes a high bandwidth sample-and-hold. The full-scale range can be set between 0.5 V and 1.5 V. It operates from a single 2.5 V supply. Its low distortion and high dynamic range provide the performance needed for demanding imaging, video, and communications applications.
The bias current level for the ADC is automatically adjusted based on the clock input frequency. Hence, the power dissipation of the device is continuously optimized for the operating frequency. The SPT7883 has a pipelined architecture, resulting in low input capacitance. Digital error correction of the 9 most significant bits ensures good linearity for input frequencies approaching Nyquist. The SPT7883 is available in a 28-lead SSOP package over the industrial temperature range (-40 to +85 C).
BLOCK DIAGRAM
EXTREF BIAS0 BIAS1
Correction Logic
REFP INP
ADC
INN REFN CM CLK
Digital Outputs
Clock Circuit
OE
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur) 25 C
Supply Voltages VDD ............................................................ -0.3 V to +3 V OVDD .............................................. -0.3 V to VDD + 0.3 V Input Voltages Digital Input..................................... -0.3 V to VDD + 0.3 V REFP .............................................. -0.3 V to VDD + 0.3 V REFN .............................................. -0.3 V to VDD + 0.3 V CLOCK ........................................... -0.3 V to VDD + 0.3 V Temperatures Operating Temperature .......................... ....-40 to +85 C Storage Temperature.. ............................. -65 to +125 C
Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA = 25 C, VDD = OVDD = 2.5 V, S = 70 MSPS, IN = 10 MHz, differential input signal, internal references, 50% clock duty cycle, typical bias, unless otherwise noted.
PARAMETER DC Performance Differential Linearity Error (DLE) Integral Linearity Error (ILE) No Missing Codes Offset Error Gain Error Analog Input Input Voltage Range (differential) Input Common Mode Voltage Timing Characteristics Conversion Rate1 Pipeline Delay CLK to Output Delay Dynamic Performance Signal to Noise and Distortion Ratio (SINAD)
TEST CONDITIONS
TEST LEVEL V V V V V V V V V
MIN
SPT7883 TYP 0.35 0.25 Guaranteed 4.88 0.98
MAX
UNITS LSB LSB mV %FS
0.5
1.0 1.2 70 6 6
1.5
V V MSPS Clocks ns
10
115
IN = 10 MHz IN = 30 MHz Signal to Noise Ratio (SNR) IN = 10 MHz IN = 30 MHz Total Harmonic Distortion (THD) IN = 10 MHz IN = 30 MHz Spurious Free Dynamic Range (SFDR) IN = 10 MHz IN = 30 MHz
V V V V V V V V V V V 2.3 2.3
60 58 60 59 -71 -68 73 70 2.5 50 8 2.5 145 2.6 2.75 2.75
dBc dBc dBc dBc dBc dBc dBc dBc V mA mA V mW mW
Power Supply Requirements Supply Voltage (VDD) Supply Current (VDD) Supply Current (OVDD) Output Driver Supply Voltage (OVDD) Power Dissipation Sleep Mode Power Dissipation
1See
S=70 MHz; IN=10 MHz Clock off
V V
graph on page 4
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ELECTRICAL SPECIFICATIONS
TA = 25 C, VDD = OVDD = 2.5 V, S = 70 MSPS, IN = 10 MHz, differential input signal, internal references, 50% clock duty cycle, typical bias, unless otherwise noted.
PARAMETER External Reference Voltages Negative Input Voltage Positive Input Voltage Reference Input Voltage Range (REFP-REFN) Internal Reference Voltages Negative Input Voltage Positive Input Voltage Common Mode Voltage Digital Inputs Logic "0" Voltage Logic "1" Voltage Logic "0" Current (VI=GND) Logic "1" Current (VI=VDD) Digital Outputs Logic "0" Voltage Logic "1" Voltage
TEST CONDITIONS EXTREF = 1
TEST LEVEL V V V
MIN 0.5 0.5
SPT7883 TYP 0.85 1.60 0.75 0.75 1.75 1.20
MAX
UNITS V V V V V V
1.9 1.4
EXTREF = 0 V V V
0.4 2.1 10 10 I = 2 mA I = -2 mA V V 0.2 90% OVDD 0.4
V V A A V V
85% OVDD
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
LEVEL
I II III IV V VI
TEST PROCEDURE
100% production tested at the specified temperature. 100% production tested at TA = +25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25 C. Parameter is guaranteed over specified temperature range.
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Linearity Error Versus Code
0.4
Differential Linearity Error Versus Code
0.4
0.2
0.2
LSBs
0
LSBs
1200
0
0.2
0.2
0.4 0 200 400
0.4
Code
600
800
1000
0
200
400
Code
600
800
1000
1200
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TYPICAL PERFORMANCE CHARACTERISTICS
Performance Versus Sample Rate @IN = 10 MHz
80 IN = 10 MHz
Performance Versus Sample Rate @IN = 30 MHz
80 IN = 30 MHz
SNR, SINAD, THD, SFDR (dB)
SNR, SINAD, THD, SFDR (dB)
75 70 65 60 55 50 45 10 30 50 SNR SINAD THD
75 70 65 60 55 50 45 THD SNR SINAD SFDR
SFDR
70
Sample Rate (MSPS)
90
110
130
10
30
50
70
90
110
130
Sample Rate (MSPS)
Performance Versus Input Frequency
80
Performance Versus Temperature
80 S = 70 MHz IN = 10 MHz
SNR, SINAD, THD, SFDR (dB)
S = 70 MHz
SNR, SINAD, THD, SFDR (dB)
75 70 65 60 55 50 45 0 5 10 SNR SINAD SFDR
75 70 65 60 55 50 45 50
SFDR THD
THD
SNR SINAD
15
20
Input Frequency (MHz)
25
30
35
25
0
Temperature (Degrees C)
25
50
75
100
Power Dissipation Versus Sample Rate
240 200 Typical Bias 160
20
Sleep Mode Power Dissipation Versus Sample Rate (Clock On)
15
mW
120 80
+12.5% Bias 12.5% Bias
10
5
40 0
0
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
Sample Rate (MSPS)
Sample Rate (MSPS)
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REFERENCES
The SPT7883 can use either an internal or external voltage reference. When the digital input EXTREF is high, the external reference is used. When EXTREF is low, the internal reference is used. INTERNAL REFERENCE The internal references are set at +0.75 V and +1.75 V. When the internal reference is used, the full-scale range of the analog input is set at 1.0 V differential. Do not connect external references when the internal reference is used. EXTERNAL REFERENCE When external references are used, the voltages applied to the VREF+ and VREF- pins determine the input voltage range, which is equal to (VREF+ - VREF-). Externally generated reference voltages must be connected to these pins and should be symmetric about the common mode voltage (1.2 V).
AC-coupled input is most conveniently implemented using a transformer with a center-tapped secondary winding. The center tap is connected to the CM node, as shown in figure 1. In order to obtain low distortion, it is important that the selected transformer does not exhibit core saturation at full scale. Excellent results are obtained with the MiniCircuits T1-6T or T4-6T. Proper termination of the input is important for input signal purity. A 50 resistor in series with each input and a small capacitor (typ 27 pF) across the inputs will attenuate kickback noise from the sampleand-hold. If a DC-coupled single-ended input is wanted, a solution based on operational amplifiers is usually preferred. The AD8138 is an easy-to-use, single-ended-to-differential converter. Its data sheet claims -87 dBc @ 20 MHz. Lower-cost operational amplifiers may be used if the demands are less strict.
CLOCK
In order to preserve accuracy at high input frequency, it is important that the clock have low jitter and fast rise and fall times. Rise/fall times should be kept shorter than 2 ns whenever possible. Overshoot should be minimized. Low jitter is especially important when converting highfrequency input signals. Jitter causes the noise floor to rise proportionally to input signal frequency. The analog input is sampled at the falling edge of the clock.
ANALOG INPUT
The SPT7883 has a differential input that should have a common mode voltage of 1.2 V. The input voltage range is determined by the reference voltages, which may be generated internally or applied externally. The input of the SPT7883 can be configured in various ways depending on whether a single-ended or differential, AC- or DC-coupled input is desired.
Figure 1 - Typical Interface Circuit
+A2.5 +A2.5
EXTREF 4.7 + 0.1 0.01 0.1 4.7 GND + 0.1 0.1 VDD REFN REFP EXTREF CM GND + 0.01 VDD INN INP BIAS0 BIAS1 CLK OE D0 D1 D2 D3 D4 GND GND OVDD OVDD D5 D6 D7 D8 D9 100pF .1 10 + 4.7 50 50 50 50
Logic Interface Circuit
50
4.7 + 50
10
+A2.5
AIN
T1
Mini-Circuits T1-6T or T4-6T +A2.5
Buffer
50 (T1-6T) or 200 (T4-6T) 50
CLK
+A2.5
+ 4.7 27 pF OE
.1
0.1 0.001
AGND
5
SPT7883
+A2.5
50 50 50 50 50
FB1 (Ferrite Bead)
DGND +D5
SPT7883
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Figure 2 - Timing Diagram
N1 AIN N N+1 N+2 N+3
Clock tD
tAP
tH
Data
Data N1
Data N
Data N+1
Data N+2
DIGITAL OUTPUTS
When the output enable is set high, then the digital output data appears in offset binary code at CMOS 2.5 V logic levels. Full-scale negative input results in output code 000...0. Full-scale positive input results in output code 111...1. Output data is available 6 clock cycles after the data is sampled. The analog input is sampled one aperture delay (tAP) after the high-to-low clock transition. Output data should be sampled as shown in the timing diagram above. When the output enable is set low, then the digital output data goes into a high Z-mode.
PCB LAYOUT AND DECOUPLING
A well designed PCB is necessary to get good spectral purity from any high-performance ADC. A multilayer PCB with a solid ground plane is recommended for optimum performance. If the system has a split analog and digital ground plane, it is recommended that all ground pins on the ADC be connected to the analog ground plane (AGND). All digital interface circuits are connected to the digital ground (DGND). AGND and DGND planes must be connected through a ferrite bead placed as close to the ADC as possible. Refer to the typical interface circuit diagram (figure 1) or AN7883 application note for recommended decoupling and PCB layout.
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PACKAGE OUTLINE
28-Lead SSOP
INCHES MIN MAX 0.397 0.407 0.002 0.008 0.0256 typ 0.010 0.015 0.004 0.008 0.066 0.070 0.025 0.037 0.301 0.311 0.205 0.212 MILLIMETERS MIN MAX 10.07 10.33 0.05 0.21 0.65 typ 0.25 0.38 0.09 0.20 1.68 1.78 0.63 0.95 7.65 7.90 5.20 5.38
28
IH
1
SYMBOL A B C D E F G H I
A F B C H D
G E
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PIN ASSIGNMENTS
D9 D8 D7 D6 D5 OVDD OVDD GND GND
1 2 3 4 5 6 7 8 9 28 27 26 25 24 23
PIN FUNCTIONS
Pin Name Description Differential input signal pins. Common-mode voltage: 1.2 V Reference I/O pins.
OE CLK BIAS1 BIAS0 INP INN VDD GND CM EXTREF REFP REFN VDD GND
INP INN REFP REFN
BIAS0, BIAS1 BIAS1=0, BIAS0=0: Sleep mode (power save) BIAS1=0, BIAS0=1: -12.5% bias BIAS1=1, BIAS0=0: +12.5% bias BIAS1=1, BIAS0=1: Typ. Bias CLK CM D9-D0 OE Clock input Common mode voltage output Digital outputs (MSB to LSB) Enable digital outputs Logic 1: Digital output enable Logic 0: Tri-state Digital input: Reference select. EXTREF=1: Use external reference. Internal reference powered down. EXTREF=0: Internal reference is used. Power supply pins Ground pins Power supply pins for output drivers
SPT7883 28L SSOP
22 21 20 19 18 17 16 15
EXTREF
D4 10 D3 11 D2 12 D1 13 D0 14
VDD GND OVDD
ORDERING INFORMATION
PART NUMBER SPT7883SIR TEMPERATURE RANGE -40 to +85 C PACKAGE 28L SSOP
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
www.fairchildsemi.com
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) Copyright 2002 Fairchild Semiconductor Corporation
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