View SN74LVC1T45_1004050.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
SCES515 - DECEMBER 2003
D Available in the Texas Instruments D D D D D D
NanoStar and NanoFree Packages Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range VCC Isolation Feature - If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State DIR Referenced to VCCA Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation
DBV OR DCK PACKAGE (TOP VIEW)
VCCA GND A
1 2 3
6 5 4
VCCB DIR B
YEP OR YZP PACKAGE (BOTTOM VIEW)
A GND VCCA
34 25 16
B DIR VCCB
description/ordering information
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A-port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B-port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. The SN74LVC1T45 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The SN74LVC1T245 is designed so that DIR is supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION
TA PACKAGE NanoStar - WCSP (DSBGA) 0.23-mm Large Bump - YEP -40C to 85C NanoFree - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) SOT (SOT-23) - DBV SOT (SC-70) - DCK Tape and reel SN74LVC1T45YZPR Tape and reel Tape and reel SN74LVC1T45DBVR SN74LVC1T45DCKR TBD TBD ORDERABLE PART NUMBER SN74LVC1T45YEPR TBD TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
PRODUCT PREVIEW
SCES515 - DECEMBER 2003
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
FUNCTION TABLE INPUT DIR L H OPERATION B data to A bus A data to B bus
logic diagram (positive logic)
DIR
5
A
3
4
PRODUCT PREVIEW
B
VCCA
VCCB
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCCA and VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCCA + 0.5V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCCB + 0.5V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
SCES515 - DECEMBER 2003
recommended operating conditions (see Notes 4 through 8)
VCCI VCCA VCCB Supply voltage 1.65 V to 1.95 V VIH High-level input voltage Data inputs (see Note 7) 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V 1.65 V to 1.95 V VIL Low-level input voltage Data inputs (see Note 7) 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V 1.65 V to 1.95 V VIH High-level input voltage DIR (Referenced to VCCA) (see Note 8) 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V 1.65 V to 1.95 V VIL Low-level input voltage DIR (Referenced to VCCA) (see Note 8) 2.3 V to 2.7 V 3 V to 3.6 V 4.5 V to 5.5 V VI VO Input voltage Output voltage 1.65 V to 1.95 V 2.3 V to 2.7 V IOH High-level output current 3 V to 3.6 V 4.5 V to 5.5 V 1.65 V to 1.95 V 2.3 V to 2.7 V IOL Low-level output current 3 V to 3.6 V 4.5 V to 5.5 V 1.65 V to 1.95 V 2.3 V to 2.7 V t/v t/ v Input transition rise or fall rate Data input 3 V to 3.6 V 4.5 V to 5.5 V Control input 1.65 V to 5.5 V 0 0 VCCA x 0.65 1.7 2 VCCA x 0.7 VCCA x 0.35 0.7 0.8 VCCA x 0.3 5.5 VCCO -4 -8 -24 -32 4 8 24 32 20 20 10 5 5 ns/V mA mA V V VCCO MIN 1.65 1.65 VCCI x 0.65 1.7 2 VCCI x 0.7 VCCI x 0.35 0.7 0.8 VCCI x 0.3 V V MAX 5.5 5.5 V UNIT
V V
TA Operating free-air temperature -40 85 C NOTES: 4. VCCI is the VCC associated with the data input port. 5. VCCO is the VCC associated with the output port. 6. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 7. For VCCI values not specified in the data sheet, VIH(min) = VCCI x 0.7 V, VIL(max) = VCCI x 0.3 V. 8. For VCCI values not specified in the data sheet, VIH(min) = VCCA x 0.7 V, VIL(max) = VCCA x 0.3 V.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
PRODUCT PREVIEW
SCES515 - DECEMBER 2003
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Notes 9 and 10)
PARAMETER TEST CONDITIONS IOH = -100 A, IOH = -4 mA, VOH IOH = -8 mA, IOH = -24 mA, IOH = -32 mA, IOL = 100 A, VOL IOL = 4 mA, IOL = 8 mA, IOL = 24 mA, IOL = 32 mA, II Ioff IOZ DIR input A port VI = VIH VI = VIH VI = VIH VI = VIH VI = VIH VI = VIL VI = VIL VI = VIL VI = VIL VI = VIL VCCA 1.65 V to 4.5 V 1.65V 2.3 V 3V 4.5 V 1.65 V to 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 0V VI or VO = 0 to 5.5 V VO = VCCO or GND 0 to 5.5 V 1.65 V to 5.5 V 1.95 V 2.7 V ICCA VI = VCCI or GND 3.6 V IO = 0 5.5 V 0V 5.5 V 1.95 V 2.7 V ICCB VI = VCCI or GND 3.6 V IO = 0 5.5 V 0V 5.5 V ICCA + ICCB (see Table 1) A port ICCA DIR ICCB Ci Cio VI = VCCI or GND IO = 0 1.65 V to 5.5 V VCCB 1.65 V to 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 4.5 V 1.65 V 2.3 V 3V 4.5 V 1.65 V to 5.5 V 0 to 5.5 V 0V 1.65 V to 5.5 V 1.95 V 2.7 V 3.6 V 0V 5.5 V 5.5 V 1.95 V 2.7 V 3.6 V 0V 5.5 V 5.5 V 1.65 V to 5.5 V TBD TBD TBD TBD MIN TA = 25C TYP MAX -40C to 85C MIN
VCCO-0.1
MAX
UNIT
1.2 1.9 2.4 3.8 0.1 0.45 0.3 0.55 0.55 5 10 10 10 1 1 1 2 0 1 1 1 1 0 2 1 4 50 A A A A A A A A A V V
VI = VCCA or GND
PRODUCT PREVIEW
B port A or B ports
A port at VCCA - 0.6 V, DIR at VCCA, B port = OPEN DIR at VCCA - 0.6 V, B port = OPEN, A port at VCCA or GND B port at VCCB - 0.6 V, DIR at GND, A port = OPEN VI = VCCA or GND VO =VCCA/B or GND 3 V to 5.5 V 3 V to 5.5 V
A 50 A pF pF
B port DIR input A or B ports
3 V to 5.5 V 3.3 V 3.3 V
3 V to 5.5 V 3.3 V 3.3 V TBD TBD
50
NOTES: 9. VCCO is the VCC associated with the output port. 10. VCCI is the VCC associated with the input port.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
SCES515 - DECEMBER 2003
switching characteristics over recommended operating VCCA = 1.8 V 0.15 V(unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) B VCCB = 1.8 V 0.15 V MIN MAX
free-air
temperature
VCCB = 5 V 0.5 V MIN MAX
range,
VCCB = 2.5 V 0.2 V MIN MAX
VCCB = 3.3 V 0.3 V MIN MAX
UNIT
A
ns
B
A
ns
DIR
A
ns
DIR
B
ns
DIR
A
ns
switching characteristics over recommended operating VCCA = 2.5 V 0.2 V(unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) B VCCB = 1.8 V 0.15 V MIN MAX
free-air
temperature
VCCB = 5 V 0.5 V MIN MAX
range,
VCCB = 2.5 V 0.2 V MIN MAX
VCCB = 3.3 V 0.3 V MIN MAX
UNIT
A
ns
B
A
ns
DIR
A
ns
DIR
B
ns
DIR
A
ns
DIR
B
ns
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
PRODUCT PREVIEW
DIR
B
ns
SCES515 - DECEMBER 2003
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
switching characteristics over recommended operating VCCA = 3.3 V 0.3 V(unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ FROM (INPUT) TO (OUTPUT) B VCCB = 1.8 V 0.15 V MIN MAX
free-air
temperature
VCCB = 5 V 0.5 V MIN MAX
range,
VCCB = 2.5 V 0.2 V MIN MAX
VCCB = 3.3 V 0.3 V MIN MAX
UNIT
A
ns
B
A
ns
DIR
A
ns
DIR
B
ns
DIR
A
ns
PRODUCT PREVIEW
tPLZ
DIR
B
ns
switching characteristics over recommended operating VCCA = 5 V 0.5 V(unless otherwise noted) (see Figure 1)
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) B VCCB = 1.8 V 0.15 V MIN MAX
free-air
temperature
VCCB = 5 V 0.5 V MIN MAX
range,
VCCB = 2.5 V 0.2 V MIN MAX
VCCB = 3.3 V 0.3 V MIN MAX
UNIT
A
ns
B
A
ns
DIR
A
ns
DIR
B
ns
DIR
A
ns
DIR
B
ns
operating characteristics, TA = 25C
PARAMETER A port input, B port output B port input, A port output A port input, B port output B port input, A port output CL = 0, f = 10 MHz, tr = tf =1 ns pF TEST CONDITIONS VCCA = VCCB = 1.8 V TYP CpdA CpdB VCCA = VCCB = 2.5 V TYP VCCA = VCCB = 3.3 V TYP VCCA = VCCB = 5 V TYP UNIT
Power dissipation capacitance
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
SCES515 - DECEMBER 2003
power-up considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies. Take the following precautions, in the order given, to guard against such power-up problems: 1. Connect ground before any supply voltage is applied. 2. Power up VCCA. 3. Ramp up VCCB along with or after VCCA.
typical total static power consumption (ICCA and ICCB)
VCCB 1.8 V 2.5 V 3.3 V 5V VCCA 1.8 V <1 <1 <1 1.5 2.5 V <1 <1 <1 1 3.3 V <1 <1 <1 <1 5V 1.5 1 <1 <1 A A UNIT
TABLE 1
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
PRODUCT PREVIEW
SCES515 - DECEMBER 2003
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE, TA = 25C,VCCA = 1.8 V
4 3.75 3.5 3.25 3 T PLH - ns 2.75 2.5 2.25 2 1.75 T PHL - ns 0 10 20 CL - pF 30 40 50 4 3.75 3.5 3.25 3 2.75 2.5 2.25 2 1.75 1.5 0 10 20 CL - pF 30 40 50
PRODUCT PREVIEW
1.5
TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE, TA = 25C,VCCA = 2.5 V
4 3.75 3.5 3.25 3 T PLH - ns 2.75 2.5 2.25 2 1.75 1.5 0 10 20 CL - pF 30 40 50 T PHL - ns 4 3.75 3.5 3.25 3 2.75 2.5 2.25 2 1.75 1.5 0 10 20 CL - pF 30 40 50
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
SCES515 - DECEMBER 2003
TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE, TA = 25C,VCCA = 3.3 V
4 3.75 3.5 3.25 3 T PLH - ns 2.75 2.5 2.25 2 1.75 1.5 0 10 20 CL - pF 30 40 50 T PHL - ns 4 3.75 3.5 3.25 3 2.75 2.5 2.25 2 1.75
0
10
20 CL - pF
30
40
50
TYPICAL PROPAGATION DELAY vs LOAD CAPACITANCE, TA = 25C,VCCA = 5 V
4 3.75 3.5 3.25 3 T PLH - ns 2.75 2.5 2.25 2 1.75 1.5 0 10 20 CL - pF 30 40 50 T PHL - ns 4 3.75 3.5 3.25 3 2.75 2.5 2.25 2 1.75 1.5 0 10 20 CL - pF 30 40 50
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
9
PRODUCT PREVIEW
1.5
SCES515 - DECEMBER 2003
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
2 x VCCO From Output Under Test CL (see Note A) RL RL S1 Open GND TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCCO GND
LOAD CIRCUIT
tw VCCI Input VCCI/2 VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION
VCCO 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V
CL 15 pF 15 pF 15 pF 15 pF
RL 2 k 2 k 2 k 2 k
VTP 0.15 V 0.15 V 0.3 V 0.3 V
tr or tf 2 ns 2ns 2.5 ns 2.5 ns Output Control (low-level enabling) tPZL VCCI Output Waveform 1 S1 at 2 x VCCO (see Note B) tPZH Output Waveform 2 S1 at GND (see Note B)
PRODUCT PREVIEW
VCCA VCCA/2 VCCA/2 0V tPLZ VCCO VCCO/2 VOL + VTP tPHZ VOH - VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL
Input
VCCI/2
VCCI/2 0V tPHL VOH VCCO/2 VOL
tPLH
Output
VCCO/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
VCCO/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 . D. The outputs are measured one at a time with one transition per measurement. E. VCCI is the power supply voltage associated with the input port. F. VCCO is the power supply voltage associated with the output port.
Figure 1. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
SCES515 - DECEMBER 2003
APPLICATION INFORMATION
The following circuit is an example of the SN74LVC1T45 used in a unidirectional logic level-shifting application.
VCC1 VCC1 VCC2 VCC2
1 2 3
6 5 4
SYSTEM-1
SYSTEM-2
PIN 1 2 3 4 5 6
NAME VCCA GND A B DIR VCCB
FUNCTION VCC1 GND OUT IN DIR VCC2
DESCRIPTION SYSTEM-1 supply voltage (1.65 V to 5.5 V)
Output level depends on VCC1 voltage Input threshold-value depends on VCC2 voltage The GND (low-level) determines B-port to A-port direction SYSTEM-2 supply voltage (1.65 V to 5.5 V)
Figure 2. Unidirectional Logic Level-Shifting Application
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
11
PRODUCT PREVIEW
Device GND
SCES515 - DECEMBER 2003
SN74LVC1T45 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS
APPLICATION INFORMATION
Figure 3 shows the SN74LVC1T45 being used in a bidirectional logic level-shifting application. Because the SN74LVC1T45 does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
VCC1 VCC1 VCC2 VCC2 I/O-1 Pullup/Down or Bus Hold 1 2 3 6 5 4 Pullup/Down or Bus Hold I/O-2
DIR CTRL
PRODUCT PREVIEW
SYSTEM-1
SYSTEM-2
The sequence in Figure 3 illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1.
STATE 1 2 3 4 DIR CTRL H H L L I/O 1 OUT HI-Z HI-Z OUT I/O 2 IN HI-Z HI-Z IN SYSTEM-1 data to SYSTEM-2 SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on pullup or pulldown. DIR bit is flipped. I/O-1 and I/O-2 are still disabled. The bus-line state depends on pullup or pulldown. SYSTEM-2 data to SYSTEM-1 DESCRIPTION
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
12
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS114 - FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,65 6 4
0,30 0,15
0,10 M
1,40 1,10
2,40 1,80
0,13 NOM
1 2,15 1,85
3
Gage Plane
0,15 0-8 0,46 0,26
Seating Plane 1,10 0,80 0,10 0,00 0,10
4093553-3/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-203
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

▲Up To Search▲

Price & Availability of SN74LVC1T45

	To Download SN74LVC1T45 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .