View SN65C1154_1003968.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D - DECEMBER 1988 - REVISED APRIL 2003
D D D D D D D
Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Very Low Power Consumption . . . 5 mW Typ Wide Driver Supply Voltage . . . 4.5 V to 15 V Driver Output Slew Rate Limited to 30 V/s Max Receiver Input Hysteresis . . . 1000 mV Typ Push-Pull Receiver Outputs On-Chip Receiver 1-s Noise Filter
SN65C1154 . . . N PACKAGE SN75C1154 . . . DW, N, OR NS PACKAGE (TOP VIEW)
VDD 1RA 1DY 2RA 2DY 3RA 3DY 4RA 4DY VSS
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC 1RY 1DA 2RY 2DA 3RY 3DA 4RY 4DA GND
description/ordering information
The SN65C1164 and SN75C1154 are low-power BiMOS devices containing four independent drivers and receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1154 and SN75C1154 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/s and the receivers have filters that reject input noise pulses of shorter than 1 s. Both these features eliminate the need for external components. The SN65C1154 and SN75C1154 have been designed using low-power techniques in a BiMOS technology. In most applications, the receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices usually are insensitive to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the SN65C1154 and SN75C1154 receiver outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families. ORDERING INFORMATION
TA -40C to 85C PDIP (N) PDIP (N) 0C to 70C SOIC (DW) PACKAGE Tube of 20 Tube of 20 Tube of 25 Reel of 2500 ORDERABLE PART NUMBER SN65C1154N SN75C1154N SN75C1154DW SN75C1154DWR TOP-SIDE MARKING SN65C1154N SN75C1154N SN75C1154
SOP (NS) Reel of 2000 SN75C1154NSR SN75C1154 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D - DECEMBER 1988 - REVISED APRIL 2003
logic diagram (positive logic)
Typical of Each Receiver RA 2, 4, 6, 8 19, 17, 15, 13 RY
Typical of Each Driver DY 3, 5, 7, 9 18, 16, 14, 12 DA
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D - DECEMBER 1988 - REVISED APRIL 2003
schematics of inputs and outputs
EQUIVALENT DRIVER INPUT VDD EQUIVALENT DRIVER OUTPUT VDD
Input DA
Internal 1.4-V Reference
VSS GND
160 74
Output DY
72 VSS
Input RA
EQUIVALENT RECEIVER INPUT 3.4 k
EQUIVALENT RECEIVER OUTPUT VCC
1.5 k ESD Protection ESD Protection 530 GND Output RY
GND Resistor values shown are nominal.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D - DECEMBER 1988 - REVISED APRIL 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage: VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30 V to 30 V Output voltage range, VO:Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VSS - 6 V) to (VDD + 6 V) Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (VCC + 0.3 V) Package thermal impedance, JA (see Notes 2 and 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 60C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage s are with respect to the network GND terminal. 2. Maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) - TA)/JA. Operating at the absolute maximum TJ of 150C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN VDD VSS VCC VI VIH VIL IOH IOL TA Supply voltage Supply voltage Supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current High-level output current O erating Operating free-air temperature tem erature Driver Receiver Driver Driver Receiver Receiver SN65C1154 SN75C1154 -40 0 2 0.8 -1 3.2 85 70 4.5 -4.5 4.5 VSS + 2 NOM 12 -12 5 MAX 15 -15 6 VDD 25 UNIT V V V V V V mA mA C
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D - DECEMBER 1988 - REVISED APRIL 2003
DRIVER SECTION electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = -12 V, VCC = 5 V 10% (unless otherwise noted)
PARAMETER VOH VOL IIH IIL IOS(H) IOS(L) IDD ISS High-level High level output voltage Low-level output voltage g (see Note 4) High-level input current Low-level input current High-level short-circuit g output current Low-level short-circuit output current Supply current from VDD Supply current from VSS VIL = 0.8 V, , See Figure 1 VIH = 2 V, , See Figure 1 VI = 5 V, VI = 0, VI = 0 8 V 0.8 V, VI = 2 V V, TEST CONDITIONS RL = 3 k, , RL = 3 k, , See Figure 2 See Figure 2 VO = 0 or VSS, VO = 0 or VDD, See Figure 1 See Figure 1 VDD = 5 V, VDD = 12 V, VDD = 5 V, VDD = 12 V, VSS = -5 V VSS = -12 V VSS = -5 V VSS = -12 V -7.5 75 7.5 75 -12 12 12 115 115 -115 -115 VDD = 5 V, VDD = 12 V, VDD = 5 V, VDD = 12 V, VSS = -5 V VSS = -12 V VSS = -5 V VSS = -12 V MIN 4 10 TYP 4.5 10.8 -4.4 -10.7 -4 -10 1 -1 -19.5 19 5 19.5 19 5 250 250 -250 -250 MAX UNIT V V A A mA mA A A
No load, All inputs at 2 V or 0.8 V No load, All inputs at 2 V or 0.8 V
ro Output resistance VDD = VSS = VCC = 0, VO = -2 V to 2 V, See Note 5 300 400 All typical values are at TA = 25C. Not more than one output should be shorted at one time. NOTES: 4. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic levels only. 5. Test conditions are those specified by TIA/EIA-232-F.
switching characteristics, VDD = 12 V, VSS = -12 V, VCC = 5 V 10%, TA = 25C (see Figure 3)
PARAMETER tPLH tPHL tTLH tTHL tTLH tTHL SR Propagation delay time, low- to high-level output Propagation delay time, high- to low-level output Transition time, low- to high-level output Transition time, high- to low-level output Transition time, low- to high-level output# Transition time, high- to low-level output# Output slew rate TEST CONDITIONS RL = 3 to 7 k, RL = 3 to 7 k, RL = 3 to 7 k, RL = 3 to 7 k, RL = 3 to 7 k, RL = 3 to 7 k, RL = 3 to 7 k, CL = 15 pF CL = 15 pF CL = 15 pF CL = 15 pF CL = 2500 pF CL = 2500 pF CL = 15 pF 4 0.53 0.53 MIN TYP 1.2 2.5 2 2 1 1 10 MAX 3 3.5 3.2 3.2 2 2 30 UNIT s s s s s s V/s
tPHL and tPLH include the additional time due to on-chip slew rate control and are measured at the 50% points. Measured between 10% and 90% points of output waveform # Measured between 3 V and -3 V points of output waveform (TIA/EIA-232-F conditions) with all unused inputs tied either high or low
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D - DECEMBER 1988 - REVISED APRIL 2003
RECEIVER SECTION electrical characteristics over operating free-air temperature range, VDD = 12 V, VSS = -12 V, = 5 V 10% (unless otherwise noted)
PARAMETER VIT IT+ VIT IT- Vhys Positive-going input gg threshold voltage Negative-going input g gg threshold voltage Input hysteresis voltage (VIT+ - VIT-) VI = 0.75 V, VOH High-level High level output voltage VI = 0 75 V 0.75 V, See Figure 5 VI = 3 V, VI = 25 V VI = 3 V VI = -25 V VI = -3 V VI = 0 75 V 0.75 V, VI = VCC, VO = 0 0, VO = VCC, See Figure 4 See Figure 4 VDD = 5 V, VDD = 12 V, VSS = -5 V VSS = -12 V IOH = -20 A, IOH = -1 mA, 1A See Figure 5 and Note 6 VCC = 4.5 V VCC = 5 V VCC = 5.5 V See Figure 5 See Figure 5 See Figure 5 TEST CONDITIONS MIN 1.7 17 0.65 0 65 600 3.5 2.8 3.8 4.3 3.6 0.43 -3.6 -0.43 4.4 4.9 5.4 0.17 4.6 0.55 -5 -0.55 8 -8 13 400 400 0.4 8.3 1 -8.3 -1 15 -15 25 600 600 V mA mA mA mA A V TYP 2.1 21 1 1000 MAX 2.55 2 55 1.25 1 25
VCC
UNIT V V mV
VOL IIH IIL IOS(H) IOS(L) ICC
Low-level output voltage High-level High level input current Low-level Low level input current Short-circuit output at high level Short-circuit output at low level Supply current from VCC
IOL = 3.2 mA,
No load, All inputs at 0 or 5 V
All typical values are at TA = 25C. NOTE 6: If the inputs are left unconnected, the receiver interprets this as an input low and the receiver outputs will remain in the high state.
switching characteristics, VDD = 12 V, VSS = -12 V, VCC = 5 V 10%, TA = 25C
PARAMETER tPLH tPHL tTLH tTHL tw(N) Propagation delay time, low- to high-level output Propagation delay time, high- to low-level output Transition time, low- to high-level output Transition time, high- to low-level output Duration of longest pulse rejected as noise CL = 50 pF, CL = 50 pF, CL = 50 pF, CL = 50 pF, CL = 50 pF, TEST CONDITIONS RL = 5 k, RL = 5 k, RL = 5 k, RL = 5 k, RL = 5 k See Figure 6 See Figure 6 See Figure 6 See Figure 6 1 MIN TYP 3 3 300 100 MAX 4 4 450 300 4 UNIT s s ns ns s
The receiver ignores any positive- or negative-going pulse that is less than the minimum value of tw(N) and accepts any positive- or negative-going pulse greater than the maximum of tw(N).
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D - DECEMBER 1988 - REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION
IOSL VDD VCC VDD or GND -IOSH VSS or GND RL = 3 k VI -IIL VO VI IIH VDD VCC
VI
VSS
VSS
Figure 1. Driver Test Circuit (VOH, VOL, IOSL, IOSH)
Figure 2. Driver Test Circuit (IIL, IIH)
VDD Input Pulse Generator (see Note A) RL VSS TEST CIRCUIT CL (see Note B) VCC Input 1.5 1.5
3V
0V tPHL 90% Output tTHL VOLTAGE WAVEFORMS 50% 10% 50% 10% tTLH tPLH 90% VOH VOL
NOTES: A. The pulse generator has the following characteristics: tw = 25 s, PRR = 20 kHz, ZO = 50 , tr = tf < 50 ns. B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
VDD VCC
-IOS(H)
VDD VCC
VI
IOS(L) VCC
VIT, VI VOH VOL IOL -IOH
VSS
VSS
Figure 4. Receiver Test Circuit (IOSH, IOSL)
Figure 5. Receiver Test Circuit (VIT, VOL, VOH)
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
7
SN65C1154, SN75C1154 QUADRUPLE LOW-POWER DRIVERS/RECEIVERS
SLLS151D - DECEMBER 1988 - REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION
VDD Input Pulse Generator (see Note A) RL CL (see Note B) VCC Input 50% 50% 0V tPHL 90% Output tTHL VOLTAGE WAVEFORMS 50% 10% 50% 10% tTLH tPLH 90% VOH VOL 4V
VSS TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: tw = 25 s, PRR = 20 kHz, ZO = 50 , tr = tf < 50 ns. B. CL includes probe and jig capacitance.
Figure 6. Receiver Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL
MPDI002C - JANUARY 1995 - REVISED DECEMBER 20002
N (R-PDIP-T**)
16 PINS SHOWN
PLASTIC DUAL-IN-LINE PACKAGE
PINS ** DIM A 16 9 A MAX
14 0.775 (19,69) 0.745 (18,92)
16 0.775 (19,69) 0.745 (18,92)
18 0.920 (23,37) 0.850 (21,59)
20 1.060 (26,92) 0.940 (23,88)
A MIN
0.260 (6,60) 0.240 (6,10)
C
MS-100 VARIATION
AA
BB
AC
AD
1 0.070 (1,78) 0.045 (1,14) D
8
0.045 (1,14) 0.030 (0,76) D
0.020 (0,51) MIN
0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gauge Plane
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
14/18 PIN ONLY 20 pin vendor option
D 4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
MECHANICAL DATA
MSOI003E - JANUARY 1995 - REVISED SEPTEMBER 2001
DW (R-PDSO-G**)
16 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 9
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 16
0.010 (0,25)
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.291 (7,39) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** DIM A MAX 0.004 (0,10)
16 0.410 (10,41) 0.400 (10,16)
18 0.462 (11,73) 0.453 (11,51)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24)
28 0.710 (18,03) 0.700 (17,78) 4040000/E 08/01
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
1
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SN65C1154

	To Download SN65C1154 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .