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TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
D D D D D D D D
Organization: - TM8SK64JPU . . . 8 388 608 x 64 Bits Single 3.3-V Power Supply (10% Tolerance) Designed for 66-MHz 4-Clock Systems JEDEC 144-Pin Small Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket Uses Eight 64M-Bit Synchronous Dynamic RAMs (SDRAMs) (8M x 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) Byte-Read/Write Capability Performance Ranges: High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface
D D D D D D D D
Read Latencies 2 and 3 Supported Support Burst-Interleave and Burst-Interrupt Operations Burst Length Programmable to 1, 2, 4, and 8 Four Banks for On-Chip Interleaving (Gapless Access) Ambient Temperature Range 0C to 70C Gold-Plated Contacts Pipeline Architecture Serial Presence Detect (SPD) Using EEPROM
SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 '8SK64JPU-10 10 ns 15 ns
ACCESS TIME CLOCK TO OUTPUT tAC3 tAC2 8 ns 9 ns
REFRESH INTERVAL tREF 64 ms
description
The TM8SK64JPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS664814DGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS690).
operation
The TM8SK64JPU operates as eight TMS664814DGE devices that are connected as shown in the TM8SK64JPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
TM8SK64JPU ( SIDE VIEW ) A[0:11] A[0:8] A13/BA0 A12/BA1 CAS CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7] NC RAS S0 SCL SDA VDD VSS WE
PIN NOMENCLATURE Row Address Inputs Column Address Inputs Bank-Select Zero Bank-Select One Column-Address Strobe Clock Enable System Clock Data-In / Data Out Data-In/Data-Out Mask Enable No Connect Row-Address Strobe Chip-Select SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable
1
59
61
143
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NO. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 PIN DQMB5 DQMB1 DQMB4 DQMB0 NAME DQ39 DQ38 DQ37 DQ36 DQ35 DQ34 DQ33 DQ32 VDD VDD VDD VDD DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VSS VSS VSS VSS VSS VSS A5 A2 A4 A1 A3 A0 NO. 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 PIN NAME
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Pin Assignments
CKE0
DQ47
DQ15
DQ46
DQ14
DQ45
DQ13
DQ44
DQ12
DQ43
DQ42
DQ10
DQ41
DQ40
DQ11
TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
VDD VDD
VDD VDD
CAS
RAS
DQ9
DQ8
VSS VSS
CK0
WE
NC
NC
NC
NC
NC
NC
NC
NC
S0
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NO. 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PIN NAME A13/BA0 DQ55 DQ23 DQ54 DQ22 DQ53 DQ21 DQ52 DQ20 DQ51 DQ19 DQ50 DQ18 DQ49 DQ17 DQ48 DQ16 VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS CK1 NC NC NC NC NC A8 A7 A6 NO. 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128AAAAAA DQ59 127 126 125 124 123 122 121 120 109 119 118 117 116 115 114 113 112 110 111AAAAAA A10 PIN NAME A12/BA1 DQMB7 DQMB3 DQMB6 DQMB2 DQ63 DQ31 DQ62 DQ30 DQ61 DQ29 DQ60 DQ28 DQ27 DQ58 DQ26 DQ57 DQ25 DQ56 DQ24 VDD VDD VDD VDD VDD VDD SDA VSS VSS VSS VSS SCL A11 A9
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
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TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
small-outline dual-in-line memory module and components
The small-outline dual-in-line memory module and components include:
D D D
PC substrate: 1,10 0,1 mm (0.04 inch) nominal thickness Bypass capacitors: Multilayer ceramic Contact area: Nickel plate and gold plate over copper
functional block diagram
S0 RC CS CS CK: U0, UB0 CK0 UB0 CK1 RC CK: U1, UB1 DQMB0 R DQ[0:7] 8 DQM DQ[0:7] U0 DQMB4 R DQ[32:39] 8 DQM DQ[0:7] RC CK: U2, UB2 RC CK: U3, UB3 RC CK2 CS CS RC CK3 DQMB1 R DQ[8:15] 8 DQM DQ[0:7] U1 DQMB5 R DQ[40:47] 8 DQM DQ[0:7] R = 10 RC = 10 C = 10 pF VDD DQMB2 R DQ[16:23] 8 DQM DQ[0:7] U2 DQMB6 R DQ[48:55] 8 DQM DQ[0:7] VSS UB2 U[0:3], UB[0:3] Two 0.22 F and one 0.01 F per SDRAM U[0:3], UB[0:3] UB1 C C
CS
CS
CS
CS
DQMB3 DQ[24:31] R 8
DQM DQ[0:7]
U3
DQMB7 R DQ[56:63] 8
DQM DQ[0:7]
UB3
RAS CAS WE CKE0 A[0:13]
RAS: SDRAM U[0:3], UB[0:3] CAS: SDRAM U[0:3], UB[0:3] WE: SDRAM U[0:3], UB[0:3] CKE: SDRAM U[0:3], UB[0:3] A[0:13]: SDRAM U[0:3], UB[0:3] LEGEND: CS = SPD =
SPD EEPROM SCL A0 A1 VSS Chip select Serial Presence Detect A2 SDA
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TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
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MIN 3 2 2 0 NOM MAX 3.6 UNIT V V V V V VDD VSS Supply voltage Supply voltage 3.3 0 VIH VIH-SPD VIL TA High-level input voltage Low-level input voltage Ambient temperature High-level input voltage for SPD device VDD + 0.3 5.5 0.8 70 -0.3 C
capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz (see Note 2)
PARAMETER TM8SK64JPU MIN MAX 5 5 5 7 5 5 9 7 UNIT pF pF pF pF pF pF pF pF
Ci(CK) Ci(AC) Co
Input capacitance, CK input
Input capacitance, address and control inputs: A0 - A13, RAS, CAS, WE Input capacitance, CKE input Output capacitance
Ci(CKE)
Ci(DQMBx) Ci(Sx) Ci/o(SDA)
Input capacitance, DQMBx input Input capacitance, Sx input
Input/output capacitance, SDA input
Ci(SPD) Input capacitance, SPD inputs (except SDA) Specifications in this table represent a single SDRAM device. NOTE 2: VDD = 3.3 V 0.3 V. Bias on pins under test is 0 V.
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TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
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PARAMETER TEST CONDITIONS '8SK64JPU-10 MIN 2.4 MAX UNIT V VOH VOL II High-level output voltage Low-level output voltage Input current (leakage) IOH = - 2 mA IOL = 2 mA 0.4AAA V A A 0 V < VI < VDD + 0.3 V, All other pins = 0 V to VDD 0 V < VO < VDD +0.3 V, Output disabled Burst length = 1, tRC tRC MIN IOH/IOL = 0 mA, (see Notes 4, 5, and 6)
electrical characteristics over recommended ranges of supply voltage and ambient temperature (unless otherwise noted) (see Note 3)
"10 "10
IO
Output current (leakage)
CAS latency = 2 CAS latency = 3
105 135 2 2 3
mA mA mA mA mA mA mA mA mA mA mA
ICC1
Operating current
ICC2P ICC2PS
Precharge standby current in power down mode power-down
CKE VIL MAX, tCK = 15 ns (see Note 7) CKE VIH MIN, tCK = 15 ns (see Note 7)
CKE and CK VIL MAX, tCK = (see Note 8)
ICC2N ICC2NS ICC3P
Precharge standby current in non-power-down g y mode
40 15 15 70 20
tCK = infinite (see Note 8) CKE VIL MAX, tCK = 15 ns (see Notes 4 and 7) CKE and CK VIL MAX, tCK = (see Notes 4 and 8)
ICC3PS ICC3N
Active standby current in power-down mode
CKE VIH MIN, tCK = 15 ns (see Notes 4 and 7) CKE VIH MIN, CK VIL MAX, tCK = (see Notes 4 and 8)
ICC3NS
Active standby current in non-power-down mode
ICC4
Burst current
Page burst, IOH/IOL = 0 mA CAS latency = 2 All banks activated, , nCCD = one cycle CAS latency = 3 (see Notes 9 and 10) tRC tRC MIN (see Notes 5 and 8) CAS latency = 2 CAS latency = 3
130
185AAA mA mA mA
ICC5
Auto refresh current Auto-refresh
1 65 1 95
ICC6 Self-refresh current CKE VIL MAX 2 mA Specifications in this table represent a single SDRAM device. NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid. 4. Only one bank is activated. 5. tRC MIN 6. Control and address inputs change state twice during tRC. 7. Control and address inputs change state once every 30 ns. 8. Control and address inputs do not change state (stable). 9. Control and address inputs change once every cycle. 10. Continuous burst access, nCCD = 1 cycle
6
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TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
ac timing requirements
'8SK64JPU-10 MIN tCK2 tCK3 tCH tCL tAC2 tAC3 tOH tLZ tHZ tIS tIH tCESP tRAS tRC tRCD tRP tRRD tRSA tAPR tAPW tWR Cycle time, CK Cycle time, CK Pulse duration, CK high Pulse duraction, CK low Access time, CK high to data out (see Note 11) Access time, CK high to data out (see Note 11) Hold time, CK high to data out Delay time, CK high to DQ in low-impedance state (see Note 12) Delay time, CK high to DQ in high-impedance state (see Note 13) Setup time, address, control, and data input Hold time, address, control, and data input time address control Power down/self-refresh exit time Delay time, ACTV command to DEAC or DCAB command Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR command Delay time ACTV command to READ, READ-P, WRT, or WRT-P command (see Note 14) Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command Delay time, ACTV command in one bank to ACTV command in the other bank Delay time, MRS command to ACTV, MRS, REFR, or SLFR command Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command Delay time, final data in of WRT operation to DEAC or DCAB command 3 1 10 50 80 30 30 20 20 tRP - (CL-1)* tCK tRP + 1 tCK 10 100000 CAS latency = 2 CAS latency = 3 3 1 8 CAS latency = 2 CAS latency = 3 15 10 3 3 9 8 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tT Transition time 1 5 ms All references are made to the rising transition of CK unless otherwise noted. Specifications in this table represent a single SDRAM device. NOTES: 11. tAC is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out tAC is referenced from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output reference level 1.4 V. 12. tLZ is measured from the rising transition of CK that is read latency (one cycle after the READ command). 13. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels. 14. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
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TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
clock timing requirements
'8SK64JPU-10 MIN tREF nCCD nCDD nCLE nCWL nDID nDOD nHZP2 nHZP3 Refresh interval Delay time, READ or WRT command to an interrupting command time Delay time, CS low or high to input enabled or inhibited Delay time, CKE high or low to CLK enabled or disabled Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P Delay time, ENBL or MASK command to enabled or masked data in Delay time, ENBL or MASK command to enabled or masked data out Delay time, DEAC or DCAB, command to DQ in high-impedance state Delay time, DEAC or DCAB, command to DQ in high-impedance state CAS latency = 2 CAS latency = 3 1 0 1 1 0 2 0 2 2 3 1 MAX 64 UNIT ms cycles cycles cycles cycles cycles cycles cycles cycles
nWCD Delay time, WRT command to first data in 0 0 cycles All references are made to the rising transition of CK unless otherwise noted. A CK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated by CKE (those CK cycles occurring during the time when CKE is asserted low).
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TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing parameters (see Table 1). Only the first 128 bytes are programmed by Texas Instruments, while the remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock (SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD standards. See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for further details. Table 1 lists SPD contents as follows: Table 1. Serial Presence Detect Data
BYTE NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DESCRIPTION OF FUNCTION Defines number of bytes written into serial memory during module manufacturing Total number of bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM, . . .) Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at maximum supported CAS latency (CL), CL = X SDRAM access from clock at CL = X SODIMM configuration type (non-parity, parity, error correcting code [ECC]) Refresh rate / type SDRAM width, primary DRAM Error-checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CAS latencies supported CS latency Write latency SDRAM module attributes LVTTL tCK = 10 ns tAC =8 ns Non-Parity 15.6 s/ self-refresh x8 N/A 1 CK cycle 1, 2, 4, and 8 4 banks 2, 3 0 0 Non-buffered/ Non-registered VDD tolerance = ("10%) Burst read / write, precharge all, auto precharge tCK = 15 ns TM8SK64JPU-10 ITEM 128 bytes 256 bytes SDRAM 12 9 1 bank 64 bits DATA 80h 08h 04h 0Ch 09h 01h 40h 00h 01h A0h 80h 00h 80h 08h 00h 01h 0Fh 04h 06h 01h 01h 00h
22
SDRAM device attributes: general
0Eh
23
Minimum clock cycle time at CL = X - 1
F0h
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TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
serial presence detect (continued)
Table 1. Serial Presence Detect Data (Continued)
BYTE NO. 24 25 26 27 28 29 30 31 32 33 34 35 36 - 61 62 63 64 - 71 72 73 - 90 91 92 93 - 94 95 - 98 99 - 125 126 - 127 128-166 167-255 DESCRIPTION OF FUNCTION Maximum data-access time from clock at CL = X - 1 Minimum clock cycle time at CL = X - 2 Maximum data-access time from clock at CL = X - 2 Minimum row precharge time Minimum row-active to row-active delay Minimum RAS-to-CAS delay Minimum RAS pulse width Density of each bank on module Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset features (may be used in the future) SPD revision Checksum for byte 0 - 62 Manufacturer's JEDEC ID code per JEP - 106E Manufacturing location Manufacturer's part number Die revision code PCB revision code Manufacturing date Assembly serial number Manufacturer specific data Vendor specific data System integrator's specific data Open Rev. 2 73 97 TBD TBD TBD TBD TBD TBD TBD TBD TBD 02h 49h 9700...00h TM8SK64JPU-10 ITEM tAC = 9 ns N/A N/A tRP = 30 ns tRRD = 20 ns tRCD = 30 ns tRAS =50 ns 64M Bytes tIS = 3 ns tIH = 1 ns tIS = 3 ns tIH = 1 ns DATA 90h 00h 00h 1Eh 14h 1Eh 32h 10h 30h 10h 30h 10h
TBD indicates values are determined at manufacturing time and are module dependent. These TBD values are determined and programmed by the customer (optional).
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TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
device symbolization (TM8SK64JPU)
TM8SK64JPU
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTE A: Location of symbolization may vary.
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11
TM8SK64JPU 8388608 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE -- SODIMM
SMMS690B - AUGUST 1997 - REVISED FEBRUARY 1998
MECHANICAL DATA
BDQ (R-SODIMM-N144)
2.665 (67,69) 2.655 (67,44) Notch 0.157 (4,00) x 0.079 (2,00) Deep 2 Places Notch 0.060 (1,52) x 0.158 (4,01) Deep 0.044 (1,12) 0.036 (0,91)
SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
0.024 (0,61) TYP 0.098 (2,49) 0.196 (4,98)
0.031 (0,79)
0.010 (0,25) MAX 0.788 (20,00) TYP 1.130 (28,70) 1.120 (28,45) 0.157 (4,00) 0.126 (3,20) 0.095 (2,41) MAX 0.150 (3,81) MAX (For Double-Sided Module Only) 4088188/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MO-190
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Price & Availability of SMMS690B

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