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TM497MBK36A, TM497MBK36Q 4194304 BY 36-BIT DYNAMIC RAM MODULE
SMMS446C - DECEMBER 1992 - REVISED JUNE 1995
D D D D D D D D D
Organization . . . 4 194 304 x 36 Single 5-V Power Supply (10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Sockets Utilizes Eight 16-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages and Four 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period 32 ms (2048 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible Common CAS Control for Nine Common Data-In and Data-Out Lines in Four Blocks Separate RAS Control for Eighteen Data-In and Data-Out Lines in Two Blocks 3-State Output
D
Performance Ranges:
ACCESS TIME tRAC (MAX) '497MBK36A-60 '497MBK36A-70 '497MBK36A-80 60 ns 70 ns 80 ns ACCESS ACCESS READ TIME TIME OR tCAC tAA WRITE CYCLE (MAX) (MAX) (MIN) 15 ns 18 ns 20 ns 30 ns 35 ns 40 ns 110 ns 130 ns 150 ns
D D D D D
Low Power Dissipation Operating Free-Air Temperature Range 0C to 70C Presence Detect Gold-Tabbed Version Available: TM497MBK36A Tin-Lead (Solder) Tabbed Version Available: TM497MBK36Q
description
The TM497MBK36A is a 16M-byte dynamic random-access memory (DRAM) organized as four times 4 194 304 x 9 (bit 9 is generally used for parity) in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight TMS417400DJ, 4 194 304 x 4-bit DRAMs, each in 24/26-lead plastic SOJ packages, and four TMS44100DJ, 4 194 304 x 1-bit DRAMs, each in 20 / 26-lead plastic SOJ packages mounted on a substrate with decoupling capacitors. Each TMS417400DJ and TMS44100DJ is described in the TMS417400 and TMS44100 data sheets (respectively). The TM497MBK36A is available in a double-sided BK leadless module for use with sockets. The TM497MBK36A features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation from 0C to 70C.
operation
The TM497MBK36A operates as eight TMS417400DJs and four TMS44100DJs connected as shown in the functional block diagram and Table 1. Refer to the TMS417400 and TMS44100 data sheets for details of operation. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q. refresh The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with RAS in order to retain data. Address line A10 must be used as most significant refresh address line (lowest frequency) to assure correct refresh for both TMS417400 and TMS44100. A0 - A9 address lines must be refreshed every 16 ms as required by the TMS44100 DRAM. CAS can remain high during the refresh sequence to conserve power. power up To achieve proper operation, an initial pause of 200 s followed by a minimum of eight initialization cycles is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh [RAS-only or CAS-before-RAS ( CBR)] cycle.
A0 - A9 address lines must be refreshed every 16 ms. Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1995, Texas Instruments Incorporated
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TM497MBK36A, TM497MBK36Q 4194304 BY 36-BIT DYNAMIC RAM MODULE
SMMS446C - DECEMBER 1992 - REVISED JUNE 1995
BK SINGLE-IN-LINE PACKAGE ( TOP VIEW )
(SIDE VIEW )
VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 NC VCC A8 A9 NC RAS2 DQ26 DQ8 DQ17 DQ35 VSS CAS0 CAS2 CAS3 CAS1 RAS0 NC NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PIN NOMENCLATURE A0 - A10 CAS0 - CAS3 DQ0 - DQ7, DQ9 - DQ16, DQ18 - DQ25, DQ27 - DQ34 DQ8, DQ17, DQ26, DQ35 NC PD1 - PD4 RAS0, RAS2 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out Parity No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable
PRESENCE DETECT SIGNAL (PIN) 80 ns TM497MBK36A 70 ns 60 ns PD1 (67) VSS VSS VSS PD2 (68) NC NC NC PD3 (69) NC VSS NC PD4 (70) VSS NC NC
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TM497MBK36A, TM497MBK36Q 4194304 BY 36-BIT DYNAMIC RAM MODULE
SMMS446C - DECEMBER 1992 - REVISED JUNE 1995
Table 1. Connection Table
DATA BLOCK DQ0 - DQ7 DQ8 DQ9 - DQ16 DQ17 DQ18 - DQ25 DQ26 DQ27 - DQ34 DQ35 RASx RAS0 RAS0 RAS2 RAS2 CASx CAS0 CAS1 CAS2 CAS3
single-in-line memory module and components
PC substrate: 1,27 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM497MBK36A: Nickel plate and gold plate over copper Contact area for TM497MBK36Q: Nickel plate and tin-lead over copper
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SMMS446C - DECEMBER 1992 - REVISED JUNE 1995
TM497MBK36A, TM497MBK36Q 4194304 BY 32-BIT DYNAMIC RAM MODULE
functional block diagram
11 RAS2
4
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Template Release Date: 7-11-94
A0 - A10 RAS0 W CAS0
CAS1 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
CAS2 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
CAS3 11 4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4
DQ0 - DQ3
DQ9 - DQ12
DQ18 - DQ21
DQ27 - DQ30
11
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
11
DQ4 - DQ7
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
11
DQ13 - DQ16
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
11
DQ22 - DQ25
4M x 4 A0 - A10 RAS W CAS OE DQ1 - DQ4 4M x 1 A0 - A10 RAS W CAS D Q
DQ31 - DQ34
11
11
11
11
DQ8
DQ17
DQ26
DQ35
TM497MBK36A, TM497MBK36Q 4194304 BY 36-BIT DYNAMIC RAM MODULE
SMMS446C - DECEMBER 1992 - REVISED JUNE 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN VCC VIH VIL TA Supply voltage High-level input voltage Low-level input voltage (see Note 2) Operating free-air temperature 4.5 2.4 -1 0 NOM 5 MAX 5.5 6.5 0.8 70 UNIT V V V C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current (see Note 3) TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC VCC = 5.5 V, CAS high VCC = 5.5 V, VO = 0 V to VCC, Minimum cycle '497MBK36A-60 MIN 2.4 0.4 120 10 1300 MAX '497MBK36A-70 MIN 2.4 0.4 120 10 1160 MAX '497MBK36A-80 MIN 2.4 0.4 120 10 1040 MAX UNIT V V A A mA
ICC2
Standby current
VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) VCC = 5.5 V, RAS low, tPC = MIN CAS cycling
24
24
24
mA
12
12
12
mA
ICC3
Average refresh current (RAS only or CBR) (see Note 3) Average page current (see Note 4)
1300
1160
1040
mA
ICC4
920
800
680
mA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH
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TM497MBK36A, TM497MBK36Q 4194304 BY 36-BIT DYNAMIC RAM MODULE
SMMS446C - DECEMBER 1992 - REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5)
PARAMETER Ci(A) Ci(C) Ci(R) Ci(W) Co Input capacitance, address inputs Input capacitance, CAS inputs Input capacitance, RAS inputs Input capacitance, write-enable input Output capacitance DQ pins Parity pins MIN MAX 60 21 42 84 7 12 UNIT pF pF pF pF pF
NOTE 5: VCC = 5 V 0.5 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER tAA tCAC tCPA tRAC tCLZ tOH Access time from column address Access time from CAS low Access time from column precharge Access time from RAS low CAS to output in low-impedance state Output disable time, start of CAS high 0 3 0 15 '497MBK36A-60 MIN MAX 30 15 35 60 0 3 0 18 '497MBK36A-70 MIN MAX 35 18 40 70 0 3 0 20 '497MBK36A-80 MIN MAX 40 20 45 80 UNIT ns ns ns ns ns ns ns
tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air temperature
'497MBK36A-60 MIN tRC tPC tRASP tRAS tCAS tCP tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tWRP Cycle time, random read or write (see Note 7) Cycle time, page-mode read or write (see Notes 7 and 8) Pulse duration, page-mode, RAS low Pulse duration, nonpage-mode, RAS low Pulse duration, CAS low Pulse duration, CAS high Pulse duration, RAS high (precharge) Pulse duration, W low Setup time, column address before CAS low Setup time, row address before RAS low Setup time, data before CAS low Setup time, W high before CAS low Setup time, W low before CAS high Setup time, W low before RAS high Setup time, W low before CAS low Setup time, W high before RAS low (CBR refresh only) 110 40 60 100 000 60 15 10 40 10 0 0 0 0 15 15 0 10 10 000 10 000 MAX '497MBK36A-70 MIN 130 45 70 70 18 10 50 10 0 0 0 0 18 18 0 10 100 000 10 000 10 000 MAX '497MBK36A-80 MIN 150 50 80 80 20 10 60 10 0 0 0 0 20 20 0 10 100 000 10 000 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be tCP.
6
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TM497MBK36A, TM497MBK36Q 4194304 BY 36-BIT DYNAMIC RAM MODULE
SMMS446C - DECEMBER 1992 - REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
'497MBK36A-60 MIN tCAH tRHCP tDH tRAH tRCH tRRH tWCH tWRH tCHR tCRP tCSH tCSR tRAD tRAL tCAL tRCD tRPC tRSH tREF tT Hold time, column address after CAS low Hold time, RAS high from CAS precharge Hold time, data after CAS low Hold time, row address after RAS low Hold time, W high after CAS high (see Note 9) Hold time, W high after RAS high (see Note 9) Hold time, W low after CAS low Hold time, W high after RAS low (CBR refresh only) Delay time, RAS low to CAS high (CBR refresh only) Delay time, CAS high to RAS low Delay time, RAS low to CAS high Delay time, CAS low to RAS low (CBR refresh only) Delay time, RAS low to column address (see Note 10) Delay time, column address to RAS high Delay time, column address to CAS high Delay time, RAS low to CAS low (see Note 10) Delay time, RAS high to CAS low Delay time, CAS low to RAS high Refresh time interval Transition time 3 15 35 15 10 0 0 10 10 10 5 60 5 15 30 30 20 0 15 32 30 3 45 30 MAX '497MBK36A-70 MIN 15 40 15 10 0 0 15 10 10 5 70 5 15 35 35 20 0 18 32 30 3 52 35 MAX '497MBK36A-80 MIN 15 45 15 10 0 0 15 10 10 5 80 5 15 40 40 20 0 20 32 30 60 40 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
NOTES: 9. Either tRRH or tRCH must be satisfied for a read cycle. 10. The maximum value is specified only to assure access time.
device symbolization
TM497MBK36A
-SS
YYMMT
YY MM T -SS
= = = =
Year Code Month Code Assembly Site Code Speed Code
NOTE: Location of symbolization may vary.
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TM497MBK36A, TM497MBK36Q 4194304 BY 36-BIT DYNAMIC RAM MODULE
SMMS446C - DECEMBER 1992 - REVISED JUNE 1995
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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