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TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
D D D
Organization . . . 1 048 576 Words by 16 Bits Single 5-V Power Supply Performance Ranges:
ACCESS ACCESS ACCESS READ OR TIME TIME TIME EDO tRAC tCAC tAA CYCLE MAX MAX MAX MIN '41x169/P-60 60 ns 15 ns 30 ns 25 ns '41x169/P-70 70 ns 18 ns 35 ns 30 ns '41x169/P-80 80 ns 20 ns 40 ns 35 ns
DZ PACKAGE ( TOP VIEW )
D D D
D D D D
Extended-Data-Out (EDO) Operation xCAS-Before-RAS ( xCBR) Refresh RAS-Only Refresh - 1 024-Cycle Refresh in 16 ms (TMS418169) - 4 096-Cycle Refresh in 64 ms (TMS416169) 3-State Unlatched Output High-Reliability Plastic 42-Lead (DZ Suffix) 400-Mil-Wide Surface-Mount (SOJ) Package Operating Free-Air Temperature Range 0C to 70C Texas Instruments Enhanced Performance Implanted CMOS (EPICTM) Process
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC W RAS A11 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
description
The TMS418169 and the TMS416169 are high-speed, 16 777 216-bit dynamic random-access memories (DRAMs) organized as 1 048 576 words of 16 bits each. Both devices employ state-of-the-art EPIC technology for high performance, reliability, and low power at low cost. These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
A10 and A11 are NC for TMS418169.
PIN NOMENCLATURE A0 - A11 DQ0 - DQ15 LCAS UCAS NC OE RAS VCC VSS W Address Inputs Data In / Data Out Lower Column-Address Strobe Upper Column-Address Strobe No Internal Connection Output Enable Row-Address Strobe 5-V Supply Ground Write Enable
The TMS416169 and TMS418169 are offered in a 42-lead plastic surface-mount SOJ (DZ suffix) package. The package is characterized for operation from 0C to 70C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1996, Texas Instruments Incorporated
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TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
logic symbol
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 17 18 19 20 23 24 25 26 27 28 16 15 RAM 1M x 16 20D8/21D0
A
0 1 048 575
RAS
14
LCAS 31
20D15/21D7 20D16 20D17 20D18 20D19 C20[ROW] G23/[REFRESH ROW] 24[PWR DWN] C21 G24 & 23C22 31 C21 G34 & 31 Z31
UCAS 30
23C32
W 13 OE 29 DQ0 2 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 3 4 5 7 8 9 10 33 34 35 36 38 39 40 41
23,21D 25 A,22D 26,27
24,25EN27 34,25EN37
A, Z26
A,32D 36,37
A, Z36
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. The pin numbers shown correspond to the DZ package. A10 and A11 are NC for TMS418169.
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TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
functional block diagram (TMS416169)
RAS UCAS LCAS W OE
Timing and Control
A0 A1 Column Address Buffers A7
8
Column Decode Sense Amplifiers 256K Array 256K Array R o w D e c o d e 256K Array 12 256K Array 256K Array 256K Array 32 32 I/O Buffers 16 of 32 Selection DataIn Reg. DataOut Reg. 16 32
32 Row Address Buffers A8 - A11 4 12
16
DQ0 - DQ15
functional block diagram (TMS418169)
RAS UCAS LCAS W OE
Timing and Control
A0 A1 Column Address Buffers A9
10
Column Decode Sense Amplifiers 256K Array 256K Array R o w D e c o d e 256K Array 10 256K Array 256K Array 256K Array 32 32 I/O Buffers 16 of 32 Selection DataIn Reg. DataOut Reg. 16 32
Row Address Buffers
32 10
16
DQ0 - DQ15
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TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
operation
dual CAS Two CAS pins (LCAS and UCAS) are provided to give independent control of the 16 data-I/O pins (DQ0- DQ15), with LCAS corresponding to DQ0 - DQ7 and UCAS corresponding to DQ8 - DQ15. For read or write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its corresponding DQx pin with data associated with the column address latched on the first falling xCAS edge. All address setup and hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS low to valid data out (see parameter tCAC) is measured from each individual xCAS to its corresponding DQx pin. In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time (see parameter tCP) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle. Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH. During tCLCH, at least one xCAS must be brought low before the other xCAS is taken high. For early-write cycles, the data is latched on the first xCAS falling edge. Data is written only into the DQs that have the corresponding xCAS low. Each xCAS must meet tCAS minimum in order to ensure writing into the storage cell. To latch a new address and new data, all xCAS pins must be high and meet tCP . extended data out Extended data out (EDO) allows for data-output rates of up to 40 MHz for 60-ns devices. When keeping the same row address while selecting random column addresses, the time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS low time (tRASP). EDO does not enter the DQs into the high-impedance state with the rising edge of xCAS. The output remains valid for the system to latch the data. After xCAS goes high, the DRAM is decoding the next address. OE and W can be used to control the output impedance. Descriptions of OE and W further explain EDO operation benefit. address: A0 - A11 ( TMS416169) and A0 - A9 ( TMS418169) Twenty address bits are required to decode one of the 1 048 576 storage cell locations. For the TMS416169, 12 row-address bits are set up on A0 through A11 and latched onto the chip by RAS. Eight column-address bits are set up on A0 through A7 and latched on the chip by the first xCAS. For the TMS418169, 10 row-address bits are set up on A0 - A9 and latched on the chip by RAS. Ten column-address bits are set up on A0 - A9 and latched on the chip by the first xCAS. All addresses must be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip-enable in that it activates the sense amplifiers as well as the row decoder. xCAS is used as a chip-select, activating its corresponding output buffer and latching the address bits into the column-address buffers. write enable ( W) The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects the write mode. The data input is disabled when the read mode is selected. When W goes low prior to xCAS (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation independent of the state of OE. This permits early-write operation to be completed with OE grounded. If W goes low in an extended-data-out read cycle, the DQs go into the high-impedance state as long as xCAS is high. data in (DQ0 - DQ15) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a
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data in (DQ0 - DQ15) (continued) delayed-write or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the output buffers to the high-impedance state prior to impressing data on the I/O lines. data out (DQ0 - DQ15) Data out is the same polarity as data-in. The output is in the high-impedance (floating) state until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC (which begins with the negative transition of xCAS) as long as tRAC and tAA are satisfied. output enable (OE) OE controls the impedance of the output buffers. While xCAS and RAS are low and W is high, OE can be brought low or high and the DQs switch from valid data to high impedance. There are two methods for placing the DQs into the high-impedance state and keeping them in that state during xCAS high time using OE. The first method is to switch OE high before xCAS goes high and keep OE high for tCHO past the CAS transition. This disables the DQs and they remain in the high-impedance state, regardless of OE, until xCAS falls again. The second method is to have OE low as xCAS transitions high. Then OE can pulse high for a minimum of tOEP anytime during CAS high time disabling the DQs regardless of further transitions on OE until CAS falls again. RAS-only refresh
TMS416169
A refresh operation must be performed at least once every 64 ms to retain data. This is achieved by strobing each of the 4 096 rows (A0 - A11). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh.
TMS418169
A refresh operation must be performed at least once every 16 ms to retain data. This is achieved by strobing each of the 1 024 rows (A0 - A9). A normal read or write cycle refreshes all bits in each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. hidden refresh Hidden refresh can be performed while maintaining valid data at the output pins. This is accomplished by holding xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored and the refresh address is generated internally. xCAS-before-RAS (xCBR) refresh xCBR refresh is achieved by bringing at least one xCAS low earlier than RAS (see parameter tCSR) and holding it low after RAS falls (see parameter tCHR). For successive xCBR refresh cycles, xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated internally. power-up To achieve proper device operation, an initial pause of 200 s followed by a minimum of eight initialization cycles is required after power-up to the full VCC level. These eight initialization cycles must include at least one refresh (RAS-only or xCBR) cycle.
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SMKS886C - MAY1995 - REVISED MARCH 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
'41x169 MIN VCC VSS VIH VIL Supply voltage Supply voltage High-level input voltage Low-level input voltage (see Note 2) 2.4 -1 4.5 NOM 5 0 6.5 0.8 MAX 5.5 UNIT V V V V
TA Operating free-air temperature 0 70 C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
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TMS416169 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other inputs = 0 V to VCC VCC = 5.5 V, xCAS high VO = 0 V to VCC, '416169 - 60 MIN 2.4 0.4 10 10 90 2 MAX '416169 - 70 MIN 2.4 0.4 10 10 80 2 MAX '416169 - 80 MIN 2.4 0.4 10 10 70 2 MAX UNIT V V A A mA mA
ICC2
Standby current
VCC = 5.5 V, Minimum cycle VIH = 2.4 V ( TTL), After 1 memory cycle, RAS and xCAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and xCAS high VCC = 5.5 V, Minimum cycle, RAS cycling, xCAS high (RAS only), RAS low after xCAS low (CBR) VCC = 5.5 V, RAS low, tHPC = MIN, xCAS cycling
1
1
1
mA
ICC3
Average refresh current (RAS-only refresh or CBR)
90
80
70
mA
ICC4
Average EDO current
100
90
80
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RAS = VIL Measured with a maximum of one address change while xCAS = VIH
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TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
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TMS418169 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
PARAMETER VOH VOL II IO ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) Read- or write-cycle current TEST CONDITIONS IOH = - 5 mA IOL = 4.2 mA VCC = 5.5 V, VI = 0 V to 6.5 V, All other inputs = 0 V to VCC VCC = 5.5 V, xCAS high VCC = 5.5 V, VO = 0 V to VCC, '418169 - 60 MIN 2.4 0.4 10 10 190 MAX '418169 - 70 MIN 2.4 0.4 10 10 180 MAX '418169 - 80 MIN 2.4 0.4 10 10 170 MAX UNIT V V A A mA
Minimum cycle
ICC2
Standby current
VIH = 2.4 V ( TTL), After 1 memory cycle, RAS and xCAS high VIH = VCC - 0.2 V (CMOS), After 1 memory cycle, RAS and xCAS high VCC = 5.5 V, Minimum cycle, xCAS high (RAS only), RAS cycling, RAS low after xCAS low (CBR) VCC = 5.5 V, RAS low, tHPC = MIN, xCAS cycling
2
2
2
mA
1
1
1
mA
ICC3 ICC4
Average refresh current (RAS-only refresh or CBR) Average EDO current
190
180
170
mA
100
90
80
mA
For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while RAS = VIL Measured with a maximum of one address change while xCAS = VIH
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capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3)
PARAMETER Ci(A) Ci(OE) Ci(RC) Ci(W) Input capacitance, A0 - A11 Input capacitance, OE Input capacitance, xCAS and RAS Input capacitance, W MIN MAX 5 7 7 7 7 UNIT pF pF pF pF pF
CO Output capacitance A10 and A11 are NC for TMS418169. NOTE 3: VCC = 5 V 0.5 V or 3.3 V 0.3 V, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 4)
PARAMETER tAA tCAC tCPA tRAC tOEA tCLZ tOEZ tREZ tCEZ tWEZ Access time from column address Access time from CAS Access time from CAS precharge Access time from RAS Access time from OE Delay time, CAS to output in the low-impedance state Output buffer turn off delay from OE (see Note 5) Output buffer turn off delay from RAS (see Note 5) Output buffer turn off delay from CAS (see Note 5) Output buffer turn off delay from W (see Note 5) 0 3 3 3 3 15 15 15 15 '41x169 - 60 MIN MAX 30 15 35 60 15 0 3 3 3 3 18 18 18 18 '41x169 - 70 MIN MAX 35 18 40 70 18 0 3 3 3 3 20 20 20 20 '41x169 - 80 MIN MAX 40 20 45 80 20 UNIT ns ns ns ns ns ns ns ns ns ns
NOTES: 4. With ac parameters, it is assumed tT = 5 ns. 5. Maximum tREZ , tCEZ , tWEZ, and tOEZ are specified when the output is no longer driven.
EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4)
'41x169 - 60 MIN tHPC tPRWC tCSH tCHO tDOH tCAS tWPE tOCH tCP tOEP Cycle time, EDO page-mode read or write Cycle time, EDO read-write Delay time, RAS active to CAS precharge Hold time, OE from CAS Hold time, output from CAS active Pulse duration, CAS active Pulse duration, W (output disable only) Setup time, OE before CAS Pulse duration, CAS precharge Precharge time, OE (output disable only) 25 80 50 10 3 10 5 10 5 5 10 000 MAX '41x169 - 70 MIN 30 90 55 10 3 12 5 10 5 5 10 000 MAX '41x169 - 80 MIN 35 100 60 10 3 15 5 10 5 5 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns
NOTE 4: With ac parameters, it is assumed tT = 5 ns.
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timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4)
'41x169 - 60 MIN tRC tWC tRWC tRASP tRAS tRP tWP tASC tASR tDS tRCS tCWL tRWL tWCS tCSR tCAH tDH tRAH tRCH tRRH tWCH tCLCH tRHCP tOEH tROH tCHR tAWD tCRP tCWD tOED tRAD tRAL tCAL Cycle time, read Cycle time, write Cycle time, read-write Pulse duration, RAS active, page mode (see Note 6) Pulse duration, RAS active, nonpage mode (see Note 6) Pulse duration, RAS precharge Pulse duration, write command Setup time, column address Setup time, row address Setup time, data in (see Note 7) Setup time, read command Setup time, write command before CAS precharge Setup time, write command before RAS precharge Setup time, write command before CAS active (early-write only) Setup time, CAS referenced to RAS (CBR refresh only) Hold time, column address Hold time, data in (see Note 7) Hold time, row address Hold time, read command referenced to CAS (see Note 8) Hold time, read command referenced to RAS (see Note 8) Hold time, write command during CAS active (early-write only) Hold time, CAS low to CAS high Hold time, RAS active from CAS precharge Hold time, OE command Hold time, RAS referenced to OE Hold time, CAS referenced to RAS (CBR refresh only) Delay time, column address to write command (read-write only) Delay time, CAS precharge to RAS Delay time, CAS to write command (read-write only) Delay time, OE to data in Delay time, RAS to column address (see Note 9) Delay time, column address to RAS precharge Delay time, column address to CAS precharge 110 110 150 60 100 000 60 40 10 0 0 0 0 10 10 0 5 10 10 10 0 0 10 5 35 15 10 10 55 5 40 15 15 30 20 20 45 30 10 000 MAX '41x169 - 70 MIN 130 130 175 70 100 000 70 50 10 0 0 0 0 12 12 0 5 12 12 10 0 0 12 5 40 18 10 10 63 5 46 18 15 35 25 20 52 35 10 000 MAX '41x169 - 80 MIN 150 150 200 80 100 000 80 60 10 0 0 0 0 15 15 0 5 15 15 10 0 0 15 5 45 20 10 10 70 5 50 20 15 40 30 20 60 40 10 000 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRCD Delay time, RAS to CAS (see Note 9) NOTES: 4. With ac parameters, it is assumed tT = 5 ns. 6. In a read-write cycle, tRWD and tRWL must be observed. 7. Referenced to the later of xCAS or W in write operations 8. Either tRRH or tRCH must be satisfied for a read cycle. 9. The maximum value is specified only to ensure access time.
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timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)
'41x169 - 60 MIN tRPC tRSH tRWD tCPW tREF tT Delay time, RAS precharge to CAS Delay time, CAS active to RAS precharge Delay time, RAS to write command (read-write only) Delay time, CAS precharge to write command (read-write only) Refresh time interval Transition time '416169 '418169 2 0 10 85 60 64 16 30 2 MAX '41x169 - 70 MIN 0 12 98 68 64 16 30 2 MAX '41x169 - 80 MIN 0 15 110 75 64 16 30 MAX UNIT ns ns ns ns ms ms ns
PARAMETER MEASUREMENT INFORMATION
1.31 V 5V
218 Output Under Test CL = 100 pF (see Note A)
828
Output Under Test CL = 100 pF (see Note A)
295
(a) LOAD CIRCUIT NOTE A: CL includes probe and fixture capacitance.
(b) ALTERNATE LOAD CIRCUIT
Figure 1. Load Circuits for Timing Parameters
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PARAMETER MEASUREMENT INFORMATION
tRC RAS tT UCAS tRCD tCAS tCLCH (see Note A) LCAS tCSH tRAD tRAH tASC tASR Address Row Column tCAL tRAL Don't Care tRRH tRCH tRSH tCRP tRAS tRP
tCP
tCAH tRCS Don't Care tCAC (see Note B) tAA
W
Don't Care
tREZ tCLZ DQ0 - DQ15 See Note C tRAC tROH OE NOTES: A. B. C. D. Don't Care tOEA Don't Care tOEZ Valid Data Out
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. tCAC is measured from xCAS to its corresponding DQx. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. xCAS order is arbitrary.
Figure 2. Read-Cycle Timing
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TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
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PARAMETER MEASUREMENT INFORMATION
tWC RAS tT UCAS tRCD tCAS tRAS tRP
tCLCH (see Note A) LCAS tASR tCSH tRAH tASC tCAL Address Row Column tRAL Don't Care tRSH tCRP
tCP
tCAH tRAD tCWL tRWL W Don't Care Don't Care
tWP tDH (see Note B) DQ0 - DQ15 Don't Care Valid Data In tDS (see Note B) tOED OE NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. Referenced to the first xCAS or W, whichever occurs last C. xCAS order is arbitrary. tOEH Don't Care Don't Care
Figure 3. Write-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tWC RAS tT tRCD tCSH UCAS tCAS tRSH tCLCH (see Note A) LCAS tASR tRAH tASC tCAL tRAL Address Row Column tCAH tWCS W tCWL tRWL tWP DQ0 - DQ15 Don't Care Valid Data In tDH tDS OE Don't Care Don't Care tWCH Don't Care tRAD tCP tCRP tRAS tRP
NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. xCAS order is arbitrary.
Figure 4. Early-Write-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tRWC RAS tT UCAS tCSH tCLCH (see Note A) tRSH LCAS tRAD tRAH tASC tASR Address Row Column tCAH tAWD tRCS W Don't Care tCWD tWP Don't Care Don't Care tCWL tRWL tRCD tCAS tRAS tRP
tCRP tCP
tRWD tCLZ See Note B DQ8 - DQ15 tAA tCAC (see Note C) tRAC tOEA OE Don't Care tOED tCAC See Note B DQ0 - DQ7 NOTES: A. B. C. D. Valid Out Valid In Don't Care tOEZ tDS Valid Out Don't Care
tDH
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. tCAC is measured from xCAS to its corresponding DQx. xCAS order is arbitrary.
Figure 5. Read-Modify-Write-Cycle Timing
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SMKS886C - MAY1995 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP RAS tRCD UCAS tRHCP tRSH tCLCH (see Note A) tCSH tCAS tCP LCAS tRAH tASC tCAH Address Row tRAD W Don't Care Column #1 Don't Care Column #2 tASR tCAL tRAL Don't Care tRCH tCAC (see Note B) tAA tCPA (see Note C) tRAC tCLZ DQ8 - DQ15 (See Note D) tAA DQ0 - DQ7 (See Note D) Data #1 Data #2 tOEZ tOEA Data #1 tDOH tRRH Don't Care tHPC tRASP tCRP
tRCS
tREZ
OE NOTES: A. B. C. D. E.
Don't Care
To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. tCAC is measured from xCAS to its corresponding DQx. Access time is tCPA or tAA dependent. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write-timing specifications are not violated. F. xCAS order is arbitrary.
Figure 6. Extended-Data-Out Read-Cycle Timing
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POST OFFICE BOX 1443
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TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP RAS tCSH tCAS xCAS tASR tRAH tASC tCAL tRAL Column #2 Column #3 tRASP
tHPC tRSH
tCP
tCAH
Addr
Row
Column #1
tRAD
tOCH
tCHO tOEP
tOEP OE tOEA tRCS tOEA tCAC W tCLZ tCAC tAA tRAC DQ DATA #1 tOEZ tAA DATA #1 DATA #2 tCPA tDOH
tRRH tRCH
tAA tOEZ tCEZ tREZ tCAC DATA #3
Figure 7. Extended-Data-Out Read-Cycle Timing With OE Control
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17
TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
RAS tCSH tHPC tCP tCAS xCAS tASR tRAH tASC Addr Row Column #1 tCAH tCAL tRAL Column #2 Column #3 tRASP tRP tRSH tCRP
tRAD OE tOEA tRCS tWPE tCAC tRCH tRRH W tCAC tAA tCLZ tRAC DQ DATA #1 DATA #2 DATA #3 tCPA tAA tWEZ tDOH tCPA tAA tCEZ tCAC
Figure 8. Extended-Data-Out Read-Cycle Timing With W Control
18
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP RAS tRASP tRSH UCAS tCLCH (see Note A) tCSH LCAS tASR tASC tRAH Address Row tRAD Column Don't Care Column tCWL tRWL tDS Don't Care tDH DQ8 - DQ15 Valid In tDH DQ0 - DQ7 tOED OE NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write-timing specifications are not violated. C. xCAS order is arbitrary. Valid In Valid In Don't Care Don't Care Don't Care tCAS tCAH tCAL tRAL Don't Care tCP tRHCP tHPC tCRP
tRCD
tCWL tWP tDS
W
Don't Care
Figure 9. Extended-Data-Out Write-Cycle Timing
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19
TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRP RAS tRASP tRSH UCAS tCLCH (see Note A) tCSH LCAS tASR tASC tRAH Address Row tRAD tCWL tWCS tDS W Don't Care tWCH Don't Care Don't Care Column Don't Care Column tCWL tRWL tCAS tCAH tCAL tRAL Don't Care tCP tRHCP tHPC tCRP
tRCD
DQ8 - DQ15
Valid In tDH
Don't Care
DQ0 - DQ7
Valid In
Valid In
Don't Care
OE NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write-timing specifications are not violated. C. xCAS order is arbitrary.
Figure 10. Extended-Data-Out Early Write-Cycle Timing
20
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRASP RAS tRCD UCAS tCSH tPRWC tCAS tCP tCLCH (see Note A) LCAS tASR tASC tRAD Address tRAH Row Column tCWD tAWD tRWD W tCAC tRCS tAA tRAC tCLZ DQ0 - DQ15 Valid Out tOEA tOEZ OE NOTES: A. B. C. D. E. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met. Access time is tCPA- or tAA-dependent. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. xCAS order is arbitrary. A read or write cycle can be intermixed with read-modify-write cycles as long as the read- and write-cycle timing specifications are not violated. F. tCAC is measured from xCAS to its corresponding DQx. Valid In tOEH tOED tAA tDS tDH (see Note C) tCPA (see Note B) Valid Out Valid In tOEH tWP tCAH Column tCWL tCPW tRWL tRSH tCRP tRP
Figure 11. Extended-Data-Out Read-Modify-Write-Cycle Timing
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21
TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC tRAS RAS tCRP tT xCAS Don't Care tASR Address Don't Care Row tRPC tRP
See Note A tRAH Don't Care Row
W
Don't Care
DQ0 - DQ15
Hi-Z
OE NOTE G: All xCAS must be high.
Don't Care
Figure 12. RAS-Only Refresh-Cycle Timing
22
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle tRAS RAS tRP tCAS xCAS tASR tRAH tCHR Memory Cycle tRAS Refresh Cycle tRP
tASC tCAH Row Col tRRH Don't Care tCAC tAA Valid Data tOEA tOEZ tREZ tCEZ Don't Care
Address
tRCS W
tRAC DQ0 - DQ15
OE
Figure 13. Hidden-Refresh-Cycle Timing
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23
TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tRC tRP tRAS
RAS tCSR tT
tRPC xCAS
tCHR
W
Don't Care
Address
Don't Care
OE
Don't Care
DQ0 - DQ15 NOTE A: Any xCAS can be used.
Hi-Z
Figure 14. Automatic (xCBR) Refresh-Cycle Timing
24
POST OFFICE BOX 1443
* HOUSTON, TEXAS 77251-1443
TMS416169, TMS418169 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
SMKS886C - MAY1995 - REVISED MARCH 1996
MECHANICAL DATA
DZ (R-PDSO-J42)
1.080 (27,43) 1.070 (27,18) 42 22
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
0.445 (11,30) 0.435 (11,05) 0,405 (10,29) 0.395 (10,03)
1 0.032 (0,81) 0.026 (0,66)
21
0.106 (2,69) NOM
0.148 (3,76) 0.128 (3,25)
Seating Plane 0.020 (0,51) 0.016 (0,41) 0.050 (1,27) 0.004 (0,10) 0.007 (0,18) M 0.380 (9,65) 0.360 (9,14) 0.008 (0,20) NOM 4040094-6 / C 4/95 NOTES: B. All linear dimensions are in inches (millimeters). C. This drawing is subject to change without notice. D. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
device symbolization (TMS416169 illustrated)
TI -SS Speed ( - 60, - 70, - 80) TMS416169 W B Y DZ Package Code M LLLL P Assembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code Wafer Fab Code
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* HOUSTON, TEXAS 77251-1443
25
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Copyright (c) 1998, Texas Instruments Incorporated

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