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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
D D D D D D D
Single 3-V Operation Low Power Consumption: - Operating Mode . . . 20 mW Typ - Standby Mode . . . 5 mW Typ - Power-Down Mode . . . 2 mW Typ Combined A/D, D/A, and Filters Extended Variable-Frequency Operation - Sample Rates up to 16 kHz - Passband up to 7.2 kHz Electret Microphone Bias Reference Voltage Available Drive a Piezo Speaker Directly Compatible With All Digital Signal Processors (DSPs)
DW OR N PACKAGE (TOP VIEW)
D
D D D
Selectable Between 8-Bit Companded and 13-Bit (Dynamic Range) Linear Conversion: - TLV320AC40 . . . -Law and Linear Modes - TLV320AC41 . . . A-Law and Linear Modes Programmable Volume Control in Linear Mode 300-Hz to 3.6-kHz Passband with Specified Master Clock Designed for Standard 1.152-MHz Master Clock in DECT Standard for Hand-Held Battery-Powered Telephones
PT PACKAGE (TOP VIEW)
PDN EARA EARB EARGS VCC MICMUTE DCLKR DIN FSR EARMUTE
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
MICBIAS MICGS MICIN VMID GND LINSEL TSX/DCLKX DOUT FSX CLK
48 47 46 45 44 43 42 41 40 39 38 37
NC NC EARGS EARB EARA PDN MICBIAS MICGS MICIN NC NC NC
NC NC NC AVCC NC NC NC NC DVCC NC MICMUTE NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
VMID NC AGND NC NC NC NC NC NC DGND LINSEL NC
NC - No internal connection
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VBAP is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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NC DCLKR DIN FSR EARMUTE NC CLK FSX DOUT TSX/DCLKX NC NC
Copyright (c) 1997, Texas Instruments Incorporated
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
description
The TLV320AC40 and TLV320AC41 voice-band audio processor (VBAP) integrated circuits perform the transmit encoding (A /D conversion) and receive decoding (D/A conversion) together with transmit and receive filtering for voice-band communications systems. Cellular telephone systems are targeted in particular; however, these integrated circuits can function in other systems including digital audio, telecommunications, and data acquisition. These devices are pin-selectable for either of two modes -- companded and linear -- providing data in two formats. In the companded mode, data is transmitted and received in 8-bit words. In the linear mode, 13 bits of data, and either three bits of gain-setting control data, or three 0 bits of padding (to create a16-bit word), are sent and received. The transmit section is designed to interface directly with an electret microphone element. The microphone input signal (MICIN) is buffered and amplified with provision for setting the amplifier gain to accommodate a range of signal input levels. The amplified signal is passed through antialiasing and bandpass filters. The filtered signal is then applied to the input of a compressing analog-to-digital converter (COADC) when companded mode is selected. Otherwise, the analog-to-digital converter performs a linear conversion. The resulting data is then clocked out of DOUT as a serial data stream. The receive section converts a frame of serial data on DIN to analog through an expanding digital-to-analog converter (EXDAC) when the companded mode is selected; otherwise, a linear conversion is performed. The analog signal then passes through switched capacitor filters, which provide out-of-band rejection, (sin x)/x correction functions, and smoothing. The filtered signal is sent to the earphone amplifier. The earphone amplifier has a differential output with adjustable gain and is designed to minimize static power dissipation. A single on-chip high-precision band-gap circuit generates all voltage references, eliminating the need for external reference voltages. An internal reference voltage, VMID, equal to VCC /2 is used to develop the midlevel virtual ground for all the amplifier circuits and the microphone bias circuit. Another reference voltage, MICBIAS, can supply bias current for the microphone. The TLV320AC4xC devices are characterized for operation from 0C to 70C. The TLV320AC4xI devices are characterized for operation from - 40C to 85C.
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
functional block diagram
LINSEL 15 MICMUTE MICIN 6 18 Input Buffer Transmit Third-Order Antialias Transmit Sixth-Order Low Pass Transmit First-Order High Pass ADC Output Logic 13 DOUT
12 MICGS 19 288 kHz Band-Gap Voltage Reference A/D Converter Voltage Reference 288 kHz D/A Converter Voltage Reference 8 kHz Autozero 8 kHz
FSX
VMID VMID MICBIAS 17 20
VMID Generator
14 Clock Generator Clock Control
TSX/DCLKX 11 CLK 7 DCLKR
288 kHz 2 EARA 3 EARB 4 EARGS 10 EARMUTE
9
FSR
Earphone Amplifier
Receive Buffer
Receive Filter
DAC
Input Logic
8
DIN
5 VCC
16 GND
1 PDN
15 LINSEL
NOTE A: Terminal numbers shown are for the DW and N packages.
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3
TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
Terminal Functions
TERMINAL NAME AGND AVCC CLK DCLKR NO. DW, N -- -- 11 7 PT 34 4 19 14 I I Ground return for all internal analog circuits 3-V supply voltage for all internal analog circuits Clock input. In the fixed-data-rate mode, CLK is the master clock input as well as the transmit and receive data clock input . In the variable-data-rate mode, CLK is the master clock input only (digital). Selection of fixed- or variable-data-rate operation. When DCLKR is connected to VCC, the device operates in the fixed-data-rate mode. When DCLKR is not connected to VCC, the device operates in the variable-data-rate mode and DCLKR becomes the receive data clock (digital). Ground return for all internal digital circuits I O Receive data input. Input data is clocked in on consecutive negative transitions of the receive data clock, which is CLK for a fixed data rate and DCLKR for a variable data rate (digital). Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit data clock, which is CLK for a fixed data rate and DCLKX for a variable data rate (digital). 3-V supply voltage for all internal digital circuits O O I Earphone output. EARA forms a differential drive when used with the EARB signal (analog). Earphone output. EARB forms a differential drive when used with the EARA signal (analog). Earphone gain set input of feedback signal for the earphone output. The ratio of an external potential divider network connected across EARA and EARB adjusts the power amplifier gain. Maximum gain occurs when EARGS is connected to EARB. Minimum gain occurs when EARGS is connected to EARA. Earphone frequency response correction is performed using an RC approach (analog). Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no audio is sent to the earphone (digital). Frame-synchronization clock input for the receive channel. In the variable-data-rate mode, this signal must remain high for the duration of the time slot. The receive channel enters the standby condition when FSR is TTL-low for five frames or longer. The device enters a production test-mode condition when either FSR or FSX is held high for five frames or longer (digital). Frame synchronization clock input for the transmit channel. FSX operates independently of FSR, but also in an analogous manner to FSR. The transmit channel enters the standby condition when FSX is low for five frames or longer. The device enters a production test-mode condition when either FSX or FSR is held high for five frames or longer (digital). Ground return for all internal circuits I Linear selection input. When low, LINSEL selects linear coding/decoding. When high, LINSEL selects companded coding/decoding. Companding code on the 'AC40 is -law, and companding code on the 'AC41 is A-law (digital). Microphone bias. MICBIAS voltage for the electret microphone is equal to VMID. Output of the internal microphone amplifier. MICGS is used as the feedback to set the microphone amplifier gain. If sidetone is required, it is accomplished by connecting a series network between MICGS and EARGS (analog). Microphone input. Electret microphone input to the internal microphone amplifier (analog) Microphone input mute control signal. When MICMUTE is active (low), zero code is transmitted (dig.). Power-down input. When PDN is low, the device powers down to reduce power consumption (digital). Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the fixed-data-rate mode, TSX/DCLKX is an open-drain output that pulls to ground and is used as an enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the transmit data clock input (digital). 3-V supply voltage for all internal circuits O VCC /2 bias voltage reference. A pair of external, low-leakage, high-frequency capacitors (1 F and 470 pF) should be connected between VMID and ground for filtering. I/O DESCRIPTION
DGND DIN DOUT DVCC EARA EARB EARGS
-- 8 13 -- 2 3 4
27 15 21 9 44 45 46
EARMUTE FSR
10 9
17 16
I I
FSX
12
20
I
GND LINSEL
16 15
-- 26
MICBIAS MICGS
20 19
42 41
O O
MICIN MICMUTE PDN TSX/DCLKX
18 6 1 14
40 11 43 22
I I I I/O
VCC VMID
5 17
-- 36
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 5.5 V Output voltage range at DOUT, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 5.5 V Input voltage range at DIN, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 5.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage value is with respect to GND. DISSIPATION RATING TABLE PACKAGE DW N PT TA 25C POWER RATING 1025 mW 1150 mW 1075 mW DERATING FACTOR ABOVE TA = 25C 8.2 mW/C 9.2 mW/C 7.1 mW/C TA = 70C POWER RATING 656 mW 736 mW 756 mW TA = 85C POWER RATING 533 mW 598 mW 649 mW
recommended operating conditions (see Note 2)
MIN Supply voltage, VCC (see Note 3) High-level input voltage, VIH Low-level input voltage, VIL Load resistance between EARA and EARB, RL (see Note 4) Load capacitance between EARA and EARB, CL (see Note 4) Operating free-air temperature, TA free air temperature TLV320AC40C, TLV320AC41C TLV320AC40I, TLV320AC41I 0 - 40 600 50 70 85 2.7 2.2 0.8 MAX 3.3 UNIT V V V nF C
NOTES: 2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up sequence detailed in the system reliability features paragraph should be followed. 3. Voltages at analog inputs, outputs, and VCC are with respect to GND. 4. RL and CL should not be applied simultaneously.
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5
TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted)
supply current, fDCLKR or fDCLKX = 1.152 MHz, outputs not loaded, VCC = 3 V, TA = 25C
PARAMETER Operating Power down ICC Supply current from VCC Standby - both Standby - one TEST CONDITIONS PDN is high with CLK signal present PDN is low for 500 s PDN is high with FSX and FSR held low PDN is high with either FSX or FSR pulsing with the other held low MIN MAX 7.5 0.75 2 4.5 mA UNIT
digital interface
PARAMETER VOH VOL IIH IIL Ci High-level output voltage Low-level output voltage DOUT TEST CONDITIONS IOH = - 3.2 mA, IOL = 3.2 mA, VI = 2.2 V to VCC VI = 0 to 0.8 V 5 5 VCC = 3 V VCC = 3 V MIN 2.4 TYP 2.8 0.2 0.4 10 10 MAX UNIT V V A A pF pF
High-level input current, any digital input Low-level input current, any digital input Input capacitance
Co Output capacitance All typical values are at VCC = 3 V, TA = 25C.
microphone interface
PARAMETER VIO IIB B1 Ci AV IOmax Input offset voltage at MICIN Input bias current at MICIN Unity-gain bandwidth, open loop at MICIN Input capacitance at MICIN Large-signal voltage amplification at MICGS Maximum output current VMID MICBIAS (source only) 3 1 1.5 5 10 000 TEST CONDITIONS VI = 0 to 3 V MIN TYP MAX 5 200 UNIT mV nA MHz pF V/ V A mA
All typical values are at VCC = 3 V, TA = 25C. The frequency of the first pole is 100 Hz.
speaker interface
PARAMETER VO(PP) VOO II(lkg) IOmax ro AC output voltage Output offset voltage at EARA, EARB (single-ended) Input leakage current at EARGS Maximum output current Output resistance at EARA, EARB Gain change All typical values are at VCC = 3 V, TA = 25C. 2.5 Vpp when VCC is 2.7 V. EARMUTE low, max level when muted - 60 Relative to GND VI = 0.5 V to (VCC - 0.5) V RL = 600 1 TEST CONDITIONS MIN TYP MAX 3 80 200 2.5 UNIT Vpp mVpk nA mA dB
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
transmit gain and dynamic range, companded mode (-law or A-law) or linear mode selected, VCC = 3 V, TA = 25C (unless otherwise noted) (see Notes 5 and 6)
PARAMETER Transmit reference-signal level (0 dB) (see Note 7) TEST CONDITIONS Companded mode selected, -law ('AC40) Companded mode selected, A-law ('AC41) Linear mode selected ('AC40 and 'AC41) Companded mode selected, -law ('AC40) Overload-signal level (MICIN at unity gain) Absolute gain error Gain error with input level relative to gain at -10 dBm0 Gain variation Companded mode selected, A-law ('AC41) Linear mode selected ('AC40 and 'AC41) 0-dB input signal MICIN to DOUT at 3 dBm0 to - 40 dBm0 MICIN to DOUT at - 41 dBm0 to - 50 dBm0 MICIN to DOUT at - 51 dBm0 to - 55 dBm0 MIN MAX 0.614 0.616 0.626 2.5 2.5 2.5 1 0.5 1.5 2 dB dB Vpp Vrms UNIT
VCC 10%, TA = 0C to 70C 0.5 dB NOTES: 5. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 6. The input amplifier is set for inverting unity gain. 7. The reference-signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 2 V.
transmit filter transfer, companded mode (-law or A-law) or linear mode selected, over recommended ranges of supply voltage and free-air temperature, CLK = 1.152 MHz, FSX = 8 kHz (see Note 6)
PARAMETER TEST CONDITIONS fMICIN = 50 Hz fMICIN = 200 Hz Gain relative to input signal gain at 1.02 kHz In ut amplifier Input am lifier set for unity gain, noninverting maximum gain output signal at MICIN i 0 dB i l is fMICIN = 300 Hz to 3 kHz fMICIN = 3.3 kHz fMICIN = 3.4 kHz fMICIN = 4 kHz fMICIN 4.6 kHz NOTE 6. The input amplifier is set for inverting unity gain. MIN -10 -2.8 - 0.55 -1 MAX 0 0 0.25 0.2 - 0.1 -14 - 32 dB UNIT
transmit idle channel noise and distortion, companded mode with -law or A-law selected, over recommended ranges of supply voltage and operating free-air temperature (see Note 8)
PARAMETER Transmit noise, psophometrically weighted Transmit noise, C-message weighted TEST CONDITIONS MICIN connected to MICGS through a 10-k resistor MICIN connected to MICGS through a 10-k resistor MICIN to DOUT at 0 dBm0 to - 24 dBm0 MICIN to DOUT at -25 dBm0 to - 30 dBm0 Transmit signal-to-distortion ratio with sine-wave input MICIN to DOUT at - 31 dBm0 to - 38 dBm0 MICIN to DOUT at - 39 dBm0 to - 40 dBm0 MICIN to DOUT at - 41 dBm0 to - 45 dBm0 Intermodulation distortion, 2-tone CCITT method, composite power level -13 dBm0 CCITT G.712 (7.1), R2 CCITT G.712 (7.2), R3 36 34 30 24 20 49 51 dB dB MIN MAX - 72 UNIT dBm0p
10 dBrnC0
NOTE 8: Transmit noise, linear mode: 200 Vrms is equivalent to -74 dB (referenced to device 0-dB level).
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7
TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
transmit idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage and operating free-air temperature (see Notes 6 and 8)
PARAMETER Transmit noise TEST CONDITIONS MICIN connected to MICGS through a 10-k resistor MICIN to DOUT at 0 dBm0 to - 10 dBm0 MICIN to DOUT at - 11 dBm0 to - 12 dBm0 Transmit signal to distortion ratio with sine-wave input signal-to-distortion sine wave MICIN to DOUT at - 13 dBm0 to - 18 dBm0 MICIN to DOUT at - 19 dBm0 to - 24 dBm0 MICIN to DOUT at - 25 dBm0 to - 40 dBm0 MICIN to DOUT at - 41 dBm0 to - 45 dBm0 NOTES: 6. The input amplifier is set for inverting unity gain. 8. Transmit noise, linear mode: 200 Vrms is equivalent to -74 dB (referenced to device 0-dB level). 46 44 40 35 20 18 dB MIN MAX 200 UNIT Vrms
receive gain and dynamic range, companded mode (-law or A-law) or linear mode selected, VCC = 3 V, TA = 25C (unless otherwise noted) (see Notes 9 and 10)
PARAMETER Receive reference-signal level (0 dB) (see Note 11) TEST CONDITIONS Companded mode selected, -law ('AC40) Companded mode selected, A-law ('AC41) Linear mode selected ('AC40 and 'AC41) Companded mode selected, -law ('AC40) Overload-signal level Absolute gain error Gain error with output level relative to gain at -10 dBm0 Companded mode selected, A-law ('AC41) Linear mode selected ('AC40 and 'AC41) 0-dB input signal DIN to EARA and EARB at 3 dBm0 to - 38 dBm0 DIN to EARA and EARB at - 39 dBm0 to - 50 dBm0 DIN to EARA and EARB at - 51 dBm0 to - 55 dBm0 MIN MAX 0.736 0.739 0.751 3 3 3 1 0.5 1.5 2 dB dB Vpp Vrms UNIT
Gain variation VCC 10%, TA = 0C to 70C 0.5 dB NOTES: 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected. 10. Unless otherwise noted, the digital input is a word stream generated by passing a 0-dB sine wave at 1020 Hz through an ideal encoder, where 0 dB is defined as the zero reference. 11. This reference-signal level is measured at the speaker output of the receive channel with the gain of the output speaker amplifier set to unity.
receive filter transfer, companded mode (-law or A-law) or linear mode selected, over recommended ranges of supply voltage and operating free-air temperature, FSR = 8 kHz (see Note 9)
PARAMETER TEST CONDITIONS fDIN = < 200 Hz fDIN = 200 Hz Gain relative to gain at 1.02 kHz DIN = 0 dBm0 fDIN = 300 Hz to 3 kHz fDIN = 3.3 kHz fDIN = 3.4 kHz fDIN = 4 kHz MIN - 0.5 - 0.55 -1 MAX 0.25 0.25 0.25 0.2 - 0.1 - 14 dB UNIT
fDIN = > 4.6 kHz - 30 NOTE 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
receive idle channel noise and distortion, companded mode with -law or A-law selected, over recommended ranges of supply voltage and operating free-air temperature (see Note 9)
PARAMETER Receive noise, psophometrically weighted Receive noise, C-message weighted TEST CONDITIONS DIN = 11010101 (A-law) DIN = 11111111 (-law) DIN to EARA and EARB at 0 dBm0 to - 18 dBm0 DIN to EARA and EARB at - 19 dBm0 to - 24 dBm0 Receive signal-to-distortion ratio with sine-wave input DIN to EARA and EARB at - 25 dBm0 to - 30 dBm0 DIN to EARA and EARB at - 31 dBm0 to - 38 dBm0 DIN to EARA and EARB at - 39 dBm0 to - 45 dBm0 36 34 30 23 17 dB MIN MAX - 72 UNIT dBm0p
8 dBrnC0
NOTE 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
receive idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage and operating free-air temperature (see Notes 9 and 12)
PARAMETER Receive noise TEST CONDITIONS DIN = 00000000 DIN to EARA and EARB at 0 dBm0 to - 12 dBm0 DIN to EARA and EARB at - 13 dBm0 to - 18 dBm0 Receive signal-to-distortion ratio with sine-wave input DIN to EARA and EARB at - 19 dBm0 to - 24 dBm0 DIN to EARA and EARB at - 25 dBm0 to - 40 dBm0 DIN to EARA and EARB at - 41 dBm0 to - 45 dBm0 Intermodulation, 2-tone CCITT distortion method, composite power level - 13 dBm0 CCITT G.712 (7.1), R2 CCITT G.712 (7.2), R3 46 38 32 18 15 50 54 dB dB MIN MAX 200 UNIT Vrms
NOTES: 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected. 12. Receive noise, linear mode: 200 Vrms is equivalent to -71 dB (referenced to device 0-dB level).
power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and operating free-air temperature
PARAMETER Supply voltage rejection, transmit channel TEST CONDITIONS Idle channel, supply signal = 100 mVrms, f = 0 to 30 kHz (measured at DOUT) Idle channel, supply signal = 100 mVrms, EARGS connected to EARB, f = 0 to 30 kHz (measured differentially between EARA and EARB) MICIN = 0 dB, f = 1.02 kHz, unity transmit gain, EARGS connected to EARB, measured differentially between EARA and EARB DIN = 0 dBm0, f = 1.02 kHz, unity transmit gain, measured at DOUT MIN TYP - 30 MAX UNIT dB
Supply voltage rejection, receive channel
- 30
dB
Crosstalk attenuation, transmit-to-receive (differential)
50
dB
Crosstalk attenuation, receive-to-transmit All typical values are at VCC = 3 V, TA = 25C.
50
dB
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9
TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1 through Figure 4)
MIN tt Transition time, CLK and DCLKX /DCLKR Duty cycle, CLK Duty cycle, DCLKX /DCLKR All nominal values are at VCC = 3 V, TA = 25C. 45% 45% 50% 50% NOM MAX 10 55% 55% UNIT ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figure 2)
MIN tsu(FSX) th(FSX) Setup time, FSX high before CLK Hold time, FSX high after CLK 20 20 MAX 468 468 UNIT ns ns
receive timing requirements over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate mode (see Figure 1)
MIN tsu(FSR) th(FSR) tsu(DIN) th(DIN) Setup time, FSR high before CLK Hold time, FSR high after CLK Setup time, DIN high or low before CLK Hold time, DIN high or low after CLK 20 20 20 20 MAX 468 468 UNIT ns ns ns ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode (see Figure 4)
MIN tsu(FSX) th(FSX) Setup time, FSX high before DCLKX Hold time, FSX high after DCLKX MAX UNIT ns ns 40 tc(DCLKX)- 40 35 tc(DCLKX)-35
receive timing requirements over recommended ranges of supply voltage and operating free-air temperature, variable-data-rate mode (see Figure 3)
MIN tsu(FSR) th(FSR) tsu(DIN) th(DIN) Setup time, FSR high before DCLKR Hold time, FSR high after DCLKR Setup time, DIN high or low before DCLKR Hold time, DIN high or low after DCLKR 40 35 30 30 tc(DCLKR)-35 MAX UNIT ns ns ns ns
switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode, CL = 0 to 10 pF (see Figure 2)
PARAMETER tpd1 tpd2 tpd3 tpd4 tpd5 From CLK bit 1 high to DOUT bit 1 valid From CLK high to DOUT valid, bits 2 to n From CLK bit n low to DOUT bit n Hi-Z From CLK bit 1 high to TSX active (low) From CLK bit n low to TSX inactive (high) Rpullup = 1.24 kW Rpullup = 1.24 k 30 30 40 TEST CONDITIONS MIN MAX 35 35 UNIT ns ns ns ns ns
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see Figure 4)
PARAMETER tpd6 tpd7 tpd8 FSX high to DOUT bit 1 valid DCLKX high to DOUT valid, bits 2 to n FSX low to DOUT bit n Hi-Z TEST CONDITIONS CL = 0 to 10 pF CL = 0 to 10 pF 20 MIN MAX 30 40 UNIT ns ns ns
PARAMETER MEASUREMENT INFORMATION
All timing parameters are referenced to VIH and VIL. Bit 1 = MSB (most significant bit) and is clocked in first on DIN or clocked out first on DOUT. Bit N = LSB (least significant bit) and is clocked in last on DIN or is clocked out last on DOUT. N = 8 for the companded mode, and N = 16 for the linear mode.
Receive Time Slot 0 80% CLK tsu(FSR) FSR See Note B See Note A DIN See Note C NOTES: A. This window is allowed for FSR high. B. This window is allowed for FSR low. C. Transitions are measured at 50%. tsu(DIN) N-1 N 1 2 3 4 N-2 th(DIN) N-1 N 1 20% th(FSR) 1 2 3 4 N-2 20% N-1 N 80% N+1
Figure 1. Fixed-Data Rate Mode, Receive Side Timing Diagram
0 CLK tsu(FSX) FSX See Note B See Note A DOUT See Note C tpd1 20% tpd4 NOTES: A. This window is allowed for FSX high. B. This window is allowed for FSX low (th(FSX) max determined by data collision considerations). C. Transitions are measured at 50%. 1 2 3 tpd2 N-2 tpd3 N-1 tpd5 80% N 80% 20% th(FSX) 20% 1 2 3 Transmit Time Slot 4 N-2 N-1 N 80% N+1
TSX
Figure 2. Fixed-Data Rate Mode, Transmit Side Timing Diagram
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
11
TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
Receive Time Slot 0 DCLKR 80% 1 20% 20% tsu(FSR) FSR See Note A DIN See Note C N-1 N 1 2 3 4 th(DIN) N-2 See Note B N-1 tsu(DIN) N 1 th(FSR) 2 3 4 N-2 N-1 N 80% N+1 80%
NOTES: A. This window is allowed for FSR high (tsu(FSR) max determined by data collision considerations). B. This window is allowed for FSR low. C. Transitions are measured at 50%.
Figure 3. Variable-Data Rate Mode, Receive Side Timing Diagram
Transmit Time Slot 4 N-2
0 DCLKX 80%
1 20%
2 80%
3
N-1
N 80% 20% th(FSX)
N+1
tsu(FSX) FSX See Note A tpd6 DOUT See Note C 1 2 3 4 N-2 tpd7
See Note B tpd8 N-1 N
NOTES: A. This window is allowed for FSX high. B. This window is allowed for FSX low without data repetition. C. Transitions are measured at 50%.
Figure 4. Variable-Data Rate Mode, Transmit Side Timing Diagram
12
POST OFFICE BOX 655303
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
PRINCIPLES OF OPERATION general
system reliability features The device should be powered up and initialized as follows: 1. 2. 3. 4. 5. Apply GND. Apply VCC. Connect all clocks. Apply TTL high to PDN. Apply synchronizing pulses to FSX and/or FSR.
Even though the VBAP is heavily protected against latch-up, it is still possible to cause it to latch up under certain improper power conditions. To help ensure that latch-up does not occur, a reverse-biased Schottky diode with a forward voltage drop of less than or equal to 0.4 V (1N5711 or equivalent) should be connected between VCC (power supply) and GND. On the transmit channel, digital outputs DOUT and TSX are held in the high-impedance state for approximately four frames (500 s) after power up or application of VCC. After this delay, DOUT, TSX, and signaling are functional and occur in the correct time slot. The analog circuits on the transmit side require approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. To further enhance system integrity, DOUT and TSX are placed in the high-impedance state after an interruption of CLK. power-down and standby operations To minimize power consumption, a power-down mode and three standby modes are provided. For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is internally pulled up to a high logic level and the device remains active. In the power-down mode, the average power consumption is reduced to 2 mW. Three standby modes give the user the option of placing the entire device on standby, placing only the transmit channel on standby, or placing only the receive channel on standby. To place the entire device on standby, both FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is pulsing and FSR is held low. For receive-only operation (transmit section on standby), FSR is pulsing and FSX is held low. When the entire device is in standby mode, power consumption is reduced to 5 mW. See Table 1 for power-down and standby procedures.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
13
TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
PRINCIPLES OF OPERATION
Table 1. Power-Down and Standby Procedures
DEVICE STATUS PROCEDURE PDN = high, FSX = pulses, FSR = pulses PDN = low, FSX, FSR = X FSX = low, FSR = low, PDN = high FSX = low, FSR = pulses, PDN = high FSR = low, FSX = pulses, PDN = high TYPICAL POWER CONSUMPTION 20 mW DIGITAL OUTPUT STATUS
Power on
Digital outputs active but not loaded
Power down Entire device on standby mode Only transmit channel in standby mode Only receive channel in standby mode X = don't care
2 mW
TSX and DOUT in the high-impedance state
5 mW
TSX and DOUT in the high-impedance state
10 mW
TSX and DOUT in the high-impedance state within five frames
10 mW
Digital outputs active but not loaded
fixed-data-rate timing Fixed-data-rate timing is selected by connecting DCLKR to VCC and uses the master clock (CLK), frame synchronization clocks (FSX and FSR), and the TSX output. FSX and FSR are inputs that set the sampling frequency. Data is transmitted on DOUT on the positive transitions of CLK following the rising edge of FSX. Data is received on DIN on the falling edges of CLK following FSR. A D/A conversion is performed on the received digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred to the receive filter. The data word is eight bits long in the companded mode and 16 bits long in the linear mode. variable-data-rate timing Variable-data-rate timing is selected by connecting DCLKR to the receive data clock. In this mode, the master clock (CLK) controls the switched-capacitor filters, while data transfer into DIN and out of DOUT is controlled by DCLKR and DCLKX respectively. This allows the data to be transferred in and out of the device at any rate up to the frequency of the master clock. DCLKR and DCLKX must be synchronous with CLK. While the FSX input is high, data is transmitted from DOUT on consecutive positive transitions of DCLKX. Similarly, while the FSR input is high, the data word is received at DIN on consecutive negative transitions of DCLKR. The transmitted data word at DOUT is repeated in all remaining time slots in the frame as long as DCLKX is pulsed and FSX is held high. This feature, which allows the data word to be transmitted more than once per frame, is available only with variable-data-rate timing. asynchronous operations To avoid crosstalk problems associated with special interrupt circuits, the design includes separate converters, filters, and voltage references on the transmit and receive sides to allow completely independent operation of the two channels. In either timing mode, the master clock, data clock, and time-slot strobe must be synchronized at the beginning of each frame. precision voltage references A precision band-gap reference voltage is generated internally and is used to supply all the references required for operation of both the transmit and receive channels. The gain in each channel is trimmed during the manufacturing process. This ensures very accurate, stable gain performance over variations in supply voltage and device temperature.
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POST OFFICE BOX 655303
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
PRINCIPLES OF OPERATION
conversion laws The TLV320AC40 provides -law companding operation that approximates the CCITT G.711 recommendation. The TLV320AC41 provides A-law companding operation that approximates the CCITT G.711 recommendation. The linear mode of operation uses a 13-bit two's-complement format and is the same for both the TLV320AC40 and the TLV320AC41.
transmit operation
microphone input The microphone input amplifier is designed specifically to interface to electret-type microphone elements, as shown in Figure 5. The VMID buffer circuit provides a voltage (MICBIAS) equal to 1/2 VCC as a reference for the microphone amplifier and a bias voltage to the electret microphone. The microphone amplifier output (MICGS) is used in conjunction with a feedback network and applied to the amplifier inverting input (MICIN) to set the amplifier gain. In the companded mode, when the MICIN signal level decreases to a level near the noise floor, the VBAP mutes the signal and outputs zero bits while continuing to monitor the signal level. When the input level once again exceeds the noise threshold, the mute is released and normal operation resumes. Input hysteresis is provided to ensure noiseless transitions in to and out of the muted condition. VMID appears at a terminal to provide a place to filter the VMID voltage.
VMID 17 1 F 470 pF VMID Buffer MICBIAS 20 + - -
VMID Reference For Amplifiers VMID Generator +
VDD
2 k 3.3 F + 10 k Electret Microphone
10 k
MICGS 19 MICIN 18
Microphone Amplifier - + To Transmit Filters
MICMUTE TLV320AC40/41 VBAP 6
NOTE A: Terminal numbers shown are for the DW and N packages.
Figure 5. Typical Microphone Interface microphone mute function The MICMUTE input causes the digital circuitry to transmit all zero code on DOUT. transmit filter A low-pass antialiasing section is included on the device and achieves a 35-dB attenuation at the sampling frequency. No external components are required to provide the necessary antialiasing function for the switched-capacitor section of the transmit filter.
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15
TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
PRINCIPLES OF OPERATION
encoding The encoder internally samples the output of the transmit filter and holds each sample on an internal sample-and-hold capacitor. The encoder performs an A/D conversion on a switched-capacitor array. Digital data representing the sample is transmitted on the first 8 or 16 data clock cycles of the next frame. The autozero circuit corrects for dc offset on the input signal to the encoder using the sign-bit averaging technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the encoder. data word structure The data word is eight bits long in the companded mode and all eight bits represent one audio data sample. The sign bit is the first bit transmitted. The data word is 16 bits long in the linear mode. The first 13 bits comprise the audio data sample, and the last three bits form the volume control word in the receive direction (DIN) and are zero pad bits in the transmit direction (DOUT). The sign bit is transmitted first.
receive operation
decoding In the companded mode, the serial data word is received at DIN on the first eight clock cycles in fixed-data rate and on the last eight clock cycles in variable-data rate. In the linear mode, the serial data word is received at DIN on the first 13 clock cycles. D/A conversion is performed, and the corresponding analog sample is held on an internal sample-and-hold capacitor. This sample is transferred to the receive filter. receive filter The receive section of the filter provides passband flatness and stopband rejection that approximates both the AT&T D3/D4 specification and CCITT recommendation G.712 when operated at the recommended frequencies. The filter contains the required compensation for the (sin x)/x response of such decoders. receive buffer The receive buffer contains the volume control. earphone amplifier The earphone audio-output amplifier has a balanced output, as shown in Figure 6, to allow maximum flexibility in output configuration. The output amplifier is designed to directly drive a piezo earphone in the differential configuration without any additional external components. The output can also be used to drive a single-ended load with the output signal voltage centered around VCC /2. The receive-channel output level can be adjusted between specified limits by connecting an external resistor network to EARGS.
16
POST OFFICE BOX 655303
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
PRINCIPLES OF OPERATION
- + 4 EARGS
IN
_ +
2
EARA
_ VMID +
3
EARB
NOTE A: Terminal numbers shown are for the DW and N packages.
Figure 6. Earphone Audio-Output Amplifier Configuration and Internal Gain-Setting Network receive data format In the companded mode, eight bits of data are received. The sign bit is the first bit received (see Table 2). In the linear mode, 16 bits of data are received. The first 13 bits are the D/A code, and the remaining three bits form the volume control word (see Table 2). The volume control function is actually an attenuation control in which the first bit received is the most significant. The maximum volume occurs when all three volume control bits are zero. Eight levels of attenuation are selectable in 3-dB steps, giving a maximum attenuation of 21 dB when all bits are 1s. The volume control bits are not latched into the VBAP and must be present in each received data word.
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
PRINCIPLES OF OPERATION
Table 2. Receive-Data Bit Definitions
BIT NO. 0 1 2 3 4 5 6 7 8 9 A B C D E F COMPANDED MODE CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 - - - - - - - - LINEAR MODE LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 V2 V1 V0
Volume control and other control bits always follow the PCM data in time:
Companded Mode: MSB (sign bit) LSB CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 Companded Data
Linear Mode:
MSB (sign bit)
LSB LD12 LD11 LD10 LD9 LD8 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 Linear Data Time
V2
V1
V0
Volume Control
where: CD7- CD0 = Data word when in companded mode LD12- LD0 = Data word when in linear mode V2, V1, V0 = Volume (attenuation control) 000 = maximum volume, 3 dBm0 111 = minimum volume, -18 dBm0
18
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
APPLICATION INFORMATION output gain set design considerations (see Figure 7)
EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are: VO + at EARA VO - at EARB VOD = VO + - VO - (total differential response) R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS. A value greater than 10 k and less than 100 k for R1 + R2 is recommended because of the following: The parallel combination R1 + R2 and RL sets the total loading. The total capacitance at EARGS and the parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies. VA represents the maximum available digital mW output response (VA = 1.001 Vrms). VOD = A x VA where A = 1 + (R1/R2) 4 + (R1/R2)
EARA
2 R1
VO+
Digital mW Sequence IAW CCITT G.712
DIN
EARGS
4 R2
VO
RL
EARB
3
VO -
NOTE A: Terminal numbers shown are for the DW and N packages.
Figure 7. Gain-Setting Configuration
higher clock frequencies and sample rates
The VBAP is designed to work with sample rates up to 16 kHz where the frequency of the frame sync determines the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock frequency, fCLK, to the frame sync frequency, fFSR/fFSX. This ratio for the VBAP is 1.152 MHz/8 kHz, or 144 master clocks per frame sync. For example, to operate the VBAP at a sampling rate of fFSR and fFSX equal to 16 kHz, fCLK must be 144 times 16 kHz, or 2.304 MHz. If the VBAP is operated above an 8-kHz sample rate, however, it is expected that the performance becomes somewhat degraded. Exact parametric specifications for rates up to 16-kHz sample rate are not specified at this time.
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19
TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
MECHANICAL DATA
DW (R-PDSO-G**)
16 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) DIM 0.020 (0,51) 0.014 (0,35) 16 9 0.010 (0,25) M
PINS **
16 0.410 (10,41) 0.400 (10,16)
20 0.510 (12,95) 0.500 (12,70)
24 0.610 (15,49) 0.600 (15,24)
28 0.710 (18,03) 0.700 (17,78)
A MAX
A MIN
0.419 (10,65) 0.400 (10,15) 0.299 (7,59) 0.293 (7,45) 0.010 (0,25) NOM
Gage Plane 0.010 (0,25) 1 A 8 0- 8 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) 4040000 / B 03/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013
20
POST OFFICE BOX 655303
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TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
MECHANICAL DATA
N (R-PDIP-T**)
16 PIN SHOWN PINS ** DIM A 16 9 A MAX
PLASTIC DUAL-IN-LINE PACKAGE
14 0.775 (19,69) 0.745 (18,92)
16 0.775 (19,69) 0.745 (18,92)
18 0.920 (23.37) 0.850 (21.59)
20 0.975 (24,77) 0.940 (23,88)
A MIN
0.260 (6,60) 0.240 (6,10)
1
8 0.070 (1,78) MAX
0.035 (0,89) MAX
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38)
0- 15 0.010 (0,25) NOM
0.010 (0,25) M
14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
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21
TLV320AC40, TLV320AC41 3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045A - JUNE 1996 - REVISED APRIL 1997
MECHANICAL DATA
PT (S-PQFP-G48)
0,27 0,17 36 25
PLASTIC QUAD FLATPACK
0,50
0,08 M
37
24
48
13 0,13 NOM 1 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 0,25 1,45 1,35 0,05 MIN 0- 7 Gage Plane 12
Seating Plane 1,60 MAX 0,10
0,75 0,45
4040052 / B 03/95 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MO-136 This may also be a thermally-enhanced plastic package with leads connected to the die pads.
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Copyright (c) 1998, Texas Instruments Incorporated

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