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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
features
D D D D D D D D D D D D D
PW PACKAGE (TOP VIEW)
Dual-Channel High-Side MOSFET Drivers 1 20 DISCH1 GATE1 IN1: 3 V to 13 V; IN2: 3 V to 5.5 V 2 19 DISCH2 GATE2 Inrush Current Limiting With dv/dt Control 3 18 ENABLE DGND 4 17 Circuit-Breaker Control With Programmable TIMER PWRGD1 5 16 Current Limit and Transient Timer VREG FAULT 6 15 VSENSE2 ISET1 Power-Good Reporting With Transient 7 14 VSENSE1 ISET2 Filter 8 13 AGND PWRGD2 CMOS- and TTL-Compatible Enable Input 9 12 ISENSE2 IN2 Low, 5-A Standby Supply Current . . . Max 10 11 ISENSE1 IN1 Available in 20-Pin TSSOP Package NOTE: Terminal 18 is active high on TPS2301. - 40C to 85C Ambient Temperature Range typical application Electrostatic Discharge Protection
VO1 + V1 3 V - 13 V IN1 VREG ISET1 ISENSE1 GATE1 DISCH1 VSENSE1
applications
Hot-Swap/Plug/Dock Power Management Hot-Plug PCI, Device Bay Electronic Circuit Breaker
description
The TPS2300 and TPS2301 are dual-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush current control, output-power status reporting, and separation of load transients from actual load increases, are critical requirements for hot-swap applications.
AGND DGND
TPS2300
PWRGD1 FAULT TIMER PWRGD2
ENABLE IN2 ISET2 ISENSE2 GATE2 DISCH2
VSENSE2
VO2 V2 3 V - 5.5 V +
The TPS2300/01 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the device is off at start-up and confirm the status of the output voltage rails during operation. Each internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pumps control both the rise times and fall times (dv/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period.
AVAILABLE OPTIONS TA HOT-SWAP HOT SWAP CONTROLLER DESCRIPTION Dual-channel with independent OCP and adjustable PG - 40C to 85C Dual-channel with interdependent OCP and adjustable PG Dual-channel with independent OCP Single-channel with OCP and adjustable PG PIN COUNT 20 20 16 14 TSSOP PACKAGES (PW, PWR) ENABLE TPS2300IPW TPS2310IPW TPS2320IPW TPS2330IPW ENABLE TPS2301IPW TPS2311IPW TPS2321IPW TPS2331IPW
The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2301IPWR). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
functional block diagram
IN1 VREG PREREG ISET1 ISENSE1 GATE1 Clamp dv/dt Rate Protection 50 A UVLO and Power-Up Circuit Breaker Charge Pump Pulldown FET Circuit Breaker 75 A 20-s Deglitch DISCH1
AGND
VSENSE1 PWRGD1
DGND
ENABLE
Logic 50-s Deglitch
FAULT
TIMER
Second Channel
PWRGD2
IN2
ISET2
ISENSE2 GATE2
DISCH2
VSENSE2
Terminal Functions
TERMINAL NAME AGND DGND DISCH1 DISCH2 ENABLE/ ENABLE FAULT GATE1 GATE2 IN1 IN2 ISENSE1 ISENSE2 ISET1 ISET2 PWRGD1 PWRGD2 TIMER VREG VSENSE1 VSENSE2 NO. 8 3 20 19 18 16 1 2 11 12 10 9 15 14 17 13 4 5 7 6 I/O I I O O I O O O I I I I I I O O O O I I DESCRIPTION Analog ground, connects to DGND as close as possible Digital ground Discharge transistor 1 Discharge transistor 2 Active low (TPS2300) or active high enable (TPS2301) Overcurrent fault, open-drain output Connects to gate of channel 1 high-side MOSFET Connects to gate of channel 2 high-side MOSFET Input voltage for channel 1 Input voltage for channel 2 Current-sense input channel 1 Current-sense input channel 2 Adjusts circuit-breaker threshold with resistor connected to IN1 Adjusts circuit-breaker threshold with resistor connected to IN2 Open-drain output, asserted low when VSENSE1 voltage is less than reference. Open-drain output, asserted low when VSENSE2 voltage is less than reference. Adjusts circuit-breaker deglitch time Connects to bypass capacitor, for stable operation Power-good sense input channel 1 Power-good sense input channel 2
2
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
detailed description
DISCH1, DISCH2 - DISCH1 and DISCH2 should be connected to the sources of the external N-channel MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate voltage-clamp circuitry. ENABLE or ENABLE - ENABLE for TPS2300 is active low. ENABLE for TPS2301 is active high. When the controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When the ENABLE pin is pulled high for TPS2300 or the ENABLE pin is pulled low for TPS2301 for more than 50 s, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is less than 5 A. FAULT - FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is sustained long enough to charge TIMER to 0.5 V, the overcurrent channel latches off and pulls this pin low. The other channel will run normally if not in overcurrent. In order to turn the channel back on, either the enable pin has to be toggled or the input power has to be cycled. GATE1, GATE2 - GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15 A to each. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If desired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during powerup. The charge-pump circuitry will generate gate-to-source voltages of 9 V-12 V across the external MOSFET transistors. IN1, IN2 - IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET transistors connected to GATE1 and GATE2, respectively. The TPS2300/TPS2301 draws its operating current from IN1, and both channels will remain disabled until the IN1 power supply has been established. The IN1 channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been constructed to support 3-V or 5-V operation ISENSE1, ISENSE2, ISET1, ISET2 - ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implement overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that generates an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws 50 A from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which is also connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled below ISET2. PWRGD1, PWRGD2 - PWRGD1 and PWRGD2 signal the presence of undervoltage conditions on VSENSE1 and VSENSE2, respectively. These pins are open-drain outputs and are pulled low during an undervoltage condition. To minimize erroneous PWRGDx responses from transients on the voltage rail, the voltage sense circuit incorporates a 20-s deglitch filter. When VSENSEx is lower than the reference voltage (about 1.23 V), PWRGDx will be active low to indicate an undervoltage condition on the power-rail voltage. TIMER - A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering.
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
detailed description (continued)
VREG - The VREG pin is the output of an internal low-dropout voltage regulator. This regulator draws current from IN1. A 0.1-F ceramic capacitor should be connected between VREG and ground. VREG can be connected to IN1, IN2, or to a separated power supply through a low-resistance resistor. However, the voltage on VREG must be less than 5.5 V. VSENSE1, VSENSE2 - VSENSE1 and VSENSE2 can be used to detect undervoltage conditions on external circuitry. If VSENSE1 senses a voltage below approximately 1.23 V, PWRGD1 is pulled low. Similarly, a voltage less than 1.23 V on VSENSE2 causes PWRGD2 to be pulled low.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Input voltage range: VI(IN1), VI(ISENSE1), VI(VSENSE1), VI(VSENSE2), VI(ISET1), VI(ENABLE), VI(VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 15 V VI(IN2), VI(ISENSE2), VI(ISET2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V Output voltage range: VO(GATE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 30 V VO(GATE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 22V VO(DISCH1), VO(PWRGD1), VO(PWRGD2), VO(FAULT) VO(DISCH2), VO(TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 15V Sink current range: IGATE1, IGATE2, IDISCH1, IDISCH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 100 mA IPWRGD1, IPWRGD2, ITIMER, IFAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 mA to 10 mA Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 100C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are respect to DGND. DISSIPATION RATING TABLE PACKAGE PW-20 TA 25C POWER RATING 1015 mW DERATING FACTOR ABOVE TA = 25C 13.55 mW/C TA = 70C POWER RATING 406 mW TA = 85C POWER RATING 203 mW
recommended operating conditions
MIN Input voltage VI voltage, VI(IN1), VI(ISENSE1), VI(VSENSE1), VI(VSENSE2), VI(ISET1) VI(IN2), VI(ISENSE2), VI(ISET2), VI(VREG) 3 3 -40 NOM MAX 13 5.5 100 UNIT V C
Operating virtual junction temperature, TJ
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating temperature range (-40C < TA < 85C), 3 V VI(IN1) 13 V, 3 V VI(IN2) 5.5 V (unless otherwise noted)
general
PARAMETER II(IN1) II(IN2) II(stby) Input current, IN1 Input current, IN2 Standby current ( y (sum of currents into IN1, IN2, ISENSE1, ISENSE2, ISET1, and ISET2) TEST CONDITIONS VI(ENABLE) = 5 V (TPS2301), VI(ENABLE) = 0 V (TPS2300) VI(ENABLE) = 0 V (TPS2301) VI(ENABLE) = 5 V (TPS2300) MIN TYP 0.5 75 MAX 1 200 5 UNIT mA A A
GATE1
PARAMETER VG(GATE1_3V) VG(GATE1_4.5V) VG(GATE1_10.8V) VC(GATE1) IS(GATE1) Clamping voltage, GATE1 to DISCH1 Source current, GATE1 Sink current, GATE1 3 V VI(IN1) 13.2 V, 3 V VO(VREG) 5.5 V, VI(GATE1) = VI(IN1) + 6 V 3 V VI(IN1) 13.2 V, 3 V VO(VREG) 5.5 V, VI(GATE1) = VI(IN1) Cg to GND = 1 nF (see Note 2) VI(IN1) = 3 V VI(IN1) = 4.5 V VI(IN1) = 10.8 V VI(IN1) = 3 V tf(GATE1) ( ) Fall time, GATE1 Cg to GND = 1 nF (see Note 2) VI(IN1) = 4.5 V VI(IN1) = 10.8 V Gate voltage TEST CONDITIONS II(GATE1) = 500 nA, nA DISCH1 o en open VI(IN1) = 3 V VI(IN1) = 4.5 V VI(IN1) = 10.8 V MIN 9 10.5 16.8 9 10 50 TYP 11.5 14.5 21 10 14 75 0.5 0.6 1 0.1 0.12 0.2 ms ms 12 20 100 V A A V MAX UNIT
tr(GATE1) ( )
Rise time, GATE1
GATE2
PARAMETER VG(GATE2_3V) VG(GATE2_4.5V) VC(GATE2) IS(GATE2) Clamping voltage, GATE2 to DISCH2 Source current, GATE2 Sink current, GATE2 tr(GATE2) (GATE2) tf(GATE2) Rise time GATE2 time, Fall time GATE2 time, 3 V VI(IN2) 5.5 V, 3 V VO(VREG) 5.5 V, VI(GATE2) = VI(IN2) + 6 V 3 V VI(IN2) 5.5 V, 3 V VO(VREG) 5.5 V, VI(GATE2) = VI(IN2) Cg to GND = 1 nF (see Note 2) Cg to GND = 1 nF (see Note 2) VI(IN2) = 3 V VI(IN2) = 4.5 V VI(IN2) = 3 V VI(IN2) = 4.5 V Gate voltage TEST CONDITIONS II(GATE2) = 500 nA, DISCH2 o en nA open VI(IN2) = 3 V VI(IN2) = 4.5 V MIN 9 10.5 9 10 50 TYP 11.7 14.7 10 14 75 0.5 VO(VREG) = 3 V 0.6 0.1 0.12 12 20 100 V A A ms ms MAX UNIT V
NOTE 2: Specified, but not production tested.
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating temperature range (-40C < TA < 85C), 3 V VI(IN1) 13 V, 3 V VI(IN2) 5.5 V ( unless otherwise noted) (continued)
TIMER
PARAMETER VOT(TIMER) Threshold voltage, TIMER Charge current, TIMER Discharge current, TIMER VI(TIMER) = 0 V VI(TIMER) = 1 V TEST CONDITIONS MIN 0.4 35 1 TYP 0.5 50 2.5 MAX 0.6 65 UNIT V A mA
circuit breaker
PARAMETER VIT(CB) IIB(ISENSEx) Undervoltage voltage, circuit breaker Input bias current, ISENSEx Discharge current, GATEx current tpd(CB) Propagation (delay) time, comparator inputs to gate output VO(GATEx) = 4 V VO(GATEx) = 1 V Cg = 50 pF, (50% to 10%), 10 mV overdrive, CO(timer) = 50 pF 400 25 TEST CONDITIONS RISETx = 1 k MIN 40 TYP 50 0.1 800 150 1.3 MAX 60 5 UNIT mV A mA s
ENABLE, active low (TPS2300)
PARAMETER VIH(ENABLE) VIL(ENABLE) RI(ENABLE) td_off(ENABLE) td_on(ENABLE) High-level input voltage, ENABLE Low-level input voltage, ENABLE Input pullup resistance, ENABLE Turnoff delay time, ENABLE Turnon delay time, ENABLE See Note 3 VI(ENABLE) increasing above stop threshold; 100 ns rise time, 20 mV overdrive (see Note 2) VI(ENABLE) decreasing below start threshold; 100 ns fall time, 20 mV overdrive (see Note 2) 1V I 100 200 60 125 TEST CONDITIONS MIN 2 0.8 300 TYP MAX UNIT V V k s s
NOTES: 2. Specified, but not production tested. 3. Test IO of ENABLE at VI(ENABLE) = 1 V and 0 V, then RI(ENABLE) = I O_ 0V
* O_1V
MIN 2 0.7 100 150 85 100 300 TYP MAX UNIT V V k s s
ENABLE, active high (TPS2301)
PARAMETER VIH(ENABLE) VIL(ENABLE) RI(ENABLE) td_on(ENABLE) td_off(ENABLE) High-level input voltage, ENABLE Low-level input voltage, ENABLE Input pulldown resistance, ENABLE Turnon delay time, ENABLE Turnoff delay time, ENABLE VI(ENABLE) increasing above start threshold; 100 ns rise time, 20 mV overdrive (see Note 2) VI(ENABLE) decreasing below stop threshold; 100 ns fall time, 20 mV overdrive (see Note 2) TEST CONDITIONS
NOTE 2: Specified, but not production tested.
PREREG
PARAMETER VREG Vdrop_PREREG PREREG output voltage PREREG dropout voltage VI(IN1) = 3 V TEST CONDITIONS 4.5 VI(IN1) 13 V MIN 3.5 TYP 4.1 MAX 5.5 0.1 UNIT V V
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating temperature range (-40C < TA < 85C), 3 V VI(IN1) 13 V, 3 V VI(IN2) 5.5 V (unless otherwise noted) (continued)
VREG UVLO
PARAMETER VOT(UVLOstart) VOT(UVLOstop) Vhys(UVLO) Output threshold voltage, start Output threshold voltage, stop Hysteresis UVLO sink current, GATEx VI(GATEx) = 2 V TEST CONDITIONS MIN 2.75 2.65 50 10 TYP 2.85 2.78 75 MAX 2.95 UNIT V V mV mA
PWRGD1 and PWRGD2
PARAMETER VIT(ISENSEx) Vhys VO(sat)(PWRGDx) VO(VREGmin) IIB Ilkg(PWRGDx) tdr Trip threshold, VSENSEx Hysteresis voltage, power-good comparator Output saturation voltage, PWRGDx Minimum VO(VREG) for valid power-good Input bias current, power-good comparator Leakage current, PWRGDx Delay time, rising edge, PWRGDx IO = 2 mA IO = 100 A, VO(PWRGDx) = 1 V VI(VSENSEx) = 5.5 V VO(PWRGDx) = 13 V VI(VSENSEx) increasing, Overdrive = 20 mV, tr = 100 ns, See Note 2 VI(VSENSEx) decreasing, Overdrive = 20 mV, tr = 100 ns, See Note 2 25 TEST CONDITIONS VI(VSENSEx) decreasing MIN 1.2 20 TYP 1.225 30 0.2 MAX 1.25 40 0.4 1 1 1 UNIT V mV V V A A s
tdf
Delay time, falling edge, PWRGDx
2
s
NOTE 2: Specified, but not production tested.
FAULT output
PARAMETER VO(sat)(FAULT) Ilkg(FAULT) Output saturation voltage, FAULT Leakage current, FAULT TEST CONDITIONS IO = 2 mA VO(FAULT) = 13 V MIN TYP MAX 0.4 1 UNIT V A
DISCH1 and DISCH2
PARAMETER IDISCH VIH(DISCH) VIL(DISCH) Discharge current, DISCHx Discharge on high-level input voltage Discharge on low-level input voltage TEST CONDITIONS VI(DISCHx) = 1.5 V, VI(VIN1) = 5 V MIN 5 2 1 TYP 10 MAX UNIT mA V V
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
Load 12
Load 12 VI(ENABLE) 5 V/div VI(ENABLE) 5 V/div VO(GATE1) 10 V/div
VO(GATE1) 10 V/div
VO(DISCH1) 5 V/div
VO(DISCH1) 5 V/div t - Time - 10 ms/div
t - Time - 10 ms/div
Figure 1. Turnon Voltage Transition of Channel 1
Figure 2. Turnoff Voltage Transition of Channel 1
Load 5 VI(ENABLE) 5 V/div VI(ENABLE) 5 V/div
Load 5
VO(GATE2) 10 V/div
VO(GATE2) 10 V/div
VO(DISCH2) 5 V/div
VO(DISCH2) 5 V/div
t - Time - 10 ms/div
t - Time - 10 ms/div
Figure 3. Turnon Voltage Transition of Channel 2
Figure 4. Turnoff Voltage Transition of Channel 2
8
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
VI(ENABLE) 5 V/div
No Capacitor on Timer
VI(ENABLE) 5 V/div VO(GATE1) 10 V/div
No Capacitor on Timer
VO(GATE1) 10 V/div VO(FAULT) 10 V/div VO(FAULT) 10 V/div
IO(OUT1) 2 A/div
IO(OUT1) 2 A/div
t - Time - 5 ms/div
t - Time - 1 ms/div
Figure 5. Channel 1 Overcurrent Response: Enabled Into Overcurrent Load
Figure 6. Channel 1 Overcurrent Response: an Overcurrent Load Plugged Into the Enabled Board
VI(ENABLE) 5 V/div
No Capacitor on Timer VI(ENABLE) 5 V/div VO(GATE2) 10 V/div
No Capacitor on Timer
VO(GATE2) 10 V/div VO(FAULT) 10 V/div VO(FAULT) 10 V/div
IO(OUT2) 2 A/div t - Time - 2 ms/div
IO(OUT2) 2 A/div
t - Time - 0.5 ms/div
Figure 7. Channel 2 Overcurrent Response: Enabled Into Overcurrent Load
Figure 8. Channel 2 Overcurrent Response: an Overcurrent Load Plugged Into the Enabled Board
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
VI(ENABLE) 5 V/div
No Capacitor on Timer
VI(ENABLE) 5 V/div
No Capacitor on Timer
VO(GATE1) 10 V/div VO(FAULT) 10 V/div
VO(GATE2) 5 V/div VO(FAULT) 10 V/div
IO(IN1) 2 A/div
IO(IN2) 2 A/div
t - Time - 1 ms/div
t - Time - 1 ms/div
Figure 9. Channel 1 - Enabled Into Short Circuit
Figure 10. Channel 2 - Enabled Into Short Circuit
No Capacitor on Timer VI(IN1) 10 V/div
VI(IN1) 10 V/div VO(GATE1) 10 V/div
No Capacitor on Timer
VO(GATE1) 10 V/div VO(OUT1) 10 V/div VO(OUT1) 10 V/div IO(OUT1) 1 A/div IO(OUT1) 1 A/div
t - Time - 5 ms/div
t - Time - 1 ms/div
Figure 11. Channel 1 - Hot Plug
Figure 12. Channel 1 - Hot Removal
10
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
PARAMETER MEASUREMENT INFORMATION
No Capacitor on Timer VI(IN2) 5 V/div
VO(GATE2) 10 V/div
VO(OUT2) 5 V/div IO(OUT2) 1 A/div t - Time - 5 ms/div
Figure 13. Channel 2 - Hot Plug
VI(IN2) 5 V/div VO(GATE2) 10 V/div
No Capacitor on Timer
VO(OUT2) 5 V/div IO(OUT2) 1 A/div
t - Time - 1 ms/div
Figure 14. Channel 2 - Hot Removal
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT (ENABLED) vs VOLTAGE
52 IN2 = 5.5 V 51 I I1 - Input Current 1 - A 50 49 48 47 46 45 44 43 4 5 6 8 9 10 11 12 VI1 - Input Voltage 1 - V 7 13 14 68.5 68 2.5 TA = 0C TA = -40C TA = 25C TA = 85C I I2 - Input Current 2 - A 71 71.5 IN1 = 13 v TA = 0C TA = -40C 70.5 TA = 25C 70 TA = 85C 69.5 69
SUPPLY CURRENT (ENABLED) vs VOLTAGE
3
3.5 4 4.5 5 VI2 - Input Voltage 2 - V
5.5
6
Figure 15
SUPPLY CURRENT (DISABLED) vs VOLTAGE
15 IN2 = 5.5 V 14 TA = 25C I I1 - Input Current 1 - nA TA = -40C 12 TA = 0C 11 10 9 8 7 4 5 6 7 8 9 10 11 12 VI1 - Input Voltage 1 - V 13 14 I I2 - Input Current 2 - nA 13 19 17 15 13 11 9 7 5 2.5 3 TA = 85C 23
Figure 16
SUPPLY CURRENT (DISABLED) vs VOLTAGE
IN1 = 13 V 21 TA = 85C TA = -40C
TA = 0C TA = 25C
3.5 4 4.5 5 VI2 - Input Voltage 2 - V
5.5
6
Figure 17
Figure 18
12
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
TYPICAL CHARACTERISTICS
GATE1 VOLTAGE vs INPUT VOLTAGE
22 CL(GATE1) = 1000 pF VO - GATE1 Output Voltage - V 20 TA = 85C t r - GATE1 Voltage Rise Time - ms 15 18 IN1 = 12 V TA = 25C
GATE1 VOLTAGE RISE TIME vs GATE1 LOAD CAPACITANCE
TA = 25C TA = 0C TA = -40C
18
12
16
9
14
6
12
3
10 2 3 4 9 10 6 7 8 VI1 - Input Voltage1 - V 5 11 12
0 0 9 12 3 6 CL(GATE1) - GATE1 Load Capacitance - nF
Figure 19
GATE1 VOLTAGE FALL TIME vs GATE1 LOAD CAPACITANCE
4 IN1 = 12 V TA = 25C 3 I - GATE1 Current - A 15 14.5 14
Figure 20
GATE1 OUTPUT CURRENT vs GATE1 VOLTAGE
t f - GATE1 Voltage Fall Time - ms
TA = -40C 13.5 13 12.5 12 11.5 IN1 = 13 V
TA = 85C TA = 25C
2
TA = 0C
1
0 0 3 6 9 12 CL(GATE1) - GATE1 Load Capacitance - nF
11 14 15 16 17 18 19 20 21 V - GATE1 Voltage 22 23 24
Figure 21
Figure 22
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
TYPICAL CHARACTERISTICS
CIRCUIT BREAKER RESPONSE vs TIMER CAPACITANCE
12 t res - Circuit Braker Response Time - s IN1 = 12 V TA = 25C 9 320 280 240 200 160 120 80 40 0 0 0.8 0.2 0.4 0.6 C(timer) - TIMER Capacitance - nF 1 0 0 400 100 200 300 CL - Load Capacitance - F 500 IN1 = 12 V IO1 = 0 A TA = 25C
LOAD VOLTAGE 1 DISCHARGE TIME vs LOAD CAPACITANCE
6
3
Figure 23
UVLO START AND STOP THRESHOLDS vs TEMPERATURE
2.9 V ref - Reference Voltage UVLO Threshold - V VIT- Input Threshold Voltage PWRGDx - V 2.88 2.86 2.84 2.82 2.8 2.78 2.76 2.74 2.72 2.7 -45-35-25-15 -5 5 15 25 35 45 55 65 75 85 95 TA - Temperature - C Stop Start 1.27 1.26
t - Discharge Time - ms
Figure 24
PWRGDx THRESHOLD vs TEMPERATURE
Up
1.25 1.24 1.23 1.22 Down
1.21 1.20 -45-35-25 -15 -5 5 15 25 35 45 55 65 75 85 95 TA - Temperature - C
Figure 25
Figure 26
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
APPLICATION INFORMATION typical application diagram
This diagram shows a typical dual hot-swap application. The pullup resistors at PWRGD1, PWRGD2 and FAULT should be relatively large (e.g. 100 k) to reduce power loss unless they are required to drive a large load.
System 3 V 12 V IN1 Board RSENSE1 1 F 10 F RISET1 RVSENSE1_BOTTOM 0.1 F Vreg IN1 ISET1 ISENSE1 GATE1 DISCH1 VSENSE1 ENABLE ENABLE DGND AGND FAULT PWRGD1 PWRGD2 FAULT PWRGD1 PWRGD2 RVSENSE1_TOP + VO1
TPS2301
TIMER IN2 ISET2 ISENSE2 GATE2 DISCH2 VSENSE2
RISET2
VO1 or VO2
3 V 5 V IN2
1 F 10 F
RSENSE2
RVSENSE2_TOP
+
VO2
RVSENSE2_BOTTOM
Figure 27. Typical Dual Hot-Swap Application
input capacitor
A 0.1-F ceramic capacitor in parallel with a 1-F ceramic capacitor should be placed on the input power terminals near the connector on the hot-plug board to help stabilize the voltage rails on the cards. The TPS2300/01 does not need to be mounted near the connector or these input capacitors. For applications with more severe power environments, a 2.2-F or higher ceramic capacitor is recommended near the input terminals of the hot-plug board. A bypass capacitor for IN1 and for IN2 should be placed close to the device.
output capacitor
A 0.1-F ceramic capacitor is recommended per load on the TPS2300/01; these capacitors should be placed close to the external FETs and to TPS2300/01. A larger bulk capacitor is also recommended on the load. The value of the bulk capacitor should be selected based on the power requirements and the transients generated by the application.
external FET
To deliver power from the input sources to the loads, each channel needs an external N-channel MOSFET. A few widely used MOSFETs are shown in Table 1. But many other MOSFETs in the market can also be used with TPS23xx in hot-swap systems.
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
APPLICATION INFORMATION
Table 1. Some Available N-Channel MOSFETs
CURRENT RANGE (A) PART NUMBER IRF7601 0 to 2 MTSF3N03HDR2 IRF7101 MMSF5N02HDR2 IRF7401 2 to 5 MMSF5N02HDR2 IRF7313 SI4410 5 to 10 IRLR3103 IRLR2703 DESCRIPTION N-channel, rDS(on) = 0.035 , 4.6 A, Micro-8 N-channel, rDS(on) = 0.040 , 4.6 A, Micro-8 Dual N-channel, rDS(on) = 0.1 , 2.3 A, SO-8 Dual N-channel, rDS(on) = 0.04 , 5 A, SO-8 N-channel, rDS(on) = 0.022 , 7 A, SO-8 N-channel, rDS(on) = 0.025 , 5 A, SO-8 Dual N-channel, rDS(on) = 0.029 , 5.2 A, SO-8 N-channel, rDS(on) = 0.020 , 8 A, SO-8 N-channel, rDS(on) = 0.019 , 29 A, d-Pak N-channel, rDS(on) = 0.045 , 14 A, d-Pak MANUFACTURER International Rectifier ON Semiconductor International Rectifier ON Semiconductor International Rectifier ON Semiconductor International Rectifier Vishay Dale International Rectifier International Rectifier
timer
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. This capacitor should be connected between TIMER and ground. The presence of an overcurrent condition on either channel of the TPS2300/01 causes a 50-A current source to begin charging this capacitor. If the overcurrent condition persists until the capacitor has been charged to approximately 0.5 V, the TPS2300/01 will latch off the offending channels and will pull the FAULT pin low. The timer capacitor can be made as large as desired to provide additional time delay before registering a fault condition.
output-voltage slew-rate control
When enabled, the TPS2300/01 controllers supply the gates of each external MOSFET transistor with a current of approximately 15 A. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain capacitance Cgd of the external MOSFET capacitor to a value approximating: dvs dt
+ 15 mA C
gd
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external MOSFET and ground.
VREG capacitor
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-F or 0.22-F ceramic capacitor is recommended.
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SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
APPLICATION INFORMATION gate drive circuitry
The TPS2300/01 includes four separate features associated with each gate-drive terminal:
D D D D
A charging current of approximately 15 A is applied to enable the external MOSFET transistor. This current is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH1 or DISCH2) of 9 V-12 V. DISCH1 and DISCH2 must be connected to the respective external MOSFET source terminals to ensure proper operation of this circuitry. A discharge current of approximately 75 A is applied to disable the external MOSFET transistor. Once the transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while ensuring that the gates of the external MOSFET transistors remain at a low voltage. During a UVLO condition, the gates of both MOSFET transistors are pulled down by internal PMOS transistors. These transistors continue to operate even if IN1 and IN2 are both at 0 V. This circuitry also helps hold the external MOSFET transistors off when power is suddenly applied to the system. During an overcurrent fault condition, the external MOSFET transistor that exhibited an over-current condition will be rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) from the pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLO driver is enabled instead. If one channel experiences an overcurrent condition and the other does not, then only the channel that is conducting excessive current will be turned off rapidly. The other channel will continue to operate normally.
setting the current-limit circuit-breaker threshold
Using channel one as an example, the current sensing resistor RISENSE1 and the current limit setting resistor RISET1 determine the current limit of the channel, and can be calculated by the following equation: I LMT1
+ RISET1 R
50
10 -6
ISENSE1
Typically RISENSE1 is usually very small (0.001 to 0.1 ). If the trace and solder-junction resistances between the junction of RISENSE1 and ISENSE1 and the junction of RISENSE1 and RISET1 are greater than 10% of the RISENSE1 value, then these resistance values should be added to the RISENSE1 value used in the calculation above. The above information and calculation also apply to channel 2. Table 2 shows some of the current sense resistors available in the market. Table 2. Some Current Sense Resistors
CURRENT RANGE (A) 0 to 1 1 to 2 2 to 4 4 to 6 6 to 8 8 to 10 PART NUMBER WSL-1206, 0.05 1% WSL-1206, 0.025 1% WSL-1206, 0.015 1% WSL-2010, 0.010 1% WSL-2010, 0.007 1% WSR-2, 0.005 1% DESCRIPTION 0.05 , 0.25 W, 1% resistor 0.025 , 0.25 W, 1% resistor 0.015 , 0.25 W, 1% resistor 0.010 , 0.5 W, 1% resistor 0.007 , 0.5 W, 1% resistor 0.005 , 0.5 W, 1% resistor Vishay Dale MANUFACTURER
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
APPLICATION INFORMATION setting the power good threshold voltage
The two feedback resistors RVSENSEx_TOP and RVSENSEx_BOT connected between VOx and ground form a resistor divider setting the voltage at the VSENSEx pins. VSENSE1 voltage equals to VI(SENSE1) = VO x RVSENSE1_BOT/(RVSENSE1_TOP + RVSENSE1_BOT) This voltage is compared to an internal voltage reference (1.225 V 2%) to determine whether the output voltage level is within a specified tolerance. For example, given a nominal output voltage at VO1, and defining VO1_min as the minimum required output voltage, then the feedback resistors are defined by: R VSENSE1_TOP
+
V O1_min
* 1.225
1.225
R VSENSE1_BOT
Start the process by selecting a large standard resistor value for RVSENSE1_BOT to reduce power loss. Then RVSENSE1_TOP can be calculated by inserting all of the known values into the equation above. When VO1 is lower than VO1_min, PWRGD1 will be low as long as the controller is enabled.
undervoltage lockout (UVLO)
The TPS2300/01 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on the VREG pin. This feature will disable both external MOSFETs if the voltage on VREG drops below 2.78 V (nominal) and will re-enable normal operation when it rises above 2.85 V (nominal). Since VREG is fed from IN1 through a low-dropout voltage regulator, the voltage on VREG will track the voltage on IN1 within 50 mV. While the undervoltage lockout is engaged, both GATE1 and GATE2 are held low by internal PMOS pulldown transistors, ensuring that the external MOSFET transistors remain off at all times, even if all power supplies have fallen to 0 V.
single-channel operation
Some applications may require only a single external MOS transistor. Such applications should use GATE1 and the associated circuitry (IN1, ISENSE1, ISET1, DISCH1). The IN2 pin should be grounded to disable the circuitry associated with the GATE2 pin. The VSENSE2 and PWRGD2 circuitry is unaffected by disabling GATE2, and may still be used if so desired.
power-up control
The TPS2300/01 includes a 500 s (nominal) startup delay that ensures that internal circuitry has sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only upon the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout circuitry will provide adequate protection against undervoltage operation.
3-channel hot-swap application
Some applications require hot-swap control of up to three voltage rails, but may not explicitly require the sensing of the status of the output power on all three of the voltage rails. One such application is device bay, where dv/dt control of 3.3 V, 5 V, and 12 V is required. By using channel 2 to drive both the 3.3-V and 5-V power rails and channel 1 to drive the 12-V power rail, as is shown below, TPS2300/01 can deliver three different voltages to three loads while monitoring the status of two of the loads.
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SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
APPLICATION INFORMATION
System 12 V IN1 Board RSENSE1 1 F 10 F RISET1 RVSENSE1_BOTTOM 0.1 F Vreg IN1 ISET1 ISENSE1 GATE1 DISCH1 VSENSE1 ENABLE ENABLE DGND AGND FAULT PWRGD1 PWRGD2 FAULT PWRGD1 PWRGD2 RVSENSE1_TOP + VO1
TPS2301
TIMER IN2 ISET2 ISENSE2 GATE2 DISCH2 VSENSE2
RISET2
Rg1
VO1 or VO2
3.3 V IN2
1 F 10 F
RSENSE2 Rg2
RVSENSE2_TOP
+
VO2
RVSENSE2_BOTTOM
5 V IN3
1 F 10 F
+
VO3
Figure 28. Three-Channel Application Figure 29 shows ramp-up waveforms of the three output voltages.
VO1 VO - Output Voltage - 2 V/div
VO3 VO2
t - Time - 2.5 ms/div
Figure 29
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TPS2300, TPS2301 DUAL HOT SWAP POWER CONTROLLERS WITH INDEPENDENT CIRCUIT BREAKER AND POWER-GOOD REPORTING
SLVS265C - FEBRUARY 2000 - REVISED JULY 2000
MECHANICAL DATA
PW (R-PDSO-G**)
14 PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65 14 8
0,30 0,19
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX
8
14
16
20
24
28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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