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TC9495F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9495F
Digital Servo Single Chip Processor Built in 1 Bit DA Converter
The TC9495F is a single chip processor which incorporates the following function: synchronous separation protection and interpolation, EFM demodulation, Error correction, micro controller interface, digital equalizer for use in servo LSI and servo control circuit. In addition, the TC9495F incorporates a 1 bit DA converter. In combination with the head amplifier TA2109F, TA2150FN, TA2153FN for digital servo, the TC9495F allow simplified, adjustment-free structuring of CD player system.
Features
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * Capable of decode the text data. Built in EFM demodulation circuit, subcode demodulation circuit. Capable of correcting dual C1 correction and quadruple C2 correction using the CIRC correction theoretical format. The TC9495F respond to variable playback system. Jitter absorbing capacity of 6 frames. Built in 16 KB RAM. Built in digital out circuit. Built in L/R independent digital attenuator. Audio output responds to bilingual function. Reed timing free subcode Q data and capable of synchronous output with audio data. Built in data slicer and analog PLL (free-adjustment VCO). Capable of automatic adjustment function of focus servo and tracking servo, for loop gain, offset and balance. Built in RF gain automatic adjustment circuit. Built in digital equalizer for phase compensation. Built in RAM for digital equalizer for coefficient, and capable of variable pickup. Built in focus, tracking servo control circuit. Search control corresponds to every mode and can realize high speed and stable search. Lens-kick and feed-kick are using speed controlled form. Built in AFC circuit and APC circuit for CLV servo of disc motor. Built in anti-defect and anti-shock circuit. Built in 8 times over sampling digital filter and 1 bit DA converter. Built in analog filter for 1 bit DA converter. Output format for audio out can be selected 32 fs, 48 fs, or 64 fs modes. Built in zero data detect output circuit. The TC9495F capable of 4 times speed operation. Built in micro controller interface circuit. CMOS silicon structure and high speed, low power consumption. 100 pin flat package. Weight: 1.6 g (typ.) Sync pattern detection, sync signal protection and synchronization can be made correctly.
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TC9495F
Block Diagram (top view)
VDD
FLGD
FLGC FLGB
FLGA SEL
VDD
PXO PXI
VSS
TESIO1 TESIN
IO2
IO1
DACT
IO3
IO0
CKSE
DMOUT
2VREF
DMO FVO
FMO
TEBC 52 51
XVSS
XVDD
XO
80
79 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 53
XI
VSS
78
77
54
DVSR 81 Servo 1 bit DAC control Clock generator PWM D/A
RFGC
50 VREF 49 TRO 48 FOO 47 TEZI 46 TEI 45 TSIN ROM Digital equalizer A/D Address circuit RAM Automatic adjustment circuit 44 SBAD 43 FEI 42 RFRP 41 RFZI 40 RFCT 39 AVDD CLV servo 16 KRAM Data slicer 38 RFI 37 SLCO 36 AVSS 35 VCOF VCO Audio out circuit Digital out Sub code decoder status PLL TMAX 34 VCOREF 33 PVREF 32 LPFO 31 LPFN Correction circuit
RO 82
DVDD 83
LPF
DVR 84
LO 85
DVSL 86
TEST1 87
TEST2 88
TEST3 89
BUS0 90
BUS1 91
BUS2 92
Micon interface
BUS3 93
VDD 94 Synchronous guarantee EFM decode
VSS 95
BUCK 96
CCE 97
TEST4 98
TSMOD 99
RST 100
1 VSS BCK LRCK AOUT DOUT
2
3
4
5
6
7
8
9
10 MBOV
11 IPF
12 SBOK
13 CLCK
14 VDD
15 VSS
16 DATA
17 SFSY
18 SBSY
19 SPCK
20 SPDA
21 COFS
22 MONIT
23 VDD
24 TESIO0
25 P2VREF
26 HSSW
27 ZDET
28 PDO
29 TMAXS
30 TMAX
HSO
UHSO
TEST0
EMPH
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Pin Function
Pin No. 1 Symbol TEST0 I/O I Functional Description Test mode terminal. Normally, keep at open. Playback speed mode flag output terminal. 2
HSO
Remarks With pull-up resistor.
O
UHSO
HSO
Playback Speed Normal 2 times 4 times 3/4 3/4
H H L 3
UHSO
H L H L
O
L
Subcode Q data emphasis flag output terminal. 4 EMPH O Emphasis ON at "H" level and OFF at "L" level. The output polarity can invert by command. Channel clock output terminal. (44.1 kHz) 5 LRCK O 3/4 O L-ch at "L" level and R-ch at "H" level. The output polarity can invert by command. Digital GND terminal. Bit clock output terminal. 7 BCK Output is selectable 1.4112 MHz, 2.1168 MHz or 2.8224 MHz. Audio data output terminal. Digital data output terminal. Buffer memory over signal output terminal. 10 MBOV O Over at "H" level. Correction flag output terminal. 11 IPF O At "H" level, AOUT output is made to correction impossibility by C2 correction processing. Subcode Q data CRCC check adjusting result output terminal. The adjusting result is OK at "H" level. Subcode P~W data readout clock input/output terminal. 13 14 15 16 17 18 19 20 21 CLCK VDD VSS DATA SFSY SBSY SPCK SPDA COFS I/O This terminal can select by command bit. 3/4 3/4 O O O O O O (7.35 kHz) Internal signal (DSP internal flag and PLL clock) output terminal. Selected by command. This terminal output the text data with serial by command. 23 VDD TESIO0 3/4 I Digital power supply voltage terminal. Test input/output terminal. Normally, keep at "L" level. 24 The terminal that inputted the clock for read of text data by command. 3/4 3/4 Digital power supply voltage terminal. Digital GND terminal. Subcode P~W data output terminal. Play-back frame sync signal output terminal. Subcode block sync signal output terminal. Processor status signal readout clock output terminal. Processor status signal output terminal. Correction frame clock output terminal. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
6
VSS
8 9
AOUT DOUT
O O
12
SBOK
O
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
22
MONIT
O
3/4
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Pin No. 25 26 27 28 Symbol P2VREF HSSW ZDET PDO I/O 3/4 O O O Functional Description PLL double reference voltage supply terminal. 2-state output. 2/4 times speed at "VREF" voltage. 1 bit DA converter zero detect flag output terminal. Phase difference signal output terminal of EFM signal and PLCK signal. TMAX detection result output terminal. Selected by command bit (TMPS). TMAX detection result output terminal. Selected by command bit (TMPS). Difference Result 30 TMAX O Longer than fixed freq. Shorter than fixed freq. Within the fixed freq. TMAX Output 3-state output. "P2VREF" "VSS" "HiZ" (P2VREF, HiZ, VSS) 3-state output. (P2VREF, PVREF, VSS) 3-state output. (P2VREF, PVREF, VSS) (PVREF, HiZ) 3/4 Remarks 3/4
29
TMAXS
O
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
LPFN LPFO PVREF VCOREF VCOF AVSS SLCO RFI AVDD RFCT RFZI RFRP FEI SBAD TSIN TEI
I O 3/4 I
LPF amplifier inverting input terminal for PLL. LPF amplifier output terminal for PLL. PLL reference voltage supply terminal. VCO center frequency reference level terminal. Normally, keep at "PVREF" level.
Analog input. Analog output. 3/4 3/4 Analog output. 3/4 Analog output. Analog input.
O 3/4 O I 3/4 I I I I I I I
VCO filter terminal. Analog GND terminal. Data slice level output terminal. RF signal input terminal.
(Zin: selected by command) Analog power supply voltage terminal. Analog input. RFRP signal center level input terminal. (Zin: 50 kW) RFRP zero cross input terminal. RF ripple signal input terminal. Focus error signal input terminal. Sub-beam adder signal input terminal. Test input terminal. Normally, keep at "VREF" level. Tracking error signal input terminal. Analog input. Take in at tracking servo on. Analog input. 47 48 49 50 51 52 53 54 TEZI FOO TRO VREF RFGC TEBC FMO FVO I O O 3/4 O O O O Tracking error zero cross input terminal. (Zin: 10 kW) Focus servo equalizer output terminal. Tracking servo equalizer output terminal. Analog reference voltage supply terminal. RF amplitude adjustment control signal output terminal. Tracking balance control signal output terminal. Feed equalizer output terminal. Speed error signal or feed search equalizer output terminal. 3-state output. (2VREF, VREF, VSS) 3/4 3/4 Analog output. (2VREF~AVSS) 3/4 Analog input. Analog input. Analog input. Analog input. Analog input. 3/4
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Pin No. 55 56 Symbol DMO 2VREF SEL I/O O 3/4 O Functional Description Disk equalizer output terminal. (PWM carrier = 88.2 kHz for DSP, Synchronize to PXO) Analog double reference voltage supply terminal. APC circuit ON/OFF indication signal output terminal. 57 At the laser on time, UHF = L at "HiZ" level and UHF = H at "H" level. Extemal flag output terminal for internal signal. 58 FLGA O Can select signal from TEZC, FOON , FOK and RFZC by command. Extemal flag output terminal for internal signal. 59 FLGB O Can select signal from DFCT , FOON , FMON and RFZC by command. Extemal flag output terminal for internal signal. 60 FLGC O Can select signal from TRON , TRSR , FOK and SRCH by command. Extemal flag output terminal for internal signal. 61 FLGD O 3/4 3/4 Can select signal from TRON , DMON , HYS and SHC by command. Digital power supply voltage terminal. Digital GND terminal. General I/O terminal. Can change over input port or output port by command. At the input mode time can readout a state of terminal (H/L) by read command. At the output mode time can control a state of terminal (H/L/HiZ) by command. This terminal controls IO0~IO3 terminal. 68
DMOUT
Remarks 3/4 3/4 3/4
3/4
3/4
3/4
3/4 3/4 3/4
62 63 64 65 66 67
VDD VSS IO0 IO1
I/O IO2 IO3
3/4
I
At "L" level time, IO0, 1 out feed equalizer signal of 2-state PWM, IO2, 3 out disk equalizer signal of 2-state PWM. Normally, keep at open. DAC test mode terminal. Normally, keep at open. Test input terminal. Normally, keep at "L" level. Test input/output terminal. Normally, keep at "L" level. Digital GND terminal. Crystal oscillator connecting input terminal for DSP.
With pull-up resistor.
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87
CKSE DACT
I I I I 3/4 I
With pull-up resistor. With pull-up resistor. Analog input. 3/4 3/4
TESIN TESIO1 VSS PXI PXO VDD XVSS XI XO XVDD DVSR RO DVDD DVR LO DVSL TEST1
Normally, keep at "L" level. O 3/4 3/4 I O 3/4 3/4 O 3/4 3/4 O 3/4 I Crystal oscillator connecting output terminal for DSP. Digital power supply voltage terminal. Oscillator GND terminal for system clock. Crystal oscillator connecting input terminal for system clock. Crystal oscillator connecting output terminal for system clock. Oscillator power supply voltage terminal for system clock. Analog GND terminal for DA converter. (R-ch) R channel data forward output terminal. Analog supply voltage terminal for DA converter. Reference voltage terminal for DA converter. L channel data forward output terminal. Analog GND terminal for DA converter. (L-ch) Test mode terminal. Normal, keep at open.
Analog input.
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 With pull-up resistor.
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Pin No. 88 89 90 91 92 93 94 95 96 Symbol TEST2 TEST3 BUS0 BUS1 BUS2 BUS3 VDD VSS BUCK I/O I I I/O I/O Micon interface data input/output terminal. I/O I/O 3/4 I Digital power supply voltage terminal. Digital GND terminal. Micon interface clock input terminal. Command and data sending/receiving chip enable signal input terminal. The bus line becomes active at "L" level. 98 99 100 TEST4
TSMOD RST
Functional Description Test mode terminal. Normal, keep at open. Test mode terminal. Normal, keep at open.
Remarks With pull-up resistor. With pull-up resistor.
Schmit input. CMOS port.
3/4 3/4 Schmit input.
97
CCE
I
Schmit input.
I I I
Test mode terminal. Normal, keep at open. Local test mode selection terminal. Reset signal input terminal. Reset at "L" level.
With pull-up resistor. With pull-up resistor. With pull-up resistor.
Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage Input voltage Power dissipation Operating temperature Storage temperature Symbol VDD VIN PD Topr Tstg Rating -0.3~6.0 -0.3~VDD + 0.3 1420 -40~85 -55~150 Unit V V mW C C
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Electrical Characteristics
(unless otherwise specified, VDD = AVDD = DVDD = XVDD = 5 V, 2VREF = P2VREF = 4.2 V, VREF = PVREF = 2.1 V, Ta = 25C) DC Characteristics
Characteristics Assured supply voltage Symbol VDD Test Circuit 3/4 Test Condition Ta = -40~85C Normal speed 4 times speed XI = 16.9344 MHz Min 4.5 45 50 3.5 3/4 4.0 Schmit input terminal VIH = 5 V VIL = 0 V VIH = 5 V VIL = 0 V CMOS Input Terminal (except analog input) following (1) 3/4 3/4 -1.0 3/4 -0.1 3/4 2.0 3/4 2.0 following (3) -1.4 0.6 following (4) 3/4 2.0 following (6) 3/4 4.0 3/4 25.0 Typ. 5.0 50 55 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 50.0 Max 5.5 60 mA 65 3/4 1.5 3/4 1.0 1.0 mA 3/4 0.1 3/4 -1.0 3/4 -1.0 3/4 -0.6 1.4 -1.0 3/4 -2.0 3/4 500 75.0 W kW mA mA V Unit V
Assured supply current
IDD
3/4
"H" Level "L" Level Input voltage "H" Level "L" Level "H" Level Input current "L" Level "H" Level Tri-state leak current "L" Level "H" Level "L" Level "H" Level "L" Level Output current "H" Level "L" Level "H" Level "L" Level "H" Level "L" Level VREF output ON resistor Pull-up resistor
VIH (1) VIL (1) VIH (2) VIL (2) IIH IIL ITLH ITLL IOH (1) IOL (1) IOH (2) IOL (2) IOH (3) IOL (3) IOH (4) IOL (4) IOH (5) IOL (5) RON RUP
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
CMOS Input Terminal (except analog input)
VOH = 4.6 V following (1) (except TMAXS, VOL = 0.4 V TMAX) VOH = 4.6 V VOH = 0.4 V VOH = 4.6 V VOL = 0.4 V VOH = 3.8 V VOL = 0.4 V VOH = 3.8 V VOL = 0.4 V following (4) (except TMAXS, TMAX) following (5) following (2)
Terminal Name
HSO , UHSO , EMPH, DOUT, MBOV, IPF, SBOK, CLCK, TESIO1
(1) Terminal
DATA, SFSY, SBSY, SPCK, MONIT, TESIO0, TMAXS, TMAX, SEL FLGA, FLGB, FLGC, FLGD, IO0, IO1, IO2, IO3
(2) Terminal (3) Terminal (4) Terminal (5) Terminal (6) Terminal
LRCK, SPDA, COFS, ZDET BUS0~3 PDO, TMAXS, TMAX, RFGC, TEBC, FMO, FVO, DMO
DMOUT , CKSE , DACT , TSMOD, RST , TEST0~4
BCK, AOUT
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AC Characteristics 1. Microcomputer Interface Timing
Characteristics
CCE "H" clock pulse width CCE status data access time
Symbol tCC tCS tSZ1 tCB tBLW tBLW
Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Test Condition 3/4
CCE falling reference CCE rising reference CCE falling reference
Min 120 0 0 0 120 240 120 3000 1500 800 60 20 0 0 0 0
Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Max 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Unit
Status data disable time
CCE , BUCK delay pulse width
Write, SRC mode QDRC mode Write, SRC mode QDRC mode (1) QDRC mode (2) QDRC mode (4) BUCK rising reference BUCK rising reference BUCK falling reference BUCK falling reference BUCK falling reference BUCK rising reference
BUCK "L" clock pulse width BUCK "H" clock pulse width (1) BUCK "H" clock pulse width (2) BUCK "H" clock pulse width (3) BUCK "H" clock pulse width (4) Write data set-up time Write data hold time PRTY data access time Data disable time Read data access time Data disable time
tBHW tBHW tBHW tBHW tWS tWH tBA tSZ2 tRD tSZ3
ns
(1)
Idle mode
CCE
tCC
BUCK
BUSi
BUSi (output)
ST tCS Idol mode tSZ1
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(2) Write command mode
tCC CCE tBLW tBHW BUCK tCB BUSi (input) tCS BUSi (output) ST Idol mode Write mode tWS tWH CM tSZ2 CL DM DL tBA PRTY tSZ3
(3)
BXXXXX, FXXXXX command at
tCC
CCE tBLW tBHW BUCK tCB BUSi (input) tCS BUSi (output) ST tWS tWH CM tSZ2 CL DM DL EM EL tBA tSZ3 PRTY
(4)
Read command mode
tCC
CCE tBLW tBHW BUCK tCB BUSi (input) tCS BUSi (output) ST Idol mode tWS tWH CM tSZ2 tRD tSZ3 RD0 Write mode tBA RDn PRTY tSZ3
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2. AOUT Terminal Output Data Timing
Characteristics Transfer time (1) "H" Level "L" Level Symbol tpLH tpHL Test Circuit 3/4 Test Condition BCK (R) AOUT Min 3/4 3/4 Typ. 3/4 3/4 Max 5 5 Unit ns
BCK tpHL tpLH AOUT
3. SPDA Output Timing
Characteristics Transfer time "H" Level "L" Level Symbol tpLH tpHL Test Circuit 3/4 Test Condition SPCK (R) SPDA Min 3/4 3/4 Typ. 3 3 Max 3/4 3/4 Unit ns
SPCK
SPDA tpHL tpLH
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4. DATA, CLCK Input/Output Timing
(1) CLCK input mode
Characteristics Clock pulse width Input set-up time Transfer time (1) Transfer time (2) "L" Level "L" Level "H" Level "H" Level "L" Level Symbol tHW tLW tSu tpHL1 tpLH2 tpHL2 tpHL2 tpLH2 3/4 CLCK input mode Test Circuit Test Condition Min 200 200 200 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 Max 3/4 3/4 3/4 5 20 20 ns Unit
tpHL1 SFSY/COFS tSU CLCK tHW
tLW
DATA
SUBP
SUBQ
(2)
CLCK output mode (tHW, tLW, tpLH3; 2 times speed = 1/2, 4 times speed = 1/4)
Characteristics Symbol tHW tLW tpHL1 tpLH2 tpHL2 tpLH3 tpHL2 tpLH2 3/4 CLCK output mode Test Circuit Test Condition Min 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 Max 1000 1000 5 20 20 900 ns Unit
Clock pulse width Transfer time (1) Transfer time (2)
"H" Level "L" Level "L" Level "H" Level "L" Level
Transfer time (3)
"H" Level
tpHL1 SFSY/COFS tpLH3 CLCK tHW
tLW
DATA
SUBP
SUBQ
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5. SBSY, SBOK Input/Output Control
Characteristics Transfer time (1) "H" Level "L" Level "H" Level Transfer time (2) "L" Level Symbol tpLH1 tpHL1 tpLH2 tpHL2 Test Circuit 3/4 SBSY Test Condition Min 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 Max 5 5 15 15 ns Unit
3/4
SBOK
SFSY/COFS
tpLH1 SBSY
tpHL1
SBOK
tpLH2 tpHL2
6. Output Terminal Timing
Characteristics Output rising time (1) Output falling time (1) Output rising time (2) Output falling time (2) Output rising time (3) Output falling time (3) Output rising time (4) Symbol tor1 tof1 tor2 tof2 tor3 tof3 tor4 3/4 Output falling time (4) tof4 Terminal (4) Test Circuit 3/4 Test Condition Terminal (1) Min 3/4 3/4 3/4 3/4 3/4 3/4 VREF (R) 2VREF VSS (R) VREF 2VREF (R) VREF VREF (R) VSS 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 20 15 20 15 20 15 20 10 15 10 ns Unit
3/4
Terminal (2)
3/4
Terminal (3)
Terminal Name (1) Terminal (2) Terminal (3) Terminal (4) Terminal AOUT, BCK, COFS, LRCK BUS0, BUS1, BUS2, BUS3, CLCK DATA, DOUT, EMPH, FLGA, FLGB, FLGC, FLGD, HSO , IO0, IO1 IO2, IO3, IPF, MONIT, MBOV, SBOK, SBSY, SEL, SFSY, SPCK, UHSO PDO, TMAXS, TMAX, RFGC, TEBC, FMO, DMO, FVO
VOH VOH/2 VSS tor tof
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Analog Circuit Characteristics 1. A/D Converter
Characteristics Resolution FE TE Sampling frequency SBAD RFRP Conversion input range 3/4 Ex. VSS = 0 V, 2VREF = 4.2 V 3/4 XI = 16.9344 MHz Test Circuit 3/4 Test Condition 3/4 Min 3/4 3/4 3/4 3/4 3/4 0.15 2VREF Typ. 8 176.4 176.4 88.2 176.4 3/4 Max 3/4 3/4 3/4 3/4 3/4 0.85 2VREF V kHz Unit bit
2. D/A Converter (focus, tracking equalizer output)
Characteristics Bit number Sampling frequency Output signal range Test Circuit 3/4 3/4 3/4 Test Condition 3/4 3/4 3/4 Min 3/4 3/4 AVSS Typ. 5 2.8 3/4 Max 3/4 3/4 2VREF Unit bit MHz V
3. PLL Filter Amp.
Characteristics Input/output signal range Frequency characteristics Test Circuit 3/4 3/4 Test Condition 3/4 -3 dB point, RNF = 15 kW Min VSS 2 Typ. 3/4 4 Max 2VREF 3/4 Unit V MHz
4. VCO (PLL)
Characteristics Center oscillation frequency Test Circuit 3/4 3/4 Frequency variation range 3/4 VCOREF terminal input voltage range upper limit lower limit 3/4 Test Condition LPFO = VREF, VCOREF = VREF VCOREF = VREF, VCOGSL = "H" VCOREF = VREF, VCOGSL = "L" VREF reference Min 3/4 40 3/4 3/4 -0.5 Typ. 34.6 50 40 3/4 3/4 Max 3/4 3/4 % 3/4 1.0 3/4 V Unit MHz
5. TEZI Signal Comparator
Characteristics Input range Input amplitude Hysteresis voltage Test Circuit 3/4 3/4 3/4 Test Condition 3/4 3/4 VREF reference Min VSS 1.0 3/4 Typ. 3/4 3/4 100 Max 2VREF 3.5 3/4 Unit V Vp-p mV
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6. RFZI Signal Comparator
Characteristics Input range Input amplitude Hysteresis voltage Test Circuit 3/4 3/4 3/4 Test Condition 3/4 3/4 VREF reference (no external register to RFCT terminal) Min VSS 1.0 3/4 Typ. 3/4 3/4 100 Max 2VREF 3.5 3/4 Unit V Vp-p mV
7. Data Slicer Circuit
Characteristics (comparator) Input amplitude Response time (R-2R DAC) Output conversion range Output impedance 3/4 3/4 3/4 3/4 1.58 3/4 3/4 2.5 2.59 3/4 V kW 3/4 3/4 VREF reference RFI = 0.6 Vp-p, f = 700 kHz 3/4 30 1.2 60 2.0 90 Vp-p ns Test Circuit Test Condition Min Typ. Max Unit
8. PWM Converter Output (RFGC, TEBC, FMO, FVO, DMO)
Characteristics PWM accuracy Sampling frequency Output signal range Test Circuit 3/4 3/4 3/4 Test Condition 3/4 3/4 3/4 Min 3/4 3/4 AVSS Typ. 8 88.2 3/4 Max 3/4 3/4 2VREF Unit bit kHz V
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DAC Characteristics
Characteristics Total harmonic distortion + noise S/N ratio Dynamic range Cross talk Analog output amplitude Symbol THD + N S/N DR CT DAC out Test Circuit 1 1 1 1 1 Test Condition 1 kHz sine wave, full scale input, PXI = "L" PXI = "L" 1 kHz sine wave, -60dB input conversion 1 kHz sine wave, full scale input, PXI = "L" 1 kHz sine wave, full scale input, PXI = "L" Min 3/4 90 85 3/4 1.12 Typ. -85 100 90 -90 1.20 Max -80 3/4 3/4 -85 1.28 Unit dB dB dB dB Vrms
Test Circuit 1: Application Circuit is Used.
TC9495F Application circuit LOUT ROUT
20 kHz ideal LPF
Distortion meter
LPF: SHIBASOKU 725C Distortion meter: SHIBASOKU 725C
Characteristics THD + N, CT S/N, DR
Distortion Filter Setting: A-wait OFF ON
A-WAIT: IEC-A (corresponding)
Application Circuit
TC9495F 5V XVDD XI XO XVSS DVSR RO DVDD DVR LO PXI DVSL 100 mF 0.1 mF 270 W 3.3 mF 2200 pF L-ch Analog out 10 k9 270 W 5V 3.3 mF 2200 pF R-ch Analog out 10 k9
16.9344 MHz
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Package Dimensions
Weight: 1.6 g (typ.)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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