 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ICs for Communication Equipment AN6591FJM Transmission / reception, single chip PLL IC for PHS, cordless telephone AN6591FJM is a single chip IC optimum for PHS, and a quadrature modulator, reception IF and PLL are integrated in it. As this IC is housed in a QFN package (quad flat nonleaded PKG), realization of compact equipment through this super-small package is possible. 0. 50 Overview 33 34 23 22 3C 6.200.10 (6.00) Unit: mm 44 R0.30 1 11 12 Features * Transmission and reception PLL block on a single chip * Transmission block: A quadrature modulator, a phase shifter APC (auto power control) and an up-converter * Reception block: A down-mixer (to 300 MHz), an IF amplifier and an RSSI circuit * PLL block: PLLs for 1st and 2nd local oscillators. * 6 mm x 6 mm small package 5.000.10 0.10 5.000.10 (1.10) 1 11 12 Seating plane 34 33 0.40 23 22 (0.48) 0.10 M 0.160.06 QFN044-P-0606A (Lead-free package) Applications * PHS, digital cordless telephone, etc. (1.10) (0.48) 44 0.200.10 0.80 max. 6.200.10 (6.00) Publication date: October 2002 SDM00007BEB 1 AN6591FJM Application Circuit Example fREFIN Controller LD 5 F VCC LPF2 Data Clock LD PSRF PSIF 1 000 pF 33 32 31 30 29 28 27 26 25 24 23 STROBE 34 35 23-bit shift register IO 1st R counter latch 14-bit 1st R counter 2nd charge pump 2nd phase comparator 50 kHz 2nd R counter (384) 2nd N counter (291) A counter (7) 2nd prescaler (1 / 16, 1 / 17) IO 22 21 20 19 18 17 VCC LPF1 36 1st charge pump 300 kHz 1st phase comparator 18-bit 1st A / N counter 1st N counter latch Lock detection VCC 37 38 39 40 IO 1st prescaler VCO2 fIFIN VCO1 100 pF 1 000 pF fRFIN 0 0 VCC1 16 1 k 1 649.7 MHz to 1 686.3 MHz 560 560 47 Lo1 I 100 pF 1 k 41 2 200 pF IO 15 14 13 12 4 700 pF I 100 pF 1 k VCC1 1 000 pF 5 F 42 43 Q 100 pF 1 k P0 Q 100 pF 1 000 pF 44 IO IO RSSI 10 22 nF 0 47 100 pF 223.15 MHz 100 pF 47 330 22 nF 2 200 pF 2 200 pF 100 pF 5 F 2 200 pF 330 47 11 560 pF 1 2 3 4 5 6 7 8 VMI 47 Lo3 9 VLM 1 000 pF Ceramic MIXO filter (Maker: Murata) VCC2 VS Lo2 223.15 MHz VLI 2 SDM00007BEB AN6591FJM Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol RXMXIN RXLOIN VCC2 MXO LMDEC1 LMIN LMDEC2 VCC2 LMO TXLO2 RSO GND Q-in Q-in I-in I-in VCC1 GNDM IFIN N.C. GND2 VCC Description RX mix. in RX local in VCC mix. Mix. out Lim. decouple1 Lim. in Lim. decouple2 VCC lim. Lim. out TX local2 in RSSI out GND Q-input Q-input I-input I-input VCC TX mod. GND TX mod. 2nd prescaler in GND 2nd CMOS VCC 1st 2nd BIP Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol N.C. N.C. N.C. VCC CP2 PSIF PSRF Ref. LD Clock Data STROBE GND CP1 VCC RFIN TXLO1 TXLO1R APC / BS VCC1 TXO GNDO VCC 2nd CMOS 2nd charge pump out 2nd power save in 1st power save in Reference in Lock detect out Clock in Serial data in Strobe in GND 1st / 2nd CMOS 1st charge pump out VCC 1st CMOS 1st prescaler in TX local 1 TX local 1ref. APC / BS VCC TX out TX output GND TX out Description Absolute Maximum Ratings Parameter Supply voltage Symbol VCC VCC1 VCC2 ICC *2 *1 Rating 3.5 Unit V Supply current *2 Power dissipation 54 194 -20 to +70 -55 to +125 mA mW C C PD Topr Tstg *1 Operating ambient temperature Storage temperature Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25C. *2: The above power dissipation PD shows the power dissipation of the package without heat sink. Refer to " Technical Data" when mounting this IC to a PCB and check that the IC will operate within the package power dissipation range. Recommended Operating Range Parameter Supply voltage Symbol VCC , VCC1 , VCC2 SDM00007BEB Range 2.7 to 3.3 Unit V 3 AN6591FJM Electrical Characteristics at Ta = 25C Parameter Symbol Test circuit 2 1 1 1 1 1 1 1 1 Conditions No signal input VMI = 70 dB Filter loss excluded. VMI = 105 dB Filter loss excluded. VMI = 20 dB VLI = 80 dB VLI: No signal input VLI = 115 dB VS (VIS) = VS(1) + 0.15 V DS (1) = VS (VIS + 65 dB) - VS (VIS) DS (n) = 5 (VS (VIS + n13 dB) - VS (VIS + (n - 1) 13 dB)) / DS (1) n = 1 to 5 Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 672.5 MHz, -10 dBm VAPC = 2.75 V No signal input, VAPC = 0 V Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 660 MHz, -10 dBm, VAPC = 2.2 V Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 687 MHz, -10 dBm, VAPC = 2.2 V Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 672.5 MHz, -10 dBm VAPC = 2.75 V, I / Q: No level adjusted Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 672.5 MHz, -10 dBm VAPC = 2.75 V, I / Q: DC offset adjusted Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 672.5 MHz, -10 dBm Make VAPC adjustments so that the Po value will be -13 dBm. Note) 1. Unless otherwise specified, at reception: VCC2 = 3.0 V, VLO3 = -10 dBm, f = 233.15 MHz, VMI: f = 243.95 MHz, SW1 = a, VLI: f = 10.8 MHz (The input level of pin 6, except the signal attenuation at the matching circuit and filter circuit.) The VMO and VLO values are at high impedance. (VLM shall be measured at probe load conditions of 27 pF and 1 M.) 2. The VIS is the input level VLI where the RSSI output voltage is VS (1) + 0.15 V. At transmission: VCC1 = 3.0 V, I / Q signal amplitude: 0.5 V[p-p] in both phases, DC bias: 1.5 V, SW1: a ICCTX , IL1, CL: / 4 QPSK-modulated wave, P01, P02, DU: PN9-level-modulated wave I / Q signal input condition: Make an amplitude adjustment of / 4 QPSK modulation signal 0000 to 0.5 V[p-p] with an oscilloscope and change the signal wave to a PN9-level continuous wave. Spectrum analyzer setting conditions for transmission output level measurement: SPAN = 2 MHz, RBW = 3 MHz, VBW = 3 MHz, SWPT = 5 s Det.: Pose. peak *: P01 output frequency: 1 893.15 MHz, P02 output frequency: 1 920.15 MHz Min 13 105 63 350 0 1.60 1.0 0.75 Typ 5.3 16 110 68 400 0.2 1.80 1.25 1.0 Max 6.8 19 73 0.5 1.5 1.25 Unit mA dB dB dB mV[p-p] V V V Current consumption (reception) ICCRX Mix. conversion gain Mix. max. output level Lim. voltage gain Lim. max. output amplitude RSSI output voltage (1) RSSI output voltage (2) Change in RSSI output Gradient of RSSI output GMX VMX GLM VLM VS (1) VS (2) DS DS(n) Current consumption (transmission) Sleep current in transmission Transmission output level 1 * Transmission output level 2 * Image leakage suppression ICCTX 1 28 37 mA ISL P01 P02 IL1 2 1 1 1 -13 -13 0 -9 -9 -35 10 -30 A dBm dBm dBc fLO1 + fLO2 leakage suppression Proximity spurious suppression CL 1 -35 -30 dBc DU 1 -55 -51 dBc 4 SDM00007BEB AN6591FJM Electrical Characteristics at Ta = 25C (continued) Parameter Current consumption 1 (PLL) Current consumption 2 (PLL) Current consumption 3 (PLL) Current consumption 4 (PLL) 1st RF input level 2nd IF input level Symbol Test circuit ICC1 ICC2 ICC3 ICC4 VRFIN VIFIN 1 1 1 1 1 1 1 Conditions 1st PLL and 2nd PLL blocks are simultaneously turned on. 1st PLL block is turned on while the 2nd PLL block is turned off. 1st PLL block is turned off while the 2nd PLL block is turned on. Power save mode fRFIN = 1 500 MHz to 1 800 MHz fIFIN = 120 MHz to 300 MHz fREFIN = 10 MHz to 25 MHz Min 3.7 3.0 1.2 -15 -10 0.2 Typ 5.4 4.4 1.7 0 Max 7.0 5.7 2.2 10 -2 +6 1.2 Unit mA mA mA A dBm dBm V[p-p] Reference signal input level VREFIN Note) Unless otherwise specified, VCC is 3.0 V and reference signal input level VREFIN is 0.6 V[p-p] at fREFIN = 19.2 MHz. * Design reference data Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter 1st local leakage suppression Symbol Test circuit CL1 1 Conditions Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 672.5 MHz, -10 dBm VAPC = 2.75 V Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 672.5 MHz, -10 dBm VAPC = 2.75 V Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 660 MHz to 1 687 MHz, -10 dBm, VAPC = 2.2 V Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 672.5 MHz, -10 dBm VAPC = 2.75 V Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 672.5 MHz, -10 dBm VAPC = 2.2 V Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 672.5 MHz, -10 dBm VAPC = 1.0 V Lo1 = 233.15 MHz, -10 dBm Lo2 = 1 672.5 MHz, -10 dBm VAPC = 2.75 V No signal input Min Typ -25 Max -20 Unit dBc 2nd local leakage suppression CL2 1 -15 -10 dBc In-band output level deviation P 1 1.0 dB Adjacent channel leakage power suppression (600 kHz detuning) Modulation accuracy BL1 1 -60 dBc EVM 1 3 5 %[rms] Min. output level Pmin 1 -30 -25 dBm RF + 233.15 MHz leakage suppression Mixer output resistance IIL 1 -36 dBc Rmix 2 330 Note) Unless otherwise specified, VCC = VCC1 = VCC2 = 3.0 V I / Q signal: 0.5 V[p-p] in both phases, DC bias: 1.5 V CL1, CL2, P, BL1, EVM, Pmin, IIL : PN9-level modulated wave. SDM00007BEB 5 AN6591FJM Electrical Characteristics at Ta = 25C (continued) * Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level input current 1 Low-level input current 1 High-level input current 2 Low-level input current 2 High-level output current 1 / 2 (High power) Low-level output current 1 / 2 (High power) High-level output current 1 / 2 (Low power) Low-level output current 1 / 2 (Low power) Output leakage current High-level output current 3 Low-level output current 3 Lockup time (1st) Symbol Test circuit VIH VIL VOH VOL IIH1 IIL1 IIH2 IIL2 IOH1H,2H IOL1H,2H IOH1L,2L IOL1L,2L IOZ IOH3L IOL3L rockt1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 Conditions Min 2.4 2.4 Typ 0 0 0 0 -2.6 3.5 Max 0.6 0.6 10 10 10 10 -1.9 4.4 Unit V V V V A A A A mA mA mA mA A mA mA s VIH of 3.0 V applied VIL of 0 V applied VIH of 3.0 V applied VIL of 0 V applied High power with VOH of 2.4 V applied. -3.2 High power with VOL of 0.6 V applied. 2.8 Low power with VOH of 2.4 V applied. - 0.74 - 0.6 - 0.46 Low power with VOL of 0.6 V applied. 0.53 VOZ of 0 V / 3.0 V applied VOH of 2.4 V applied VOL of 0.6 V applied 1st PLL block and 2nd PLL block are simultaneously turned on for all channels with RX-to-TX and TX-to-RX burst. -1 -3.6 1.9 0.7 0 -2.6 3.3 0.87 1 -1.5 4.6 600 Lockup time (2nd) rockt2 1 1st PLL block and 2nd PLL block are simultaneously turned on intermittently (during PS triggering) 1st PLL block and 2nd PLL block are simultaneously turned on. L-channel to H-channel 1st PLL block and 2nd PLL block are simultaneously turned on. df = 1 kHz, L-channel to H-channel 1st PLL block and 2nd PLL block are simultaneously turned on. df = 600 kHz, BW192 kHz 600 s 1st spurious 50 kHz Lspu1 1 -40 dBc 1st proximity C / N Lspu2 1 -70 dBc / Hz dBc 1st reference leakage Lspu3 1 -67 Note) Unless otherwise specified, VCC is 3.0 V and reference signal input level VREFIN is 0.6 V[p-p] at fREFIN of 19.2 MHz. 6 SDM00007BEB AN6591FJM Electrical Characteristics at Ta = 25C (continued) * Design reference data (continued) Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed. Parameter 2nd reference leakage 50 kHz 2nd proximity C / N Symbol Test circuit Lspu4 1 Conditions 1st PLL block and 2nd PLL block are simultaneously turned on. RW 1 kHz, VW 1 kHz 1st PLL block and 2nd PLL block are simultaneously turned on. df = 1 kHz Min Typ Max -40 Unit dBc Lspu5 1 -76 dBc / Hz Note) Unless otherwise specified, VCC is 3.0 V and reference signal input level VREFIN is 0.6 V[p-p] at fREFIN of 19.2 MHz. 1. Test circuit 1 fREFIN Controller LD 5 F VCC LPF2 Data Clock 33 32 STROBE 34 35 LD 31 30 PSRF 29 PSIF 28 27 1 000 pF 26 25 24 23 23-bit shift register IO 1st R counter latch 14-bit 1st R counter 2nd charge pump 2nd phase comparator 22 21 20 19 18 17 VCC LPF1 VCC 1 651.2 MHz to 1 684.8 MHz 36 1st charge pump 37 38 IO 1st prescaler 300 kHz 1st phase comparator 18-bit 1st A / N counter 1st N counter latch Lock detection 50 kHz 2nd R counter (384) 2nd N counter (291) A counter (7) VCO2 223.15 VCO1 100 pF 1 000 pF 2nd prescaler (1 / 16, 1 / 17) IO fRFIN fout1 (Lo1) 0 fIFIN MHz fout2 (Lo2, Lo3) VCC1 39 40 0 1 651.2 MHz to 1 684.8 MHz 560 560 4 700 pF 47 Lo1 16 1 k I 100 pF 1 k 41 2 200 pF IO 15 14 13 12 I 100 pF 1 k VAPC/BS VCC1 1 000 pF 5 F 42 43 Q 100 pF 1 k P0 Q 100 pF 1 000 pF 44 IO 1 2 3 4 5 6 7 2 200 pF IO 10 22 nF 0 47 RSSI 11 9 100 pF 223.15 MHz 100 pF 47 330 22 nF 2 200 pF 100 pF 5 F 2 200 pF 330 47 8 VLM 560 pF VMI 47 Lo3 1 000 pF Ceramic MIXO filter (Maker: Murata) VCC2 VS Lo2 223.15 MHz VLI SDM00007BEB 7 AN6591FJM Electrical Characteristics at Ta = 25C (continued) 2. Test circuit 2 VOH, VOL, IOH2, IOL2, 10 z VOH, VOL, IOH3, IOL3 VIH, VIL, IIH1, IIL1 VIH, VIL, IIH1, IIL1 VIH, VIL, IIH2, IIL2 VIH, VIL, IIH2, IIL2 5 F VCC Data Clock 33 32 LD 31 30 PSRF 29 PSIF 28 27 1 000 pF 26 25 24 23 VIH, VIL, IIH1, IIL1 STROBE 34 35 23-bit shift register IO 1st R counter latch 14-bit 1st R counter 2nd charge pump 2nd phase comparator 50 kHz 2nd R counter (384) 2nd N counter (291) A counter (7) 2nd prescaler (1 / 16, 1 / 17) IO 22 21 20 19 18 17 16 VCC VOH, VOL, IOH1, IOL1, 10 z 36 1st charge pump 300 kHz 1st phase comparator 18-bit 1st A / N counter 1st N counter latch Lock detection VCC 37 38 39 IO 1st prescaler 0 100 pF 40 41 VCC1 1 k 100 pF 1 k 100 pF 1 k 100 pF 1 k 100 pF 1.5 V IO 15 14 13 12 VAPC/BS VCC1 1 000 pF 42 5 F 43 44 IO 1 2 3 4 5 6 7 P0 IO 10 8 RSSI 11 9 100 pF VMI 100 pF MIXO 2 200 pF 2 200 100 pF pF 22 nF 5 F VCC2 22 nF Lo2 560 pF VS Lo3 LIMIN VLM 1 000 pF 8 SDM00007BEB AN6591FJM Terminal Equivalent Circuits Pin No. 1 Equivalent circuit Description RXMIXIN: Reception mixer input pin with an input impedance of approx. 16 k. I/O I 1 2 RXLOIN: Local input pin. I 2 3 4 VCC2: Mixer power supply pin. MXO: Mixer output pin. 4 O 5 6 5 7 LMDEC1, 2: Coupling pin for limiter amplifier feedback. Ground this pin through an external capacitor. 7 6 LMIN: Limiter amplifier input pin with an input impedance of approx. 330 . VCC2: Pin to provide power supply to the limiter amplifier and RSSI. LMO: Limiter amplifier output pin. 9 I 8 9 O SDM00007BEB 9 AN6591FJM Terminal Equivalent Circuits (continued) Pin No. 10 42 Equivalent circuit Description TXLO2: Quadrature modulator local input pin I/O I 10 11 11 RSO: RSSI output pin with DC output according to the input signal level of the limiter amplifier. O 12 13 GNDR: Ground pin. Q-in: Q signal input pin with the following relationship between the input DC bias and amplitude. DC bias (V) Amplitude V[p-p] 1.5 0.5 (Both phases) I 17 14 14 13 Q-in: Q signal input pin with the following relationship between the input DC bias and amplitude. DC bias (V) Amplitude V[p-p] 1.5 0.5 (Both phases) I 15 42 I-in: I signal input pin with the following relationship between the input DC bias and amplitude. DC bias (V) Amplitude V[p-p] 1.5 0.5 (Both phases) I 16 16 15 I-in: I signal input pin with the following relationship between the input DC bias and amplitude. DC bias (V) Amplitude V[p-p] 1.5 0.5 (Both phases) I 10 SDM00007BEB AN6591FJM Terminal Equivalent Circuits (continued) Pin No. 17 Equivalent circuit Description VCC1: Pin to provide supply voltage to the quadrature modulator. The pin is connected to the built-in band gap regulator, thus providing stable bias voltage without being affected by VCC or temperature changes as much as possible. GNDM: Ground pin for the quadrature modulator. Keep the grounding surface wide to lower the impedance. 2nd prescaler in: 2nd PLL prescaler input pin. I/O I 18 19 I 19 21 22 26 27 GND 2nd CMOS: Ground pin for the 2nd PLL. VCC: Bip power supply pin for the PLL. VCC: 2nd CMOS power supply pin for the PLL. 2nd chargepump out: 2nd PLL charge pump output pin. O 27 28 29 28 29 28: 2nd power save in: 29: 1st power save in: 2nd PLL and 1st PLL power save control input pins. Reference in: Reference signal input pin. I 30 I 30 SDM00007BEB 11 AN6591FJM Terminal Equivalent Circuits (continued) Pin No. 31 Equivalent circuit Description Lock detect out: Lock detection output pin. I/O O 31 32 33 34 35 36 32 33 34 32: Clock in: Clock input pin. 33: Serial data in: Data input pin. 34: Strobe in: Strobe input pin. GND 1st / 2nd CMOS: 1st and 2nd PLL ground pin. 1st charge pump out: 1st PLL charge pump output pin. I O 36 37 38 VCC: 1st PLL CMOS power supply pin. 1st prescaler in: 1st PLL prescaler input pin. I 38 39 42 TX LO1: Local input pin for the up-mixer. The use of an external balancer is recommended to apply balanced input. TX LO1R: Local input pin for the up-mixer. The use of an external balancer is recommended to apply balanced input. I 40 I 39 40 12 SDM00007BEB AN6591FJM Terminal Equivalent Circuits (continued) Pin No. 41 Regulator Equivalent circuit Description APC / BS: Pin used for the battery save of the transmission circuit block and the power control of RF output. VAPC (V) Status Off On (APC control) I/O I 41 (APC control) 0 to 0.3 1.0 to VCC The impedance is a minimum of 5 k. 42 VCC1: Pin to provide power supply to the upmixer and output amplifier circuit. This pin is connected to the built-in stabilized power supply circuit and provides stable bias voltage without being affected by VCC or temperature changes as much as possible. 42 43 TXO: RF output pin connected to the output amplifier circuit and has emitter follower output. O 43 44 GNDO: Ground pin for the up-mixer and output amplifier circuit. This pin is a highfrequency ground pin. Therefore, keep the grounding surface wide to lower the impedance. SDM00007BEB 13 AN6591FJM Technical Data 1. Serial data interface specifications Carrier data is transferred in 23-bit serial data transfer. The serial data is set at the clock falling edge and latched onto the synthesizer at the clock rising edge. It is necessary to input a single STROBE pulse when the 23-bit serial data transfer is completed. 1) Serial interface of 1st synthesizer 1st synthesizer serial data input format MSB N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 A6 A5 A4 A3 A2 A1 A0 PD P LSB TC C1 C0 X X X TO X R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 T1 T0 C1 C0 X: don't care N data input direction fout = (P x N + A) x fin / R Possible set range: 1st A = 0 to 127 or 63, N = 5 to 2 047 (N > A) R = 5 to 16 383 (1) Control bit C0 1 1 C1 0 1 1st synthesizer R counter frequency dividing ratio setting 1st synthesizer A / N counter frequency dividing ratio setting (2) Test contents T0 2nd synthesizer R counter output 2nd synthesizer N counter output 1st synthesizer R counter output 1st synthesizer N counter output 0 0 1 1 T1 0 1 0 1 (3) Data contents PD Phase comparator polarity selection 0 1 negative positive P Prescaler frequency dividing ratio 128 / 129 64 / 65 TC Counter test mode setting LD output Counter output TO Output pin test normal test 2) Serial transfer timing Timing chart 22 t1 t2 Clock STROBE 21 20 19 18 2 1 0 (t1 , t2 50 ns) Data 14 SDM00007BEB AN6591FJM Technical Data (continued) 2. 2nd synthesizer frequency dividing ratio Set frequency (frequency dividing ratio) fout2 = 233.15 MHz, fr = 50 kHz, (P = 16, N = 291, A = 7, R = 384 fixed) Reference frequency fREFIN = 19.2 MHz MSB N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 0 0 1 0 0 1 0 0 0 1 1 X 0 X 0 X 0 A3 A2 A1 A0 PD 0 1 1 1 1 P 0 LSB X 0 X 0 X 0 X 0 X 0 X R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 X 0 X 0 X: don't care 3. Unlock detection and LD output specifications 1) The AND of the LD signal (2) of the 1st synthesizer block and the LD signal (3) of the 2nd synthesizer block is output. 2) 1st synthesizer block When the synthesizer block is locked, the LD output level will be high. When the synthesizer block is unlocked, the LD output level will be low. The detection time is 3.3 s. As for the precision of detection, unlock output turns on if the devided frequency output of the circuit is (52 x 4) ns slower or faster than it should be at the frequency fref of 300 kHz. The lock signal is output in power save mode. 3) 2nd synthesizer block When the synthesizer block is locked, the LD output level will be high. When the synthesizer block is unlocked, the LD output level will be low. The detection time is 20 s. As for the precision of detection, unlock output turns on if the devided frequency output of the circuit is (52 x 4) ns slower or faster than it should be at the frequency fref of 50 kHz. The lock signal is output in power save mode. 1st synthesizer Lock or power save mode Unlock Lock or power save mode Unlock 2nd synthesizer Lock or power save mode Lock or power save mode Unlock Unlock LD output High Low Low Low 4. Other specifications 1) Clock, Data, and STROBE all are high-active logics. 2) When the IC is turned on, set the IC to power save mode by setting both PS1 and PS2 to low-level. After serial data is input, set the IC to operating mode by setting both PS1 and PS2 to high-level. SDM00007BEB 15 AN6591FJM Technical Data (continued) 3. TX-RX burst / intermittent reception lockup time 450 Lockup time (s) RX TX 350 250 TX RX 255 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 max. Intermittent Channel (ch) Unless otherwise specified, VCC = 3.0 V, and fREF = 19.2 MHz. The lockup time means converging time into 1 kHz. 1) Test circuit 100 pF 33 pF TCX03V 15 nH 27 68 pF MA2Z331 PLL3V 1 000 pF 0.68 F 470 2.2 k CP2 15 k 68 pF Ref. VCC1/2/B CP1 8.2 k 680 pF 4 700 pF 12 nH 0.68 1 000 F pF 5.6 k 10 k XN06543 1.5 k 1.5 pF 33 pF 39 pF 22 pF 1 000 pF 1 000 pF 180 56 pF 47 AN6591FJM IFIN RFIN 47 pF 5 600 pF PS1 Clock PS2 Data STROBE Time-98 Data generator 2.5 pF 47 PLL3V TCX03V VCO ENFVJ1G 1 000 2S03 pF 1 000 pF TCX03V 0.68 F 2) Serial control timing (1) At TX-RX burst (2) At intermittent reception 1.25 ms 1.25 ms 1.25 ms 1.25 ms PS1 PS2 Data Clock STROBE 27 s 15.2 s RX TX 1.2 s 13.5 ms TCX03V PLL3V PS2 PS1 Channel setting 4 ms2 ms 1 ms 3.5 ms 16 SDM00007BEB AN6591FJM Technical Data (continued) 4. Oscillator frequency by channel (fRFIN) ch 251 252 253 254 255 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 fRFIN SDM00007BEB 17 AN6591FJM Technical Data (continued) 4. Oscillator frequency by channel (fRFIN) (continued) ch 66 67 68 69 70 71 72 73 74 75 76 fRFIN 5. PD Ta curves of QFN044-P-0606A PD Ta 1.500 1.400 1.392 1.300 1.200 Mounted on standard board (glass epoxy: 50 mm x 50 mm x t0.8 mm) Rth(j-a) = 71.8C/W Power dissipation PD (W) 1.100 1.000 0.900 0.800 0.700 0.600 0.500 0.400 0.353 0.300 0.200 0.100 0.000 0 Independent IC without a heat sink Rth(j-a) = 282.9C/W 25 50 75 100 125 Ambient temperature Ta (C) 18 SDM00007BEB AN6591FJM Technical Data (continued) Transmission output level (dBm) / adjacent channel leakage suppression (dBc) / 8 x Lo (dBc) 6. Main characteristics APC control voltage characteristics 0 -10 -20 -30 -40 -50 Transmission output Adjacent channel at 300 kHz 8 x Lo 20 18 16 Wideband spurious characteristics 0 -10 -20 Modulation accuracy (%) 14 12 10 8 6 4 -30 Spurious (dBm) -40 -50 -60 -70 -80 -90 -100 0.6 6 60 600 6k RLV: 0.0 dBm AT 15 dB RB 1 MHz ST 200 ms VB 1MHz 60k 600k 6M 60M 600M 6G -60 Adjacent channel at 600 kHz -70 Modulation accuracy -80 -90 Lo1:1 672.5 MHz, -10 dBm Lo2: 233.15 MHz, -10 dBm 2 I / Q signal DC bias: 1.5 V, amplitude: 500 mV[p-p], PN9-level continuous wave 0 -100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 APC control voltage (V) (Hz) AN6591FJM Mix.I / O characteristics 120 110 100 AN6591FJM Lim. characteristics 120 110 100 25C -20C 60C Mix. output level (dB) Lim. output level (dB) 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 60C -20C 25C 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 Mix. input level (dB) Limiter input level (dB) Note) 1. Unless otherwise specified, the test conditions conform to electrical characteristics. 2. The values in the above are reference values for designing and not guaranteed. SDM00007BEB 19 AN6591FJM Technical Data (continued) 6. Main characteristics (continued) AN6591FJM RSSI characteristics 2.2 2.0 1.8 AN6591FJM Mix. characteristics 130 120 IM / Mix. output level (dB) 60C 110 100 90 80 70 60 50 40 30 20 IM Output level RSSI output level (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 10 20 30 40 50 60 70 80 90 100 110 120 -20C 25C 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Limiter input level (dB) Mix. input level (dB) AN6591FJM Mix. characteristics 20 18 16 14 CG Mix. CG (dB) NF (dB) 12 10 8 6 4 2 0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 NF Local input level (dBm) Note) 1. Unless otherwise specified, the test conditions conform to electrical characteristics. 2. The values in the above are reference values for designing and not guaranteed. 20 SDM00007BEB Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. 2002 JUL |
Price & Availability of AN6591FJM
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |