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| CXG1156K Power Amplifier Module for JCDMA Description The CXG1156K is the power amplifier module which operates at a single power supply. This IC is designed using the Sony's original p-Gate HFET process. Features * Single power supply operation: VDD1 = VDD2 = 3.5V (High power mode), 1.3V (Low power mode 1), 1.0V (Low power mode 2), VGG = 2.7V * Small package: 0.065cc (6.2mm x 6.2mm x 1.7mm) * High efficiency: add = 40%@POUT = 27.5dBm (High power mode), add = 23%@POUT = 15dBm (Low power mode 1) * Output power (high/low power mode switching supported): POUT = 18 to 27.5dBm: High power mode, POUT = 15 to 18dBm: Low power mode 1, POUT 15dBm: Low power mode 2 * Gain: Gp = 29dB (@900MHz) Applications Power amplifier for JCDMA system cellular phones Structure p-Gate HFET module Absolute Maximum Ratings (Ta = 25C) * Operating case temperature Tcase -30 to +90 C * Storage temperature Tstg -30 to +125 C * Bias voltage VDD1, VDD2 6 V * Bias voltage VGG 3.3 V (@VDD1 = VDD2 = 3.5V) * Input power PIN 8 dBm Recommended Operating Conditions* * VDD1 = VDD2 = 3.2 to 4.2V@POUT = 18 to 27.5dBm, 1.3 to 2.0V@POUT 18dBm, 1.0 to 2.0V@POUT 15dBm * VGG = 2.7V 1% 10 pin LCC (Ceramic) *This recommended operating voltage is the value that specified the supply voltage range where the functional operation was confirmed by the Sony's recommended evaluation board. GaAs module is ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E02641-PS CXG1156K Package Outline/Pin Configuration Front GND 10 GND 9 PIN 1 8 VGG VDD1 2 7 GND VDD2 3 6 POUT 4 GND 5 GND Back GND 4 GND 5 VDD2 3 6 POUT VDD1 2 11 GND 7 GND PIN 1 8 VGG 10 GND 9 GND Note) Be sure to solder the GND part (11) to the land. For the land where the GND part (11) is connected, form the GND pattern by making the throgh holes in the land. -2- CXG1156K Electrical Characteristics Item Frequency Current consumption 1 Current consumption 2 Current consumption 3 Gain 1 Gain 2 Gain 3 ACPR1 (High power mode) ACPR2 (High power mode) ACPR1 (Low power mode 1) ACPR2 (Low power mode 1) ACPR1 (Low power mode 2) ACPR2 (Low power mode 2) 2nd, 3rd harmonics Input VSWR Gate current Conditions (ZS = ZL = 50, IS-95 Modulation, Tc = 25C) Min. 887 POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V POUT = 15dBm, VDD = 1.3V, VGG = 2.7V POUT = 12dBm, VDD = 1.0V, VGG = 2.7V POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V POUT = 18dBm, VDD = 1.3V, VGG = 2.7V POUT = 15dBm, VDD = 1.0V, VGG = 2.7V POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V, 900kHz offset, 30kHz band width POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V, 1.98MHz offset, 30kHz band width POUT = 18dBm, VDD = 1.3V, VGG = 2.7V, 900kHz offset, 30kHz band width POUT = 18dBm, VDD = 1.3V, VGG = 2.7V, 1.98MHz offset, 30kHz band width POUT = 15dBm, VDD = 1.0V, VGG = 2.7V, 900kHz offset, 30kHz band width POUT = 15dBm, VDD = 1.0V, VGG = 2.7V, 1.98MHz offset, 30kHz band width POUT = 27.5dBm, VDD = 3.5V, VGG = 2.7V VDD = 3.5V, VGG = 2.7V VGG = 2.7V, POUT 27.5dBm 25 22 20 405 105 79 29 24 22 -54 -64 -56 -63 -56 -63 -27 1.3 1.7 -47 -58 -50 -58 -50 -58 -23 2 2.5 mA Typ. Max. 925 420 110 90 Unit MHz mA mA mA dB dB dB dBc dBc dBc dBc dBc dBc dBc -3- CXG1156K Recommended External Circuit C1: 1F C2: 10F GND GND PIN C1 VDD1 C2 VDD2 C2 C1 C1 GND GND C2 VGG POUT GND GND Recommended Evaluation Board Board material: Glass fabric-base epoxy Size: 40mm x 50mm x 0.6mm Relative dielectric constant: 4.6 Front VGG GND C2 Back GND C1 PIN POUT VDD1 C1 C2 C1 C2 GND VDD2 GND -4- CXG1156K Example of Representative Characteristics Conditions: f = 900MHz VDD1 = VDD2 = 3.5V, VGG = 2.7V (High power mode) VDD1 = VDD2 = 1.3V, VGG = 2.7V (Low power mode 1) Ta = 25C POUT vs. PIN 32 30 VDD = 3.5V 28 VDD = 1.3V 26 24 22 20 18 16 14 12 10 8 6 4 2 -26 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 PIN [dBm] 600 550 500 450 400 VDD = 3.5V VDD = 1.3V IDD vs. POUT POUT [dBm] IDD [mA] 350 300 250 200 150 100 50 0 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] ACPR1 vs. POUT -34 -36 -38 -40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 -74 VDD = 3.5V VDD = 1.3V -48 -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 -74 -76 -78 ACPR2 vs. POUT VDD = 3.5V VDD = 1.3V ACPR1 [dBc] 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] ACPR2 [dBc] 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 POUT [dBm] -5- CXG1156K Package Outline Unit: mm 10PIN LCC 6.2 0.3 6.0 SOLDERING POINT X 1.7 0.15 6.0 + 0.5 6.2 - 0.3 0.1Max PIN 1 INDEX SOLDERING POINT 0.2 S Detail X 3.8 1.4 0.9 4 3 2 1 10 2 x 2-R0.2 2-R0.2 9 4-R0.2 TERMINAL 1.6 5 6 4.9 TERMINAL 7 8 1.7 0.1 3.4 0.15 C0.1 0.15 0.15 0.15 0.6 0.2 Detail Y COAT PACKAGE STRUCTURE NOTE: Dimension "" does not include cutting burr. SONY CODE JEITA CODE JEDEC CODE LCC-10C-03 PACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS CERAMIC SUBSTRATE GOLD PLATING NICKEL PLATING 0.8g 1.1 0.15 0.15 Y COAT SUBSTRATE S R0.2 -6- Sony Corporation 0.1 S |
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