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Technical Brief
OKI ASIC P R O D U C T S
W812 IEEE 1394 Controller 0.35 m Technology Mega Macrofunction
November 1997
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Contents Description................................................................................................................................................................ 1 Features .....................................................................................................................................................................1 Signal Descriptions ..................................................................................................................................................4 Functional Description ............................................................................................................................................5 Functional Modules ...........................................................................................................................................5 Data Path Interface ......................................................................................................................................5 Asynchronous Transfer Request Block ....................................................................................................5 Isochronous Transfer Request Block ........................................................................................................5 Read-Write Request Block .........................................................................................................................5 Annex J Request Block ................................................................................................................................5 Transmitter and Receiver Block ................................................................................................................5 Byte-wide Serializer and Deserializer ......................................................................................................6 Quadlet Serializer and Deserializer ..........................................................................................................6 Quadlet Buffer .............................................................................................................................................6 Link Core Controller State Machine .........................................................................................................6 CRC Generator and Checker .....................................................................................................................6
Oki Semiconductor
W812 IEEE 1394 Link Layer Controller
0.35 m Technology Mega Macrofunction DESCRIPTION
The W812, Oki Semiconductor's 1394 Link Layer Controller, is IEEE 1394-1995 compliant and features an embedded high-performance application bus interface. This device performs data packaging according to the IEEE 1394-1995 Standard, and bidirectional asynchronous/isochronous data transfers to/from an IEEE 1394 serial bus physical layer (PHY) device. The W812 is optimized for use as a peripheral link layer controller. The application bus interface, which transfers data between a FIFO and the host controller, is designed for highly efficient transport. Oki also provides an optional FIFO controller, the W812-F to readily interface with the W812. Oki's W812 accommodates different application needs by using a flexible architecture which to support both asynchronous and isochronous data transfers or only asynchronous data transfers. This technology give system designers the maximum flexibility in their design.
FEATURES
* Compliant with IEEE 1394-1995 Standard Link Layer Controller * Compatible with Texas Instruments' Physical Layer Controllers * Offers programmable FIFO channel for asynchronous and isochronous transmission and general reception * Supports transfer rates of 100, 200, and 400 Mbps * Uses flexible architecture to support both asynchronous and isochronous data transfers or only asynchronous data transfers * Offers high performance application bus interface * Has 32-bit cyclic redundancy check (CRC) for transmission and reception of 1394 packets
Recommended Operating Conditions (VSS = 0 V)
Parameter Power supply voltage Operating temperature Symbol VDD Tj Min. 2.7 -40 Typ. 3.3 +25 Max. 3.6 +85 Unit V C
Mega Macrofunction Characteristics
Mega Macrofunction W812 Description IEEE 1394 Link Layer Controller Logic Gate Count 12K Logic Pin Count 95
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W812 DPBdata DPBdrive DPBValid DPBValid_en DPBFifoStatus [0:2] DPBadr [0:12] DPBadr_en DPBWrite DPRegLink DPRegWrLink DPAckLink DPStallLink DPBWait MasterReset CycleIn CycleOut Lclk AnxJLReg Ctlln [0:1] CtlOut [0:1] CtlTriEnb AnxJDin [0:7] AnxJDout [0:7] DataTriEnb [0:7] Direct LinkPowerOn
Application Bus Interface
PHY-Link Interface
Isochronous Control
Figure 1. W812 Logic Symbol
Async Transfer Request
Isochronous Transfer Request
Read and Write Request
Application Bus Interface
DPIF Quadlet Serializer and Deserializer
Transmitter and Receiver
Quadlet Buffer
Link Core Controller AnxJRequest
CRC
Byte-wide Serializer and Deserializer
PHY-Link Interface
Figure 2. W812 Block Diagram
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W812-F FIFO Controller
(Optional)
Application Module
DPIF
W812
PHY-Link Interface
PHY
1394Cable
IEEE 1394 Link Layer
IEEE 1394 PHY Layer
Figure 3. Example W812 Application
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SIGNAL DESCRIPTIONS
PHY-Link Interface
Signal Lclk AnxJLReg Ctlln CtlOut CtlTriEnb AnxJDin AnxJDout DataTriEnb Direct LinkPowerOn Type In Out In Out Out In Out Out In Out Assertion -- -- -- -- HIGH -- -- HIGH HIGH HIGH 50-MHz SCLK from PHY. LINK request port to PHY. Used to make bus requests or accesses to PHY. Input from Bi-di control port for bi-directional pins. Output to Bi-di control port for bi-directional pins. Tri-state enable to Bi-di control port. Input from Bi-di data port. Used to exchange data with PHY. Output to Bi-di data port. Used to exchange data with PHY. Tri-state enable to Bi-di data port. Indicates LINK and PHY are directly connected, rather than through an isolation barrier. Indicates LINK is powered on. Description
Application Bus Interface
Signal DPBdata DPBdrive DPBValid DPBValid_en DPBFifoStatus DPBadr DPBadr_en DPBWrite DPReqLink DPReqWrLink DPAckLink DPStallLink DPBWait MasterReset Type Bi-di Out Bi-di Out In Bi-di Out Bi-di Out Out In Out In In Assertion -- HIGH HIGH HIGH -- -- HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH Description Data Path Data Bus. Used to exchange data with other application modules. Indicates W812 is driving DPBdata. Indicates the quality description of DPBdata. Enable to DPBValid signal Indicates the FIFO status for fetches and stores by FIFO controller, such as Oki's W812-F. Data Path Bus Address. Specifies the DPBus transfer. Enables to DPBadr signals. Specifies whether the DPBus transfer is a read or write. DPBus request line for LINK. DPBus request operation type line for LINK. DPBus request grant line to LINK. LINK indication of need to extend current DPBus cycle. Indicates the DPBus operation is to be extended a cycle. Initializes the whole module. It is a synchronous reset, clocked by Lclk.
Isochronous Control Interface
Signal CycleIn CycleOut Type In Out Assertion -- -- Description 8-kHz clock to optionally indicate isochronous cycle. 20-ns pulse to indicate the start of an isochronous cycle.
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FUNCTIONAL DESCRIPTION
The W812 controller has three basic interfaces: * Application Bus * PHY-Link * Isochronous Control The Application Bus and Isochronous Control interfaces are application interfaces; whereas, the LinkPHY interface conforms to the IEEE 1394-1995 Standard (as described in Annex J section) and provides an industry standard interface to the PHY. The Application Bus interface provides a highly efficient interface to other application modules including the FIFO controller. Oki also provides an optional W812-F FIFO controller which is ready to interface with the W812. Functional Modules Data Path Interface (DPIF) This block interfaces with Oki's high performance application bus which is a multi-drop multiple master bus that uses a streamlined, 3-phase protocol. W812 uses this interface to communicate with the application modules and necessary FIFO controller. Oki's bus interface is simple and relatively inexpensive in terms of pin and interface count. Yet the W812 has good bandwidth of ~200 MBps and a low and predictable latency. Oki's optional W812-F FIFO controller also uses this busing scheme to provide an overall high performance 1394 Link Layer solution. Asynchronous Transfer Request This block queues requests for asynchronous transmission by fetching all the necessary parameters to the transmitter and receiver. Isochronous Transfer Request This block queues requests for isochronous transmission by fetching all the necessary parameters to the transmitter and receiver. Read-Write Request This block queues read and write requests to the PHY register through the Annex J request block and formats and fetches request packets to the Annex J Request Block. Annex J Request This block generates the Annex J Request to the PHY. When more than one request is queued at the same time, this block prioritizes the queued requests. Transmitter and Receiver This block generates the flow control signals for the W812 and determines when, what, where, and how a packet is fetched during transmission and stored during reception. This block performs the following functions: * Format appropriate packets * Cycle monitor * Cycle master
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* Packet header check and decoding * Coordinate function with optional FIFO controller * Packet flow control for transmission and receiving Byte-wide Serializer and Deserializer During transmission, this block serializes an 8-bit byte into appropriate size of data according to the associated transmission speed. During receiving, this block accumulates receiving data, deserialzies it, and passes data one byte at a time to the Quadlet Serializer and Deserializer. This block also generates signal pertaining to the Annex J states like start and end of a receive, states during transmit or receive. It controls when to read and or write a byte from or to the Quadlet Serializer and Desirializer and when to compute new CRC. Quadlet Serializer and Deserializer During transmission, this block serializes 32-bit data into four 1-byte data. During receiving, this block deserialzies four 1-byte data at a time into a 32-bit quadlet. Quadlet Buffer This block is a FIFO-type storage area. Link Core Controller State Machine This machine performs link layer packet transmit and receive operations as described in Figure 6-19, of IEEE Standard 1394-1995. CRC Generator and Checker This block generates and checks the CRC. The 32-bit polynomial function is as follows:
G(x) = x(32) + x(26) + x(23) + x(22) + x(16) + x(12) + x(11) + x(10) + x(8) + x(7) + x(5) + x(4) + x(2) + x + 1
To run the W812 at 400 Mbps, this block uses a specialized scheme to achieve desired performance.
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Notes:
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Notes:
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References See the IEEE 1394-1995 Standard for more information on Link Layer Controller functionality.
The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. OKI assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Copyright 1997 Oki Semiconductor Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by OKI Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of OKI.
Oki Semiconductor
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