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| SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415 - JUNE 2000 D D D D D D D D D D D D D >400 Mbps (200 MHz) Signaling Rates Flow-Through Pinout Simplifies PCB Layout 50 ps Channel-to-Channel Skew (Typ) 200 ps Differential Skew (Typ) Propagation Delay Times 2.7 ns (Typ) 3.3 V Power Supply Design High Impedance LVDS Inputs on Power Down Low-Power Dissipation (40 mW at 3.3 V Static) Accepts Small Swing (350 mV) Differential Signal Levels Supports Open, Short, and Terminated Input Fail-Safe Industrial Operating Temperature Range (-40C to 85C) Conforms to TIA/EIA-644 LVDS Standard Available in SOIC and TSSOP Packages D OR PW PACKAGE (TOP VIEW) RIN1- RIN1+ RIN2+ RIN2- RIN3- RIN3+ RIN4+ RIN4- 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 EN ROUT1 ROUT2 VCC GND ROUT3 ROUT4 EN functional diagram EN EN RIN1+ RIN1- RIN2+ RIN2- R1 ROUT1 R2 ROUT2 description RIN3+ The SN65LVDS048 is a quad differential line receiver ROUT3 R3 RIN3- that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling RIN4+ technique lowers the output voltage levels of 5-V ROUT4 R4 differential standard levels (such as EIA/TIA-422B) to RIN4- reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the quad differential receivers will provide a valid logical output state with a 100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics. The SN65LVDS048 is characterized for operation from -40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415 - JUNE 2000 TRUTH TABLE DIFFERENTIAL INPUT RIN+ / RIN- VID 100 mV VID -100 mV Open/short or terminated X ENABLES EN H EN L or OPEN OUTPUT ROUT H L H All other conditions Z H = high level, L = low level, X = irrelevant, Z = high impedance (off) equivalent input and output schematic diagrams VCC VCC VCC 50 300 k 300 k EN,EN 50 Output 7V Input 7V 7V Input 300 k 7V absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range, VI(RIN+, RIN-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Enable input voltage (EN, EN ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (VCC +0.3 V) Output voltage, VO(ROUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (VCC +0.3 V) Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. DISSIPATION RATING TABLE PACKAGE D TA 25C POWER RATING 950 mW OPERATING FACTOR ABOVE TA = 25C 7.6 mW/C TA = 85C POWER RATING 494 mW PW 774 mW 6.2 mW/C 402 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415 - JUNE 2000 recommended operating conditions MIN Supply voltage, VCC Receiver input voltage Common-mode input voltage, VIC |V | 2.4 3 GND ID 2 NOM 3.3 MAX 3.6 3 ID * |V2 | UNIT V V V C Operating free-air temperature, TA -40 25 VCC - 0.8 85 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Note 2) PARAMETER VIT+ VIT- V(CMR) IIN Differential input high threshold voltage Differential input low threshold voltage Common mode voltage range Input current TEST CONDITIONS , , VCM = 1.2 V, 0.05 V, 2.35 V (see Note 3) VID = 200 mV pk to pk (see Note 4) VIN = 2.8 V VCC = 3.6 V or 0 V 36 VIN = 0 V VIN = 3.6 V VCC = 0 V IOH = -0.4 mA, VID = 200 mV VOH VOL IOS IO(Z) VIH VIL II VIK ICC Output high voltage Output low voltage Output short circuit current Output 3-state current Input high voltage Input low voltage Input current (enables) Input clamp voltage No load supply current, receivers enabled VIN = 0 V or VCC, Other input = VCC or GND ICL = -18 mA EN = VCC, Inputs open IOH = -0.4 mA, input terminated IOH = -0.4 mA, input shorted IOL = 2 mA, VID = -200 mV Enabled, VOUT = 0 V (see Note 5) Disabled, VOUT = 0 V or VCC -1 2.0 GND -10 -1.5 -0.8 8 15 MIN -100 0.1 -20 -20 -20 2.7 2.7 2.7 1 1 1 3.2 3.2 3.2 0.05 -65 0.25 -100 1 VCC 0.8 10 2.3 20 20 20 TYP MAX 100 UNIT mV V A A A V V V V mA A V V A V mA ICC(Z) No load supply current, receivers disabled EN = GND, Inputs open 0.6 1.5 mA All typical values are at 25C and with a 3.3-V supply. NOTES: 2. Current into device pin is defined as positive. Current out of the device is defined as negative. All voltages are referenced to ground, unless otherwise specified. 3. VCC is always higher than RIN+ and RIN- voltage, RIN- and RIN+ have a voltage range of -0.2 V to VCC-VID/2. To be compliant with ac specifications the common voltage range is 0.1 V to 2.3 V. 4. The VCMR range is reduced for larger VID, Example: If VID = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs shorted is not supported over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external common-mode voltage applied. A VID up to VCC-0 V may be applied to the RIN+ and RIN- inputs with the common-mode voltage set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew specifications apply for 200 mV < VID < 800 mV over the common-mode range. 5. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time. Do not exceed maximum junction temperature specification. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415 - JUNE 2000 switching characteristics over recommended operating conditions (unless otherwise noted) (see Notes 6) PARAMETER tPHL tPLH tSK(p) tSK(o) tSK(pp) tSK(lim) tr tf tPHZ tPLZ tPZH tPZL Differential propagation delay, high-to-low Differential propagation delay, low-to-high Differential pulse skew (tPHLD - tPLHD) (see Note 7) Differential channel-to-channel skew; same device (see Note 8) Differential part-to-part skew (see Note 9) Differential part-to-part skew (see Note10) Rise time Fall time Disable time high to Z Disable time low to Z Enable time Z to high Enable time Z to low RL = 2 K F CL = 15 pF ( g (see Figure 3 and 4 ) 0.5 0.5 8 6 8 7 CL = 15 pF VID = 200 mV (see Figure 1 and 2 ) TEST CONDITIONS MIN 1.9 1.9 TYP 2.7 2.9 200 50 MAX 3.7 3.7 450 500 1 1.5 1 1 9 8 10 8 UNIT ns ns ps ps ns ns ns ns ns ns ns ns f(MAX) Maximum operating frequency (see Note 11) All channel switching 250 MHz All typical values are at 25C and with a 3.3-V supply. NOTES: 6. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 , tr and tf (0% - 100%) 3 ns for RIN. 7. tSK(p)|tPLH - tPHL| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 8. tSK(o) is the differential channel-to-channel skew of any event on the same device. 9. tSK(pp) is the differential part-to-part skew, and is defined as the difference between the minimum and the maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5C of each other within the operating temperature range. 10. tsk(lim) part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tsk(lim) is defined as |Min - Max| differential propagation delay. 11. f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels switching PARAMETER MEASUREMENT INFORMATION RIN+ Generator 50 RIN- 50 R CL ROUT Receiver Enabled Figure 1. Receiver Propagation Delay and Transition Time Test Circuit 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415 - JUNE 2000 PARAMETER MEASUREMENT INFORMATION RIN- OV Differential VID = 200 mV 1.2 V 1.3 V 1.1 V tPLH tPHL 1.5 V 20% tr 80% 80% VOH 1.5 V 20% VOL RIN+ ROUT tf Figure 2. Receiver Propagation Delay and Transition Time Waveforms VCC S1 RIN+ Generator 50 EN EN 1/4 65LVDS048 CL Includes Load and Test Jig Capacitance. S1 = VCC for tPZL and tPLZ Measurements. S1 = GND for tPZH and tPHZ Measurements. RIN- RL Device Under Test CL ROUT Figure 3. Receiver 3-State Delay Test Circuit EN When EN = GND or Open 1.5 V 1.5 V 3V 0V 3V EN When EN = VCC tPLZ tPZL 0V VCC Output When VID = -100 mV Output When VID = 100 mV 50% 0.5 V tPHZ 0.5 V 50% GND tPZH VOL VOH Figure 4. Receiver 3-State Delay Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415 - JUNE 2000 TYPICAL CHARACTERISTICS OUTPUT HIGH VOLTAGE vs POWER SUPPLY VOLTAGE 3.6 TA = 25C VID = 200 mV VOH - Output High Voltage - V 3.4 VOL - Output Low Voltage - mV 56 57 TA = 25C VID = 200 mV OUTPUT LOW VOLTAGE vs POWER SUPPLY VOLTAGE 55 3.2 54 3 53 2.8 3 3.3 VCC - Power Supply Voltage - V 3.6 52 3 3.3 VCC - Power Supply Voltage - V 3.6 Figure 5 OUTPUT SHORT CIRCUIT CURRENT vs POWER SUPPLY VOLTAGE - Differential Transition Voltage - mV -80 I OS - Output Short Circuit Current - mA TA = 25C VO = 0 V 50 TA = 25C 40 Figure 6 DIFFERENTIAL TRANSITION VOLTAGE vs POWER SUPPLY VOLTAGE -76 -72 30 -68 20 -64 -60 -56 VIT+ VIT- 3 3.3 VCC - Power Supply Voltage - V 3.6 10 0 3 3.3 VCC - Power Supply Voltage - V 3.6 Figure 7 Figure 8 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415 - JUNE 2000 TYPICAL CHARACTERISTICS DIFFERENTIAL PROPAGATION DELAY vs DIFFERENTIAL INPUT VOLTAGE t PLH, t PHL - Differential Propagation Delay - ns t PLH, t PHL - Differential Propagation Delay - ns 4 4 DIFFERENTIAL PROPAGATION DELAY vs COMMON-MODE VOLTAGE 3 tPHL 2 tPLH 3 tPLH tPHL 2 1 TA = 25C, f = 20 MHz, VCM = 1.2 V, CI = 15 pF, VCC = 3.3 V 0 500 1000 1500 2000 2500 Differential Input Voltage - mV 3000 1 TA = 25C, f = 20 MHz, VCM = 1.2 V, CI = 15 pF, VCC = 3.3 V 0 0.5 1 1.5 Common-Mode Voltage - V 2 2.5 0 0 -0.5 Figure 9 Figure 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415 - JUNE 2000 MECHANICAL DATA D (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M Gage Plane 0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX 8 0.197 (5,00) 0.189 (4,80) 14 0.344 (8,75) 0.337 (8,55) 16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96 A MIN NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN65LVDS048 LVDS QUAD DIFFERENTIAL LINE RECEIVER SLLS415 - JUNE 2000 MECHANICAL DATA PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,65 14 8 0,30 0,19 0,10 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 8 14 16 20 24 28 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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