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  Datasheet File OCR Text:
 ERRATA TO THE TSB21LV03A DATA SHEET FOR SN104903PM DEVICE
(TEXAS INSTRUMENTS LITERATURE NO. SLLS278, NOVEMBER 1997)
This document contains corrections and additions to information in the TSB21LV03A data sheet (TI Literature Number SLLS278, November 1997) and is applicable to the SN104903PM device (symbolized TSB21LV03A1).
Application notes:
a. If a network of 5 or more SN104903PMs is connected, upon bus reset the SN104903PM network may not initially issue the correct number of self-ID packets. If this occurs, the SN104903PMs that did not issue a self-ID packet will cause another bus reset. This bus reset process will continue until the correct number of self-ID packets are issued, unless the process is interrupted by receipt of a non-self-ID packet. With 4 or fewer nodes the problem does not occur. The occurrences are greater at higher operating voltages. The average frequency of occurrence (number of resets before multiple self-ID packages occur) at room temperature with a supply voltage of 3.3 V is shown below: 5 nodes 6 nodes 7 nodes 8 nodes 9 nodes 10 nodes 84 resets 20 resets 16 resets 11 resets 3 resets 0 resets
With 10 or more nodes, every initiation of a reset will typically generate at least 1 more reset. These numbers are representative -- actual results may vary. Workaround: To allow the bus reset sequence described above to complete, it must not be interrupted by cycle start packets, PHY configuration packets, or asynchronous packets. It is recommended that upon bus reset, the isochronous resource manager node (and/or the bus manager node) should wait for 450 microseconds after the start of the initial bus reset and then check to see if another bus reset indication has been sent to the link. If another bus reset has been indicated, repeat the wait. If another bus reset has not been indicated, then resume cycle start packets and asynchronous packets. The bus manager should use the final package of self-IDs received. Note that if multiple bus resets occur, all nodes will have their gap counts reset to 3F hex (2 bus resets in a row set all gap counts to the default 3F hex). If operating in a larger network (5 or more SN104903PM PHYs in a branching configuration, or more than 7 in a daisy chain configuration), setting the gap counts to any value other than 3F may require multiple attempts and is not recommended. With more than 9 nodes, setting the gap count to any value other than 3F typically will not work.
1
Printed in U.S.A.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SLLS307 - June 1998
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated


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