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| General TSB12LV23 (OHCILynx) Implementation Guide June 1999 Mixed Signal Products SLLA045 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated Contents 1 Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 World Wide Web . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 TSB12LV23 (OHCI-Lynx) Function and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 TSB12LV23 Feature Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 OHCILynx System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Drop-In Compatiblity with the TSB12LV22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1 Serial EEPROM Drop-In Compatiblity Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.2 Connecting the Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 2 3 4 4 5 2 TSB12LV23 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Passive Component Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Required Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 The PHY-Link Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 The Link Layer - TSB12LV23 OHCI-Lynx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 The Link Layer - Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Isolation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Isolation vs Nonisolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Isolated Designs that Require Special Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Special Considerations for Bus Holder Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Standard TSB12LV23 Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.6 Impementing Galvanic Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Design Check List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Standard Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Design Specific Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 11 12 12 12 12 12 13 13 13 Appendix A PCI Bus Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 PCI Bus Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2 Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Appendix B Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.1 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B.2 Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Appendix C Terminal Descriptions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 C.1 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 C.2 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Appendix D Definitions Used with the Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 D.1 I/O Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 General TSB12LV23 (OHCI-Lynx) Implementation iii Figures List of Figures 1 TSB12LV23 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Typical System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Connecting the Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Link On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Clamping Voltage Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 TSB12LV23 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Reset Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 B-1 GPIO2 and GPIO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 C-1 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 D-1 3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 List of Tables 1 Internal Resistors and OHCI-Lynx Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Required Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 A-1 Minimum and Typical PCI Pull-Up Resistor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A-2 32-Bit PCI Signal System Board Pull-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 B-1 Registers and Bits Loadable through Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B-2 Serial EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 C-1 Signals Sorted by Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 C-2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 C-3 PCI System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 C-4 PCI Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 C-5 PCI Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 C-6 IEEE1394 PHY/Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 C-7 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 iv SLLA045 General TSB12LV23 (OHCILynx) Implementation Guide John Mayberry ABSTRACT This implementation guide assists platform hardware developers designing with the TSB12LV23 1394 Open Host Controller Interface (OHCI) Link-Layer Controller (LLC), referred to herein as the OHCI-Lynx. The document includes an overview of the TSB12LV23 function and features, terminal assignments and pinout illustrations, TSB12LV23 I/O electrical characteristics, identification of required passive components and recommendations for system implementation, and phy/link signal isolation considerations. 1 Product Support 1.1 Related Documentation The following list specifies product names, part numbers, and literature numbers of corresponding TI documentation. * Galvanic Isolation of the IEEE 1394-1995 Serial Bus, Literature number SLLA001 * Reference Designs for Host System Boards (SLLA049), Adapter Cards, Literature number SLLA048 and SLLA052, and Mobile, Literature number SLLA047 * TSB12LV23 Data Manual, Literature number SLLS328 1.2 World Wide Web Our World Wide Web site at www.ti.com contains the most up-to-date product information, revisions, and additions. Users registering with TI&ME can build custom information pages and receive new product updates automatically via email. 1.3 TSB12LV23 (OHCI-Lynx) Function and Features The Texas Instruments TSB12LV23 is a PCI-to-1394 host controller compatible with the latest PCI local bus, PCI bus power management interface, IEEE 1394-1995, and 1394 open host controller interface (OHCI) specifications. The chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. As required by the 1394 Open Host Controller Interface (OHCI) and IEEE 1394A Specifications, internal control registers are memory-mapped and non-prefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and provides Plug-and-Play (PnP) compatibility. Furthermore, the TSB12LV23 is compliant with the PCI Bus Power Management Interface Specification, per the PC 98 requirements. TSB12LV23 supports the D0, D2, and D3 power states. 1 The TSB12LV23 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at 132 Mbytes/s after connection to the memory controller. Since PCI latency can be large even on a PCI Revision 2.1 system, deep FIFOs are provided to buffer 1394 data. The TSB12LV23 provides physical write posting buffers and a highly tuned physical data path for SBP-2 performance. The TSB12LV23 also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus holding buffers on the PHY/Link interface, thus, making the TSB12LV23 the best-in-class 1394 OHCI solution. An advanced CMOS process is used to achieve low power consumption while operating at PCI clock rates up to 33 MHz. 1.4 TSB12LV23 Feature Set * IEEE1394 Open Host Controller Interface Specification 1.0 Compliant * IEEE1394-1995 and 1394.A Compliant * PCI Local Bus Specification Revision 2.1 Compliant and PCI 2.2 ready * PCI Power Management Compliant * 3.3-V Core Logic with Universal PCI Interface Compatible with 3.3-V and 5-V * * * * * * * * * * * * PCI Signalling Environment Supports Serial Bus Data Rates of 100, 200, and 400Mbit/s Provides Bus-Hold Buffers on Physical Interface for Low-Cost Single Capacitor Isolation Supports Physical Write Posting of up to Three Outstanding Transactions Serial ROM Interface Supports 2-Wire Devices Supports External Cycle Timer Control for Customized Synchronization Implements PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency Provides Two General-Purpose I/Os Fabricated in Advanced Low-Power CMOS Process Packaged in 100-Pin (PZ) LQFP Package Supports CLKRUN Drop-In Replacement for the TSB12LV22 Supports PCI and CardBus Applications 2 SLLA045 PCI Target SM Internal Registers Serial ROM OHCI PCI Power Mgmt & CLKRUN GPIOs MISC Interface ISO Transmit Contexts Async Transmit Contexts Transmit FIFO Physical DMA & Response Link Transmit Resp Timeout PCI Host Bus Interface Receive Acknowledge Central Arbiter & PCI Initiator SM PHY Register Access & Status Monitor Cycle Start Generator & Cycle Monitor CRC Request Filters Synthesized Bus Reset PHY / Link Interface General Request Receive Link Receive Async Response Receive Receive FIFO ISO Receive Contexts Figure 1. TSB12LV23 Block Diagram 1.5 OHCILynx System Implementation Figure 1 illustrates a platform using the TSB12LV23, which, along with the TSB41LV03, provides the necessary interface to implement a three-port IEEE1394 node. General TSB12LV23 (OHCILynx) 3 CPU VGA Controller AGP North Bridge Memory PCI Bus Phy/Link Interface Super I/O South Bridge TSB12LV23 1394 LLC TSB41LV03 Physical Layer ISA Figure 2. Typical System Architecture 1.6 Drop-In Compatibility with the TSB12LV22 The TSB12LV23 can be placed on a pad layout for the TSB12LV22 with no changes. It uses the exact same WDM drivers as the TSB12LV22 (i.e., 1394bus.sys and ohci1394.sys), which makes it a direct replacement for the TSB12LV22. The TSB12LV23 is designed to be drop-in compatible with OHCI-Lynx designs. Some I/Os implement weak pullup or pulldown resistors for drop-in compatibility with OHCI-Lynx. These internal resistors and OHCI-Lynx implementation requirements are noted in the following table. Table 1. Internal Resistors and OHCI-Lynx Implementation TERMINAL TERMINAL NAME CARDBUS/CYCLEOUT CLKRUN RST NO. 77 7 10 WEAK RESISTOR Pullup Pulldown Pullup DROP-IN DROP IN COMPATIBILITY NOTE OHCI-Lynx CYCLEOUT must be tied high or pulled up OHCI-Lynx RSVD must be unconnected or pulled down OHCI-Lynx TEST_EN must be tied high Refer, also, to the TSB12LV22 (OHCI-Lynx) Implementation Guide (literature number: SLLA025) for more information. 1.6.1 Serial EEPROM Drop-In Compatibility Implementation There has been no major change in the implementation of the serial EEPROM. However, The EEPROM programming code will need to be upgraded for the new TSB12LV23 register set. The EEPROM is used to load the system specific registers, such as the GUID. The data file, which loads the EEPROM, will need to be modified. However, for new boards, the EEPROM should be programmed with the modified data from the start. For retrofitted boards, the EEPROM should be reprogrammed so it loads all ,of the system specific registers correctly. If the EEPROM is being programmed from BIOS, programming the EEPROM is not a concern. 4 SLLA045 NOTE: Do not set GlobalByte swap bit via the EEPROM data file. This will cause problems (bit 0 at offset 13) In Addition, use TI's latest version of the EEPROM software to program the EEPROM, and follow these steps. The EEPROMs of all modified boards must be written, as the new registers beyond EEPROM word address 0xFh are written by the TSB12LV23 and the default value 0xFFh will set the GlobalSwap bit, which will effect operation. The following list of steps is a general procedure and should be used when modifying a PCB from the TSB12LV22 to the TSB12LV23. NOTE: The following procedure assumes that the EEPROM has been previously programmed with valid data. If the EEPROM has not previously been programmed, use the TSB12LV23 data file as a template to edit and program the EEPROM accordingly. 1. After replacing the TSB12LV22 with the TSB12LV23, dump the current contents of the serial EEPROM using TI's EEPROM utility: eelynx /d temp.dat 2. Edit the temp.dat file, appending the following register data to the end of the file: 010 011 012 013 014 0x10 0x00 0x24 0x00 0x00 ;00010000 Link Enhancement Byte 1 ;00000000 PCI Misc Byte 0 ;00100100 PCI Misc Byte 1 ;00000000 PCI OHCI Control Byte 0 ;00000000 CIS Offset 3. Program the EEPROM with the new file using the EELynx utility: eelynx /p temp.dat This procedure will set the proper defaults for the TSB12LV23 and will maintain the existing GUID as previously programmed. 1.6.2 Connecting the Serial EEPROM Implementation requires the connection of GPIO2 to SCL, and GPIO3 to SDA to enable on-board EEPROM programming. * It is recommended that header and jumpers for SCL and SDA lines be used to meet 1394.a security requirements. Jumpers on the EEPROM with write control can also be used. * Another alternative is to use a serial EEPROM with software write protection (SGS M34C02). General TSB12LV23 (OHCILynx) 5 U1 EEPROM 1 2 3 4 A0 A1 A2 GND VCC WC SCL SDA VCC 8 7 6 5 R1 2.7 k VCC VCC R2 2.7 k SCL SDA 3.3 V R3 4.7 k GPIO2 3.3 V R4 4.7 k JP1 JP2 GPIO3 Figure 3. Connecting the Serial EEPROM 6 SLLA045 2 TSB12LV23 Implementation 2.1 Passive Component Requirements 2.1.1 Required Pullup/Pulldown Resistors Several signals on the TSB12LV23 require a pullup or pulldown resistor. Table 2 provides a list of required resistors. Table 2. Required Pullup/Pulldown Resistors (see Note 1) SIGNAL SDA SCL RST RESISTOR Pullup Pullup Pullup Pullup (Default) Pulldown CYCLEIN GPI02 GPI03 Pullup Pulldown Pulldown RECOMMENDED VALUE () 2.7 k 2.7 k 4.7 k 4.7 k 220 4.7 k 220 220 CONDITION Required if implementation includes a serial EEPROM. Required if implementation includes a serial EEPROM. If the design does not use the D3_cold Power Management, then this terminal can be pulled up or RST can be connected to G_RST directly. Required when not implementing bus holder isolation Required when bus holder isolation is implemented Required if not implementing optional external 8-kHz clock. Required Required ISOLATED NOTE 1: All pullup/pulldown resistor value recommendations are provided as guidelines only. The best value for an individual design may vary depending upon board characteristics, standard design rules and practices, etc. General TSB12LV23 (OHCILynx) 7 The PHY-Link Interface 3 The PHY-Link Interface The PHY-Link interface follows the IEEE 1394-1995 and 1394.a standards. No isolation is implemented in this schematic. The PHY and Link operate with common power and ground planes. The schematic shows no adjustment for EMI considerations. To help minimize EMI, we suggest including a 0- resistor on the SCLK signal as close as possible to the PHY. If EMI issues are a concern, the value of this resistor can be adjusted to reduce emissions. This will also reduce reflections that may occur when the distance between the PHY and Link is large (greater than 4 inches.) The SCLK is a 49.152-MHz clock provided by the PHY to the Link. SCLK is essential for transactions on the PHY-Link interface as well as transactions within the Link. The LREQ, or Link Request, signal is an input to the PHY from the Link. The Link uses this to initiate a service request to the PHY. CTL0 and CTL1 are bidirectional signals used to control communication between the PHY and the Link. These terminals should be directly connected between the PHY and Link. Both the TSB12LV23 (Link layer) and the TSB41LV03 (Phy) are 400-Mbps devices, which use terminals D0-D7 to transport data bidirectionally, and should be connected directly to each other respectively (i.e., D0 D0 . . . D7 D7). The Link's PHY_LPS (Link Power Status) terminal is asserted to indicate that the Link is powered on. The LPS input on the PHY can be tied to either the Link layer's PHY_LPS terminal or the Link layer's VCC. In addition, the line connecting the Link's PHY_LPS terminal with the PHY's LPS terminal should be pull down to ground through a 1-k resistor. As is shown in Figure 4, the BMC/PHY_LINKON terminal on the TSB12LV23 is connected to the TSB41LV03 C/LKON terminal through a 1-k series resistor and 10-k pulldown resistor on the TSB41LV03 side. The PHY's LKON signal is used to activate (wake) the Link when the Link is not active. This signal is driven low as long as the Link is not active. R19 PHY Side C/LKON 1 k R22 10 k LINK Side BMC/PHY_LINKON Figure 4. Link On All of the above PHY-Link interface signals could also be connected to test header that would provide test points for new prototype. 8 SLLA045 The Link Layer - TSB12LV23 OHCI-Lynx 4 The Link Layer - TSB12LV23 OHCI-Lynx The TSB12LV23 is a 400-Mbps Link-layer specifically designed with power management and CARDBUS features. All of the 3.3-V VCC power terminals on the TSB12LV23 should be coupled together and grounded through a series of high-frequency decoupling capacitors. * Place one 0.01-F and one 0.1-F capacitor as closely as possible to each power terminal on the Link. This will help minimize switching noise. * Also use a single 47-F capacitor to reduce dc ripple. The VCCP power terminals provide a voltage clamping rail for 5-V tolerant inputs. The VCCP voltage is determine by the PCI bus voltage. Figure 5 illustrates the voltage clamping rail. 3.3 V VCCP D1 3.3 V D2 PAD Figure 5. Clamping Voltage Diagram If the design uses a 5-V supply, the VCCP terminals should be tied to the 5-V supply. Otherwise, VCCP should be connected to the 3.3-V. The ISOLATED terminal is used to the enable bus holders for isolated designs. However, for most designs this is not required. * To disable the bus-holders connect the ISOLATED terminal to 3.3 V through a 4.7-k pullup resistor. * To enable the bus-holders connect the ISOLATED terminal to GND through a 220- pulldown resistor. The CARDBUS/CYCLEOUT terminal is sampled when G_RST is asserted, and it selects between the PCI and CardBus buffers. After reset, this terminal may also function as CYCLEOUT which provides an 8-kHz cycle timer synchronization signal. * To use the PCI bus buffers this terminal should be left unconnected, and an internal pullup resistor will enable the PCI buffers. * To enable the CardBus buffers this terminal should be pulled down with a 220- resistor. It is important that a weak pulldown resistor be used if the design is going to use the CYCLEOUT feature. General TSB12LV23 (OHCILynx) 9 The Link Layer - TSB12LV23 OHCI-Lynx The CYCLEIN terminal can be used to receive an optional external 8-kHz clock used as a cycle timer, which provides synchronization with other system devices. If not implemented, a 4.7-k pullup resistor should be used to tie this terminal to 3.3 V. The TSB12LV23's G_RST terminal allows for retaining context from a D3 to D0 transition when the PCI interface may transition from B3 to B0 and issue a PCI reset. The TSB12LV23 resets are illustrated in Figure 6. RST 1 2 3 RESET Non-PME Context RESET G_RST PME Context Figure 6. TSB12LV23 Reset Block Diagram If the design supports D3_Wake, then the G_RST terminal provides the hardware reset at power on, while the RST terminal should be connected to the PCI Bus RST, which will provides resets that retain the PME context. For designs that will not support D3_Wake, the RST terminal can either be pulled up to 3.3 V through a 4.7-k resistor or tied together with the G_RST terminal. An example implementation is shown in Figure 7. RST (76) R2 0 R1 Power On Reset 0 NOTE: For normal operation populate R2 and do not populate R1 For Mobile or D3_Wake operation populate R1 and do not populate R2 RST G_RST (10) Figure 7. Reset Schematic The CLKRUN terminal is used to turn the clock on and off. This is useful in mobile design where conserving power is important. When implementing CLKRUN, this terminal is connected to external circuitry that provides a common CLKRUN control signal. If the clock is never turned off, then this terminal should be left unconnected and an internal pulldown resistor will keep the clock active. The GPIO2 and GPIO3 are general-purpose I/O terminals that should each be pulled down to GND through a 220- resistors. For more information on the TSB12LV23, consult the TI data manual, TSB12LV23 (OHCI-LYNX) IEEE 1394-1995 Link-Layer Controller (literature number SLLS328). 10 SLLA045 The Link Layer - Serial EEPROM 5 The Link Layer - Serial EEPROM The Serial EEPROM provides a convenient mechanism to load system-specific data and is detected at reset via SDA and SCL terminals. The following are the types of data stored in the EEPROM: * PCI: Max latency, min grant, subsystem VID, subsystem ID, Link enhancements, miscellaneous control, and CIS offset * OHCI: GUID, HCControl.programPhyEnable The serial EEPROM is required for adapter cards, but it is optional for implementations where the BIOS is used to load GUID and other system-specific registers. SDA and SCL should each be pulled up to EEPROM VCC through 2.7-k resistors, and then connected to the EPROM's SDA and SCL terminals respectively (as is illustrated in Figure 8). If no serial EEPROM is used, then both the SDA and SCL terminals should be connected to ground through 220- pulldown resistors. R7 SDA (5) 2.7 k R8 SCL (4) 2.7 k R9 4.7 k 5 JP1 EEPROM VCC 6 7 8 U4 SDA SCL WC VCC EEPROM GND A2 A1 A0 4 3 2 1 EEPROM VCC Figure 8. Serial EEPROM If the EEPROM has a write enable terminal, it should be connected to EEPROM VCC with a pullup resistor. In addition, a jumper to GND should be connected in series the pullup, as illustrated in Figure 8. This will allow the EEPROM to be write-enabled and write-disabled. 5.1 Isolation Considerations 5.1.1 Isolation vs Nonisolation * Isolation provides protection against data corruption and/or physical harm * that can be caused by ground potential differences between nodes. Typical PC usage models do not require isolation (i.e., all connected devices share a common green-wire ground). NOTE: LAN type environments may be a special case General TSB12LV23 (OHCILynx) 11 The Link Layer - Serial EEPROM 5.1.2 Isolated Designs that Require Special Consideration * PHY/Link signal isolation * Phy/Link ground return * Isolated power supply 5.1.3 Special Considerations for Bus Holder Isolation Phy/Link interface signals must be ac coupled. * Single 0.001-F (non-polarized) decoupled capacitor per signal SCLK, LREQ, CTL0, CTL1, D0 - D7 LPS and LINKON require additional considerations A current path must be provided between the PHY ground and the Link ground to ensure signal integrity. 5.1.4 Standard TSB12LV23 Considerations * ISOLATED terminal must be pulled down to enable the bus holders * VCCP clamp should be tied to 5 V only if a PCI-Bus voltage is 5 V. Otherwise, * VCCP should be tied to 3.3 V. The serial EEPROM is required for adapter cards. 5.1.5 Power Requirements * Alternate power providers Requires isolated load output from the power supply - Alternate dc-to-dc converter, but expensive for power densities required - Single diode isolation of power source - Standard power provider or alternate power provider with launch voltage > 20 V requires per power diode isolation. - Per port current limit (1.5 A) required. PHY decoupling capacitor considerations apply. - * 5.1.6 Implementing Galvanic Isolation For detailed information on galvanic isolation, refer to the Galvanic Isolation Applications Note (literature number: SLLA011). 12 SLLA045 The Link Layer - Serial EEPROM 5.2 Design Check List 5.2.1 Standard Requirements * Required pullup and pulldown resistors * Decoupling capacitors * Clamping voltage VCCP * ISOLATED terminal must be pulled up to disable the bus holders 5.2.2 Design Specific Requirements * Drop-in replacement for the TSB12LV22 RST should either be pulled up or tied directly to G_RST terminal (RST was TEST_EN on the TSB12LV22). - CARDBUS/CYCLEOUT is pulled up - CLKRUN unconnected - Serial EEPROM has been reprogrammed or programmed with the GlobalByte swap bit 0 at offset 13h has been cleared (set = 0) Adapter card design - Serial EEPROM required - 3.3-V supply for Link Core - CLKRUN unconnected - RST should either be pulled up or tied directly to G_RST terminal (RST was TEST_EN on the TSB12LV22). Mobile or Wake D3_cold Design - 3.3-V EEPROM if required - VCCP = 3.3 V - G_RST and RST are configured for D3_cold - CLKRUN has optional 0- resistor or has been connected to external CLKRUN circuitry Isolated Design In addition to one of the previous selections, this design will also be isolated. - ISOLATED terminal must be pulled down to enable the bus holders - Single 0.001-F (non-polarized) decoupled capacitor per signal SCLK, LREQ, CTL0, CTL1, D0 - D7 LPS and LINKON require additional considerations - PHY/Link signal isolation - Phy/Link ground return - Isolated power supply - * * * General TSB12LV23 (OHCILynx) 13 14 SLLA045 PCI Bus Requirements Appendix A A.1 PCI Bus Requirements PCI Bus Requirements The following paragraph summarizes paragraph 4.3.3 of the PCI Local Bus Specification Revision 2.1 and is provided for reference only. Please refer to the PCI Local Bus Specification for a full discussion on pull-up resistors required for PCI local bus implementations. All PCI control signals require pullup resistors on the motherboard to guarantee that they are at a stable state when no agent is actively driving the signal. Pullups should be implemented on the motherboard only. Expansion boards or add-in cards should not provide pullup resistors for the PCI control signals. The following PCI signals require pullup resistors: * FRAME * TRDY * IRDY * DEVSEL * STOP * SERR * PERR * LOCK * INTA * INTB * INTC * INTD * REQ64 (when used) * ACK64 (when used) Pullups are not required on point-to-point or shared 32-bit signals, as bus parking guarantees their stability. If the 64-bit data path expansion signals, AD(63:32), C/BE(7:4)#, and PAR64, are connected they must be pulled-up as well. Table xxx lists the 32-bit PCI signals implemented on the TSB12LV23 that require pullup resistors on the system board. Minimum and maximum values for required PCI pullup resistors can be calculated using the following formulas: R min + I CC min ol ) 16 V * Vol I il Where 16 = maximum number of loads R min V *V CC min + num_loads ol I il Where: VX = 2.7V for 5-V signaling VX = 0.7 VCC for 3.3-V signaling General TSB12LV23 (OHCI-Lynx) Implementation A-1 PCI Bus Requirements Minimum and typical values for both 5-V and 3.3-V signaling environments are shown in the following table. Table A-1. Minimum and Typical PCI Pull-Up Resistor Values SIGNALING RAIL 5V 3.3 V Rmin 963 2.42 k Rtyp 2.7 k 10% 8.2 k 10% Rmax Dependent on number of loads (see formula) Dependent on number of loads (see formula) Table A-2. 32-Bit PCI Signal System Board Pull-Up Requirements PCI SIGNAL FRAME TRDY IRDY DEVSEL STOP SERR PERR INTA PULL-UP VOLTAGE VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP A.2 Bypass Capacitors Standard design rules for the supply bypass should be followed. Low inductance ceramic chip capacitors are best for bypass capacitors. A value of 0.1 F is recommended for each of the power supply pins: VCC, VCCS, VCCP. A-2 SLLA045 Serial EEPROM Appendix B B.1 GPIO Interface Serial EEPROM The general-purpose input/output (GPIO) interface consists of two GPIO ports. GPIO2 and GPIO3 power up as general-purpose inputs and are programmable via the GPIO control register. B-1 shows the schematic for GPIO2 and GPIO3 implementation. GPIO0 and GPIO1 are not implemented in the TSB12LV23. The terminals for these legacy GPIOs from the TSB12LV23 have been dedicated to BMC/LINKON and LPS, respectively. GPIO Read Data GPIO Write Data D Q GPIO Port GPIO_Invert GPIO Enable Figure B-1. GPIO2 and GPIO3 B.2 Serial Bus Interface The TSB12LV23 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration registers through a serial EEPROM. The TSB12LV23 communicates with the serial EEPROM via the 2-wire serial interface. After power-up the serial interface initializes the locations listed in Table B-1. While the TSB12LV23 is accessing the serial ROM, all incoming PCI slave accesses are terminated with retry status. Table B-2 shows the serial ROM memory map required for initializing the TSB12LV23 registers. Table B-1. Registers and Bits Loadable through Serial EEPROM OFFSET OHCI register (24h) OHCI register(28h) OHCI register (50h) PCI register (2Ch) PCI register (2Dh) PCI register (3Eh) PCI register (F4h) PCI register (F0h) PCI register (40h) REGISTER 1394 GlobalUniqueIDHi 1394 GlobalUniqueIDLo Host control register PCI subsystem ID PCI vendor ID PCI maximum latency, PCI minimum grant Link enhancements control register PCI miscellaneous register PCI OHCI register BITS LOADED FROM EEPROM 31-0 31-0 23 15-0 15-0 15-0 13, 12, 9, 8, 7, 2, 1 15, 13, 10, 5-0 0 General TSB12LV23 (OHCI-Lynx) Implementation B-1 Serial EEPROM Table B-2. Serial EEPROM Map BYTE ADDRESS 00 01 02 03 04 05 [7] Link_enhancementControl.enab_unfair [6] HCControl. ProgramPhy Enable [5] RSVD PCI maximum latency (0h) PCI vendor ID PCI vendor ID (msbyte) PCI subsystem ID (lsbyte) PCI subsystem ID [4] RSVD [3] RSVD [2] Link_enhancementControl.enab_ insert_idle [1] Link_enhancementControl.enab_accel [0] RSVD BYTE DESCRIPTION PCI_minimum grant (0h) 06 07 08 09 0A 0B 0C 0D 0E 0F 10 [15] RSVD [14] RSVD Mini ROM address 1394 GlobalUniqueIDHi (lsbyte 0) 1394 GlobalUniqueIDHi (byte 1) 1394 GlobalUniqueIDHi (byte 2) 1394 GlobalUniqueIDHi (msbyte 3) 1394 GlobalUniqueIDLo (lsbyte 0) 1394 GlobalUniqueIDLo (byte 1) 1394 GlobalUniqueIDLo (byte 2) 1394 GlobalUniqueIDLo (msbyte 3) Checksum [13-12] AT threshold [11] RSVD [10] RSVD [9] Enable audio timestamp [1] Disable PCI gate [8] Enable DV CIP timestamp [0] Keep PCI 11 [7] RSVD [6] RSVD [5] RSVD [4] Disable Target Abort [12] RSVD [3] GP2IIC [2] Disable SCLK gate 12 [15] PME D3 Cold [14] RSVD [13] PME Support D2 [5] RSVD [11] RSVD [10] D2 support [9] RSVD [8] RSVD 13 [7] RSVD [6] RSVD [4] RSVD [3] RSVD [2] RSVD [1] RSVD [0] Global swap 14 15-1E 1F CIS offset address RSVD RSVD B-2 SLLA045 Terminal Descriptions and Functions Appendix C C.1 Terminal Assignments Terminal Descriptions and Functions This section provides the terminal assignments for the TSB12LV23. GND PHY_LPS BMC/PHY_LINKON PHY_LREQ 3.3 VCC PHY_SCLK GND PHY_CTL0 PHY_CTL1 3.3 VCC PHY_DATA0 PHY_DATA1 PHY_DATA2 VCCS PHY_DATA3 PHY_DATA4 PHY_DATA5 GND PHY_DATA6 PHY_DATA7 3.3 VCC ISOLATED CYCLEIN CARDBUS/CYCLEOUT RST GND GPIO2 GPIO3 SCL SDA VCCS CLKRUN PCI_INTA/CINT 3.3 VCC G_RST GND PCI_CLK 3.3 VCC PCI_GNT PCI_REQ VCCP PCI_PME/CSTSCHG PCI_AD31 PCI_AD30 3.3 VCC PCI_AD29 PCI_AD28 PCI_AD27 GND PCI_AD26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PZ PACKAGE (TOP VIEW) GND PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 3.3 VCC PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_C/BE0 PCI_AD8 VCCP PCI_AD9 PCI_AD10 GND PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 3.3 VCC PCI_AD15 PCI_C/BE1 PCI_PAR PCI_SERR PCI_AD25 PCI_AD24 PCI_C/BE3 PCI_IDSEL GND PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 3.3 VCC PCI_AD19 PCI_AD18 PCI_AD17 VCCP PCI_AD16 PCI_C/BE2 GND PCI_FRAME PCI_IRDY PCI_TRDY 3.3 VCC PCI_DEVSEL PCI_STOP PCI_PERR GND Figure C-1. Terminal Assignments General TSB12LV23 (OHCI-Lynx) Implementation C-1 Terminal Descriptions and Functions Table C-1. Signals Sorted by Pin Number NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TERMINAL NAME GND GPIO2 GPIO3 SCL SDA VCCP CLKRUN PCI_INTA/CINT 3.3 VCC G_RST GND PCI_CLK 3.3 VCC PCI_GNT PCI_REQ VCCP PCI_PME/CSTSCHG PCI_AD31 PCI_AD30 3.3 VCC PCI_AD29 PCI_AD28 PCI_AD27 GND PCI_AD26 NO. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TERMINAL NAME PCI_AD25 PCI_AD24 PCI_C/BE3 PCI_IDSEL GND PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 3.3 VCC PCI_AD19 PCI_AD18 PCI_AD17 VCCP PCI_AD16 PCI_C/BE2 GND PCI_FRAME PCI_IRDY PCI_TRDY 3.3 VCC PCI_DEVSEL PCI_STOP PCI_PERR GND NO. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 TERMINAL NAME PCI_SERR PCI_PAR PCI_C/BE1 PCI_AD15 3.3 VCC PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 GND PCI_AD10 PCI_AD9 VCCP PCI_AD8 PCI_C/BE0 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 3.3 VCC PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 GND NO. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TERMINAL NAME RST CARDBUS/CYCLEOUT CYCLEIN ISOLATED 3.3 VCC PHY_DATA7 PHY_DATA6 GND PHY_DATA5 PHY_DATA4 PHY_DATA3 VCCP PHY_DATA2 PHY_DATA1 PHY_DATA0 3.3 VCC PHY_CTL1 PHY_CTL0 GND PHY_SCLK 3.3 VCC PHY_LREQ PHY_LINKON PHY_LPS GND C.2 Terminal Functions The terminals are grouped in tables by functionality, such as PCI system function, power supply function, etc. The terminal numbers are also listed for convenient reference. Table C-2. Power Supply TERMINAL NAME GND NO. 1, 11, 24, 30, 42, 50, 60, 75, 83, 94, 100 9, 13, 20, 35, 46, 55, 70, 80, 91, 96 6, 16, 39, 63, 87 I/O DESCRIPTION I Device ground terminals 3.3 VCC VCCP I 3.3-V power supply terminals I PCI signaling clamp voltage power input. PCI signals are clamped per the PCI Local Bus Specification. C-2 SLLA045 Terminal Descriptions and Functions Table C-3. PCI System TERMINAL NAME PCI_CLK G_RST PCI_INTA/CINT NO. 12 10 8 I/O I I O DESCRIPTION PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at rising edge of PCLK. Global power reset. This reset brings all of the TSB12LV23 to its default state, including those registers not reset by RST. When asserted, the device is completely nonfunctional. Interrupt signal. This output indicates interrupts from the TSB12LV23 to the host. This terminal signals an interrupt based upon the CARDBUS input terminal. PCI or CardBus reset. When this bus reset is asserted, the TSB12LV23 places all output buffers in a high impedance state and resets all internal registers except device power management context- and vendor-specific bits initialized by host power on software. When asserted, the device is completely nonfunctional. RST 76 I Table C-4. PCI Address and Data TERMINAL NAME PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD PCI_AD0 PCI_C/BE0 PCI_C/BE1 PCI_C/BE2 PCI_C/BE3 NO. 18 19 21 22 23 25 26 27 31 32 33 34 36 37 38 40 54 56 57 58 59 61 62 64 66 67 68 69 71 72 73 74 65 53 41 28 I/O DESCRIPTION I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface during the address phase of a PCI cycle, AD31-AD0 contain a 32-bit address or other destination information. During the data phase, AD31-AD0 contain data. I/O PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI terminals. During the address phase of a bus cycle C/BE3-C/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. PCI parity. In all PCI bus read and write cycles, the TSB12LV23 calculates even parity across the AD and C/BE buses. As an initiator during PCI cycles, the TSB12LV23 outputs this parity indicator with a one PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator's parity indicator; a miscompare can result in a parity error assertion (PERR). PCI_PAR 52 I/O General TSB12LV23 (OHCI-Lynx) Implementation C-3 Terminal Descriptions and Functions Table C-5. PCI Interface Control TERMINAL NAME PCI_DEVSEL NO. 47 I/O DESCRIPTION PCI device select. The TSB12LV23 asserts this signal to claim a PCI cycle as the target device. As a PCI initiator, the TSB12LV23 monitors this signal until a target responds. If no target responds before time-out occurs, then the TSB12LV23 terminates the cycle with an initiator abort. PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue until while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase. PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB12LV23 access to the PCI bus after the current data transaction has completed. This signal may or may not follow a PCI bus request depending upon the PCI bus parking algorithm. Initialization device select. IDSEL selects the TSB12LV23 during configuration space accesses. IDSEL can be connected to 1 of the upper 24 PCI address lines on the PCI bus. PCI initiator ready. IRDY indicates the PCI bus initiator's ability to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCLK where both IRDY and TRDY are asserted; until which wait states are inserted. PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do not support burst data transfers. Clock run. This terminal provides clock control through the CLKRUN protocol. An internal pulldown resistor is implemented on this terminal for TSB12LV22 drop-in compatibility. PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match PAR when enabled through the command register. PME or card status change. This terminal indicates wake events to the host. When in a CardBus configuration, per the CARDBUS sample, the CSTSCHG output is an active high. PCI bus request. Asserted by the TSB12LV23 to request access to the bus as an initiator. The host arbiter asserts the GNT signal when the TSB12LV23 has been granted access to the bus. PCI system error. Output pulsed from the TSB12LV23 when enabled indicating an address parity error has occurred. The TSB12LV23 needs not be the target of the PCI cycle to assert this signal. PCI target ready. TRDY indicates the PCI bus target's ability to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCLK where both IRDY and TRDY are asserted; until which wait states are inserted. I/O PCI_FRAME 43 I/O PCI_GNT 14 I PCI_IDSEL 29 I PCI_IRDY 44 I/O PCI_STOP 48 I/O CLKRUN PCI_PERR PCI_PME/ CSTSCHG PCI_REQ PCI_SERR 7 49 17 15 51 I/O I/O O O O PCI_TRDY 45 I/O Table C-6. IEEE1394 PHY/Link TERMINAL NAME PHY_CTL1 PHY_CTL0 PHY_DATA7 PHY_DATA6 PHY_DATA5 PHY_DATA4 PHY_DATA3 PHY_DATA2 PHY_DATA1 PHY_DATA0 PHY_SCLK PHY_LREQ PHY_LINKON PHY_LPS NO. 92 93 81 82 84 85 86 88 89 90 95 97 98 99 I/O DESCRIPTION Phy-link interface control. These bidirectional signals control passage of information between the two devices. The TSB12LV23 can only drive these terminals after the PHY has granted permission following a link request (LREQ). I/O I/O Phy-link interface data. These bidirectional signals pass data between the TSB12LV23 and the PHY device. These terminals are driven by the TSB12LV23 on transmissions and are driven by the PHY on reception. Only DATA1-DATA0 are valid for 100-Mbit speeds, DATA3-DATA0 are valid for 200-Mbit speeds, and DATA7-DATA0 are valid for 400-Mbit speeds. I O I/O I/O System clock. This input from the PHY provides a 49.152 MHz clock signal for data synchronization. Link request. This signal is driven by the TSB12LV23 to initiate a request for the PHY to perform some service. LinkOn wake indication. Used and defined by 1394A and 3.3-V signaling is required. Link power status. Used and defined by 1394A and 3.3-V signaling is required. C-4 SLLA045 Terminal Descriptions and Functions Table C-7. Miscellaneous TERMINAL NAME SDA NO. 5 I/O DESCRIPTION Serial data. The TSB12LV23 determines whether a two-wire serial ROM, or no serial ROM is implemented at reset. If a two-wire serial ROM is detected, then this terminal provides the SDA serial data signaling. If no EEPROM is implemented, this terminal should be pulled down. Otherwise, it pullup is required. Serial clock. The TSB12LV23 determines whether a two-wire, or no serial ROM is implemented at reset. If a two-wire serial ROM is implemented, then this terminal provides the SCL serial clock signaling. If implemented, this terminal should be pulled high with a resistor. Phy-link isolation barrier mode. This terminal should be asserted when the PHY device is electrically isolated from the TSB12LV23. This input controls bus-hold I/Os. If bus holder isolation is not implemented, this terminal should be pulled high with a resistor. The CYCLEIN terminal can provide an optional external 8 kHz clock set up as a cycle timer that can be used for synchronization with other system devices. This terminal should be pulled high with a resistor. This terminal is sampled when G_RST is asserted, and it selects between PCI buffers and CardBus buffers. After reset, this terminal may also function as CYCLEOUT which provides an 8 kHz cycle timer synchronization signal. For normal operation, this terminal should be left unconnected and an internal pullup will enable the PCI buffers. General-purpose I/O [3]. This terminal requires a pull-down or pull-up resistor. General-purpose I/O [2]. This terminal requires a pull-down or pull-up resistor. I/O SCL 4 I/O ISOLATED 79 I CYCLEIN 78 I/O CARDBUS/ CYCLEOUT GPIO3 GPIO2 77 I/O 3 2 I/O I/O General TSB12LV23 (OHCI-Lynx) Implementation C-5 C-6 SLLA045 Definitions Used with the Application Examples Appendix D D.1 Definitions Used with the Application Examples I/O Electrical Characteristics Figure D-1 shows a 3-state bidirectional buffer for reference. Note that the PCI interface signals meet the AC requirements of the PCI release 2.1 specification. VCCX Tied for Open Drain Function OE Pad Figure D-1. 3-State Bidirectional Buffer General TSB12LV23 (OHCI-Lynx) Implementation D-1 D-2 SLLA045 |
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