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| TPIC5303 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS039A - SEPTEMBER 1994 - REVISED SEPTEMBER 1995 * * * * * Low rDS(on) . . . 0.4 Typ High Voltage Output . . . 60 V Extended ESD Capability . . . 4000 V Pulsed Current . . . 5 A Per Channel Fast Commutation Speed D PACKAGE (TOP VIEW) description 11 The TPIC5303 is a monolithic gate-protected 7 10 power DMOS array that consists of three 8 9 independent electrically isolated N-channel enhancement-mode DMOS transistors. Each transistor features integrated high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-k resistor. DRAIN2 DRAIN2 SOURCE2 SOURCE2 GATE2 DRAIN3 DRAIN3 GND 1 2 3 4 5 6 16 15 14 13 12 GATE1 SOURCE1 SOURCE1 DRAIN1 DRAIN1 SOURCE3 SOURCE3 GATE3 The TPIC5303 is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized for operation over the case temperature range of - 40C to 125C. schematic DRAIN1 12, 13 GATE2 5 DRAIN2 1, 2 GATE3 9 DRAIN3 6, 7 Q1 GATE1 16 Z1 D1 Q2 Z2 ZC2b ZC2a D2 Q3 Z3 ZC3b ZC3a D3 ZC1b ZC1a 14, 15 SOURCE1 8 GND 3, 4 SOURCE2 10, 11 SOURCE3 NOTE A: For correct operation, no terminal pin may be taken below GND. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1995, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TPIC5303 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS039A - SEPTEMBER 1994 - REVISED SEPTEMBER 1995 absolute maximum ratings over operating case temperature range (unless otherwise noted) Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Source-to-GND voltage (Q1, Q2, and Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage (Q1, Q2, and Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 9 V to 18 V Continuous drain current, each output, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A Continuous source-to-drain diode current, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A Pulsed drain current, each output, Imax, TC = 25C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 5 A Continuous gate-to-source zener-diode current, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Pulsed gate-to-source zener-diode current, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Single-pulse avalanche energy, EAS, TC = 25C (see Figures 4, 15, and 16) . . . . . . . . . . . . . . . . . . . 10.2 mJ Continuous total power dissipation, TC = 25C (see Figure 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.08 W Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Pulse duration = 10 ms, duty cycle = 2% 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5303 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS039A - SEPTEMBER 1994 - REVISED SEPTEMBER 1995 electrical characteristics, TC = 25C (unless otherwise noted) PARAMETER V(BR)DSX VGS(th) V(BR)GS V(BR)SG V(BR) VDS(on) VF(SD) VF IDSS IGSSF IGSSR Ilk lkg Drain-to-source breakdown voltage Gate-to-source threshold voltage Gate-to-source breakdown voltage Source-to-gate breakdown voltage Reverse drain-to-GND breakdown voltage (across D1, D2, D3) Drain-to-source on-state voltage TEST CONDITIONS ID = 250 A, ID = 1 mA, See Figure 5 IGS = 250 A ISG = 250 A Drain-to-GND current = 250 A ID = 1.4 A, See Notes 2 and 3 VGS = 10 V, VGS = 0 VDS = VGS, MIN 60 1.5 18 9 100 0.56 0.64 1.8 2.2 TYP MAX UNIT V V V V V V Forward on-state voltage, source-to-drain IS = 1.4 A, VGS = 0 (Z1, Z2, Z3), See Notes 2 and 3 and Figure 12 ID = 1.4 A (D1, D2, D3), See Notes 2 and 3 VDS = 48 V, , VGS = 0 VGS = 15 V, VSG = 5 V, VDGND = 48 V VGS = 10 V, ID = 1.4 A, , See Notes 2 and 3 and Figures 6 and 7 TC = 25C TC = 125C VDS = 0 VDS = 0 TC = 25C TC = 125C TC = 25C TC = 125C 1 0.9 1.1 V Forward on-state voltage, GND-to-drain Zero-gate-voltage Zero gate voltage drain current Forward-gate current, drain short circuited to source Reverse-gate current, drain short circuited to source Leakage current, drain-to-GND current drain to GND 5 0.05 0.5 20 10 0.05 0.5 0.4 0.62 1.19 107 137 89 28 1 10 200 100 1 10 0.46 V A nA nA A rDS( ) DS(on) Static drain-to-source on-state resistance drain to source on state 0.66 S gfs Ciss Coss Crss Forward transconductance Short-circuit input capacitance, common source Short-circuit output capacitance, common source Short-circuit reverse transfer capacitance, common source VDS = 15 V, ID = 0.7 A, See Notes 2 and 3 and Figure 9 VDS = 25 V, f = 1 MHz, VGS = 0, See Figure 11 71 22 pF F NOTES: 2. Technique should limit TJ - TC to 10C maximum. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain and GND-to-drain diode characteristics, TC = 25C PARAMETER trr QRR Reverse-recovery Reverse recovery time TEST CONDITIONS Z1, Z2, and Z3 IS = 0.7 A, VGS = 0, 0 See Figures 1 and 14 VDS = 48 V, di/dt = 100 A/s A/s, D1, D2, and D3 Z1, Z2, and Z3 D1, D2, and D3 MIN TYP 92 244 0.1 1.3 MAX UNIT ns C Total diode charge POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TPIC5303 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS039A - SEPTEMBER 1994 - REVISED SEPTEMBER 1995 resistive-load switching characteristics, TC = 25C PARAMETER td(on) td(off) tr2 tf2 Qg Qgs(th) Qgd LD LS Rg Turn-on delay time Turn-off delay time Rise time Fall time Total gate charge Threshold gate-to-source charge Gate-to-drain charge Internal drain inductance Internal source inductance Internal gate resistance VDS = 48 V, V See Figure 3 ID = 0 7 A, 0.7 A VGS = 10 V, V VDD = 25 V, , tf1 = 10 ns, RL = 36 , , See Figure 2 tr1 = 10 ns, , TEST CONDITIONS MIN TYP 25 27 15 7 2.1 0.3 1.2 5 5 0.25 nH MAX 40 40 25 14 2.6 0.38 1.5 nC ns UNIT thermal resistance PARAMETER RJA RJB Junction-to-ambient thermal resistance Junction-to-board thermal resistance TEST CONDITIONS See Notes 4 and 7 See Notes 5 and 7 MIN TYP 115 64 33 C/W MAX UNIT RJP Junction-to-pin thermal resistance See Notes 6 and 7 NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink. 5. Package mounted on a 24 inch2, 4-layer FR4 printed-circuit board. 6. Package mounted in intimate contact with infinite heatsink. 7. All outputs with equal power PARAMETER MEASUREMENT INFORMATION 1 Reverse di/dt = 100 A/s 0.5 I S - Source-to-Drain Diode Current - A 0 - 0.5 25% of IRM -1 Shaded Area = QRR - 1.5 -2 - 2.5 IRM -3 0 100 200 300 400 trr(SD) 500 600 VDS = 48 V VGS = 0 TJ = 25C Z1, Z2, and Z3 700 800 900 1000 Time - ns IRM = maximum recovery current The above waveform is representative of D1, D2, and D3 in shape only. Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5303 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS039A - SEPTEMBER 1994 - REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION VDD = 25 V tr1 RL Pulse Generator VGS DUT Rgen 50 50 CL 30 pF (see Note A) VDS td(on) tf2 VDS VGS 0V td(off) tr2 VDD VDS(on) tf1 10 V VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms Current Regulator 12-V Battery 0.2 F 50 k 0.3 F VDS VDD VGS DUT Gate Voltage Time IG CurrentSampling Resistor TEST CIRCUIT ID CurrentSampling Resistor VOLTAGE WAVEFORM Same Type as DUT 10 V Qgs(th) Qgd Qg 0V IG = 100 A Figure 3. Gate-Charge Test Circuit and Waveform POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TPIC5303 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS039A - SEPTEMBER 1994 - REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION VDD = 25 V tw VGS 0V ID IAS (see Note B) 0V 50 VDS V(BR)DSX = 60 V Min tav 15 V 476 H Pulse Generator (see Note A) 50 Rgen VDS ID VGS DUT 0V VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration (tw) is increased until peak current IAS = 5 A. I V t av AS (BR)DSX Energy test level is defined as E 10.2 mJ, where AS 2 tav = avalanche time. + + Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VGS(th) - Gate-to-Source Threshold Voltage - V 2.5 VDS = VGS 2 ID = 1 mA 1.5 ID = 100 A 1 r DS(on) - Static Drain-to-Source STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 0.8 ID = 1.4 A On-State Resistance - 0.6 VGS = 10 V 0.4 VGS = 15 V 0.2 0.5 0 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ - Junction Temperature - C 0 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ - Junction Temperature - C Figure 5 Figure 6 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC5303 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS039A - SEPTEMBER 1994 - REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 1 0.9 0.8 0.7 On-State Resistance - 0.6 VGS = 10 V I D - Drain Current - A 0.5 0.4 0.3 5 TJ = 25C VGS = 15 V 4.5 4 3.5 3 2.5 VGS = 4 V 2 1.5 1 0.5 0.1 0.1 1 ID - Drain Current - A 10 0 0 2 4 VGS = 2.8 V VGS = 5.6 V DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE r DS(on) - Static Drain-to-Source nVGS = 0.4 V TJ = 25C (unless otherwise noted VGS = 10 V VGS = 15 V 0.2 6 8 VDS - Drain-to-Source Voltage - V Figure 7 Figure 8 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE 5 Total Number of Units = 2064 VDS = 15 V ID = 0.7 A TJ = 25C TJ = - 40C 4 I D - Drain Current - A TJ = 25C TJ = 75C 3 TJ = 150C TJ = 125C DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 75 70 65 60 Percentage of Units - % 55 50 45 40 35 30 25 20 15 10 5 0 1.04 1.07 1.10 1.13 1.16 1.19 1.22 1.25 1.28 1.31 1.34 1.37 1.40 0 0 1 2 1 2 3 5 7 4 6 VGS - Gate-to-Source Voltage - V 8 gfs - Forward Transconductance - S Figure 9 Figure 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TPIC5303 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS039A - SEPTEMBER 1994 - REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 250 225 200 C - Capacitance - pF 175 150 125 100 75 50 25 0 0 4 12 16 20 24 28 32 36 VDS - Drain-to-Source Voltage - V 8 40 Crss Coss Ciss I SD- Source-to-Drain Diode Current - A VGS = 0 f = 1 MHz TJ = 25C Ciss @ 0 V = 160 pF Coss @ 0 V = 216 pF Crss @ 0 V = 78 pF SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE 10 VGS = 0 1 TJ = 75C TJ = 125C TJ = 150C TJ = 25C TJ = - 40C Figure 11 DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE 60 ID = 0.7 A TJ = 25C See Figure 3 VDD = 20 V 40 VDD = 30 V 8 12 280 260 VGS - Gate-to-Source Voltage - V 10 t rr - Reverse-Recovery Time - ns 240 220 200 180 160 140 120 100 80 60 40 20 3 3.5 4 0 0 0 100 VDS - Drain-to-Source Voltage - V 50 30 6 20 VDD = 48 V 10 VDD = 20 V 0 0 0.5 1 1.5 2 2.5 4 2 Qg - Gate Charge - nC Figure 13 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 AA AA AA 0.1 0.1 1 VSD - Source-to-Drain Voltage - V 10 Figure 12 REVERSE-RECOVERY TIME vs REVERSE di/dt VDS = 48 V VGS = 0 IS = 0.7 A TJ = 25C See Figure 1 D1, D2, and D3 Z1, Z2, and Z3 200 300 400 500 600 Reverse di/dt - A/s Figure 14 TPIC5303 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS039A - SEPTEMBER 1994 - REVISED SEPTEMBER 1995 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 10 TC = 25C 1 s I D - Maximum Drain Current - A 10 ms 1 ms 1 500 s I AS - Maximum Peak Avalanche Current - A AA AA RJA DC Conditions 1 10 RJP 0.1 0.1 100 VDS - Drain-to-Source Voltage - V Less than 2% duty cycle Device mounted on FR4 printed-circuit board with no heatsink. Device mounted in intimate contact with infinite heatsink. Figure 15 MAXIMUM PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 10 See Figure 4 TC = 25C TC = 125C 1 0.01 0.1 1 tav - Time Duration of Avalanche - ms 10 Figure 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TPIC5303 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY SLIS039A - SEPTEMBER 1994 - REVISED SEPTEMBER 1995 THERMAL INFORMATION D PACKAGE JUNCTION-TO-BOARD THERMAL RESISTANCE vs PULSE DURATION 100 DC Conditions d = 0.5 RJB - Junction-to-Board Thermal Resistance -C/W d = 0.2 10 d = 0.1 d = 0.05 d = 0.02 d = 0.01 1 Single Pulse tw tc ID 0 0.1 0.0001 0.001 0.01 0.1 tw - Pulse Duration - s 1 10 100 Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink NOTE A: Z JB(t) = r(t) RJB tw = pulse duration tc = cycle time d = duty cycle = tw/tc Figure 17 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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