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THS1408/5691 EVM for the THS14xx and THS56xx DAC Families
User's Guide
July 2000
AAP Data Conversion
SLAU045
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Information About Cautions and Warnings
Preface
Read This First
About This Manual
The purpose of this user's guide is to serve as a reference manual for the THS1408 14-bit ADC, analog-to-digital converter module (EVM). This document provides information to assist hardware and software engineers in application development.
How to Use This Manual
-
Chapter 1 - Overview Chapter 2 - Physical Description Chapter 3 - Circuit Description
Information About Cautions and Warnings
This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you.
The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.
Read This First
iii
iv
Running Title--Attribute Reference
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 THS1408/5691EVM Operational Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-2 1-2 1-3
2
Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.1 Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.2 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.4 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.1.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.1.6 Hardware Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.1.7 ADC Write/Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.1.8 Address Decode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2 Address Decode and Control Logic Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3
Chapter Title--Attribute Reference
v
Running Title--Attribute Reference
Figures
2-1 2-2 2-3 2-4 2-5 2-6 Silk Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silk Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inner Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inner Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-3 2-4 2-5 2-6 2-7
Tables
2-1 3-1 3-2 3-3 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daughtercard Connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daughtercard Connector J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jumper Settings for Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 3-3 3-4 3-5
vi
Chapter 1
Overview
This chapter presents a general overview of the THS1408_5691EVM evaluation module (EVM), and describes some of the factors that must be considered in using the module.
Topic
1.1 1.2 1.3 1.4
Page
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 EVM Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 THS1408/5691 EVM Operational Procedure . . . . . . . . . . . . . . . . . . . . . . 1-3
Overview
1-1
Purpose
1.1 Purpose
The THS1408_5691EVM evaluation module (EVM) provides a platform for evaluating the THS14XX analog-to-digital converter (ADC) and the THS56XX digital-to-analog converter (DAC) under various signal, reference, and supply conditions. Note: The EVM in its current implementation supports only the THS14XX device family and associated circuitry. Support for the THS56XX family will become available at a later date. As a result of this, only the operation of the THS14XX and its associated circuitry will be described in this user's guide.
1.2 EVM Basic Functions
Analog input to the ADC is provided via two external SMB connectors. This input can be configured onboard to be true differential or single-ended transformer-coupled to the input of the device. The EVM provides an external SMB connection for ADC clock input. This can be configured to be either ac- or dc-coupled. A site provided on the board for a crystal oscillator to perform this function can be populated if required. Further provision is made to run the ADC from a DSP timer if desired. Output from the EVM takes place via two 80-pin daughtercard connectors. The digital lines from the ADC are buffered before going to the daughtercard connectors. More information on these connectors can be found in the TMS320C6000 daughtercard specification. The EVM is powered via 4-mm banana sockets. Separate input connectors are provided for the analog and digital supplies. Provision is made to supply the EVM from the motherboard via the daughtercard connectors. The EVM has onboard logic that controls the memory mapping of the ADC within the motherboard's peripheral memory space.
1.3 Power Requirements
The EVM can be powered directly through the daughtercard connector's +3.3-V supply. Provision has also been made to allow the EVM to be powered with independent +3.3-V analog and digital supplies where ultimate performance demands. Voltage Limits Exceeding the +3.3-V maximum can damage EVM components. Undervoltage may cause improper operation of some or all of the EVM components
1-2
THS1408/5691EVM Operational Procedure
1.4 THS1408/5691EVM Operational Procedure
The THS1408_5691EVM provides a flexible means of evaluating the THS14XX in a number of modes of operation. A basic setup procedure that can be used as a board confidence check follows:
-
Verify all jumper settings against the schematic jumper table:
Jumper Table (connection) H3 pins 2-3, H5 pins 2-3, H6 pins 2-3, H7 pins 2-3, H8 pins 1-2, H9 pins 2-3, H12 pins 1-2, H13 pins 1-2
Device THS1408
-
Check that T2 is populated. Connect supplies to the EVM: +3.3 V on J7 and J8, and GND on J12 and J13. Switch power supplies on. Use a function generator with a 50- output to apply a 5-MHz, 1.5-V offset, 3-Vp-p amplitude square-wave signal to J3. Use a function generator with a 50- output to apply a 100-kHz, 0-V offset, 4-Vp-p amplitude sine-wave signal to J10. The digital pattern on the output daughtercard connector J1 should now represent a sine wave and can be monitored using a logic analyzer, or the EVM can be plugged into a motherboard and the data can be monitored using suitable software.
Overview
1-3
1-4
Chapter 2
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM and lists the components used on the module.
Topic
2.1 2.2
Page
PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Physical Description
2-1
PCB Layout
2.1 PCB Layout
The EVM is constructed on a four-layer, 100-mm (3.94 inch) x 86-mm (3.39 inch), 1.57-mm (0.062 inch) thick PCB using FR-4 material. Figures 2-1 through 2-6 show the individual layers.
Figure 2-1. Silk Top
2-2
PCB Layout
Figure 2-2. Silk Bottom
Physical Description
2-3
PCB Layout
Figure 2-3. Top Layer
2-4
PCB Layout
Figure 2-4. Inner Layer 1
Physical Description
2-5
PCB Layout
Figure 2-5. Inner Layer 2
2-6
PCB Layout
Figure 2-6. Bottom Layer
Physical Description
2-7
Parts List
2.2 Parts List
Table 2-1 lists the parts used in constructing the EVM.
Table 2-1. Parts List
Qty Reference Description 2 1 6 1 40 U3, U1 U2 C13, C15, C26, C28, C50, C30 C17 C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C14, C16, C18, C19, C21, C22, C23, C24, C25, C27, C29, C32, C34, C35, C36, C37, C38, C39, C40, C43, C45, C47, C51, C55, C56, C57, C58, C59 C20, C31, C33, C42, C44, C46 C48, C49 C52, C53, C54 C60, C61, C62 J3, J4, J6, J9, J10, J11 J5 U7 H1, H2, H12, H13, H14 H3, H4, H5, H6, H7, H8, H9, H10, H11, H15 L1, L2, L3 U8 U6 U10 J12, J13 J7, J8 P1 Description SN74ALB16244DL bus driver SN74ALB16245DL bus transceiver 10-F 10-V case A SMD tantalum capacitor 1-F 1206 SMD ceramic capacitor 16-V X7R 0.1-F 0805 SMD ceramic capacitor X7R Manufacturer Part Number TI TI AVX AVX TDK SN74ALB16244DL SN74ALB16245DL TAJA106K010R 1206YC105K2800J CC0805HX7R104KTR
6 2 3 3 6 1 1 5 10 3 1 1 1 2 2 1
470-pF 0805 SMD ceramic capacitor NPO 22-pF 0805 SMD ceramic capacitor NPO UNPOP 0.01-F 0805 SMD ceramic capacitor X7R SMB connector right angle PCB 0.1" spacing 2X5 header straight SN74AHC14D hex inverter 0.1" spacing 1X2 header straight 0.1" spacing 1X3 header straight 0R 1206 thick-film resistor MAX4212EUK 3.3-V operational amplifier 8-MHz 14-pin DIL 3.3V oscillator 100 ppm 8.0-MHz SMD 3.3V oscillator 100 ppm 4-mm PCB socket black 4-mm PCB socket red 2-k 3269P potentiometer
AVX AVX
08051A471JAT00J 08051A220JAT2A
TDK MACOM Elco TI Harwin Harwin Multicomp Maxim Golledge Golledge Deltron Deltron Bourns
CC0805HX7R103KTR B65N10G999X99 008380010000010 SN74AHC14D M20-9990206 M20-9990306 RMC18W(1206)5%0R0 MAX4212EUK GXO-U102F 8 MHz GXO-U108L 8 MHz 571-0100 571-0500 3269P1202
2-8
Parts List
Table 2-1. Parts List (Continued)
Qty Reference Description 8 3 2 2 1 3 1 1 1 2 1 4 10 R1, R2, R4, R7, R9, R10, R14 R5, R6, R8 R15, R16 R22, R23 R24 R13, R29, R30 R3 R17, R20, R21, R27, R28, R31, R32 R12 R18, R19 R26 TP3, TP4, TP13, TP14 TP1, TP2, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12 J1, J2 U4 U5 T2, T1 U9 Description 10-k 0805 thick-film resistor 1% 510R 0805 thick-film resistor 1% 39R 0805 thick-film resistor 1% 150R 0805 thick-film resistor 1% 750R 0805 thick-film resistor 1% 0R 0805 thick-film resistor 1% 1K 0805 thick-film resistor 1% 49R9 0805 SMD chip resistor 1% UNPOP 5K1 0805 thick-film resistor 1% 2-k 0805 thick-film resistor 1% 1.32-mm test pin black 1.32-mm test pin red Multicomp Rohm W Hughes W Hughes RMC110W(O8O5)5%5 K1 MCR10EZHF2001 100-103 100-107 Manufacturer Multicomp Multicomp Multicomp Multicomp Rohm Multicomp Multicomp Rohm Part Number RMC110W(O8O5)1%1 0K RMC110W(O8O5)5%5 10R RMC110W(O8O5)1%3 9R RMC110W(O8O5)1%1 50R MCR10EZHF7500 RMC110W(O8O5)5%0 R0 RMC110W(O8O5)1%1 K MCR10EZHF49R9
2 1 1 2 1
0.05" TFM-series 80-pin TH connector THS14XX ADC THS56XX DAC
Samtec TI TI
TFM-140-31-S-D-LC THS14XXPFB THS56XXVF TT1-6-KK81 XC9536XL-5VQ64C
TT1-6-KK81 RF transformer Mini Circuits XC9536XL-5VQ64C CPLD Xilinx
The following components have been left unpopulated in this implementation: C1, C2, C3, C4, C17, C18, C19, C20, C31, C32, C33, C34, C35, C48, C49, C52, C53, C54, C56, H1, H2, H4, H10, H11, J4, J6, J9, R12, R14, R16, R20, R21, R22, R23, R24, R26, R32, T1, TP6, TP9, TP10, TP12, U1, U5, U8, U10.
Physical Description
2-9
2-10
Chapter 3
Circuit Description
This chapter contains the EVM schematic diagram and discusses the various functions on the EVM.
Topic
3.1 3.2 3.3
Page
Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Address Decode and Control Logic Listing . . . . . . . . . . . . . . . . . . . . . 3-7 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Circuit Description
3-1
Circuit Function
3.1 Circuit Function
The following paragraphs describe the function of the individual circuits. Refer to the relevant data sheet for device operating characteristics.
3.1.1
Inputs and Outputs
The ADC has differential analog inputs. These are provided via SMB connectors J10 and J11 on the EVM, and can be configured in two ways:
-
For true differential input, the positive differential signal is connected to J10 and the negative differential signal is connected to J11. The jumpers on the board are then configured as: H7 (1-2), H8 (2-3), and H9 (1-2). The inputs have 50- terminators. For single-ended input, a positive signal is applied to connector J10. The jumpers on the board are then configured as: H7 (2-3), H8 (1-2), and H9 (2-3). Transformer T2 performs the single-ended to differential signal conversion. In this mode, the 50- terminators R27 and R28 perform impedance matching to attain the best distortion performance, but the signal source must be able to drive the 25- load. A 50- source can be used if R27 is removed from the board, with a resulting marginal increase in distortion.
SMB connector J3 can be used to input a clock signal to the board from an external source. If the source is not at the correct dc level required to input to the 74AHC14 hex inverter IC (U7), then it can be ac-coupled through C21, with the dc level trimmed using potentiometer P1 if necessary. The EVM is designed to comply with the TI TMS320C6000 daughtercard specification. The pinout used is listed in Tables 3-1 and 3-2. In order to make the EVM compatible with both the TMS320C6XXX and TMS320C5XXX motherboard design environments, the EVM chip enable is derived from the following sources:
-
OUT_CE (J1 P78) for the TMS320C6XXX, by inserting a jumper link in position 2-3 of H15. OUT_IS (J2 P70) for the TMS320C5XXX, by inserting a jumper link in position 1-2 of H15.
For further explanation of the daughtercard connector interface, refer to the relevant motherboard user's guide or daughtercard specification. Buffers U1, U2, and U3 are used to avoid bus contention and provide a degree of noise isolation from the DSP motherboard.
3-2
Circuit Function
Table 3-1. Daughtercard Connector J1
J1 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND GND OUT_EA5 OUT_EA4 OUT_EA3 OUT_EA2 OUT_EA6 GND GND Name Function NC NC NC NC NC NC NC NC NC NC GND GND NC NC NC NC NC NC NC Address NC NC Address Address Address Address NC NC NC NC GND GND NC NC NC NC NC NC NC NC J1 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 OUT_CE_6 GND GND GND GND BIDIR_ED15 BIDIR_ED14 BIDIR_ED13 BIDIR_ED12 BIDIR_ED11 BIDIR_ED10 BIDIR_ED9 BIDIR_ED8 GND GND BIDIR_ED7 BIDIR_ED6 BIDIR_ED5 BIDIR_ED4 BIDIR_ED3 BIDIR_ED2 BIDIR_ED1 BIDIR_ED0 GND GND OUT_ARE OUT_AWE Name +3.3V +3.3V Function POWER POWER NC NC NC NC NC NC NC NC GND GND DATA DATA DATA DATA DATA DATA DATA DATA GND GND DATA DATA DATA DATA DATA DATA DATA DATA GND GND READ STROBE WRITE STROBE NC NC NC CHIP ENABLE GND GND
Circuit Description
3-3
Circuit Function
Table 3-2. Daughtercard Connector J2
J2 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND GND GND GND GND GND GND GND GND GND Name Function NC NC GND GND NC NC GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND GND NC NC NC NC GND GND NC NC NC NC GND GND NC NC J2 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND GND GND GND OUT_IS GND GND GND GND IN_EXT_INT GND GND OUT_TOUT IN_TINP Name Function NC NC GND GND TIMER INPUT TIMER OUTPUT NC NC NC NC GND GND INTERRUPT NC NC NC NC NC NC NC GND GND NC NC NC NC NC NC NC CHIP ENABLE NC NC NC NC GND GND GND NC GND GND
3-4
Circuit Function
3.1.2
Clock Options
The EVM provides flexibility for the source of the ADC's conversion clock. This clock can come from an external source as previously described, from a standard DIL14 HCMOS crystal oscillator module populating U6, or from a U108-style surface-mount oscillator populating U10. Note: Ensure that the crystal oscillator module selected can operate at the +3.3-V supply voltage. Supplying the ADC clock using a timer output (OUT_TOUT J2 P45) is an option provided for applications that require synchronization of the ADC conversion to the DSP on the motherboard. This is selected using a jumper link on H6 (1-2). A summary of the jumper link settings required for the various clock options is shown in Table 3-3.
Table 3-3. Jumper Settings for Clock Options
Clock Options H3 H5 H6 Onboard Oscillator 1-2 2-3 2-3 External AC Coupled Via J3 - 1-2 2-3 External DC Coupled Via J3 2-3 2-3 2-3 DSP Timer Via OUT_TOUT - - 1-2
3.1.3
References
The EVM relies on the THS1408 ADC using its on-chip reference.
3.1.4
Power
Power is supplied to the EVM via 4-mm banana sockets and the daughtercard connectors. This provides flexibility and a trade-off between convenience and performance as follows:
-
For best performance: Use a separate low-noise analog power supply connected to J7 (+3.3 V) and J12 (GND). Use the digital supply from the daughtercard connectors. For good performance: Use the daughtercard connectors for both analog and digital supplies. This is achieved by inserting a jumper link in H14 on the EVM. For stand-alone operation: Use a separate low-noise analog power supply connected to J7 (+3.3 V) and J12 (GND) and a separate low-noise digital power supply connected to J8 (+3.3 V) and J13 (GND).
Circuit Description
3-5
Circuit Function
3.1.5
Interrupts
The ADC produces two signals that can be used to interrupt a DSP:
-
INT: This is routed via buffer U3 to the IN_EXT_INT pin on the daughtercard connector.
Note: This function is only supported on certain members of the THS14XX family. Refer to the device datasheet.
3.1.6
FOVL: This is routed via buffer U3 to both BIDIR_ED14 and IN_TINP. This gives the DSP code developer flexibility on using the signal in their system.
Hardware Loopback
The EVM can be configured via insertion of jumper links H12 and H13 to go into a hardware loopback mode. This is primarily intended so that the board can be put into an operational state when it is powered up stand-alone. The control logic for this is explained in section 3.2.8.
3.1.7
ADC Write/Read Cycle
The following daughtercard address and control lines are mapped directly to the ADC when performing a write to or a read from the device:
-
OUT_EA2 is mapped to A0 OUT_EA3 is mapped to A1 OUT_AWE is mapped to WRB OUT_ARE is mapped to OEB
These, combined with the address decode logic described in section 3.2.8, allow direct control of the ADC operation via the normal write/read cycles of a DSP.
3.1.8
Address Decode Logic
The EVM uses a Xilinx XC9536 (U9) CPLD to perform address decode and control. The CPLD decodes the daughtercard address and strobe lines to control the ADC chip select and the buffer direction and output-enable states. The Abel code used to generate the logic is given in Listing 3-1.
3-6
Address Decode and Control Logic Listing
3.2 Address Decode and Control Logic Listing
Module Address Address Decode for THS1408/5691
This file performs the address decode and logic control for the THS1408_5691_EV1_Rev2 PCB. The equivalent truth tables are:
Chip Select Decode
OUT_EA6 1 1 1 1 1 1 1 OUT_EA5 0 0 0 0 0 0 1 OUT_EA4 0 0 0 0 1 1 0 OUT_EA3 0 0 1 1 0 0 0 OUT_EA2 0 1 0 1 0 1 0 OUT_CE 0 0 0 0 0 0 0 ADCCSB 0 0 0 0 1 1 0 1 DACCSB 1 1 1 1 0 0 0 1
All other combinations
Buffer Control Decode
Oper ation Write to DAC Write to ADC Read from ADC Loop back ADCCSB DACCSB OUT_ARE OUT_AWE DBUFOEB ABUFDIR ABUFDIRB ABUFOEB DACMODE
1
0
1
0
0
1
1
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
1
0
0
0
1
0 1
1 1
0 1
0 1
0 1
All other combinations
Note: Bit 13 of the data bus to the DAC is inverted when in loopback mode to account for the DAC powering up in 2s-complement input mode while the ADC powers up in binary mode. Inputs OUT_EA2 OUT_EA3 OUT_EA4 OUT_EA5 pin; Address bit from DSP board pin; Address bit from DSP board pin; Address bit from DSP board pin; Address bit from DSP board
Circuit Description
3-7
Address Decode and Control Logic Listing
OUT_EA6
pin; Address bit from DSP board
BIDIR_ED13 pin; Data bit 13 OUT_AWE OUT_ARE OUT_CE Outputs DBUFOEB ABUFDIR pin istype 'com'; DAC buffers 3-state control pin istype 'com'; ADC buffer direction control pin; DSP write enable pin; DSP read enable pin; DSP chip enable
ABUFDIRB pin istype 'com'; ADC FOVL flag buffer 3-state control ABUFOEB pin istype 'com'; ADC data bus buffer 3-state control
DACMODE pin istype 'com'; DAC mode Mod_ED13 pin istype 'com'; Selectively invert BIDIR_ED13 for loopback ADCCSB Equations
!ADCCSB = (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE); !DACCSB = (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE); !DBUFOEB = (ADCCSB and !DACCSB and OUT_ARE and !OUT_AWE) # (!ADCCSB and !DACCSB and !OUT_ARE and OUT_AWE); Done in longhand so signal path is only once through device !DBUFOEB = (!((OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and ((OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and OUT_ARE and !OUT_AWE) # (((OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and ((OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)
pin istype 'com'; Chip select for ADC
3-8
Address Decode and Control Logic Listing
# (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !OUT_ARE and OUT_AWE); !ABUFDIR = (!ADCCSB and DACCSB and OUT_ARE and !OUT_AWE); Done in longhand so signal path is only once through device !ABUFDIR = (((OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !((OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 & !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and OUT_ARE and !OUT_AWE); !ABUFDIRB = (!ADCCSB and DACCSB and !OUT_ARE and OUT_AWE) # (!ADCCSB and !DACCSB and !OUT_ARE and OUT_AWE); Done in longhand so signal path is only once through device !ABUFDIRB = (((OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !((OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 & !OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !OUT_ARE and OUT_AWE); !ABUFOEB = (!ADCCSB and DACCSB and OUT_ARE and !OUT_AWE) # (!ADCCSB and DACCSB and !OUT_ARE and OUT_AWE) # (!ADCCSB and !DACCSB and !OUT_ARE and OUT_AWE); Done in longhand so signal path is only once through device !ABUFOEB = (((OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !((OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 & !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and OUT_ARE and !OUT_AWE) # (((OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !((OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 & !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !OUT_ARE and OUT_AWE) # (((OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and ((OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 & !OUT_EA2 and !OUT_CE)
Circuit Description
3-9
Address Decode and Control Logic Listing
# (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !OUT_ARE and OUT_AWE); !DACMODE = (!ADCCSB and !DACCSB and !OUT_ARE and OUT_AWE); Done in longhand so signal path is only once through device !DACMODE = (((OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE)# (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and ((OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 & !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !OUT_ARE and OUT_AWE);Mod_ED13 = (!BIDIR_ED13 and ((OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and ((OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 & !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !OUT_ARE and OUT_AWE) # (BIDIR_ED13 and !(((OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and !OUT_EA4 and OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and ((OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 & !OUT_EA2 and !OUT_CE) # (OUT_EA6 and !OUT_EA5 and OUT_EA4 and !OUT_EA3 and OUT_EA2 and !OUT_CE) # (OUT_EA6 and OUT_EA5 and !OUT_EA4 and !OUT_EA3 and !OUT_EA2 and !OUT_CE)) and !OUT_ARE and OUT_AWE)); END
3-10
Schematic Diagrams
3.3 Schematic Diagrams
This section contains the schematic diagrams for the EVM.
Circuit Description
3-11

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