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THS0842 EVM
User's Guide
May 2000
AAP Data Conversion
SLAU043B
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
How to Use This Manual
Preface
Read This First
About This Manual
This document presents a description of the THS0842 evaluation module.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 -Overview - Chapter 2 - Circuit Functionality - Chapter 3 - Layout, Decoupling, and Grounding Considerations - Chapter 4 - PC Board and Bill of Materials - Appendix A - Schematics
Read This First
iii
iv
Running Title--Attribute Reference
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 EVM Basic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Voltage Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 THS0842 EVM Operational Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Circuit Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Single-Ended Transformer Coupled Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Differential Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Onboard Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Digital Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-3 1-3 1-3 1-4 2-1 2-2 2-2 2-2 2-2 2-2 2-2 2-2 2-3 2-3 2-3 2-4 2-5
2
3 4
Layout, Decoupling, and Grounding Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 PC Board and Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 Printed-Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A
Chapter Title--Attribute Reference
v
Running Title--Attribute Reference
Figures
1-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board Layer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board Layer 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board Layer 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board Layer 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printed-Circuit Board (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9
Tables
1-1 1-2 2-1 2-2 2-3 Jumper List Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Jumper Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daughtercard Connector J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daughtercard Connector J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum/Maximum Reference Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1-4 2-3 2-4 2-5
vi
Chapter 1
Overview
This chapter gives a general overview of the THS0842 evaluation module (EVM), and describes some of the factors that must be considered in using the module.
Topic
1.1 1.2 1.3 1.4
Page
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 EVM Basic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 THS0842 EVM Operational Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Overview
1-1
Purpose
1.1 Purpose
The THS0842 evaluation module (EVM) provides a platform for evaluating the THS0842 analog-to-digital converter (ADC) under various signal, reference, and supply conditions. The system block diagram is shown below. This illustration provides a general indication of the features and functions available. It should be read in combination with the circuit schematic supplied.
Figure 1-1. Block Diagram
AIN+ THS5651A 1:1 Xfmr AIN IIN- 1:1 Xfmr AIN CML QIN+ COUT QIN- COUT J5 - Q OUT AIN- DB7 AIN+ Clock CLK REFT 80 MHz Osc Optional External Reference REFB THS5651A IOUT DB0 8 Buffer THS0842 DA7 DA0 Buffer 8 J2 - I OUT IIN+ IOUT
AIN-
1-2
EVM Basic Function
1.2 EVM Basic Function
Analog inputs to the ADC are provided via six external SMB connectors. Two pairs of SMB connectors provide true differential inputs, or two individual SMB connectors provide single-ended transformer-coupled signals to the inputs of the device. The EVM provides an external SMB connection for input of the ADC clock. A crystal oscillator is provided on the board to perform this function and can be used when required. Refer to the section on clocking for correct provisioning. Digital output from the EVM is via two 25-pin connectors. The digital lines from the ADC are buffered before going to the connectors. More information on these connectors can be found in the ADC output section. Analog output from the EVM is via two SMB connectors (J1 and J3). A pair of THS5651 10-bit DACS are used to recreate the analog signal from the ADC's digital data. More information on this can be found in the ADC analog output section. Power connections to the EVM are via a pair of screw-down connectors. Separate input connectors are provided for the analog and digital supplies.
1.3 Power Requirements
The EVM is powered directly through independent 3.3-V analog and digital supplies.
1.3.1
Voltage Limits
Exceeding the 3.3-V maximum can damage EVM components. Under voltage may cause improper operation of some or all of the EVM components.
Overview
1-3
THS0842 EVM Operational Procedure
1.4 THS0842 EVM Operational Procedure
The THS0842 EVM provides a flexible means of evaluating the THS0842 in a number of modes of operation. A basic setup procedure that can be used as a board confidence check follows: 1) Verify all jumper settings against the schematic jumper list in Table 1-1:
Table 1-1. Jumper List Table
Jumper W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 Function Reserved for future use Reserved for future use Oscillator power down Reference select THS0842 standby Select clock source Digital bus output enable Single/dual bus mode External REFB source External REFB feed External REFT feed Q+ Input select Q- Input select I+ Input select I- Input select External REFT source Installed Required Required Power down Internal Active Onboard 3-state bus Dual mode 1-2 onboard External External 1-2 differential 1-2 differential 1-2 differential 1-2 differential 1-2 onboard Removed Do not use Do not use Active External Power down Offboard Active Single mode 2-3 offboard Internal Internal 2-3 single-ended 2-3 single-ended 2-3 single-ended 2-3 single-ended 2-3 offboard Default Installed Installed Installed Installed Installed Removed Removed Installed 1-2 Removed Removed 2-3 2-3 2-3 2-3 1-2
Table 1-2. Default Jumper Positions
EVM THS0842 Jumper Table (connection) W1, W2, W4, W5, W6, W7, W9 (1-2), W12 (2-3), W13 (2-3), W14(2-3), W15 (2-3), W16(1-2)
1) Set both dc power supplies to read 3 V at the output terminals. Connect GND of the first power supply to the AGND(J6-2) terminal on the EVM, and GND of the other power supply to the DGND(J7-2) terminal on the EVM. Then connect the first power supply's 3-V output to the AVDD power (J6-1) terminal of the EVM, and the other power supply's 3-V output to the DVDD(J7-1) terminal of the EVM. 2) Switch power supplies on. 3) Set function generator number one to output a square wave at a frequency of 80 MHz, 0-V offset, and an amplitude of 3 V on the 50- output. 4) Use a 50- coaxial cable with BNC/SMB connectors to connect generator number 1 to J4 (clock input).
1-4
THS0842 EVM Operational Procedure
5) Set function generator number 2 to output a sine wave at a frequency of 1 MHz, 0-V offset, and an amplitude of 0.8 Vp-p on the 50- output. 6) Use a 50- coaxial cable with BNC/SMB connectors to connect generator number 2 to J8 (Q input). Use a T-splitter to connect the test signal to channel 1 of the oscilloscope. 7) Use a 50- coaxial cable with BNC/SMB connectors to connect the second channel of the oscilloscope to J3 (Q-output). The two sine waves should have the same period (their amplitudes may differ). 8) Repeat Step 5 with the SMB connected to J11 (I-input). 9) Repeat Step 6, except connect to J1 (I-output).
Overview
1-5
1-6
Chapter 2
Circuit Functionality
This chapter describes the digital interface-master clock, ADC data, and power supply.
Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7
Page
Circuit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Digital Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Circuit Functionality
2-1
Circuit Function
2.1 Circuit Function
The following sections describe the function of individual circuits. Refer to the relevant data sheet for device operating characteristics.
2.2 Analog Inputs
The ADC has either transformer-coupled single-ended or differential-analog inputs. These are provided on the EVM via SMB connectors J8 and J11 for single-ended inputs, or J9/J10 and J12/J13 for differential inputs, and can be configured in two ways, as discussed in Sections 2.2.1 and 2.2.2.
2.2.1
Single-Ended Transformer Coupled Interface
Connectors J8 (Q) and J11 (I) are single-ended inputs that use a 1:1 transformer to provide differential analog inputs to the I+/I- and Q+/Q- inputs of U11 (THS0842). The signal input is nominally 0.89 Vpp. W12, W13, W14, and W15 should be strapped across pins 2 and 3. The inputs have 50- terminators.
2.2.2
Differential Interface
Connectors J9 (Q+), J10 (Q-), J12 (I-), and J13 (I+) are used to connect accoupled differential signals directly to U11 (THS0842). The signal input is nominally a 0.44 Vpp. W12, W13, W14, and W15 should be strapped across pins 1 and 2.
2.3 Digital Inputs
The THS0842 EVM utilizes jumpers for all digital inputs, with the exception of the external clock. There are no connectors for setting the digital inputs. Refer to the jumper table (Table 1-1 ) for a description of the jumpers and their function.
2.3.1
Master Clock
The EVM provides flexibility as to the source of the ADC's conversion clock. This clock can be from an external source as described below, or by enabling an onboard 80-MHz oscillator. Jumper W6 selects the master clock source from either the oscillator or from external connector J4. W5 is used to place the onboard oscillator in standby mode. The internal oscillator is selected if W6 is installed and W5 is not installed. R49 must be removed in order to use the onboard oscillator. The EVM is shipped with external clock selected as a default.
2.3.2
External Clock
SMB Connector J4 can be used to input a clock signal to the board from an external source. The input source should be a 50- LVTTL square wave signal with an amplitude of 3.3 V referenced to digital ground. This is the default setup for the EVM.
2-2
Circuit Function
2.3.3
Onboard Clock
The THS0842 EVM contains an onboard 3.3-V oscillator that generates a clock frequency of 80 MHz. W5 can be used to place the onboard oscillator in standby mode. R49 must be removed in order to use the onboard oscillator.
2.4 Analog Output
The ADC digital data is buffered and sent to a pair of THS5651A DACs. The 5651 DACs latch the THS0842 data on COUT (Q-DAC) or /COUT (I-DAC). An analog signal is generated on J1 for the I-output and J3 for the Q-output. The DAC outputs can only be used when the THS0842 EVM is set up for dual-bus mode (W8 installed, SELB low). For further information on the THS5651A, please refer to the product folder on TI's website: http://www.ti.com/sc/docs/products/analog/ths5651a.html.
2.5 Digital Output
The digital-output codes of the ADC are made available on two 26-pin headers along with COUT and COUT. J2 provides access to the data from the I-input and J5 provides access to the data from the Q-input. The output is 3.3 V TTLcompatible.
Table 2-1. Daughtercard Connector J2
J2 Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 Name DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 RSVD RSVD COUT COUT 80 MHz Function IOUT0 IOUT1 IOUT2 IOUT3 IOUT4 IOUT5 IOUT6 IOUT7 NC NC COUT clock COUT clock 80-MHz clock J2 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 Name DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND Function Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground
Circuit Functionality
2-3
Circuit Function
Table 2-2. Daughtercard Connector J5
J2 Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 Name DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RSVD RSVD COUT COUT 80 MHz Function QOUT0 QOUT1 QOUT2 QOUT3 QOUT4 QOUT5 QOUT6 QOUT7 NC NC COUT clock COUT clock 80-MHz clock J2 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 Name DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND Function Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground
2.6 References
The EVM can use either the THS0842 internal reference, a tunable external reference generated on the EVM board, or a customer-provided external reference. The THS0842's input range is determined by the voltages on its VREFB and VREFT pins. Since the part has an internal-voltage reference generator, it must be powered down (W4 removed) before applying an external voltage to the REFT and REFB pins. It is advantageous to have a wider analog input range, especially at higher sampling rates. This can be achieved by using external voltage references. For example, at AVDD = 3.3 V, the full-scale range can be extended from 1 Vpp (internal reference) to 1.3 Vpp (external reference), as shown in Table 3-3. These voltages should not be derived from a powersupply source via a voltage divider. Use instead a bandgap-derived voltage reference to derive both references via an operational-amplifier circuit. Refer to the schematic of the THS0842 evaluation module for an example circuit. The full-scale ADC input range and its dc position can be adjusted when using external references. The full-scale ADC range is always equal to VREFT - VREFB. The maximum full-scale range is dependent on AVDD, as shown in the THS0842 data sheet specifications section. Aside from the constraint on their difference, there are limitations on the useful range of VREFT and VREFB individually, depending on the value of AVDD. Table 3-3 summarizes these limits for three cases.
2-4
Circuit Function
Table 2-3. Minimum/Maximum Reference Input Levels
AVDD 3.0 V 3.3 V 3.6 V VREFB(min) 0.8 V 0.8 V 0.8 V VREFB(max) 1.2 V 1.2 V 1.2 V VREFT(min) 1.8 V 2.1 V 2.4 V VREFT(max) 2.2 V 2.5 V 2.8 V [VREFT-VREFB]max 1.0 V 1.3 V 1.6 V
2.7 Power
Power is supplied to the EVM via screw-down connectors. For best performance use a separate low-noise analog power supply connected to J6-1 (+3.3 V) and J6-2 (GND). Use a separate low-noise digital power supply connected to J7-1 (+3.3 V) and J7-2 (GND). The positive side is marked by a + on the EVM's silkscreen placed next to the connectors themselves.
Circuit Functionality
2-5
2-6
Chapter 3
Layout, Decoupling, and Grounding Considerations
Proper grounding and layout of the PCB is essential to achieve the stated performance. It is advised to use separate analog and digital ground planes that are spliced underneath the device. The THS0842 has digital and analog terminals on opposite sides of the package to make this easier. Since there is no internal connection between analog and digital grounds, they have to be joined on the PCB. This should be done at one point in close proximity to the THS0842. Separate analog and digital power-supply terminals are provided on the device (AVDD /DVDD). The supply to the digital-output drivers (DRVDD) is also kept separate. Lowering the voltage on this supply to 3 V instead of the nominal 3.3 V improves performance due to the lower switching noise caused by the output buffers. Because of the high sampling rate and switched-capacitor architecture, the THS0842 generates transients on the supply and reference lines. Proper decoupling of these lines is essential. Decoupling as shown in the schematic of the THS0842 EVM is recommended.
Layout, Decoupling, and Grounding Considerations
3-1
3-2
Chapter 4
PC Board and Bill of Materials
This chapter presents the PC board design and a listing of the parts required to build this evaluation module
Topic
4.1 4.2
Page
Printed-Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
PC Board and Bill of Materials
4-1
Printed-Circuit Board
4.1 Printed-Circuit Board
This section presents the printed-circuit board for the THS0842 EVM.
Figure 4-1. Printed-Circuit Board (Top)
4-2
Printed-Circuit Board
Figure 4-2. Printed-Circuit Board Layer 1
PC Board and Bill of Materials
4-3
Printed-Circuit Board
Figure 4-3. Printed-Circuit Board Layer 2
4-4
Printed-Circuit Board
Figure 4-4. Printed-Circuit Board Layer 3
PC Board and Bill of Materials
4-5
Printed-Circuit Board
Figure 4-5. Printed-Circuit Board Layer 4
4-6
Printed-Circuit Board
Figure 4-6. Printed-Circuit Board Layer 5
PC Board and Bill of Materials
4-7
Printed-Circuit Board
Figure 4-7. Printed-Circuit Board Layer 6
4-8
Printed-Circuit Board
Figure 4-8. Printed-Circuit Board (Bottom)
PC Board and Bill of Materials
4-9
Bill of Materials
4.2 Bill of Materials
Part Type 10 F Designator C4, C8, C12, C14, C16, C18, C21, C23, C29, C44, C48, C49, C52, C54, C59, C60, C61, C62, C86, C88, C90 C2, C3, C5, C10, C11, C17, C65, C71 C6, C13, C15, C19, C24, C34, C37, C38, C40, C42, C45, C46, C47, C50, C53, C63, C67, C68, C69, C72, C73, C75, C76, C77, C78, C80, C82, C84, C85, C87, C89, C91 C43, C51 C7, C12, C20, C22, C26, C33, C35, C36, C39, C41, C64, C66, C70, C74, C79 C25, C28, C31, C32 C1, C9, C27, C30, C55, C56, C57, C58, C81, C83 D1, D2 J3 J6, J7 J1, J4, J8, J9, J10, J11, J12, J13 J2, J5 L1, L3 L2 R4, R5, R6, R8, R9, R11, R12, R13, R14, R15, R17, R18, R19, R20, R21, R24, R25, R26, R27, R28, R48 R39, R40, R41, R42, R49, R57, R58, R61, R62, R63, R64 Footprint 3528 Description Low profile tantalum capacitor Manufacturer Digikey Part Number PCS1156CT-ND
0.1 F
1206
Multilayer ceramic - variable footprint Multilayer ceramic
Mouser
77-VJ12U50V104M
0.1 F
805
Mouser
77-VJ08Y50V104K
4.7 F 470 pF
3216 805
Low profile tantalum capacitor Multilayer ceramic
Digikey Mouser
PCS1475CT-ND 77-VJ08A100V471J
1.0 F 0.01 F
805 805
Multilayer ceramic Multilayer ceramic
Digikey Mouser
PCC1807CT-ND 77-VJ08Y50V103K
GREEN LED SMA JACK KRMZ2 SMA
LED-1206 SMA_JACK 2term_screw_con SMA_JACK
LED with LENS PCB mount SMA jack 2 Terminal screw connector PCB mount SMA jack
Lumex Johnson Components
67-1357-1 142-0701-206 506-5ULV02
Johnson Components
142-0701-206
26PIN_IDC 4.7 H 1.0 H 20
13x2x0.1 DO1608C DO1608C 1206
26 Pin header DO1608C-Series - Coil Craft DO1608C-Series - Coil Craft Mouser
TSW-113-07-L-D
263-20
49.9
1206
1/4W 1210 Chip resistor
Mouser
290-49.9
4-10
Bill of Materials
Part Type 750 0 2.49K 1% 1.0 K 2K POT 33 2K 10K Designator R36 R16, R23, R35, R37, R51, R52 R38 R22, R44, R56, R59 R29, R30 R1, R3, R10 R2, R7 R31, R32, R33, R34, R43, R45, R46, R47, R50, R53, R54, R55, R60, R44 T1, T2, T3, T4 Footprint 1206 1206 1206 1206 BOURNS 2NBS16 1206 1206 Bourns 2NBS Series 1/4W 1206 Chip resistor 1/4W 1206 Chip resistor Mouser Mouser Description 1/4W 1206 Chip resistor 1% 1/4W 1206 Chip resistor 1/4W 1206 Chip resistor 1/4W 1206 Chip resistor Manufacturer Mouser Mouser Mouser Mouser Digikey Part Number 290-750 263-0 263-2.49K 263-1K 3214W-202ECT-ND 4816P-1-330 263-2.00K 263-10K
1.0K T1-1T-KK81
1206 MC_KK81
1/4W 1206 Chip resistor RF transformer MINI-circuits T1-1T-KK81 Turret terminal test point
Mouser
263-1K
TSW-101-07-LS
TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP9, TP10, TP11, TP12, TP14, TP15, TP16, TP17 TP8 TP13 U1, U2, U4, U5, U7, U9, U12 U8 U10 U14
test_point2
Samtec
TSW-101-07-LS
REF- REF+ 74LVC827A SN74HC04D SN74LVC08A TL1431CD
test_point2 24 SOP (DW) 14-SOP(D) 14-SOP(D) 8-SOP(D)
Turret terminal test point 10-Bit bus interface FF 3SO Hex inverter Quad NAND gate Precision programmable reference Dual op amp in 8 pin SOP package THS0842 2.7-5.5V, 10 bit, 125 MHz, communications DAC 2 Position jumper _ 0.1" spacing
Samtec TI TI TI TI
TSW-101-07-LS SN74LVC827ADW SN74HC04D SN74LVC08AD TL1431QD
TLV2772 THS0842 THS56X1
U13 U11 U3, U6
8-SOP(D) 48-TQFP(PFB) 28-SOIC(DW)
TI TI TI
TLV2772ID THS0842IPFB THS5651IDW
TSW-102-07-LS
W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11 W9, W12, W13, W14, W15, W16 X1
2pos_jump
Samtec
TSW-102-07-L-S
3POS_JUMPER
3pos_jump
3 Position jumper _ 0.1" spacing Crystal oscillator 80 MHz Digikey
TSW-103-07-L-S
XTAL
4PIN_XTL_DC
SG-8002DC- SCC-80.00 MHz
PC Board and Bill of Materials
4-11
Appendix A
Schematics
This Appendix contains the THS0842 EVM schematics.
Schematics
A-1
1
2
3
4
TP4
5
TP2 TP16 TP3 TP14 REV
6
REVISION HISTORY ECN Number Date Approved
DRV3
DRV3
DV3
TP15 TP17
AV3
AV3
AV3
C85 0.1uF
C33 470pF
C77 0.1uF
C22 470pF
C40 0.1uF
C41 470pF A
TP1
D
C38 0.1uF
C39 470pF
C37 0.1uF
C36 470pF
C24 0.1uF
C26 470pF
D
D
U11 DV3 27 37 41 34 35 38 39 47 R50 10k R54 10k C W8 R53 10k W7 29 REFT REFB R47 C28 1.0uF C81 .01uF 10k W4 28 36 40 46 AVss AVss AVss Vss THS0842 C83 .01uF C31 1.0uF C25 1.0uF C27 .01uF DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 R58 49.9

AVdd AVdd AVdd Q+ QI+ ICLK STBY SELB OE
DRVdd DRVdd DVdd
1 13 U7 45 DA[0..9] 1 13 R4 R5 R6 R8 R9 R11 R12 R13 R14 R15 R17 R18 R19 R20 R21 R24 R25 R26 R27 R28 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DA0 2 DA1 3 DA2 4 DA3 5 DA4 6 DA5 7 DA6 8 DA7 9 DA8 10 DA9 11 OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 23 22 21 20 19 18 17 16 15 14 QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 QA9 QA[0..9] J2 QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 QA9 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 QA[0..9]
Q+ QI+ I80M W5
42 44 48
D0A D1A D2A D3A D4A D5A D6A D7A NC NC D0B D1B D2B D3B D4B D5B D6B D7B NC NC C_OUT
23 22 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 3 2 25 26 32 43 12 24
74LVC827A
26PIN_IDC U9 1 13 2 3 4 5 6 7 8 9 10 11 OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 23 22 21 20 19 18 17 16 15 14 C COUTB
BG REFT REFB PWDN_REF
31 30 33
COUT
C_OUT CML DVss DRVss DRVss
74LVC827A U12 1 13 2 3 4 5 6 7 8 9 10 11 OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 23 22 21 20 19 18 17 16 15 14 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 QB9 QB[0..9] J5 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 QB9 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26
C84 0.1uF
QB[0..9]
B J11 Iin
B
T4
DB[0..9] W14 I+ J8 Qin
74LVC827A
26PIN_IDC
T3
R57 49.9
T1-1T-KK81

W15 I-
J13 I+in R64 49.9
C58 .01uF
T1-1T-KK81
J9 C55 .01uF

W12 Q+
+
R34 10k
Q+in R61 49.9 + R31 10k C59 10uF
C62 10uF R33 10k J10 R63 49.9 Q-in C32 1.0uF C30 .01uF +
A
J12 I-in
C57 .01uF
C56 .01uF
R32 10k
W13 Q
Title:

12500 TI Boulevard Dallas, Texas 75243
THS0842 EVM
Date:
A
C61 10uF
R62 49.9
C60 10uF
+
Drawn By: Engineer:
Paul D. Pritchett Paul D. Pritchett 5
Size: File:
1/3/00
Rev.
A
of 3
Sheet: 1
1
2
3
4
6
1
2
3
4
5
REV
6
REVISION HISTORY ECN Number Date Approved
I out
U3 T1
22 IOUT1 IOUT2 NC4 NC3 NC2 NC1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
DACA[0..9] 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DACA9 DACA8 DACA7 DACA6 DACA5 DACA4 DACA3 DACA2 DACA1 DACA0
INTA[0..9]
D
J1 R39
R40 49.9
21
T1-1T-KK81
16 17 EXTLO EXTIO BIASJ
DACA0 DACA1 DACA2 DACA3 DACA4 DACA5 DACA6 DACA7 DACA8 DACA9
R1B R1A R1C R1D R1E R1F R1G R1H R10A R10B
INTA9 INTA8 INTA7 INTA6 INTA5 INTA4 INTA3 INTA2 INTA1 INTA0 U8A
U1 1 13 QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 QA9 2 3 4 5 6 7 8 9 10 11 OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 23 22 21 20 19 18 17 16 15 14 INTA0 INTA1 INTA2 INTA3 INTA4 INTA5 INTA6 INTA7 INTA8 INTA9
D
1 DV3 SN74X04
2
C1 0.01uF
C2 0.1uF R2 2K
AV3
18
74LVC827A
CLK
28
R45 10K
U2 1 13 OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 23 22 21 20 19 18 17 16 15 14 INTA0 INTA1 INTA2 INTA3 INTA4 INTA5 INTA6 INTA7 INTA8 INTA9
24
SLEEP AVDD MODE COMP1 COMP2 AGND DVDD DGND
15 25 Installed for THS0842
W2
C65 0.1uF19
C 23
C3 0.1uF 20
DV3 27 26
QA8 QA9 QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA[0..9] QA[0..9]
2 3 4 5 6 7 8 9 10 11
C
C5 0.1uF
74LVC827A
THS56X1
COUTB
U6
Q out
DACB[0..9] 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DACB9 DACB8 DACB7 DACB6 DACB5 DACB4 DACB3 DACB2 DACB1 DACB0
INTB[0..9]
T2 J3 R41 R42 49.9
22 21
IOUT1 IOUT2 NC4 NC3 NC2 NC1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
T1-1T-KK81
16 B 17 EXTLO EXTIO BIASJ
DACB0 DACB1 DACB2 DACB3 DACB4 DACB5 DACB6 DACB7 DACB8 DACB9
R10D R10C R10E R10F R10G R10H R3A R3B R3C R3D
INTB9 INTB8 INTB7 INTB6 INTB5 INTB4 INTB3 INTB2 INTB1 INTB0 U8B
U4 1 13 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB8 QB9 2 3 4 5 6 7 8 9 10 11 OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 23 22 21 20 19 18 17 16 15 14 INTB0 INTB1 INTB2 INTB3 INTB4 INTB5 INTB6 INTB7 INTB8 INTB9
B
3 DV3 SN74X04
4
C9 0.01uF
C10 0.1uF R7 2K
AV3
18
74LVC827A
CLK
28
R43 10K
U5 1 13 OE1 OE2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 23 22 21 20 19 18 17 16 15 14 INTB0 INTB1 INTB2 INTB3 INTB4 INTB5 INTB6 INTB7 INTB8 INTB9
24
SLEEP AVDD MODE COMP1 COMP2 AGND DVDD DGND
15 25 Installed for THS0842
W1
C71 0.1uF19
23
C11 0.1uF 20
DV3 27 26
QB8 QB9 QB0 QB1 QB2 QB3 QB4 QB5 QB6 QB7 QB[0..9] QB[0..9]
2 3 4 5 6 7 8 9 10 11
C17 0.1uF
74LVC827A
A
THS56X1
12500 TI Boulevard Dallas, Texas 75243
Title:
THS0842 EVM
Date:
A
COUT
Drawn By: Engineer:
Paul D. Pritchett Paul D. Pritchett 5
Size: File:
1/3/00
Rev.
A
of 3
Sheet: 2
1
2
3
4
6
1
2
3
4
5
REV
6
REVISION HISTORY ECN Number Date Approved
AV3
TP5
AV3
9 $QDORJ
1
J6
L1 4.7uH C89 0.1uF
+ C21 10uF
C46 0.1uF
+ C44 10uF
C76 0.1uF
+ C54 10uF
C45 0.1uF
+ C4 10uF
+ C14 10uF
+
C43 4.7uF
D2
C42 0.1uF
2 D
R22 1.0K
DV3
DV3
DV3
D
C6 0.1uF
C7 470pF
C19 0.1uF
C20 470pF
C34 0.1uF
C35 470pF
DV3
TP10
DRV3
TP6
DV3
9 'LJLWDO L3
1
J7 4.7uH C53 C72 0.1uF C68 0.1uF C82 0.1uF 0.1uF
L2
+ C29 10uF
+ C8 10uF
+ C16 10uF
+ C52 10uF
+ C18 10uF
C15 0.1uF
+ C51
4.7uF
1.0uH C87 0.1uF C78 0.1uF
+ C48 10uF
+ C23 10uF
D1 R44 1.0K
DV3
DV3
DV3
2
C63 0.1uF
C66 470pF
C67 0.1uF
C64 470pF
C69 0.1uF
C70 470pF
DV3 C R46 10k X1 OE VCC C80 .1uF W3 W6 TP11 OUT GND DV3
C13 0.1uF C12 470pF C73 0.1uF C74 470pF C75 0.1uF C79 470pF
DV3
DV3
DV3
C
R30 2K POT
TP13 REF+ AV3
TP12 W11 1 REFT
J4 CLOCK IN R49 49.9 1 2
U10A 3 SN74LVC08A R48 20 80M
AV3
R35 0 R36 750
W16

R59 1.0K

R60 10K
+
8 3 2
C50 0.1uF
4
C88 10uF
+
U13A TLV2772
B
+
C49 10uF
R37 0
U14 C90 10uF TL1431CD
C91 0.1uF
B
R56 1K
TP8 REFTP9

U8C 5 SN74X04 U8D 9 SN74X04 U8E 11 SN74X04 A 13 SN74X04 U8F 12 A 10 12 13 14 7 SN74LVC08A U10D 11 8 9 10 SN74LVC08A U10C 8 6 4 5 SN74LVC08A U10B 6
R38 2.49K
W9
R55 10K
+
5 7 6
C47 0.1uF C86 10uF U13B TLV2772
W10 REFB
R29 2K POT
R23 0 ohms R16 0 ohms R52 0 ohms R51 0 ohms
TP7
12500 TI Boulevard Dallas, Texas 75243
Title:
THS0842 EVM
Date:
A
D
Drawn By: Engineer:
Paul D. Pritchett Paul D. Pritchett 5
Size: File:
1/3/00
Rev.
A
of 3
Sheet: 3
1
2
3
4
6

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