View SLAU004_1002425.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TLV2543 Evaluation Module
Technical Reference
1999
Mixed-Signal Products
Printed in U.S.A. 05/99
SLAU004
TLV2543 Evaluation Module Technical Reference
Literature Number: SLAU004 May 1999
Printed on Recycled Paper
TLV2543 Evaluation Module
Technical Reference
1999
Mixed-Signal Products
SLAU004
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated
Notational Conventions
Preface
Read This First
About This Manual
The purpose of this users guide is to serve as a reference manual for the TLV2543 12-bit analog-to-digital converter evaluation module (EVM). This document provides information to assist hardware and software engineers in application development.
How to Use This Manual
This document contains the following chapters and appendixes: Chapter 1 - Overview Chapter 2 - Hardware Description and Operation Chapter 3 - Software Program and Flowcharts Appendix A - TLC2543 Data Sheet
Notational Conventions
-
Program listings, program examples, and interactive displays are shown in a special typeface similar to a typewriter. Examples use a bold version of the special typeface for emphasis; interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays (such as prompts, command output, error messages, etc.). Here is a sample program listing:
0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even 1, 2 3, 4 6, 3
Here is an example of a system prompt and a command that you might enter:
C: csr -a /user/ti/simuboard/utilities
-
In syntax descriptions, the instruction, command, or directive is in a bold typeface font and parameters are in an italic typeface. Portions of a syntax
Read This First
iii
Information About Cautions and Warnings
that are in bold should be entered as shown; portions of a syntax that are in italics describe the type of information that should be entered. Here is an example of a directive syntax: .asect "section name", address .asect is the directive. This directive has two parameters, indicated by section name and address. When you use .asect, the first parameter must be an actual section name, enclosed in double quotes; the second parameter must be an address. Square brackets ( [ and ] ) identify an optional parameter. If you use an optional parameter, you specify the information within the brackets; you don't enter the brackets themselves. Here's an example of an instruction that has an optional parameter: LALK 16-bit constant [, shift] The LALK instruction has two parameters. The first parameter, 16-bit constant, is required. The second parameter, shift, is optional. As this syntax shows, if you use the optional second parameter, you must precede it with a comma. Square brackets are also used as part of the pathname specification for VMS pathnames; in this case, the brackets are actually part of the pathname (they are not optional). Braces ( { and } ) indicate a list. The symbol | (read as or) separates items within the list. Here's an example of a list: { * | *+ | *- } This provides three choices: *, *+, or *-. Unless the list is enclosed in square brackets, you must choose one item from the list. Some directives can have a varying number of parameters. For example, the .byte directive can have up to 100 parameters. The syntax for this directive is: .byte value1 [, ... , valuen ] This syntax shows that .byte must have at least one value parameter, but you have the option of supplying additional value parameters, separated by commas.
-
-
-
Information About Cautions and Warnings
This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
iv
Related Documentation From Texas Instruments
This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you.
The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.
Related Documentation From Texas Instruments
TLV2543 12-Bit Analog-to-digital Converters With Serial Control and 11 Analog Inputs data sheet (literature number SLAS079C) is included in Appendix A of this book. It contains electrical specifications, available temperature options general overview of the device, and application information.
Read This First
v
vi
Running Title--Attribute Reference
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Hardware Description and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Setup and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Input Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4 Power Supply Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.5 Optical Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.6 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.7 Voltage Variable Input (Potentiometer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.8 Buffered User Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.9 Unbuffered Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.10 Reference Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.11 Fast Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.12 Input Voltage Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.13 Interface Connector Provisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.14 Grounding Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.15 Driving the Input of a Switched Capacitor ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.16 Board Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.17 Part Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Software Program and Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Software Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 TLC2543 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 TLV2543 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
2
3
A
Chapter Title--Attribute Reference
vii
Running Title--Attribute Reference
Figures
2-1. 2-2. 2-3. 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. Interface Connector Hole Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Equivalent Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Board Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Main Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Initialization Subroutine Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Read Input Switch Subroutine Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Analog-to-Digital Convert Subroutine Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Delay Subroutine Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Display Subroutine Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Tables
2-1. 2-2. 2-3. 2-4. 2-5. EVM Default Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Input Select Switch Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Buffered User Input Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Interface Connector Hole Pattern Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Part Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
viii
Chapter 1
Overview
The TLV2543 evaluation module (EVM) provides a platform for evaluating the TLV2543 analog-to-digital converter (ADC). For ease of evaluation, the ADC is interfaced with a microcontroller, three sensors, and a display. The onboard sensors provided are:
-
An optical sensor A temperature sensor A variable resistor
Eight additional analog inputs are available for user-provided signals. Provisions are made for attaching these signal lines to a user-supplied connector. Terminals for an external power supply are also provided. This chapter includes the following topic:
Topic
1.1
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Overview
1-1
1.1 Introduction
The TLV2543 evaluation module consists of a TLV2543 12-bit ADC interfaced with a TSL250 optical sensor, a transistor based temperature sensor, a TL1431 voltage reference, a TLV2264 quad op-amp to provide 4 analog signal buffers, a TL7726 hex clamping circuit for signal over-voltage protection, a TMS370C712 microcontroller, three TIL311 hex display characters, and a TPS7233 3.3 volt regulator powering the TLV2543, TLC2264, 74LVC244A and the sensors. The microcontroller reads the user-programmed dip switches and communicates with the TLV2543 to select the desired analog input, initiate the conversion process, and transfer the converted data back to the microcontroller. The microcontroller then transforms the data into hex form and transfers the result to the three TIL311 displays. A 74LVC244A octal buffer is used as a buffer between the microcontroller and the displays. A TL7705 power supply voltage monitor resets the processor at power-on or if the power supply voltage drops below the proper operating level. Jumper provisions are made to connect the TLV2543 reference voltage to 3.3-V power for ratiometric measurements or to an absolute voltage provided by a TL1431 voltage reference device. A connector pattern is provided for the user to install an interface connector. An uncommitted breadboard area is also provided. An external 5-V power supply (4.75 V to 5.25 V at 0.5 A) is required for operation.
1-2
Overview
Chapter 2
Hardware Description and Operation
This chapter contains descriptions of the hardware and operation of the TLCV2543EVM. This chapter includes the following topics:
Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
Page
Setup and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Input Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Power Supply Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Optical Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Voltage Variable Input (Potentiometer) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Buffered User Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Unbuffered Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.10 Reference Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.11 Fast Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.12 Input Voltage Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.13 Interface Connector Provisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.14 Grounding Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.15 Driving the Input of a Switched Capacitor ADC . . . . . . . . . . . . . . . . . 2-11 2.16 Board Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.17 Part Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Hardware Description and Operation
2-1
2.1 Setup and Operation
The power supply terminals (J2) on the TLV2543 EVM module must be connected to a regulated 4.75-V to 5.25-V power supply capable of providing at least 0.5 A.
This evaluation module is designed to have power supplied from an external regulated 5-V power supply. No form of power supply regulation is included on the module. Damage to the components can and will occur if the voltage exceeds the maximum specified level. Under voltage can cause improper operation.
When the power supply is switched on, the microcontroller is initialized and the displays flash to indicate proper operation. The displays then show a two or three digit hex value of the voltage generated by the optical sensor and digitized by the TLV2543. The value on the displays varies with the intensity of the light striking the TSL250 sensor (See the Optical Sensor section). The input select switch (S1) is set to the hex address (LSB on the right) which selects the desired TLV2543 input (See the Input Select Switch section). The desired A/D converter reference voltage for a given sensor is selected by moving the Ref Select jumper (JP9) to the onboard reference (REF V) position or the power supply (VCC) position. The TLV2543 EVM module is shipped with the settings listed in the following table:
Table 2-1. EVM Default Settings
Function Input select switch (S1) Reference select jumper (JP9) Input jumpers (JP1, JP2, JP3, JP11, JP12) Output jumpers (JP4, JP5, JP6, JP7, JP8) Ref- jumper (JP10) Setting 0000 hex (optical sensor selected) REF V Ground Shorted Shorted
NOTE: The input and output jumpers and the REF- jumper on the TLV2543 EVM are formed by a top side copper trace on the PC board between two plated through holes. If desired, the trace can be carefully cut to remove the jumper. The two through holes allow the user to restore the jumper with a wire or connector. A hole pattern is provided for a user-supplied connector to allow easy application of external analog signals for additional evaluation (See the Interface Connector Provisions section). The following sections give more specific information about each selected sensor input and selected reference.
2-2
Hardware Description and Operation
2.2 Input Select Switch
The four position dip switch (S1) labeled input select allows the user to select the desired analog input of the TLV2543. The switch is treated as a hex address command (MSB on left, LSB on right) as listed in the following table:
Table 2-2. Input Select Switch Descriptions
Hex 0h 1h 2h 3h 4h 5h 6h-Ah Bh Ch Dh Eh Fh
Note:
Binary 0000 0001 0010 0011 0100 0101 0110-1010 1011 1100 1101 1110 1111
Function Selected Optical sensor input Temperature sensor input Potentiometer input IN3 buffer input IN4 buffer input IN5 buffer input IN6 through IN10 inputs (Vref input)/2 test -Vref input (ground) test Vref input test Enter power down mode Fast conversion rate on IN4 input
Typical Response User controlled light intensity 588h + temperature change User adjusted 000h or user input 000h or user input 000h or user input 000h or user input 800h 000h FFFh Display blank User input
Inputs IN3 through IN10 are made available to a user supplied connector (see the Interface Connector Provisions section).
Hardware Description and Operation
2-3
2.3 Microcontroller
The TMS370C712 microcontroller (U4) samples the status of the input select switch on ports A4 through A7. This sample data, which is sent to the TLV2543 through the serial peripheral interface ports SPICLK, SPISIM0, and SPISOM1, determines which specific multiplexer input is converted. The microcontroller then reads back the converted 12 bits and changes the data into three hexidecimal digit values. The hexidecimal data is transferred to the three hexidecimal displays U7, U8, and U9. Five sections of the 74LVC244A octal buffer are used to drive the common bused TTL inputs of the displays. For all input select positions except Fh, the microcontroller instructs the TLV2543 to perform the analog-to-digital conversions and display the results at a rate of approximately 2 conversions per second. When the Input Select position is Fh, the microcontroller selects input IN4 and the conversions from the TLV2543 are at a rate of approximately 30k conversions per second (See the Fast Conversion Rate section). NOTE: The following information applies to the TMS370C712 serial peripheral interface (SPI) to the TLV2543. The TLV2543 strobes in the command data bits from the microcontroller on the DIN port at the rising edge of the clock pulse on the I/O CLK terminal. The TMS370C712 generates a clock rising edge on the SPICLK port and also at that time, while conforming to the SPI interface requirements, the data output on the SPISIM0 port changes to reflect the next serial bit to be transferred. If the SPICLK output is connected directly to the TLV2543 I/O CLK input, the required data setup time for the data to be present before a rising clock edge is applied cannot be less than 100 ns (see the TLV2543 data sheet). To solve this race condition, a resistor (R24) and capacitor (C21) provide a delay to the rising clock edge. One buffer section of the 74LVC244A octal buffer (U6) is used to buffer the delayed clock signal. If only one TLV2543 is being used (as with this EVM), the buffer is not normally required. If several TLV2543 devices are being driven in a bus configuration, using this buffer is advised.
2.4 Power Supply Supervisor
Power supply voltage is monitored by the TL7705 (U5). When power is first applied, a microprocessor reset is held until the power supply voltage exceeds 4.55 V (nominal). The reset is then released and the microprocessor begins operation. During normal operation, if the power supply voltage falls below 4.55 V, a reset is activated again.
2-4
Hardware Description and Operation
2.5 Optical Sensor
The TSL250 (U1) optical sensor is connected to the AIN0 multiplexer analog input port of the TLV2543. This sensor converts light intensity to an output voltage ranging from less than 10 mV (dark) to about 2 V (at 2 mW/sq cm illumination intensity). The output of the optical sensor can be varied by placing an object such as a dark colored plastic marker pen cap over the sensor. A practical application such as sorting can be demonstrated by holding similar objects of differing shades within the optical viewing range of the sensor (under a uniform intensity light) and noting the displayed values. A simple optical hood to mask ambient light (e.g. drill a hole in the side of the marker pen cap) provides more uniform results. NOTE: Office light generated by typical artificial lighting contains a high component of ac line frequency intensity variations not normally perceived by the human eye. These variations are detected by the optical sensor. Since the ADC is commanded to make measurements at random times with respect to the ac line frequency, the converted values appear to be unstable in the lower order bits, even though each individual measurement is accurate. This line frequency light intensity variation can be minimized by using dc power to drive the dominate light source (light emitting diodes work well) in addition to shielding the sensor from the ac driven room lighting. An extension of the sorting concept can yield a simple color sorting sensor system. This system requires three optical sensors, each masked by a red, blue, or green optical filter. The individual readings from the three sensors can then be calibrated to the specific color of the object to be identified. For repeatable results, the intensity and color content of the illuminating light source must be uniform.
Hardware Description and Operation
2-5
2.6 Temperature Sensor
When a single transistor and the 12-bit A/D conversion range of the TLV2543 are used, the following characteristics can be seen:
-
A simple temperature sensor The textbook temperature variation of a transistor base-emitter junction The dc temperature instability of a simple one-transistor amplifier
The 2N2222A transistor (Q1) is connected in a classical feedback amplifier configuration that forces the collector voltage to a base-emitter junction voltage of 2 Vbe. The base-emitter junction (essentially a forward biased diode) voltage is about 0.7 V at room temperature (25C) and has a temperature variation of about -2.2 mV/C. Therefore at room temperature, the collector voltage is approximately 1.4 V with a decrease of approximately 4.4 mV for each degree of temperature increase. If the REF select jumper is set to the on-board reference (REF V) position, the conversion reference is set to approximately 2500 mV or 2.5 V. This setting allows the display to decrement approximately 1.6 counts for each mV or about 7 counts per C of temperature increase. If the ambient room temperature is approximately 25C and human body temperature is approximately 38C, the display should reduce about 91 counts when the transistor is held firmly between two fingers. For a more exact analysis, exact transistor characteristics, absolute reference voltage levels, exact room and finger temperatures, etc. would have to be taken into account.
2.7 Voltage Variable Input (Potentiometer)
The IN2 input is controlled by a potentiometer (R13). One section of the TLC2264 (U2) serves as a buffer amplifier for the AIN2 TLV2543 input port. When the potentiometer is adjusted over its range, the input voltage changes from 0 to VCC/2 (approximately 3.3 V/2 = 1.65 V). Since the buffer amplifier has a gain of 2, the input to the TLV2543 port varies from 0 to VCC. For ratiometric measurements, the REF select jumper should be set to the VCC position. Then the TLV2543 reference becomes VCC and all A/D conversions are made relative to the value of VCC. The potentiometer output voltage, by its connection, is also relative to VCC. An A/D conversion of that voltage yields a value proportional to the setting of the potentiometer and independent of the power supply voltage.
2-6
Hardware Description and Operation
2.8 Buffered User Inputs
The IN3 input is connected to the TLV2543 input port through unity gain configured buffer amplifiers (one section of the TLC2264, U2). Although providing unity gain (gain = +1), the input signal can only be within approximately 1.5 V (see the common mode input voltage range specifications of the TLC2264) of the power supply voltage to maintain predictable operation. As long as the power supply voltage to the TLC2264 remains at 3.3 V, this restricts the usable signal input voltage range from 0 V to 1.8 V, however this range can be acceptable for some input level requirements. The input impedance is dictated by the 10 k value of resistor R14 and can be changed to almost any suitable value due to the extremely high input impedance of the TLC2264. Inputs IN4 and IN5 are connected to the TLV2543 input ports, each through a buffer stage of the TLC2264, and each with a gain of 2. The full output voltage swing of 0 V to 3.5 V to the ADC inputs is achieved with signal inputs of 0 V to 1.65 V as listed in Table 2-3.
Table 2-3. Buffered User Input Descriptions
Input IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 Gain
1 2 2
Unbuffered N N N Y Y Y Y Y
Input Range 0 V - 1.8 V (input to ADC is 1.8/3.3 of full scale) 0 V - 1.65 V 0 V - 1.65 V 0 V - 3.3 V 0 V - 3.3 V 0 V - 3.3 V 0 V - 3.3 V 0 V - 3.3 V
2.9 Unbuffered Inputs
The IN6 through IN10 inputs are connected to ground by the top side circuit board etch jumpers JP1, JP2, JP3, JP12, and JP11, respectively. Any etch jumper can be removed by carefully cutting the copper trace between the feed-through holes at the JP marking, allowing that input to be connected to an external signal. When these unbuffered inputs are used, the required TLV2543 specifications such as a low source impedance (see the Driving the Input of a Switched Cpacitor ADC section) and input voltage range (0 V to 3.3 V) must be used. The signal grounds should not be improperly connected to the high current power supply grounds (see the Grounding Considerations section).
Hardware Description and Operation
2-7
2.10 Reference Select
The REF select jumper is provided to allow ratiometric measurements (jumper set to VCC) or allow absolute measurements (jumper set to REF V) relative to a voltage reference established by the TL1431 (D1). This voltage reference is approximately 2.5 V. Ratiometric measurements are made relative to the 3.3-V power supply voltage. If a sensor or input signal voltage is used that varies proportional to the 3.3-V power supply voltage (such as the potentiometer R13), then the signal becomes a ratio of the absolute value of the power supply voltage. Then, if the reference voltage is connected to 3.3 V (REF SELECT jumper position at VCC), the TLV2543 tracks the power supply voltage and provides a converted result independent of the power supply voltage variations. Absolute measurements are required if the sensor or input analog signal does not change with the power supply voltage. The previously described optical and temperature sensors are in this category. For these sensors, the REF select jumper is set to the REF V position.
2.11 Fast Conversion Rate
When the input select switch is set to Fh, the EVM module operates in a fast conversion rate mode. In this mode, the conversion rate is approximately 30k conversions per second from the IN4 input. The displays are updated once every 20 conversions.
2.12 Input Voltage Clamp
The TL7726 (VZ1) is connected to inputs IN3 through IN8. The TL7726 clamps an input signal voltage in excess of the power supply voltage level to prevent damage to the semiconductor inputs. Signal voltages below 0 V (ground) are clamped to ground. Signal inputs between 3.3 V and ground are not affected. The TL7726 provides protection for inputs from incidental transients due to static discharge, excessive signals, etc. Transient current protection is limited to 25 mA.
2-8
Hardware Description and Operation
2.13 Interface Connector Provisions
A hole pattern for a user-supplied interface connector is provided at J1. A standard 8 x 2 set of header posts (such as an AMP 87215-5 or Molex 10-89-1161) can be soldered in place. This arrangement allows several different styles of connector to be installed as necessary to satisfy user requirements.
Figure 2-1. Interface Connector Hole Pattern
2 J1 4 6 8 10 12 14 16
1
3
5
7
9
11
13
15
Table 2-4. Interface Connector Hole Pattern Descriptions
Hole 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Note:
Circuit Function NC NC IN3 input (buffered with +1X gain) IN4 input (buffered with +2X gain) IN5 input (buffered with +2X gain) IN6 input IN7 input IN8 input IN9 input IN10 input 5V Signal ground 5V Power ground 5V Power ground
Hole 12 can be used as a signal ground return to avoid the higher current ground return paths that are associated with a power supply ground.
2.14 Grounding Considerations
When designing analog circuits that share a ground with digital and high current power supplies, the voltage drop along the high current paths must be taken into account. This voltage drop is a result of the current flowing through the greater-than-zero resistance of the current path, and/or high frequency current transients flowing through the greater-than-zero inductance of a current path. If the signal ground is connected to the power supply ground at the improper location, this voltage drop is injected into the signal ground and appears as part of the signal, causing an error.
Hardware Description and Operation
2-9
The solution is to establish a single ground point on the PC board and connect all grounds individually to that point (the EVM single ground point is at the GND terminal of the power supply connector). By using this method, currents flowing along any one path to ground do not inject error voltages in any other ground path. As a practical implementation, however, it may not be reasonable to run a separate ground trace for each component that connects to ground. Therefore, the next best approach is to group the higher current grounds (such as the power supply and digital grounds) together and run them to the central PC board ground point, while still maintaining separate ground paths for the analog grounds. An analysis of current flow paths within the analog section will give an indication of which grounded components could be lumped together into a common ground path and which should be kept separate. For instance, on the EVM, it would be reasonable to use a common path for the TLV2543 REF- terminal and the TL1431 anode. This is because the only significant current flow is through the TL1431 (only about 1 mA) and is not enough to cause a significant error. A 1/2 LSB error at a reference voltage of 2.5 V would be about 0.3 mV, so the ground trace would have to be in excess of 0.3 to cause such an error. If all of the input signals are low current, such as the optical sensor (about 2 mA), the temperature sensor (about 1 mA) and the potentiometer (about 0.25 mA), it may be reasonable to use a common ground trace. As always, wider trace widths are desirable to keep the resistance low. If high currents are associated with any input signal, always use a separate PC board trace directly to the central ground point location. Even though the operating current of the TLV2543 is low (2.5 mA max), some high speed current transients due to the internal digital switching are present and a separate ground trace is reasonable. Note: Always keep the power supply decoupling capacitor as close as possible to the supply pins. This means that the separate ground trace would actually be for the decoupling capacitor and the TLV2543 ground pin. If free area is available, or if the PC board is multilayer, a large ground plane may be acceptable to connect all the analog side ground connections providing that any one signal ground connection is not carrying a large current. That ground plane should be connected directly to the central ground point without touching any of the digital or power supply ground locations along its path. Treating the distribution of the digital and analog 5-V and 3.3 V current paths on the PC board in a similar manner to the grounds is also a good practice. The designated central power point location is the 5-V terminal of the power supply connector (J2) on the EVM board.
2-10
Hardware Description and Operation
2.15 Driving the Input of a Switched Capacitor ADC
When applying an analog signal to the input of a switched capacitor ADC such as the TLV2543, care must be taken to provide a low enough impedance to the input terminal to charge the internal capacitor enough for an accurate conversion during the sampling phase of the converter. The sampling time will depend on the period of the I/O clock rate being used to drive the converter and the number of transfer bits commanded. With the maximum I/O clock frequency of 4.1 MHz and a 12-bit transfer mode, the TLV2543 uses 8 clock cycles (or about 2 s) for the sampling time. The input equivalent circuit of the TLV2543 looks like a series resistance and a capacitor to ground during sampling and an open circuit during conversion. For accurate operation the input capacitor must be charged to the required accuracy of 1/2 LSB (or more, depending on the required system error budget) during the sampling phase of the ADC cycle.
Figure 2-2. Equivalent Input Circuit
Driving Source RS TLV2543 Equivalent Input Circuit R1 Vc 1 k VS C1 60 pF (MAX)
The voltage on capacitor C1 is given by: Vc
+ Vs 1-e*t TC
(1)
Where TC is the time constant C1(Rs+R1) The final voltage value of Vc within 1/2 LSB of Vs is Vc 1 2 LSB
+ Vs * Vs 2n ) 1
(2)
Where n is the resolution of the converter. So equating equation 1 to equation 2 then Vs
* Vs 2n)1 + Vs 1 * e *t TC + TCln 2n)1
therefore the charging time in terms of the circuit time constants is t 1 2 LSB
For a 12-bit converter this would be: ts = TC x ln(8192) = 9 TC
Hardware Description and Operation
2-11
The internal capacitance for the TLV2543 is 60 pF max and the internal series resistance is 1 K. Therefore, with an I/O clock at 4.1 MHz, and a 12-bit transfer mode (sample period = 2 s), the time constant should be no more than: 1/9 x 2 s = 0.22 s Therefore C1(Rs+R1) = 0.22 s So (Rs+R1) = 3.67 K Since Rs = 1K, then the source impedance should be less than 2.67 K to stay within 1/2 LSB error. Good design practice dictates that the source impedance be as low as possible, such as the output of an op-amp. However in an application where fast conversion time is not critical, slow I/O clock rates can allow the driving source impedance to be relatively large.
2-12
Hardware Description and Operation
2.16 Board Schematic
The schematic of the EVM is shown in the following figure.
Figure 2-3. Board Schematic
5V J1 1 IN3 IN5 IN7 IN8 5V 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 1 R10 10 k R8 49.9 k 2 Temperature Sensor IN4 IN6 IN8 IN10 2 U1 TSL250 Optical Sensor 3 TP2
_ +
5V 1 1 R9 4.99 k R7 49.9 k 2 2 TP 7 1 2 C5 0.1 F
1 2 3.3 V U2A TLC2264 1 11 1 2 R11 10 k R12 10 k U2B TLC2264 4 TP5 7 11 2 U2C TLC2264 1 2 TP6
3.3 V
1
Q1 2N2222A 1 C4 0.1 F 2 1 2 3 4 5 6 7 8 9 10 12 2 2 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10
R13 10 k Pot AIN2 Voltage Adjust
3 2
4
+ _
IN6 IN7 IN8 IN9 IN10 VZ1C VZ1A VZ1B 2 2 2
1
1X Input
IN3 5 1 R14 10 k
5 6
+ _
1
1
1
1
1
VZ1D TL7726
1
TL7726
JP1 JP2 JP3 5V JP12 JP11
2X Input
IN4 6 1 R18 10 k 2
10 9 1 2
4
TP4 8 1 5V Power Supply Terminals GND
+ _
11 2 R20 10 k
J2 1 2 1 C1 2 100 F Signal GND U10 TPS7233Q 5 6 4 2 PQ 1 IN SENSE 7 OUT 8 OUT EN IN 3 1
VZ1E TL7726
1
1
R19 10 k
Power GND U2D TLC2264 TP5 14 1
2X Input
IN5 6 1 R17 10 k 2
12 13 1 2
+ _
4
3.3 V 1 + C6 2 10 F R25 1
VZ1F TL7726
11 2 R15 10 k R16 10 k C8 C9 C12 C17 C18 C19 0.1 F 10 F 0.1 F 0.1 F 10 F 0.1 F 5V TP 1 1 GND 1 2 1 2 1 2 1 2 1 2 1 2
1
2
1
Hardware Description and Operation
2-13
Figure 2-3 Board Schematic (continued)
5V 5V U5 TL7705B 7 R6 499 11 C15 0.1 F 3.3 V 20 VCC CS I/O CLK DIN DOUT EOC 15 16 17 18 19 1 1 1 1 1 2 JP8 2 JP5 2 JP6 2 JP7 2 JP4 Y1 12 MHz C20 10 F 1 2 2 5V JP10 1 1 2 3 1 1 C10 2 15 pF 8 1 2 C13 0.1 F 2 3 21 1 2 VCC SENSE 5 RESIN RESET CT 6 RESET REF GND 4 U6 74LVC244 7 13 1 19 U6 5 15 C21 2 47 pF R24 1 k 5V 1 R5 10 k 2 5V 4 18 INT3 17 INT2 16 INT1 22 TXXX/CR 21 TXXX 20 TXXX 24 SPICLK 23 SPISIMO 25 SPISOMI 27 RESET 19 NC VCC U4 TMS370C712 MSB 1 2 3 4 Input Select
8
7
6
5 S1 LSB
REF + REF - GND 18
14 13
3 A7 7 A6 8 A5 9 A4 10 A3 11 A2 13 A1 14 A0 2 D7 1 D6 15 D5 26 D4 28 D3 5 XTAL2/CLKIN 6 XTAL1 VSS 12
1 R1 10 k R2 10 k 2
1 R3 10 k 2
1
1 R4 10 k 2
2
U6 74LVC244 A1 1 A2 4 A3 1 A4 8 11 12 6 16 2
1 18 Y1
Y2 1 14 Y3
C11 2 15 pF
Y4 1 9 BI
U3 TLV2543 1
VOC REF V REF Select
5V
2 R21 1 k 3 1 2 5V 1 VCC
D1 TL1431ACLP
5V 14 VCC
U7 TIL311
5V 1 VCC
5V 14 VCC
U8 TIL311
5V 1 VCC
5V 14 VCC
U9 TIL311
7 4
GND LDP A BCD 3 2 11 12
B1 RDP ST 5
8 10
7 4
GND LDP A BCD 3 2 11 12
B1 RDP ST 5
8 10
7 4
GND LDP A BCD 3 2 11 12
B1 RDP ST 5
8 10
Y1 Y2 Y3 Y4
BI
Y1 Y2 Y3 Y4
BI
Y1 Y2 Y3 Y4
BI
C2 C3 C16 C7 C14 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 V 1 2 1 2 1 2 1 2 1 2
2-14
Hardware Description and Operation
2.17 Part Descriptions
A list of the TLV2543 EVM parts are listed in the following table.
Table 2-5. Part Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Quantity 1 14 2 2 2 1 1 1 1 1 1 16 1 2 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 Reference C1 100 F, 16V Aluminum Description
C2, C3, C4, C5, C7, C8, C12, C13, C14, C15, 0.1 F Ceramic, Z5U, 0.2 Inch C16, C17, C18, C19 C20 C9, C6 C10, C11 C21 D1 JP9 JP9 J2 Q1 R1, R2, R3, R4, R5, R10, R11, R12, R14, R15, R16, R17, R18, R19, R20 R6 R7, R8 R9 R21, R24 R25 R13 S1 U1 U2 U3 U4 U5 U6 U7, U8, U9 U10 VZ1 Y1 10 F, 6.3 V Tantalum, 0.2 Inch 10 F, 10 V Alum 15 pF Ceramic, NPO, 0.2 Inch 47 pF TL1431ACLP 3 Pin Header Shorting jumper, 2 Pin Terminal block, 2 Pos, 5 mm, side entry (OST ED1601) 2N2222A (T0-18 metal can) 10K , 1%, 0.25 W 499 O 49.9K 4.99K 1K 1 10K Pot, single turn, top adj, 3/8 inch sq (Bourns 3386 P) DIP switch, 4 pos, Gold TSL250 TLC2264 TLV2543 (3V) TMS370C712 TL7705B 74LVC244A TIL311 TPS7233Q (SOJC) TL7726 12 MHz crystal, HC-49/s PC board, TLV2543 EVM
R22, R23, C4, C5 designations unused
Hardware Description and Operation
2-15
2-16
Hardware Description and Operation
Chapter 3
Software Program and Flowcharts
The TLV2543 EVM uses a TI TMS370C712 microcontroller to interface with the TLV2543 ADC. The program reads a four position DIP switch to determine which input is selected to be digitized. The program then uses the onboard SPI interface to communicate with the TLV2543. Sixteen bits of data (12 significant bits and 4 fill bits) are read into the processor and output on the three LED displays. This is repeated approximately every 0.5 seconds. A fast mode can also be selected with the DIP switch. In this mode, channel four is selected as input and 20 samples are taken at about a 30 kHz rate, data is converted and displayed, and the process is repeated until another input is selected with the DIP switch. A power-down mode can also be selected which places the TLV2543 in a power-down mode and blanks the display. This chapter includes the following topics.
Topic
3.1 3.2
Page
Software Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Software Program and Flowcharts
3-1
3.1 Software Program
TMS370 Macro Assembler Copyright (c) 1986-1995 adc_evm.asm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Version 5.20 Thu Aug 17 17:20:54 1995 Texas Instruments Incorporated PAGE ;;;;;;;;;;;;;;;;;;;;;;;; ; ; TLV2543 EVALUATION MODULE PROGRAM ; ; VERSION 1.2 8/17/95 ; ; THIS PROGRAM READS A FOUR POSITION DIP ; SWITCH WHICH IS USED TO SELECT THE INPUT ; SIGNAL CHANNEL TO THE ADC. THE PROGRAM ; THEN SELECTS THIS CHANNEL ON THE ADC AND ; CONVERTS THE ANALOG INPUT TO A 12 BIT ; HEX NUMBER AND OUTPUTS THE RESULTS ON ; 3 7-SEGMENT DISPLAYS. POSITIONS ARE ALSO ; PROVIDED TO PUT THE ADC IN A POWER DOWN ; MODE AND A FAST MODE (APPROX 26 KHZ RATE). ; ;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;; ; ; SYSTEM EQUATES ; ;;;;;;;;;;;;;;;;;;;;;;;; ; ; SERIAL PERIPHERAL INTERFACE (SPI) REGISTERS ; SPICCR .EQU P030 ;SPI CONFIG REG SPICTL .EQU P031 ;SPI OPERATION CONTROL REG SPIBUF .EQU P037 ;SPI INPUT BUFFER SPIDAT .EQU P039 ;SPI SERIAL DATA REG SPIPC1 .EQU P03D ;SPI PORT CONTROL REG1 SPIPC2 .EQU P03E ;SPI PORT CONTROL REG2 SPIPRI .EQU P03F ;SPI INTERRUPT CONTROL REG ; ; PORT A AND D REGISTERS ; APORT2 .EQU P021 ;PORT A CONTROL REG ADATA .EQU P022 ;PORT A DATA ADIR .EQU P023 ;PORT A DIRECTION DPORT1 .EQU P02C ;PORT D CONTROL REG1 DPORT2 .EQU P02D ;PORT D CONTROL REG 2 DDATA .EQU P02E ;PORT D DATA DDIR .EQU P02F ;PORT D DIRECTION ; ; TIMER 1 DEFINITIONS ; T1CNTR1 .EQU P040 ;MSB OF COUNTER T1CNTR2 .EQU P041 ;LSB OF COUNTER TC11 .EQU P042 ;MSB OF COMPARE REGISTER TC12 .EQU P043 ;LSB OF COMPARE REGISTER T1CTL1 .EQU P049 ;TIMER 1 CONTROL REG 1 T1CTL2 .EQU P04A ;TIMER 1 CONTROL REG 2 T1CTL3 .EQU P04B ;TIMER 1 CONTROL REG 3 ; ; BIT DEFINITIONS ; 1
0030 0031 0037 0039 003d 003e 003f
0021 0022 0023 002c 002d 002e 002f
0040 0041 0042 0043 0049 004a 004b
3-2
Software Program and Flowcharts
TMS370 Macro Assembler Copyright (c) 1986-1995 adc_evm.asm 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 2e 31 2e 2e 2e 2e 4a 4b
Version 5.20 Thu Aug 17 17:20:54 1995 Texas Instruments Incorporated PAGE 2
6000
6000 6002 6003 6006 6009 600c 600f 6012
5260 fd '8e6014 '8e6056 '8e60ed '8e614d '8e6126 '00f2
6014 6017 601a 601d 6020 6023 6026 6029 602c 602f 6032
f70021 f70f23 f7002c f7002d f7f82f f78030 f70730 f7033d f7223e 720019 72001d
6035 6038
720314 2208
CSBIT .DBIT 3,DDATA ;ADC CHIP SELECT BIT SPIF .DBIT 6,SPICTL ;SPI INTR FLAF DOUT1 .DBIT 5,DDATA ;STROBE FOR DISPLAY 1 DOUT2 .DBIT 6,DDATA ;STROBE FOR DISPLAY 2 DOUT3 .DBIT 7,DDATA ;STROBE FOR DISPLAY 3 DBLANK .DBIT 4,DDATA ;BLANK STROBE RST .DBIT 0,T1CTL2 ;SW TIMER RESET TOUT .DBIT 5,T1CTL3 ;TIMER 1 TIME OUT ; ;;;;;;;;;;;;;;;;;;;;;;;; ; .TEXT 6000H ;START OF PROGRAM ; ;;;;;;;;;;;;;;;;;;;;;;;; ; ; MAIN PROGRAM ; START MOV #60H,B LDSP ;SET STACK POINTER TO 60H CALL INIT ;INITIALIZE SYSTEM ; LOOP CALL READSW ;READ INPUT DIP SWITCH CALL ADC ;DIGITIZE INPUT CALL DISPLAY ;DISPLAY VALUE CALL DELAY ;DELAY .5 SEC JMP LOOP ; ;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;; ; ; INIT ; ; THIS ROUTINE INITIALIZES PORTS A AND ; D, SETS UP THE SPI, AND INITIALIZES ; THE DISPLAYS BY FLASHING 8 AND 0 THREE ; TIMES. ; INIT MOV #0,APORT2 ;SET PORT A TO I/O MOV #0FH,ADIR ;SET A4-A7=INPUT, A0-A3=OUTPUT MOV #0,DPORT1 ;SET PORT D TO I/O MOV #0,DPORT2 MOV #0F8H,DDIR ;SET D3-D7 OUTPUTS ; MOV #80H,SPICCR ;INIT SPI MOV #07H,SPICCR ;SET CLOCK, 8BIT CHAR LEN MOV #03H,SPIPC1 ;SET SPI CLK TO OUTPUT MOV #22H,SPIPC2 ;SET SPISOMI AND SPISIMO TO SPI DATA ; MOV #0,R25 ;CLR CHANNEL REGS MOV #0,R29 ; ; FLASH DISPLAY ; MOV #03,R20 ;SET LOOP CTR TO 3 CYCLES MOV #08H,A ;SET DISPLAY REGS TO 8
Software Program and Flowcharts
3-3
TMS370 Macro Assembler Copyright (c) 1986-1995 adc_evm.asm 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 603a 603c 603e 6040 6043 6046 6049 604c 604f 6052 6055 d01a d01b d01c '8e614d 720218 '8e6126 a4102e '8e6126 a3ef2e 'da14eb f9
Version 5.20 Thu Aug 17 17:20:54 1995 Texas Instruments Incorporated PAGE MOV MOV MOV CALL MOV CALL SBIT1 CALL SBIT0 DJNZ A,R26 A,R27 A,R28 DISPLAY #02H,R24 ;SET DELAY TO .5 SEC DELAY DBLANK ;BLANK DISPLAY DELAY DBLANK ;TURN OFF BLANK R20,LOOP1 ;JMP BACK IF NOT DONE 3
LOOP1
6056 6058 6059 605b 605d 605f
8022 b7 230f 1d1d '0601 f9
6060 6062 6065 6068 606a 606b 606d 606f
d01d 720318 '8e6126 8022 b7 230f 1d1d '06ef
6071 6074 6076 6079 607c 607f 6082 6084 6085
7d0e1d '061b a4102e a3f72e f70631 f7ec39 8022 b7 230f
RTS ; ;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;; ; READSW ; ; THIS ROUTINE READS THE 4 POSITION DIP ; SWITCH FOR THE CHANNEL NUMBER AND SAVES ; IT IN R29. IF 0EH IS SELECTED THE ADC ; IS PLACED IN A POWER DOWN MODE. IF 0FH ; IS SELECTED THE INPUT ON CHANNEL 4 IS ; CONVERTED IN FAST MODE. ADC CHANNEL NUMBER ; IS STORED IN R25. ; ; READSW MOV ADATA,A ;READ SWITCHES SWAP A ;SWAP NIBBLES AND #0FH,A CMP R29,A JNE READ1 ;JMP IF ADC INPUT CHANGED RTS ; ; ADC INPUT CHANGED - WAIT FOR COMPLETE ; READ1 MOV A,R29 ;SAVE IT MOV #03,R24 ;SET DELAY FLAG TO 2 SEC CALL DELAY MOV ADATA,A ;CHECK AGAIN SWAP A AND #0FH,A CMP R29,A JNE READ1 ; ;SEE IF POWER DOWM MODE ; CMP #0EH,R29 JNE READ2 ;JMP IF NOT POWER DOWN SBIT1 DBLANK ;BLANK DISPLAY SBIT0 CSBIT ;ENABLE ADC MOV #06H,SPICTL MOV #0ECH,SPIDAT READ3 MOV ADATA,A ;WAIT FOR CHANGE SWAP A AND #0FH,A
3-4
Software Program and Flowcharts
TMS370 Macro Assembler Copyright (c) 1986-1995 adc_evm.asm 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 6087 * 4d001d 608a '02f6 608c a3ef2e 608f '00cf
Version 5.20 Thu Aug 17 17:20:54 1995 Texas Instruments Incorporated PAGE CMP JEQ SBIT0 JMP A,R29 READ3 DBLANK READ1 4
;CLEAR BLANK
6091 6094 6096 6099 609c 609e 60a1 60a4 60a6 60aa 60ad 60af 60b3 60b6 60b7 60b8 60b9 60bc 60bf 60c1 60c4 60c7 60ca 60cd 60cf 60d2 60d5
7d0f1d '0650 a3f72e 720419 224c 721414 f70631 2139 'a74031fc a21537 2139 'a74031fc a21637 ff ff ff 'da14e8 42151a d71a 730f1a 42151b 730f1b 42161c d71c 730f1c '8e614d a4082e
60d8 8022 60da b7 60db 230f 60dd * 4d001d 60e0 '02b4 60e2 *'89ff7b 60e5 f9
60e6 60e9 60ec
421d19 720218 f9
; ; SEE IF FAST MODE ; READ2 CMP #0FH,R29 ;IS IT FAST MODE JNE READ4 RLOOP1 SBIT0 CSBIT ;ENABLE ADC MOV #04H,R25 ;CHANNEL 4 - FAST MODE MOV #4CH,A ;CHANNEL 4,16BITS,MSB 1ST MOV #20,R20 ;DO 20 FAST THEN UPDATE MOV #06H,SPICTL RLOOP2 MOV A,SPIDAT RFLG1 JBIT0 SPIF,RFLG1 ;WAIT FOR DATA MOV SPIBUF,R21 MOV A,SPIDAT RFLG2 JBIT0 SPIF,RFLG2 ;WAIT FOR DATA MOV SPIBUF,R22 NOP ;GIVE TIME FOR NOP ; CONVERSION TO NOP ; COMPLETE DJNZ R20,RLOOP2 ;DISPLAY VALUE MOV R21,R26 SWAP R26 AND #0FH,R26 ;SAVE MSDIGIT IN R26 MOV R21,R27 AND #0FH,R27 ;SAVE MIDDLE DIGIT IN R27 MOV R22,R28 SWAP R28 AND #0FH,R28 ;SAVE LSDIGIT IN R28 CALL DISPLAY SBIT1 CSBIT ;DISABLE ADC ;SEE IF FAST MODE STILL SELECTED MOV ADATA,A ;WAIT FOR CHANGE SWAP A AND #0FH,A CMP A,R29 JEQ RLOOP1 JMP READ1 RTS ; ; SETUP CHANNEL # IN R25 ; READ4 MOV R29,R25 MOV #02,R24 ;SET DELAY TO .5SEC RTS ; ;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;; ; ; ADC ;
Software Program and Flowcharts
3-5
TMS370 Macro Assembler Copyright (c) 1986-1995 adc_evm.asm 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 ; ; ; ; ADC
Version 5.20 Thu Aug 17 17:20:54 1995 Texas Instruments Incorporated PAGE THIS ROUTINE DIGITIZES THE INPUT ON THE CHANNEL SPECIFIED IN R25. THE RESULTS ARE PLACED IN REGISTERS R26, R27, AND R28. 5
60ed 60ef 60f0 60f2 60f4 60f7 60fa 60fc 6100 6103 6105 6109
1219 b7 23f0 240c a3f72e f70631 2139 'a74031fc a21537 2139 'a74031fc a21637
610c 610f 6111 6114 6117 611a 611d 611f 6122 6125
42151a d71a 730f1a 42151b 730f1b 42161c d71c 730f1c a4082e f9
6126 6129 612b 612c 612f 6131 6134 6137 613a 613d 6140 6144 6145
7d0118 '0601 f9 7d0218 '0614 f71642 f7e343 a40749 a4014a a3df4b 'a7204bfc f9 f75b42
MOV R25,A SWAP A AND #0F0H,A ;CHANNEL # IN MS NIBBLE OR #0CH,A ;16 BITS, MSB 1ST, BINARY SBIT0 CSBIT ;ENABLE ADC MOV #06H,SPICTL MOV A,SPIDAT ADCFLG1 JBIT0 SPIF,ADCFLG1 ;WAIT FOR DATA MOV SPIBUF,R21 ;SAVE MSBYTE MOV A,SPIDAT ADCFLG2 JBIT0 SPIF,ADCFLG2 ;WAIT FOR DATA MOV SPIBUF,R22 ;SAVE LSBYTE ; ; SAVE DATA ; MOV R21,R26 SWAP R26 AND #0FH,R26 ;SAVE MSDIGIT IN R26 MOV R21,R27 AND #0FH,R27 ;SAVE MIDDLE DIGIT IN R27 MOV R22,R28 SWAP R28 AND #0FH,R28 ;SAVE LSDIGIT IN R28 SBIT1 CSBIT ;DISABLE ADC RTS ; ;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;; ; ; DELAY ; THIS ROUTINE USES TIMER 1 AS ; A GENERAL PURPOSE TIMER TO ; DELAY 0, .5, OR 2 SECONDS. ; R24 IS SET AS FOLLOWS: ; 1=0 SEC. ; 2=.5 SEC. ; 3=2 SEC. ; DELAY CMP #1,R24 ;SEE IF NO DELAY JNE DELAY1 RTS DELAY1 CMP #2,R24 ;SEE IF .5 SEC DELAY JNE DELAY2 MOV #16H,TC11 ;.5 SEC COMPARE VALUE MOV #0E3H,TC12 DLOOP OR #07H,T1CTL1 ;SET PRESCALER TO 256 OR #1,T1CTL2 ;START COUNTER AT ZERO SBIT0 TOUT ;CLR CMP FLAG DFLAG1 JBIT0 TOUT,DFLAG1 ;WAIT FOR TIMEOUT RTS DELAY2 MOV #5BH,TC11 ;2 SEC COMPARE VALUE
3-6
Software Program and Flowcharts
TMS370 Macro Assembler Copyright (c) 1986-1995 adc_evm.asm 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 6148 614b f78d43 '00ea
Version 5.20 Thu Aug 17 17:20:54 1995 Texas Instruments Incorporated PAGE MOV JMP #8DH,TC12 DLOOP 6
614d 614f 6152 6154 6157 615a 615c 615f 6161 6164 6167 6169 616c 616e 6171 6174 6175 6176 6177 6178 6179 617a 617b 617c 617d 617e 617f 6180 6181 6182 6183 6184
321a 'aa6175 2122 a3df2e a4202e 321b 'aa6175 2122 a3bf2e a4402e 321c 'aa6175 2122 a37f2e a4802e f9 00 08 04 0c 02 0a 06 0e 01 09 05 0d 03 0b 07 0f
7ffe 7ffe
6000
; ;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;; ; ; DISPLAY ; ; THIS ROUTINE DISPLAYS THE HEX ; DIGITS STORED IN REGS R26, R27, ; AND R28. ; DISPLAY MOV R26,B ;OUTPUT LSD MOV *DTBL[B],A MOV A,ADATA SBIT0 DOUT1 ;STROBE IT SBIT1 DOUT1 MOV R27,B ;OUTPUT MIDDLE DIGIT MOV *DTBL[B],A MOV A,ADATA SBIT0 DOUT2 SBIT1 DOUT2 MOV R28,B ;OUTPUT MSD MOV *DTBL[B],A MOV A,ADATA SBIT0 DOUT3 SBIT1 DOUT3 RTS DTBL .BYTE 00H ;0 .BYTE 08H ;1 .BYTE 04H ;2 .BYTE 0CH ;3 .BYTE 02H ;4 .BYTE 0AH ;5 .BYTE 06H ;6 .BYTE 0EH ;7 .BYTE 01H ;8 .BYTE 09H ;9 .BYTE 05H ;A .BYTE 0DH ;B .BYTE 03H ;C .BYTE 0BH ;D .BYTE 07H ;E .BYTE 0FH ;F ;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;; .SECT "RESET",7FFEH ;RESET VECTOR ADDR .WORD 6000H ;PROGRAM START ; .END
No Errors,
No Warnings
Software Program and Flowcharts
3-7
3.2 Flowcharts
The flowcharts for the TLV2543 EVM are shown in the following figures.
Figure 3-1. Main Program Flowchart
TLV2543 EVM VER 1.1 MAIN PROGRAM START
SETUP STACK POINTER
CALL INIT
INITIALIZATION SUBROUTINE
CALL READSW
READ INPUT SELECTION
CALL ADC
CONVERT ANALOG INPUT TO DIGITAL
CALL DISPLAY
DISPLAY RESULTS
CALL DISPLAY
DELAY
3-8
Software Program and Flowcharts
Figure 3-2. Initialization Subroutine Flowchart
INITIALIZATION SUBROUTINE START
SETUP PORTS, SPI, AND REGISTERS
FLASH DISPLAY 3 TIMES
RETURN
Software Program and Flowcharts
3-9
Figure 3-3. Read Input Switch Subroutine Flowchart
READ INPUT SWITCH SUBROUTINE START
READ DIP SWITCH SETTING
YES SAME AS BEFORE? RETURN
1
NO
DELAY 2 SECOND
YES ANY MORE CHANGES?
NO
YES POWER-DOWN MODE SELECTED?
BLANK DISPLAY AND POWER DOWN ADC
NO 2 YES POWER-DOWN MODE STILL SELECTED?
NO 1
3-10
Software Program and Flowcharts
Figure 3-3 Read Input Switch Subroutine Flowchart (continued)
READ INPUT SWITCH SUBROUTINE (CONTINUED) 2
FAST MODE SELECTED?
NO SAVE CHANNEL NUMBER
YES RETURN SELECT CHANNEL 4 AND DIGITIZE 20 TIMES
DISPLAY DATA
YES FAST MODE STILL SELECTED?
NO 1
Software Program and Flowcharts
3-11
Figure 3-4. Analog-to-Digital Convert Subroutine Flowchart
ANALOG-TO-DIGITAL CONVERT SUBROUTINE START
GET CHANNEL NUMBER, 16 BIT DATA, AND MSB FIRST FOR ADC
ENABLE ADC
START SERIAL OUTPUT (SPI)
NO
DATA BACK FROM ADC?
YES
SAVE DATA
START CLOCK AGAIN FOR LAST 8 BITS
NO
DATA BACK FROM ADC
SAVE DATA IN R26, R27, R28 DISABLE ADC
RETURN
3-12
Software Program and Flowcharts
Figure 3-5. Delay Subroutine Flowchart
DELAY SUBROUTINE START
YES NO DELAY SELECTED? RETURN
NO
0.5 SECOND DELAY SELECTED
YES
SETUP TIMER 1 CONTROL REGISTER FOR 0.5 SECONDS
NO
SETUP TIMER 1 CONTROL REGISTER FOR 2 SECONDS
NO
TIMER TIMED OUT?
YES RETURN
Software Program and Flowcharts
3-13
Figure 3-6. Display Subroutine Flowchart
DISPLAY SUBROUTINE START
GET BIT PATTERN FOR LSD
OUTPUT DATA AND STROBE IT
GET BIT PATTERN FOR MIDDLE DIGIT
OUTPUT DATA AND STROBE IT
GET BIT PATTERN FOR MSD
OUTPUT DATA AND STROBE IT
RETURN
3-14
Software Program and Flowcharts
Appendix A
TLC2543 Data Sheet
This appendix includes the TLV2543 data sheet.
Topic
Page
TVC2543 Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
TLC2543 Data Sheet
A-1
A-2
TLC2543 Data Sheet
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
D D D D D D D D D D D D D D
12-Bit-Resolution A/D Converter 10-s Conversion Time Over Operating Temperature 11 Analog Input Channels 3 Built-In Self-Test Modes Inherent Sample and Hold Linearity Error . . . 1 LSB Max On-Chip System Clock End-of-Conversion (EOC) Output Unipolar or Bipolar Output Operation (Signed Binary With Respect to 1/2 the Applied Voltage Reference) Programmable MSB or LSB First Programmable Power Down Programmable Output Data Length CMOS Technology Application Report Available
AIN3 AIN4 AIN5 AIN6 AIN7
DB, DW, OR N PACKAGE (TOP VIEW)
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC EOC I/O CLOCK DATA INPUT DATA OUT CS REF + REF - AIN10 AIN9
FN PACKAGE (TOP VIEW)
description
The TLC2543C and TLC2543I are 12-bit, switchedcapacitor, successive-approximation, analog-to-digital converters. Each device has three control inputs [chip select (CS), the input-output clock (I/O CLOCK), and the address input (DATA INPUT)] and is designed for communication with the serial port of a host processor or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host.
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
AIN2 AIN1 AIN0 VCC EOC I/O CLOCK DATA INPUT DATA OUT CS REF +
Copyright (c) 1995, Texas Instruments Incorporated
In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating temperature range. The TLC2543 is available in the DB, DW, FN, and N packages. The TLC2543C is characterized for operation from 0C to 70C, and the TLC2543I is characterized for operation from - 40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Microcontroller Based Data Acquisition Using the TLC2543 12-bit Serial-Out ADC (SLAA012)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
AIN8 GND AIN9 AIN10 REF -
A-3
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
AVAILABLE OPTIONS PACKAGE TA 0C to 70C - 40C to 85C SMALL OUTLINE (DB) (DW) TLC2543CDB -- TLC2543CDW TLC2543IDW PLASTIC CHIP CARRIER (FN) TLC2543CFN TLC2543IFN PLASTIC DIP (N) TLC2543CN
TLC2543IN Available in tape and reel and ordered as the TLC2543CDBLE, TLC2543CDWR, TLC2543IDWR, TLC2543CFNR, or TLC2543IFNR.
functional block diagram
REF + 14 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 1 2 3 4 5 6 7 8 9 11 12 Sample and Hold REF - 13
12-Bit Analog-to-Digital Converter (switched capacitors)
14-Channel Analog Multiplexer
12 Output Data Register 12 12-to-1 Data Selector and Driver
16
4
DATA OUT
Input Address Register
4 3 Self-Test Reference DATA INPUT I/O CLOCK CS 17 Control Logic and I/O Counters 19 EOC
18 15
A-4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
Terminal Functions
TERMINAL NAME AIN0 - AIN10 NO. 1 - 9, 11, 12 15 I/O I DESCRIPTION Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than or equal to 50 for 4.1-MHz I/O CLOCK operation and capable of slewing the analog input voltage into a capacitance of 60 pF. Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup time. Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next. The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK. After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order. The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB / LSB, and the remaining bits are shifted out in order. End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and data are ready for transfer. Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. I Input /output clock. I/O CLOCK receives the serial input and performs the following four functions: 1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK with the multiplexer address available after the fourth rising edge. 2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of I/O CLOCK. 3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK. 4. It transfers control of the conversion to the internal state controller on the falling edge of the last I/O CLOCK. Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF - terminal. Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF -. Positive supply voltage
CS
I
DATA INPUT
17
I
DATA OUT
16
O
EOC GND I/O CLOCK
19 10 18
O
REF +
14
I
REF - VCC
13 20
I
detailed description
Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the high-impedance state. CS, going low begins the conversion sequence by enabling I/O CLOCK and DATA INPUT and removes DATA OUT from the high-impedance state. The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7 - D4), a 2-bit data length select (D3 - D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to DATA INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the input data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clocks long depending on the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
A-5
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
converter operation The operation of the converter is organized as a succession of two distinct cycles: 1) the I/O cycle and 2) the actual conversion cycle. The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods, depending on the selected output data length. 1. I/O cycle During the I/O cycle, two operations take place simultaneously. a. An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data is shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after the first eight clocks during 12 or 16 clock I/O transfers. b. The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the first output data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK. 2. Conversion cycle The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to I/O CLOCK. During the conversion period, the device performs a successive-approximation conversion on the analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion. power up and initialization After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data register is set to all zeroes. The contents of the output data register are random, and the first conversion result should be ignored. To initialize during operation, CS is taken high and returned low to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling. operational terminology
Current (N) I/O cycle Current (N) conversion cycle The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks the digital result from the previous conversion from DATA OUT The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the output register when conversion is complete. The current conversion result is serially shifted out on the next I/O cycle. The conversion cycle just prior to the current I/O cycle The I/O period that follows the current conversion cycle
Current (N) conversion result Previous (N - 1) conversion cycle Next (N + 1) I/O cycle
Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this corrupts the output data from the previous conversion. The current conversion is begun immediately after the twelfth falling edge of the current I/O cycle. data input The data input is internally connected to an 8-bit serial-input address and control register. The register defines the operation of the converter and the output data length. The host provides the data word with the MSB first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 1 for the data input-register format).
A-6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
Table 1. Input-Register Format
INPUT DATA BYTE FUNCTION SELECT ADDRESS BITS D7 (MSB) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 D6 D5 D4 L1 D3 L0 D2 LSBF D1 BIP D0 (LSB)
Select input channel AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 Select test voltage (Vref + - Vref -)/2 Vref - Vref + Software power down Output data length 8 bits 12 bits 16 bits Output data format MSB first LSB first Unipolar (binary) Bipolar (2s complement) X represents don't care condition.
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 X 1 1 0 1 0 1 0 1
data input address bits The four MSBs (D7 - D4) of the data register address one of the 11 input channels, a reference-test voltage, or the power-down mode. The address bits affect the current conversion, which is the conversion that immediately follows the current I/O cycle. The reference voltage is nominally equal to Vref+ - Vref -. data output length The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current I/O cycle, allows device startup without losing I/O synchronization. A data length of 8, 12, or 16 bits can be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested. With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current conversion is output as a 12-bit serial-data stream during the next I/O cycle. The current I/O cycle must be exactly 12 bits long for proper synchronization, even if this means corrupting the output data from a previous conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle. With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial-data stream during the next I/O cycle with the four LSBs always set to 0 (pad bits). The current I/O cycle must be exactly 16 bits long to maintain synchronization even if this means corrupting the output data from the previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current I/O cycle.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
A-7
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
data output length (continued) With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial-data stream during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even if this means corrupting the output data from the previous conversion. The four LSBs of the conversion result are truncated and discarded. The current conversion is started immediately after the eighth falling edge of the current I/O cycle. Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when the data format is selected to be least significant bit first, since at the time the data length change becomes effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation, when different data lengths are required within an application and the data length is changed between two conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first format. sampling period During the sampling period, one of the analog inputs is internally connected to the capacitor array of the converter to store the analog input signal. The converter starts sampling the selected input immediately after the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge of the I/O CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has begun. After EOC goes low, the analog input can be changed without affecting the conversion result. Since the delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty. After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC goes high (indicating the conversion is complete) to maximize the sampling accuracy and minimize the influence of external digital noise. data register, LSB first D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is set to 0, the conversion result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to another, the current I/O cycle is never disrupted. data register, bipolar format D0 (BIP) in the input data register controls the binary data format used to represent the conversion result. When D0 is set to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an input voltage equal to Vref - is a code of all zeros (000 . . . 0), the conversion result of an input voltage equal to Vref + is a code of all ones (111 . . . 1), and the conversion result of (Vref + + Vref - ) /2 is a code of a one followed by zeros (100 . . . 0). When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion of an input voltage equal to Vref - is a code of a one followed by zeros (100 . . . 0), conversion of an input voltage equal to Vref + is a code of a zero followed by all ones (011 . . . 1), and the conversion of (Vref + + Vref -) /2 is a code of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other's complement. Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the current I/O cycle is not affected.
A-8
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
EOC output The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes low, the analog input signal can be changed without affecting the conversion result. The EOC signal goes high again after the conversion is completed and the conversion result is latched into the output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins. On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the falling edge of CS. data format and pad bits D3 and D2 of the input data register determine the number of significant bits in the digital output that represent the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines the arithmetic conversion. The numerical data is always justified toward the MSB in any output format. The internal conversion result is always 12 bits long. When an 8-bit data transfer is selected, the four LSBs of the internal result are discarded to provide a faster one-byte transfer. When a 12-bit transfer is used, all bits are transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are zeros. When CS is held low continuously, the first data bit of the just completed conversion occurs on DATA OUT on the rising edge of EOC. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes low and the serial output is forced to a setting of 0 until EOC goes high again. When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in the serial conversion result until the required number of bits has been output. chip-select input (CS) The chip-select input (CS) enables and disables the device. During normal operation, CS should be low. Although the use of CS is not necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data transfer of several devices sharing the same bus. When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is inhibited, thus preventing any further change in the internal state. When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low) for a minimum time before a new I/O cycle can start. CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough before the end of the current conversion cycle, the previous conversion result is saved in the internal output buffer and shifted out during the next I/O cycle.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
A-9
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
power-down features When a binary address of 1110 is clocked into the input data register during the first four I/O CLOCK cycles, the power-down mode is selected. Power down is activated on the falling edge of the fourth I/O CLOCK pulse. During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed, and the internal output buffer keeps the previous conversion cycle data results, provided that all digital inputs are held above VCC - 0.5 V or below 0.5 V. The I/O logic remains active so the current I/O cycle must be completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle, the converter normally begins in the power-down mode. The device remains in the power-down mode until a valid (other than 1110) input address is clocked in. Upon completion of that I/O cycle, a normal conversion is performed with the results being shifted out during the next I/O cycle. analog input, test, and power-down mode The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer according to the input addresses shown in Tables 2, 3, and 4. The input multiplexer is a break-before-make type to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then sampled and converted in the same manner as the external analog inputs. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling. Table 2. Analog-Channel-Select Address
ANALOG INPUT SELECTED AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 VALUE SHIFTED INTO DATA INPUT BINARY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 HEX 0 1 2 3 4 5 6 7 8 9 A
A-10
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
Table 3. Test-Mode-Select Address
INTERNAL SELF-TEST VOLTAGE SELECTED Vref + - Vref - 2 VALUE SHIFTED INTO DATA INPUT BINARY 1011 HEX B 200 UNIPOLAR OUTPUT RESULT (HEX)
Vref - 1100 C 000 Vref + 1101 D 3FF Vref + is the voltage applied to REF +, and Vref - is the voltage applied to REF -. The output results shown are the ideal values and may vary with the reference stability and with internal offsets.
Table 4. Power-Down-Select Address
INPUT COMMAND Power down VALUE SHIFTED INTO DATA INPUT BINARY 1110 HEX E ICC 25 A RESULT
converter and analog input The CMOS threshold detector in the successive-approximation conversion system determines each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the conversion process, the analog input is sampled by closing the SC switch and all ST switches simultaneously. This action charges all the capacitors to the input voltage. In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF -) voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF -. When the voltage at the summing node is greater than the trip point of the threshold detector (approximately 1/2 VCC ), a bit 0 is placed in the output register and the 4096-weight capacitor is switched to REF -. When the voltage at the summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and this 4096-weight capacitor remains connected to REF + through the remainder of the successive-approximation process. The process is repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down the line until all bits are determined. With each step of the successive-approximation process, the initial charge is redistributed among the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB. reference voltage inputs There are two reference inputs used with the device, the voltages applied to the REF+ and REF- terminals. These voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero-scale reading respectively. These voltages and the analog input should not exceed the positive supply or be lower than ground consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REF+ terminal voltage and at zero when the input signal is equal to or lower than REF- terminal voltage.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
A-11
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996 SC
Threshold Detector
4096 Node 4096
2048 REF+
1024 REF+
16 REF+
8 REF+
4 REF+
2 REF+
1 REF+
1
To Output Latches
REF -
REF - ST
REF - ST
REF - ST
REF - ST
REF - ST
REF - ST
REF - ST
REF - ST ST
VI
Figure 1. Simplified Model of the Successive-Approximation System
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Positive reference voltage, Vref + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.1 V Negative reference voltage, Vref - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.1 V Peak input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak total input current, II (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Operating free-air temperature range, TA: TLC2543C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C TLC2543I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminal with REF - and GND wired together (unless otherwise noted).
A-12
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
recommended operating conditions
MIN Supply voltage, VCC Positive reference voltage, Vref + (see Note 2) Negative reference voltage, Vref - (see Note 2) Differential reference voltage, Vref + - Vref - (see Note 2) Analog input voltage (see Note 2) High-level control input voltage, VIH Low-level control input voltage, VIL Clock frequency at I/O CLOCK Setup time, address bits at DATA INPUT before I/O CLOCK, tsu(A) (see Figure 5) Hold time, address bits after I/O CLOCK, th(A) (see Figure 5) Hold time, CS low after last I/O CLOCK, th(CS) (see Figure 6) Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 6) Pulse duration, I/O CLOCK high, twH(I/O) Pulse duration, I/O CLOCK low, twL(I/O) Transition time, I/O CLOCK, tt(I/O) (see Note 4 and Figure 7) Transition time, DATA INPUT and CS, tt(CS) Operating free-air temperature, TA free air temperature TLC2543C TLC2543I 0 - 40 VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2.5 0 2 0.8 0 100 0 0 1.425 120 120 1 10 70 85 4.1 4.5 NOM 5 VCC 0 VCC VCC + 0.1 VCC MAX 5.5 UNIT V V V V V V V MHz ns ns ns s ns ns s s C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied to REF- convert as all zeros (000000000000). 3. To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed. 4. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 s for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 4.1 MHz (unless otherwise noted)
PARAMETER VOH VOL IOZ IIH IIL ICC ICC(PD) High-level High level output voltage Low level output voltage Low-level High-impedance off-state g output current High-level input current Low-level input current Operating supply current Power-down current Selected channel leakage g current Maximum static analog reference current into REF + Ci Input capacitance Analog inputs Control inputs TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VO = VCC, VO = 0, VI = VCC VI = 0 CS at 0 V For all digital inputs, 0 VI 0.5 V or VI VCC - 0.5 V Selected channel at VCC, Unselected channel at 0 V Selected channel at 0 V, Unselected channel at VCC Vref + = VCC, Vref - = GND 1 30 5 IOH = -1.6 mA IOH = -20 A IOL = 1.6 mA IOL = 20 A CS at VCC CS at VCC 1 1 1 1 1 4 MIN 2.4 VCC - 0.1 0.4 0.1 2.5 - 2.5 2.5 - 2.5 2.5 25 1 -1 2.5 60 15 TYP MAX UNIT V V A A A mA A A A pF
All typical values are at VCC = 5 V, TA = 25C.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
A-13
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 4.1 MHz
PARAMETER EL ED EO EG ET Linearity error (see Note 5) Differential linearity error Offset error (see Note 6) Gain error (see Note 6) Total unadjusted error (see Note 7) DATA INPUT = 1011 Self-test output code (see Table 3 and Note 8) tconv tc Conversion time DATA INPUT = 1100 DATA INPUT = 1101 See Figures 10 - 15 See Figures 10 - 15 and Note 9 2048 0 4095 8 10 10 + total I/O CLOCK periods + td(I/O-EOC) 4 10 150 1.5 0.7 70 15 15 15 15 2.2 100 1.3 150 50 50 50 50 5 12 s s TEST CONDITIONS See Figure 2 See Figure 2 See Note 2 and Figure 2 See Note 2 and Figure 2 MIN TYP MAX 1 1 1.5 1 1.75 UNIT LSB LSB LSB LSB LSB
Total cycle time (access, sample, and conversion)
tacq tv td(I/O-DATA) td(I/O-EOC) td(EOC-DATA) tPZH, tPZL tPHZ, tPLZ tr(EOC) tf(EOC) tr(bus) tf(bus) td(I/O-CS)
Channel acquisition time (sample) Valid time, DATA OUT remains valid after I/O CLOCK Delay time, I/O CLOCK to DATA OUT valid Delay time, last I/O CLOCK to EOC Delay time, EOC to DATA OUT (MSB / LSB) Enable time, CS to DATA OUT (MSB / LSB driven) Disable time, CS to DATA OUT (high impedance) Rise time, EOC Fall time, EOC Rise time, data bus Fall time, data bus Delay time, last I/O CLOCK to CS to abort conversion (see Note 10)
See Figures 10 - 15 and Note 9 See Figure 7 See Figure 7 See Figure 8 See Figure 9 See Figure 4 See Figure 4 See Figure 9 See Figure 8 See Figure 7 See Figure 7
I/O CLOCK periods ns ns s ns s ns ns ns ns ns s
All typical values are at TA = 25C. NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (111111111111), while input voltages less than that applied to REF - convert as all zeros (000000000000). 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. 6. Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point. 7. Total unadjusted error comprises linearity, zero-scale, and full-scale errors. 8. Both the input address and the output codes are expressed in positive logic. 9. I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7). 10. Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at 5 s of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 s and 10 s, the result is uncertain as to whether the conversion is aborted or the conversion results are valid.
A-14
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
15 V 50 C1 10 F C2 0.1 F C3 470 pF TLC2543 AIN0 - AIN10 C3 470 pF 50 - 15 V LOCATION U1 C1 C2 C3 DESCRIPTION OP27 10-F 35-V tantalum capacitor 0.1-F ceramic NPO SMD capacitor 470-pF porcelain Hi-Q SMD capacitor PART NUMBER -- -- AVX 12105C104KA105 or equivalent Johanson 201S420471JG4L or equivalent
VI C1 10 F C2 0.1 F
_ U1 +
10
Figure 2. Analog Input Buffer to Analog Inputs AIN0 - AIN10
Test Point VCC RL = 2.18 k EOC 12 k DATA OUT 12 k Test Point VCC RL = 2.18 k
CL = 50 pF
CL = 100 pF
Figure 3. Load Circuits
Data Valid 2V CS tPZH, tPZL 2.4 V DATA OUT 0.4 V 0.8 V tPHZ, tPLZ 90% 10% I/O CLOCK 0.8 V DATA INPUT 2V 0.8 V tsu(A) th(A)
Figure 4. DATA OUT to Hi-Z Voltage Waveforms
Figure 5. DATA INPUT and I/O CLOCK Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
A-15
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
2V CS tsu(CS) I/O CLOCK 0.8 V Last Clock 0.8 V 0.8 V th(CS)
Figure 6. CS and I/O CLOCK Voltage Waveforms
To ensure full conversion accuracy, it is recommended that no input signal change occurs while a conversion is ongoing. tt(I/O) I/O CLOCK 2V 0.8 V 2V 0.8 V I/O CLOCK Period td(I/O-DATA) tv DATA OUT 2.4 V 0.4 V 2.4 V 0.4 V tr(bus), tf(bus) 0.8 V tt(I/O)
Figure 7. I/O CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK
Last Clock td(I/O-EOC)
0.8 V
EOC
2.4 V 0.4 V tf(EOC)
Figure 8. I/O CLOCK and EOC Voltage Waveforms
tr(EOC) EOC 0.4 V td(EOC-DATA) DATA OUT 2.4 V 0.4 V Valid MSB 2.4 V
Figure 9. EOC and DATA OUT Voltage Waveforms
A-16
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
CS (see Note A) I/O CLOCK
1 2 3 4 5 6 7 8 11 12
Access Cycle B DATA OUT
A11 A10 A9 A8 A7 A6
Sample Cycle B
A5 A4 A1 A0
MSB DATA INPUT
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize tconv A/D Conversion Interval
Initialize
Figure 10. Timing for 12-Clock Transfer Using CS With MSB First
CS (see Note A) I/O CLOCK
1 2 3 4 5 6 7 8 11 12 1
Access Cycle B DATA OUT
A11 A10 A9 A8 A7 A6
Sample Cycle B
A5 A4 A1 A0 B11
Low Level
MSB DATA INPUT
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize tconv A/D Conversion Interval
Initialize
Figure 11. Timing for 12-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIII IIII
IIIII IIIII
IIIIIII IIIIIII
Hi-Z State
1
B11
IIIIIIII I IIIIIIII IIIIIIII I IIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII
C7
C7
A-17
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
CS (see Note A) I/O CLOCK
1 2 3 4 5 6 7 8
Access Cycle B
A7 A6 A5 A4 A3
Sample Cycle B
A2 A1 A0
DATA OUT
MSB DATA INPUT
Previous Conversion Data
LSB
EOC
Initialize
CS (see Note A) I/O CLOCK
1 2 3 4 5 6 7 8 1
DATA OUT
DATA INPUT
EOC
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
A-18
IIIII IIIIIIIIII I IIIIIIII IIIII IIIIIIIIII I IIIIIIII
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value
A/D Conversion Interval
Figure 12. Timing for 8-Clock Transfer Using CS With MSB First
Access Cycle B
A7 A6 A5 A4 A3
Sample Cycle B
A2 A1 A0
MSB
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize
tconv A/D Conversion Interval
Figure 13. Timing for 8-Clock Transfer Not Using CS With MSB First
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IIII IIII
IIIIII IIIIII
Hi-Z tconv Low Level
1
B7
C7
Initialize
B7
IIIIIIIIIII IIIIII IIIIIIIIIII IIIIII
C7
Initialize
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
PARAMETER MEASUREMENT INFORMATION
CS (see Note A)
1 2 3 4 5 6 7 8 15 16
Access Cycle B
Sample Cycle B
DATA OUT
A15
A14
A13
A12
A11
A10
A9
A8
A1
A0
DATA INPUT
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize tconv A/D Conversion Interval
Figure 14. Timing for 16-Clock Transfer Using CS With MSB First
CS (see Note A) I/O CLOCK
1 2 3 4 5 6 7 8 15 16 1
Access Cycle B DATA OUT
A15 A14 A13 A12 A11 A10
Sample Cycle B
A9 A8 A1 A0
Low Level
MSB DATA INPUT
Previous Conversion Data
LSB
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
EOC
Shift in New Multiplexer Address, Simultaneously Shift Out Previous Conversion Value Initialize
tconv A/D Conversion Interval
Figure 15. Timing for 16-Clock Transfer Not Using CS With MSB First
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
III II
IIIII IIIII
IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII
MSB
Previous Conversion Data
LSB
IIIIIII IIIIIII
Hi-Z State Initialize
B15 C7
I/O CLOCK
1
B15
C7
IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II
A-19
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
APPLICATION INFORMATION
111111111111 See Notes A and B 111111111110 111111111101 VFS 4094 VFSnom 4093 4095
Digital Output Code
VFT = VFS - 1/2 LSB 100000000001 100000000000 011111111111 VZS 000000000010 000000000001 000000000000 0
2049 2048 Step
VZT = VZS + 1/2 LSB 2047
2 1 0 4.9152
0.0006
0.0012
0.0024
2.4564
2.4576
2.4588
4.9128
4.9134
4.9140
VI - Analog Input Voltage - V NOTES: A. This curve is based on the assumption that Vref+ and Vref - have been adjusted so that the voltage at the transition from digital 0 to 1 (VZT) is 0.0006 V and the transition to full scale (VFT) is 4.9134 V. 1 LSB = 1.2 mV. B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is the step whose nominal midstep value equals zero.
Figure 16. Ideal Conversion Characteristics
TLC2543 1 2 3 4 5 Analog Inputs 6 7 8 9 11 12 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 GND 10 To Source Ground REF+ REF- 14 13 5-V DC Regulated DATA OUT EOC 16 19 CS I/O CLOCK DATA INPUT 15 18 17 Processor Control Circuit
Figure 17. Serial Interface
A-20
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
TLC2543C, TLC2543I 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS079C - DECEMBER 1993 - REVISED JUNE 1996
APPLICATIONS INFORMATION simplified analog input analysis
Using the equivalent circuit in Figure 18, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: The capacitance charging voltage is given by V where Rt = Rs + ri The final voltage to 1/2 LSB is given by VC (1/2 LSB) = VS - (VS /8192) Equating equation 1 to equation 2 and solving for time tc gives V and tc (1/2 LSB) = Rt x Ci x ln(8192) Therefore, with the values given, the time for the analog input signal to settle is tc (1/2 LSB) = (Rs + 1 k) x 60 pF x ln(8192) This time must be less than the converter sample time shown in the timing diagrams.
Driving Source Rs VS ri VC 1 k MAX Ci 60 pF MAX TLC2543
C
+ VS 1-e-tc RtCi
(1)
(2)
S
*
V
S
8192
+ VS 1-e-tc RtCi
(3) (4)
(5)
VI
VI = Input Voltage at AIN VS = External Driving Source Voltage Rs = Source Resistance ri = Input Resistance Ci = Input Capacitance VC = Capacitance Charging Voltage Driving source requirements: * Noise and distortion for the source must be equivalent to the resolution of the converter. * Rs must be real at the input frequency.
Figure 18. Equivalent Input Circuit Including the Driving Source
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
A-21
A-22

▲Up To Search▲

Price & Availability of SLAU004

	To Download SLAU004 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .