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TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997
D D D D D D D D D
Color or Gray Scale Operation Signals Processed in the Digital Domain Differential RGB Input Multiplexer Three 8-bit DACs for CCD Offset Level Shifting With Bipolar Correction Range Two Sampling Modes: - DAC Referenced - Correlated Double Sampling (CDS) 12-Bit ADC with 6 MSPS Operation Digital dc Restoration Pixel-By-Pixel Offset and Shading (Gain) Compensation Global Gain Adjust for Each Color (Channel)
D D D D D D D D
Compatible with 600 dpi CCD Image Sensors Global Offset Adjust for Each Color (Channel) Output Word Length Programmable to 8, 10, 12, or 16 Bits Programmable Threshold Detector for Each Color (Channel) Dual Internal Default Registers for Even/Odd Pixel Offset Correction 68-Terminal PLCC Package
applications
Handy Scanners Flatbed Scanners
description
The TLC8044 is a 12-bit analog-to-digital interface subsystem for charge-coupled device (CCD) image sensors and scanners. An input multiplexer allows color operation with a single on-chip 12-bit ADC. The TLC8044 uses DSP circuits to correct for nonideal CCD image sensor and scanning system characteristics. Cost effective gray scale operation is obtained using a single multiplexer input. The TLC8044 three-channel input multiplexer and sampling function has two basic modes of operation: normal sampling and correlated double sampling. The internal sample and hold allows all three channels to be sampled simultaneously in color operation. Three DACs (8 bits + sign) are provided to allow bipolar adjustment of the dc level of the signal at the ADC input. Digital dc restoration is provided following the ADC. Variations in offset and luminance across a scan are dynamically corrected on a pixel-by-pixel basis, using calibration data provided by an external data store. Provisions are made for global adjustments of gain, contrast and color balance, and offset for brightness. The output word length can be programmed to 8, 10, 12, or 16 bits, and a programmable threshold detector is provided for use during calibration and OCR applications. The TLC8044 is characterized for operation from 0C to 70C.
AVAILABLE OPTIONS PACKAGE TA 0C to 70C CHIP CARRIER (FN) TLC8044FN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997
FN PACKAGE (TOP VIEW)
CC1 CC0 ORNG DETOP DGND PSC11 PSC10 PSC9 PSC8 PSC7 PSC6 PSC5 PSC4 PSC3 PSC2 PSC1 PSC0
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 10 59 11 58 12 57 13 56 14 55 15 54 16 53 17 52 18 51 19 50 20 49 21 48 22 47 23 46 24 45 25 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 DVDD2 OP8 OP9 OP10 OP11 OP12 OP13 OP14 OP15 DVDD1 ONE SDI SCK SEN MCLK VSMP OE RINP RINN GINP GINN AVDD AGND BINP BINN DAC
2
POC11 POC10 POC9 POC8 POC7 POC6 POC5 POC4 POC3 POC2 POC1 POC0 RESET RT RB RU RL
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functional block diagram
RB RL DAC ONE POC PSC
RU
RT
12
12
MCLK REF 3 12- Bit ADC DC Restore MUX 2:1 MUX 12 16 16 12 16 Pixel Offset Adjust Global Offset Adjust Global Gain Adjust Pixel Shading MUX Adjust 16 16 16
VSMP
Timing Control
CC
OE 16 OP ORNG Output Word Length Select
CDS
RINP RINN Video Sample/MUX
GINP GINN
BINP BINN 3:1 MUX Reg R Reg G Reg B Reg Be Reg Bo Reg B Reg B Reg Ge Reg Go Reg G Reg G Reg Re Reg Ro Reg R Reg R Reg R Reg G Reg B 3:1 MUX 3:1 MUX 3:1 MUX 3:1 MUX 3:1 MUX
+ - + + - + + - +
Threshold Detect
DETOP
8-Bit + Sign DACB
8-Bit + Sign DACG
SDI Serial Interface SCK SEN
TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
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8-Bit + Sign DACR
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TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
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Terminal Functions
TERMINAL NAME AGND AVDD BINN BINP CC1,0 DAC DETOP DGND DVDD1,2 GINN GINP MCLK NO. 47 48 45 46 10, 11 44 13 14 60, 1 49 50 55 TYPE Analog Analog Analog Analog Digital Analog Digital Digital Digital Analog Analog Digital I I O O O I I I I I I/O I Analog ground (0 V) Positive analog supply (5 V) Negative blue channel input video Positive blue channel input video Color code outputs. CC0 and CC1 indicate which channel the current output sample was taken from (R = 00, G = 01, B = 10). Buffered midpoint of ADC reference string. DAC is used internally to set DAC reference voltages. Threshold detector output (active high). DETOP indicates that the current output pixel has exceeded the internally programmed threshold for that channel. Digital ground (0 V) Positive digital supply (5 V) Negative green channel input video Positive green channel input video Master clock. MCLK is applied at either six times or twice the input pixel rate for color and monochrome operation, respectively. MCLK is divided by two internally to define the ADC sample rate and to provide the clock source for the DSP section. Output 3-state control. Outputs are enabled when OE = 0. Odd not even. ONE defines the even and odd pixels when the internal pixel offset correction registers are in use (even = 0, odd = 1). Digital 16-bit output (3-state). In 8-, 10-, and 12-bit output modes, OP15 is used to indicate that the output pixel is negative; i.e., OP15 can be used as an under range indicator. OP15 is active high when indicating under range. Over range signal (active high). In 8-, 10-, and 12-bit output modes, this signal indicates that the current output pixel has exceeded the maximum achievable for the output word length in use. Pixel offset coefficient input. The POC11-POC0 12-bit word is applied at the multiplexed pixel rate (i.e., three samples per pixel period in color mode) to correct offset errors in a pixel-by-pixel fashion. Pixel shading coefficient input. The PSC11-PSC0 12-bit quantity is applied at the multiplexed pixel rate (i.e., three samples per pixel period in color mode) to correct shading effects in a pixel-by-pixel fashion. Reset input (active high). RESET forces a reset of all internal registers in the TLC8044. Negative red channel input video Positive red channel input video ADC reference terminals. The voltage applied between RT (full scale) and RB (zero level). define the ADC reference range. RU and RL, upper and lower resistor terminals, are used to derive optimum reference voltages from an external 5-V reference. Serial clock. Serial interface clock signal. Serial data in. Serial interface input data signal. Serial enable Video sample synchronization pulse. VSMP applied synchronously with MCLK specifies the point in time that the input is sampled. The timing of internal multiplexing between the R, G, and B channels is derived from this signal. DESCRIPTION
OE ONE OP15-OP0
53 59 61-68, 2-9 12 27-38
Digital Digital Digital
I I O
ORNG POC11-POC0
Digital Digital
O I
PSC11-PSC0
15-26
Digital
I
RESET RINN RINP RU, RT, RB, RL SCK SDI SEN VSMP
39 51 52 42, 40, 41, 43 57 58 56 54
Digital Analog Analog Analog
I I I I
Digital Digital Digital Digital
I I I I
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TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, DVDD1, DVDD2, AVDD, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital inputs (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Analog inputs (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Digital outputs, maximum external voltage applied (see Note 1) . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Reference input (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3 V Operating temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50C to 150C Lead temperature, soldering, 10 sec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltages applied to DVDD1 and DVDD2 are measured with respect to the DGND terminal. AVDD is measured with respect to the AGND terminal. For the following specifications, unless otherwise noted, AGND and DGND are tied togather (and represent 0 volts) and are referred to simply as GND. When the voltages applied to DVDD1, DVDD2, and AVDD are equal, they are referred to simply as VDD, unless otherwise noted.
recommended operating conditions
total device
MIN Supply voltage, VCC 4.75 NOM MAX 5.25 UNIT V
digital inputs
MIN High-level input voltage, VIH Low-level input voltage, VIL 0.9 VDD 0.1 VDD NOM MAX UNIT V V
input multiplexer
TEST CONDITIONS Setup time, input video before MCLK, tsu(V) Hold time, input video after MCLK, th(V) Setup time, reset video before MCLK, tsu(R) Hold time, reset video after MCLK, th(R) CDS mode only CDS mode only MIN 10 25 10 25 NOM MAX UNIT ns ns ns ns
serial interface
MIN Cycle time, MCLK, tcyc1 Pulse duration, MCLK high, tw1(MCLKH) Pulse duration, MCLK low, tw2(MCLKL) Setup time, VSMP to MCLK, tsu(D) Hold time, MCLK to VSMP, th(D) Setup time, POC/PCS to MCLK, tsu(P) Hold time, MCLK to POC/PCS, th(P) Cycle time, SCK, tcyc2 Pulse duration, SCK high, tw3(SCKH) Pulse duration, SCK low, tw4(SCKL) Setup time, SDI to MCLK, tsu(S) Hold time, MCLK to SDI change, th(S) Setup time, SCK to SEN, tsu(SCE) Setup time, SEN to SCK, tsu(SEC) Pulse duration, SEN high, tw(SEN) 83.3 37.5 37.5 10 10 10 30 83.3 37.5 37.5 10 10 20 20 50 NOM MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
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electrical characteristics, VDD = 5 V, AGND = DGND = 0 V, TA = full range (unless otherwise noted)
total device
PARAMETER ICC ICC Supply current, active Supply current, standby MIN TYP 80 8 MAX 130 10 UNIT mA mA
digital inputs
PARAMETER IIH IIL Ci High-level input current Low-level input current Input capacitance 10 MIN TYP MAX 1 1 UNIT A A pF
digital outputs
PARAMETER VOH VOL IOZ High-level output voltage Low-level output voltage High-impedance output current TEST CONDITIONS IOH = -1 mA IOL = 1 mA MIN VDD - 0.75 0.75 1 TYP MAX UNIT V V A
input multiplexer
PARAMETER Channel-to-channel gain matching VICR Common mode input voltage 0.5 MIN TYP 0.5% MAX 5% 4.5 V UNIT
reference string
PARAMETER Z Z Vref(RT) Vref(RB) Vref(DAC) Impedance, RT to RB Impedance, RU to RL Reference voltage, top Reference voltage, bottom DAC reference voltage VI(RU) = 5 V, VI(RU) = 5 V, VI(RU) = 5 V, VI(RL) = 0 V VI(RL) = 0 V VI(RL) = 0 V TEST CONDITIONS MIN 595 1190 3.7125 1.2375 2.475 TYP 850 1700 3.75 1.25 2.5 MAX 1105 2210 3.7875 1.2625 2.525 UNIT V V V
8-bit DACs
PARAMETER Resolution Zero-scale voltage Full-scale voltage Differential nonlinearity (DNL) Integral nonlinearity (INL) MIN 8 0 Vref(DAC) -10 0.1 0.4 10 Vref(DAC) +10 TYP MAX UNIT Bits mV mV LSB LSB
t1
1
6
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TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997
electrical characteristics, VDD = 5 V, AGND = DGND = 0 V, TA = full range (unless otherwise noted) (continued)
12-bit ADC
PARAMETER Resolution Sampling rate Full-scale transition error voltage at xINP (see Note 2) Single-ended mode, VI(xINN) = 2.5 V, DAC code = 000H Single-ended mode, VI(xINN) = 2.5 V, DAC code = 000H Differential mode, DAC code = 000H Differential mode, DAC code = 000H -100 TEST CONDITIONS MIN 12 6 100 TYP MAX UNIT Bits MSPS mV
Zero-scale transition error voltage at xINP (see Note 3)
-100
100
mV
Full-scale transition error voltage, VI(xINP) - VI(xINN) (see Note 2) Zero-scale transition error voltage, VI(xINP) - VI(xINN) (see Note 3) Differential nonlinearity (DNL) (see Note 4) Maximum number of missing codes Integral nonlinearity (INL) (see Note 5)
-25 -25
25 25 1.5
mV mV LSB CODES LSB
0 2
8 5
NOTES: 2. The full-scale transition at xINP is the difference between the signal input voltage that causes the 4094 to 4095 transition and the measured reference voltage Vref(RT). 3. The zero-scale transition at xINP is the difference between the signal input voltage that causes the 0 to 1 transition and the reference voltage Vref(RB). 4. Differential nonlinearity (DNL) is the difference between the measured value between any two adjacent codes and the ideal 1 LSB value. 5. Integral nonlinearity (INL) is the maximum deviation of the output from the ideal straight line between zero and the full-scale value.
switching characteristics
PARAMETER tpd(D) ten(PZE) tdis(PEZ) Propagation delay time, MCLK to output valid Enable time, output, OE to data valid Disable time, output, OE to high impedance MIN TYP 50 70 70 MAX 75 75 25 UNIT ns ns ns
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PARAMETER MEASUREMENT INFORMATION
MCLK tsu(D) VSMP tsu(V) th(V) th(D) tsu(D) th(D)
R,G,B Video Inputs (Normal Mode) tsu(V) R,G,B Video Inputs (CDSR1 = 0, CDSR0 = 0) tsu(V) R,G,B Video Inputs (CDSR1 = 0, CDSR0 = 1) tsu(V) R,G,B Video Inputs (CDSR1 = 1, CDSR0 = 0) tsu(V) R,G,B Video Inputs (CDSR1 = 1, CDSR0 = 1) th(V) tsu(R) th(V) tsu(R) th(V) tsu(R) th(V) tsu(R) th(R) th(R)
tsu(V)
th(V)
tsu(V)
th(V)
tsu(V)
th(V)
th(R) tsu(V) th(R)
th(V)
Figure 1. Detailed Video Input Timing - Color Mode
MCLK th(D) tsu(D) VSMP
tsu(V) R,G,B Input Video Reset Video
th(V)
tsu(V)
th(V)
Figure 2. Detailed Video Input Timing - Monochrome Mode
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SLAS128 - JUNE 1997
PARAMETER MEASUREMENT INFORMATION
tcyc1 MCLK th(D) tsu(D) SMP th(D) tsu(D) POC11 - POC0 Red POC11 - POC1 ONE tpd(D) OP15 - OP0 Red tpd(D) Green tpd(D) Blue tpd(D) Green Blue tsu(D) th(D) tsu(D) th(D) tw1(MCLKH) tw2
CC0
CC1
Figure 3. Detailed Digital Timing - Color Mode
tcyc1 MCLK th(D) tsu(D) SMP th(D) tsu(D) POC11 - POC0 PSC11 - PSC0 ONE tpd(D) OP15 - OP0 tpd(D) tpd(D) tpd(D) th(D) tsu(D) th(D) tsu(D) tw1(MCLKH) tw2(MCLKL)
Figure 4. Detailed Digital Timing - Monochrome Mode
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TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
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PARAMETER MEASUREMENT INFORMATION
tcyc2 SCK th(S) tsu(S) SDI tw(SEN) tsu(SCE) SEN tsu(SEC) tw(SCKH) tw(SCKL)
Figure 5. Detailed Digital Timing - Serial Interface
TYPICAL CHARACTERISTICS
DNL - Differential Nonlinearity - LSB 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1023 2047 Input Code 3071 4095
Figure 6. Differential Linearity With Code
INL - Integral Nonlinearity - LSB 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 1023 2047 Input Code 3071 4095
Figure 7. Integral Linearity With Code
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SLAS128 - JUNE 1997
PRINCIPLES OF OPERATION general CCD system operation
CCD image sensor array output summary Figure 8 shows a simplified CCD image sensor linear array system with typical CCD array inputs and outputs. The inputs for the shift gate (SH), reset, and two-phase clock drive the array. An electronic charge proportional to the light input is generated by a photo diode for each pixel of the array. The charge for each pixel is transferred in parallel into the analog CCD shift register using the shift gate input and then shifted out serially using a two-phase clock. At the CCD output (OS terminal), the array converts the charge for each pixel into a voltage using a capacitor and source follower MOS transistor. The charge on this capacitor is reset for each pixel by the reset pulse input. A typical output signal then includes a reset period, a dark period, and a period containing video output for each pixel, as shown in Figure 9. This signal sits on a varying dc offset of typically 5 V and is negative going for an increase in video output. An output (DOS terminal) also provides only the dc level from the CCD array.
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TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 - JUNE 1997
12
RU 12 12 Gate Array OE OP ORNG 16 Signal Processing CC DAC MCLK GR VSMP RINP RINN R GINP 2GR 2GR GINN BINP R ONE POC(0-11) PSC(0-11) RT RB RL AVDD AGND DVDD1 DVDD2 DGND
Clock Generator
OS
+ _
DOS
CCD Image Sensor
TLC8044
DETOP RESET
BINN GR R
Memory Control
OS
Template Release Date: 7-11-94
+ _
R 2GR 2GR
SDI SCK SEN
DOS
3 GR R MUC RAM
OS
+ _
R 2GR 2GR
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DOS
Figure 8. System Diagram
TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997
PRINCIPLES OF OPERATION
CCD image sensor array output summary (continued)
Reset Feedthrough Reset Level Video Level
Black
Amplitude
White Period of One Pixel Period of One Pixel
Figure 9. A Typical Charge-Coupled Display (CCD) Output Signal CCD array analog-to-digital interface functions The interface to the CCD array analog output and the conversion of the output into digital form involves the following functions: 1. The video output waveform first has to be removed from the varying dc level on which it sits and shifted in level to be compatible with an interface device running from a single 5-V supply rail. 2. Gain has to be applied to bring the signal up to the full-scale range of the analog-to-digital converter (ADC) and a means provided to adjust static gain to compensate for variations between devices or multiple outputs of color arrays. Once these static dc levels (offsets) and gain levels have been adjusted, dynamic corrections are needed on a pixel-by-pixel basis. 3. Dynamic gain adjustment is needed to compensate for the fall off in output from the center to the ends of the array when used in scanner applications (see Figure 10). Dynamic offset adjustments are required to compensate for the pixel-by-pixel variation in black dc levels obtained from different CCD array elements. 4. DC restoration may optionally be required. Global adjustments of gain and offset across a whole scan are respectively used to correct color balance and contrast and to change brightness.
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PRINCIPLES OF OPERATION
CCD array analog-to-digital interface functions (continued)
Ideal Output (As Corrected By Pixel Shading Adjust Block)
Relative Pixel Output Value
Scanning System Output Error Pixel Width Time
Scanner System Pixel Outputs
Figure 10. Scanner System Relative CCD Pixel Output CCD scanner analog-to-digital interface subsystem
input dc level shift, output offset, and channel gain
The TLC8044 uses external operational amplifiers configured as differential amplifiers to remove the dc level present in the CCD outputs by using the common mode voltages from the OS and DOS outputs for each channel (see the functional block and system diagrams). DC bias is provided for the external differential amplifier from the TLC8044 DAC output as shown in the system diagram in Figure 8. Without any residual offset from the CCD, the differential amplifier minimum output is (DAC result)/2 and is uneffected by the external differential amplifier gain setting (G). The offset at the output of the external differential amplifiers, including residual offset from the CCD, should be low enough to ensure the CCD amplified signal is within the input common mode range of the TLC8044 and that the offset can be adjusted out by the TLC8044 internal DACs. The external differential amplifiers also provide the system gain for each channel to ensure the output amplitude of each channel is greater than one half the ADC full-scale range. Variations between the RGB channels of the CCD can have a 10 to 1 ratio in output. To minimize the offset at the amplifier output with the highest gain, the external amplifiers should be configured for gains in the range 1/3 to 3 rather than 1 to 10 to compensate for this output variation. This is achieved by scaling the gain setting resistors shown in the system diagram by the gain factor (G) over this 1/3 to 3 range.
RGB channel multiplexer and sampler
For color CCD image sensor arrays, a combined three-input multiplexer and sampler is used enabling the use of a single fast 12-bit ADC and DSP channel. The TLC8044 multiplexer has three differential inputs for each of the RGB channel outputs and a further internal input for each channel which is used to compensate for the residual offset in the input signal. This internal offset compensation is provided by the TLC8044 three 8-bit plus sign DACs, which provide bipolar offset correction with respect to the input reference levels. The DACs are updated through the serial interface.
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PRINCIPLES OF OPERATION
RGB channel multiplexer and sampler (continued)
The input structure can be set up for use in single-ended or fully differential mode, under control of the serial interface data. The configuration shown in the system diagram is single ended, with the negative inputs tied to the DAC, which is the buffered midpoint of the ADC reference chain. Differential mode can be used when an amplifier with differential outputs is placed between the CCD image sensor and the TLC8044. In color operation, the three-channel sampling system multiplexes the three channels to the ADC input in a sequence defined by the VSMP input synchronization pulse. In monochrome operation, channel synchronization between R, G, and B inputs is achieved through the serial interface.
analog-to-digital converter
The ADC is implemented using a 12-bit pipelined architecture which performs conversions at one half the MCLK clock rate. The ADC full-scale range is defined by the voltages applied to terminals RT and RB, which should be set to 3.75 V and 1.25 V respectively to give a full-scale range of 3.75 V -1.25 V = 2.5 V. The ADC internal input is differential with an input signal of 2.5 V corresponding to full scale (output code FFF hex) and -2.5 V corresponding to zero scale (output code 000 hex). The RU and RL terminals are connected to extensions of the internal reference chain, which allow the 3.75-V and 1.25-V levels to be derived from a 5-V reference applied between RU and RL. All reference terminals should be capacitively decoupled externally. The combination of the input multiplexer structure with the internal offset correction DACs accomodates a wide range of input voltages. The relationships between input voltage levels (at the positive and negative inputs INP and INN) and ADC full-scale and zero-scale results are shown in Tables 1 and 2 for a range of input offset voltages for both single-ended and differential input modes. The tables also show the DAC correction voltage and code required in each case. The basic difference between single-ended and differential input modes is that a gain of 2 is applied to the input signal between INP and INN in the single-ended case. Thus an input differential of 1.25 V is converted to a full-scale ADC differential input of 2.5 V. Any residual offset present on the input signal is also gained by 2 in the single-ended mode, resulting in the required DAC values shown in Table 1. Table 1. Single-Ended Mode Input Voltage Ranges
INPUT OFFSET VOLTAGE 0.625 0 -0.625 FULL-SCALE INPUT VOLTAGE VI(INP) 4.375 3.75 3.125 VI(INN) 2.5 2.5 2.5 ZERO-SCALE INPUT VOLTAGE VI(INP) 1.875 1.25 0.625 VI(INN) 2.5 2.5 2.5 -1.25 0 1.25 DAC VOLTAGE DAC CODE (HEX) 17F 000 07F
Table 2. Differential Mode Input Voltage Ranges
DIFFERENTIAL INPUT OFFSET VOLTAGE 1.25 0 -1.25 FULL-SCALE INPUT VOLTAGE VI(INP) 4.375 3.75 3.125 VI(INN) 0.625 1.25 1.875 ZERO-SCALE INPUT VOLTAGE VI(INP) 1.875 1.25 0.625 VI(INN) 3.125 3.75 4.375 -1.25 0 1.25 DAC VOLTAGE DAC CODE (HEX) 17F 000 07F
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PRINCIPLES OF OPERATION
analog-to-digital converter (continued)
The examples in Tables 1 and 2 assume that the ADC reference terminals RT and RB are set to 3.75 V and 1.25 V, respectively. The signals shown in the tables cover the full-scale range of the ADC. In practice, a reduced range is used to allow some headroom, accomodating a wider range of input offset voltages. The ADC output code can be inverted under control of the serial interface. When not in use, the ADC can also be put into standby mode through the serial interface to reduce system power consumption.
sample modes
Two input sampling modes are provided, normal and correlated double sampling (CDS). Sampling mode selection is made through the serial interface. All video input timing and sampling is performed relative to the rising edge of the MCLK clock input signal. MCLK is applied to twice the required ADC conversion rate. Synchronization of sampling and channel multiplexing to the incoming video signals is performed by the VSMP input synchronization pulse. Table 3 is a summary of the device operating modes.
normal sampling mode
Figure 11(a) and Figure 11(b) show the timing of signals in normal sampling mode for both color and monochrome operation. In color operation, all three input channels are sampled at the same instant on the first rising edge of MCLK after the VSMP pulse. An internal timing circuit then controls the multiplexing of the three channels to the ADC input in the R,G,B sequence. In this mode, VSMP is applied at the input pixel rate, and ADC conversions are performed at three times the input pixel rate. For monochrome (single channel) operation, VSMP is again applied at the input pixel rate, however, for monochrome, the ADC is supplied with a continuous stream of samples from a single input channel. Input channel selection in this mode is achieved through the serial interface. In both color and monochrome operation, a simple external delay circuit can be used to align the video data with the sampling instant, provided that the CCD clocks are generated from MCLK. Detailed timings for both cases are shown in Figures 3 and 4.
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Table 3. Mode Summary
CDS AVAILABLE MAX SAMPLE RATE SENSOR INTERFACE DESCRIPTION The three input channels (R, G, B) are sampled in parallel at 2 MSPS maximum. The sampled data is multiplexed into a single data stream before the internal ADC, giving an internal serial data rate of maximum 6 MSPS. One input channel is continuously sampled. The internal multiplexer is held in one position under control of the user. REGISTER CONTENTS WITH CDS REGISTER CONTENTS WITHOUT CDS
MODE
DESCRIPTION
TIMING REQUIREMENTS
1
Color
Yes
2 MSPS
MCLK max: 12 Mhz MCLK: VSMP ratio is 6:1
Setup register 1: Word 1: 00h Word 2: 81h
Setup register 1: Word 1: 00h Word 2: 80h
2
Monochrome
Yes
2 MSPS
Identical to mode 1
Setup register 1: Word 1: 00h Word 2: 91h Setup register 2: Word 2: bits b(1,0) define which channel to be sampled Identical to mode 2 plus Setup register 2: Word 1: bits b(1,0) must be set to 00h
Setup register 1: Word 1: 00h Word 2: 90h Setup register 2: Word 2: bits b(1,0) define which channel to be sampled
TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
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3
Fast monochrome
Yes
4 MSPS
Identical to mode 2
MCLK max: 12 MHz MCLK: VSMP ratio is 3:1
Identical to mode 2 Setup register 1: 5Dh Setup register 2: Word 2: bits b(1,0) define which channel to be sampled
4
Max speed monochrome
No
6 MSPS
Identical to mode 2
MCLK max: 12 MHz MCLK: VSMP ratio is 2:1
Not supported
Only indicates relevant register bits.
SLAS128 - JUNE 1997
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TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997
PRINCIPLES OF OPERATION
MCLK VSMP
r1, g1, b1 r2, g2, b2 r3, g3, b3
Video Sample ADC Input
b0
r1
g1
b1
r2
g2
ADC Sample
(a) COLOR OPERATION
MCLK VSMP
m1
m2
m3
m4
m5
Input Video
Video Sample ADC Input
m0
m1
m2
m3
m4
m5
ADC Sample
(b) MONOCHROME OPERATION
Figure 11. Normal Mode Input Timing
MCLK VSMP
r1, g1, b1 r2, g2, b2 r3, g3, b3
Input Video
Reset Sample Video Sample
2
1
2
ADC Input
b0
r1
g1
b1
r2
g2
ADC Sample
Video Sample 2 - Reset Sample 2
Figure 12. CDS Mode Input Timing
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III III IIIIIIII
b2 m6 m7 m6
IIIIIIII IIIIIIII
III III III IIIIII III III III III IIIIII III IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII
b2
III III
III III IIIIIII IIIIIII IIIIIII III III
III III IIIIII IIIIII IIIIII III III III II III II III III
Input Video
3
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SLAS128 - JUNE 1997
PRINCIPLES OF OPERATION
correlated double sampling
Correlated double sampling is a circuit technique for reducing any correlated noise between the reset (black) level and the video level of the CCD array. Referring to the block diagram shown in Figure 13(a), a sample of the CCD output is taken and held at the reset level and another sample is taken and held at the video level. These two levels are subtracted essentially nulling any common signal, and thereby minimizing the correlated noise that exists at both the reset level and the video level. Figure 13(b) shows relative timing.
S/H AMP
Video Out +
S/H AMP VIN (CCD Output) Reset Out
Subtractor -
Vout = Video Out - Reset Out
Reset S/H
Video S/H (a)
VIN (CCD Output)
Reset (Black) Level Video
Reset S/H
Reset Out
Video S/H
Video Out ADC Clock
(b)
Figure 13. Samplified Correlated Double Sampling
correlated double sampling mode
In CDS mode, two samples are taken per channel within each pixel period. Figure 12 shows the timing diagram for this mode of operation. The video signal is sampled during the reset phase and during the video information with timing defined relative to the VSMP input. The difference between these two samples forms the input to the ADC. The relative timing of the reset and video samples shown in Figure 12 is the default (post-reset) condition. The timing of the reset sample relative to the video sample can be advanced by one or retarded by one or two MCLK periods under control of the serial interface. Figure 1 shows a detailed video input timing diagram with all four CDS timing options.
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PRINCIPLES OF OPERATION
correlated double sampling mode (continued)
To perform CDS input sampling, the device should be set up in single-ended mode with the differential inputs of each channel (xINP, xINN) connected together to the video input signal. For positive going input signals, i.e., white signal level greater than the reset level, the offset DACs should be set to the maximum negative value (DAC code 1FF hex). This configuration sets the zero signal level (video input equal to the reset level) at the ADC zero-scale code transition. Increasing the DAC code towards zero moves the zero signal level up from the ADC zero-scale code transition. For negative-going input signals, i.e., white signal level less than the reset level, the DACs should be set to the maximum positive value (DAC code 0FF hex). This configuration sets the zero signal level at the ADC full-scale code transition. The polarity of the ADC output signal can be inverted under control of the serial interface data. The multiplexing shown in Figure 12 refers to color operation, however the same overall timing scheme applies to monochrome CDS operation, in that a single input sample is applied to the ADC per VSMP period. Thus the maximum sampling rate in monochrome CDS mode is limited to one third of the maximum rate achievable in normal monochrome sampling mode.
digital image processing
The digital image processing functions following the ADC as shown in the functional block diagram include the following:
* * * * * * *
DC restore: This allows fine adjustment of the dc video level at the ADC output with adjustment values being programmed through the serial interface. Pixel-by-pixel offset compensation: This uses offset coefficients that are either externally supplied at the multiplexed channel rate or supplied from internal default registers whose values are programmed through the serial interface. Compensation for pixel-by-pixel shading curve nonuniformity and photo response nonuniformity within the sensor: Coefficients are externally supplied at the multiplexed channel rate. Default registers are provided for use during calibration. Global offset adjust: Offset adjust over the whole scan for each channel to give brightness control. Values are programmed through the serial interface. Global gain adjust: Independent gain adjust over the whole scan for each channel to give contrast and color balance control. Gain values are programmed through the serial interface. Programmable output word length selection: The output word length can be programmed to 8, 10, 12, or 16 bits through the serial interface. Programmable threshold detector with independent thresholds for each channel.
Global adjustments are implemented after the pixel-by-pixel compensations allowing calibrations and modifications in operational use without having to recalibrate the pixel-by-pixel factors.
DC restore
The dc restore block is used for fine adjustment of the dc signal level at the ADC output by adding a value stored in an internal register. Separate level adjust registers are provided for each channel (color) with multiplexing between channels controlled internally. The level adjust registers are programmed through the serial interface as 12-bit 2s complement numbers with a range of 0.5 of the ADC full scale, allowing 1-bit resolution in adjustment of the ADC output. The dc adjustment registers are reset to zero.
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PRINCIPLES OF OPERATION
pixel offset compensation
The output of the dc restore circuit is passed to an adder which performs pixel-by-pixel offset compensation. Compensation values can either be supplied externally at the multiplexed pixel rate, allowing different correction values for each pixel in the array, or supplied from internal default values programmed through the serial bus. Selection between the two sources is controlled through the serial bus. Two sets of internal default registers are provided to allow correction values to be stored internally for use on even and odd pixels with selection between the two sets under control of the ONE terminal (ONE low for even registers, ONE high for odd registers). This feature allows correction of differing dc offsets output on even and odd pixels, which occur in some CCD sensors, using internally stored data. Pixel offset correction values are input or stored as 12-bit 2s complement numbers. Programmable internal scaling is provided which allows the offset correction factors to cover 0.5, 0.25, 0.125, or 0.0625 of the ADC full-scale range. The internal pixel correction registers are reset to zero.
pixel shading compensation
This stage is implemented as a digital multiplier which corrects for nonuniform shading using externally supplied 12-bit unsigned values. The external correction factors are supplied at the multiplexed pixel rate. The external correction range is from 0 to 4, which allows shading nonuniformity of up to 75% (i.e., the minimum input signal is 25% of the peak) to be corrected without loss of resolution in the high gain pixels at the center of the scan. Internal default registers are provided to set the gain through this block during calibration. The internal registers default to a value of 1 (equivalent to decimal 1024 in this range) on reset.
global offset adjust
Global offset adjust is provided by an adder using three independent bipolar offset coefficients set through the serial interface. A range of 4 times the ADC full-scale range in steps of a half output LSB is provided. This range allows the output signal to be shifted across the entire range of the 16-bit output bus. The global offset coefficients are programmed as 16-bit 2s complement numbers, which default to zero on reset.
global gain adjust
Global gain adjust is provided by a multiplier using gain values set through the serial interface. Three independent 16-bit gain values with a range of 0 to 2 are stored (one for each channel). The default value of the global gain coefficients is 1 (equivalent to decimal 32768 in this range).
threshold detector
The threshold detector operates on the output signal from the global gain adjust stage, comparing the signal to individual threshold levels for each color channel, which are programmed through the serial interface. If the signal exceeds the threshold, the DETOP terminal is forced high. Two basic modes of operation can be programmed, either multiplexing between the three channels in sequence with the internal data, or operating continuously on one of the three channels. The input signals to the threshold detector are represented as 16-bit bipolar 2s complement numbers. Threshold values should be programmed as 15-bit unipolar numbers in the range 0 to 32767.
effect of image processing on ADC output
The combined effect of the image processing sections on the ADC output is summarized by the formula in the note following Table 4. All values are shown in decimal. Examples of the process are given in Table 4. Examples 1-8 show the results with no pixel offset scaling. Examples 9-11 show the added effect of pixel offset scaling. All examples use a half range ADC value (2048) for the ADC output (ADCOP). If defaults are used throughout, then the output of the ADC is output directly on the OP0-OP11 bus as listed in Table 4, example 1.
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PRINCIPLES OF OPERATION
effect of image processing on ADC output (continued)
In Table 4, example 2 shows how the half range ADCOP value (2048) is affected by adding dc restoration (value 128). This value is added directly to the ADCOP value. All other parameters are default, so this result passes directly to the OP0-OP11 output. Inserting the values in the formula gives: OP0-OP11 = (((2048 + 128 + (0 x 1)) x 1) + (0.5 x 0)) x 1 In Table 4, example 9 shows the effect of internal scaling (POSCL) on the pixel offset compensation (POC). The value 01 on POSCL indicates a scaling factor of 0.5 (refer to Table 5, setup register 2). The POC value of 128 is multiplied by 0.5. The result is added to the ADC output. Defaults have been used on all other stages, so the resulting value of 2048 is directly output on OP0-OP11. Examples 10 and 11 show the effect of different scaling factors. Inserting the values in the formula gives: OP0-OP11 = (((2048 + 0 + (128 x 0.5)) x 1) + (0.5 x 0)) x 1 Table 4. Examples of Image Processing on ADC Output
PARAMETER Range Default Example 1 Example 2 Example 3 Example 4 Example 5 Example 6 Example 7 Example 8 Example 9 Example 10 Example 11 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 ADCOP 0 to 4095 DCREST -2048 to 2047 0 0 128 0 0 -64 0 0 -64 0 0 0 POC -2048 to 2047 0 0 0 -256 0 128 0 0 128 128 128 128 00 00 00 00 00 00 00 00 00 01 10 11 NOTE: POSCL PCS 0 to 4095 1024 1024 1024 1024 512 1536 1024 1024 512 1024 1024 1024 GLOBAL OFFSET -32768 to 32767 0 0 0 0 0 0 1024 0 1024 0 0 0 GLOBAL GAIN 0 to 65536 32768 32768 32768 32768 32768 32768 32768 16384 16384 32768 32768 32768 2048 2176 1792 1024 3168 2560 1024 784 2112 2080 2064 OP0-OP11 0 to 4095
OP0-OP11 = (((ADCOP + DCREST + (POC x POSCL)) x PSC) + (0.5 x Global Offset)) x Global Gain where: ADCOP DCREST POC POSCL PSC Global Offset Global Gain OP0-OP11 12-bit output of the ADC 2s complement 12-bit number source directly from the DC restore registers 2s complement 12-bit number source directly from the POC bus or registers scaling factor as defined in Table 5 setup register 2 12-bit unsigned number sourced from the PSC bus or register and divided by 1024 16-bit 2s complement number sourced directly form the global offset adjust registers 16-bit unsigned number sourced from the global gain register and divided by 32768 12-bit result of the image processing that is output from the device on the bus OP0-OP15
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PRINCIPLES OF OPERATION
output word length select
This block is used to define the output word length, which can be programmed to 8, 10, 12, or 16 bits through the serial interface. An internal clip function is provided that can be used in unipolar or bipolar fashion. For example, if an 8-bit output word length is selected, the output data on OP0 - OP15 is limited to the range 0 to 255 for unipolar clipping or - 128 to 127 for bipolar clipping. If the signal to this block exceeds the positive clip level, the ORNG signal is forced high. In 8-, 10-, and 12-bit output modes, the output data bit OP15 functions as an under range flag; i.e., it is driven high if the input signal is less than the negative clip level. OP15 also functions as an under range signal in 16-bit unipolar clipping mode.
serial interface
The serial interface data is used to configure the device operation and to program internal data registers. Figure 14 shows a timing diagram of a serial write operation. A serial data stream applied to the SDI terminal is clocked into the device on the rising edge of SCK. The data stream comprises 6 address bits and two 8-bit data words. When this data has is shifted into the device, a pulse applied to SEN transfers the data to the appropriate internal register. Tables 5 and 6 define the internal register map for the device and control bit functionality, respectively. The first 4 addresses in Table 5 (address bit a5 = 0) are used to program setup registers and to provide a software reset feature. The remaining eight entries in Table 5 define the address locations of internal data registers, and three additional subaddresses are defined for the red, green, or blue registers. Address bits a1 and a0 select between the red, green, and blue registers, as defined in Table 5. When a1 and a0 are set to 1, all three registers are updated to the same date value, as specified in data words 1 and 2. Blank entries in Table 5 are taken as don't care values.
SCK SDI
a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Address
Data Word 1
Data Word 2
SEN
Figure 14. Serial Interface Timing
system timing
System timing diagrams that relate the timing between taking an input sample, applying the related pixel offset and shading coefficients, and the output of the digital video data are shown in Figures 1 and 2. These diagrams show the overall latency of the device in both color and monochrome operating modes. Detailed digital timing diagrams are shown in Figure 15, 16, and 17.
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II
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PRINCIPLES OF OPERATION
Table 5. Serial Interface Register Map
ADDRESS 000000 000001 000010 000011 1000xx 1001xx 1010xx 1011xx 1100xx 1101xx 1110xx 1111xx DESCRIPTION Setup register 1 Setup register 2 Reserved Software reset DAC values DC restore values Default even pixel offsets Default odd pixel offsets Default pixel gains Global offsets Global gains Threshold values DATA WORD 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 D7 D7 D7 D7 D7 D15(MSB) D7 D15(MSB) D7 D7 D6 D6 D6 D6 D6 D14 D6 D14 D6 D14(MSB) D6 D5 D5 D5 D5 D5 D13 D5 D13 D5 D13 D5 D4 D4 D4 D4 D4 D12 D4 D12 D4 D12 D4 D3 D11(MSB) D3 D11(MSB) D3 D11(MSB) D3 D11(MSB) D3 D11 D3 D11 D3 D11 D3 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 POL D0(LSB) D8 D0(LSB) D8 D0(LSB) D8 D0(LSB) D8 D0(LSB) D8 D0(LSB) D8 D0(LSB) D8 D0(LSB) BIT b7 ENADC POSCL1 b6 BICLIP POSCL0 b5 ADCMX WLSEL1 b4 MONO WLSEL0 b3 DEFPG THSEL1 b2 DEFPO THSEL0 b1 DNS CDSREF1 CHAN1 b0 INVADC CDS CDSREF0 CHAN0
xx a1 0 0 1 1 a0 0 1 0 1
ADDRESS LSB DECODE Red register Green register Blue register Red, green, and blue
DEFAULT PIXEL DECODE Blue register Red register Green register Red, green, and blue
Default address The address decoding is applicable for default pixel gain in monochrome mode.
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PRINCIPLES OF OPERATION
Table 6. Control Bit Descriptions
REGISTER Setup Register 1 BITS ENADC DEFAULT 1 ADC standby control: 0 = standby 1 = active Bipolar clip enable: 0 = unipolar clip 1 = bipolar clip ADC MUX control: 0 = normal operation 1 = ADC output multiplexed to OP Mono/color select: 0 = color operation 1 = monochrome operation Select default pixel gain: 0 = external pixel gain 1 = default (internal) Select default pixel offsets: 0 = external pixel offsets 1 = default (internal) Select differential/single-ended mode: 0 = single ended 1 = differential ADC output polarity: 0 = noninverted 1 = inverted Select correlated double sampling mode: 0 = normal sampling 1 = CDS mode Pixel offset scaling: 00 = 0.5 fs 01 = 0 25 fs 0.25 10 = 0.125 fs 11 = 0.0625 fs Output word length select: 00 = 8 bits (OP0 - OP7 contains output word) 01 = 10 bits (OP0 - OP9 contains output word) 10 = 12 bits (OP0 - OP11 contains output word) 11 = 16 bits (OP0 - OP15 contains output word) Threshold detector operating mode: 00 = Operating on red channel only 01 = Operating on green channel only 10 = Operating on blue channel only 11 = Three channel CDS mode reset timing adjust: 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods Monochrome mode channel select: 00 = Red channel 01 = Green channel 10 = Blue channel 11 = Not used DESCRIPTION
BICLIP
0
ADCMX
0
MONO
0
DEFPG
0
DEFPO
0
DNS
0
INVADC
0
CDS Setup Register 2 POSCL1 0 POSCL1,
0
00
WLSEL1, WLSEL1 0
10
THSEL1, THSEL1 0
11
CDSREF1 0 CDSREF1,
01
CHAN1, CHAN1 0
00
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PRINCIPLES OF OPERATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MCLK VSMP Video Sample R, G, B Input Video
n n+1 n+2
POC11 - POC0 PSC11 - PSC0 ONE
rn - 2 rn - 2
gn - 2 gn - 2 n-2
bn - 2 bn - 2
rn - 1 rn - 1
gn - 1 gn - 1 n-1
bn - 1 bn - 1
OP15 - OP0 CC0
rn - 3
gn - 3
bn - 3
CC1
Pixel Period
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
MCLK VSMP Video Sample R, G, B Input Video
POC11 - POC0 PSC11 - PSC0 ONE
rn rn
gn gn n
bn bn
OP15 - OP0 CC0
rn - 2
CC1
26
IIIII I IIIII I
gn - 2 bn - 2
rn - 1
gn - 1
bn - 1
rn
gn
bn
Figure 15. System Timing - Color Mode
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PRINCIPLES OF OPERATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MCLK VSMP
Video Sample
POC11 - POC0 PSC11 - PSC0 ONE
n -2 n -2 n -2
n -1 n -1 n -1
OP15 - OP0 CC0 CC1
Pixel Period
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
MCLK VSMP
Video Sample
R, G, or B Input Video
POC11 - POC0 PSC11 - PSC0 ONE
n n n
n +1 n +1 n +1
n +2 n +2 n +2
OP15 - OP0 CC0 CC1
n -2
n -1
n
n +1
n +2
The CC(10) output state is defined via the serial bus in monochrome mode.
Figure 16. System Timing - Monochrome Mode
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I I I I
27
II
R, G, or B Input Video
n -2
n -1
n
n +1
n +2
TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 - JUNE 1997
PRINCIPLES OF OPERATION
MCLK
R G 0F B 0F R 0F G 1F B 0F R 1F G 0F B 0F R 0F
OP15-OP0 DETOP in Normal Mode DETOP in Single Channel Mode (Red Channel Selected) DETOP in Single Channel Mode (Green Channel Selected)
0F
1F
NOTE A: All thresholds are set to 10 hex.
Figure 17. Timing of Threshold Detector Output DETOP
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APPLICATION INFORMATION running the TLC8044 at 4-megasamples/sec in CDS monochrome mode
The TLC8044 can be set up to provide a 4-megasample/sec throughput when in CDS monochrome mode; however, the VSMP input must run continuously at 4 MHz. The following paragraphs describe operation of the TLC8044 in monochrome mode (sampling one channel only). The maximum sample rate in color CDS mode is 2-megasamples/channel/sec. In CDS mode, the video signal is sampled both during the reset phase and when video information is present with timing defined to a VSMP input. The difference between these two samples forms the input to the ADC. In monochrome mode, all samples are taken from one input video channel. The device is set up as listed in Table 6. See Tables 4 and 5 for offset DAC values in CDS mode. System timing is shown in Figure 18. MCLK clocks the device at 12 MHz (as normal). VSMP, which controls the sample rate, is run at 4 MHz. A reset sample is taken on the rising edge of MCLK after VSMP is asserted. The corresponding video sample is taken on the next MCLK rising edge. Compensation coefficients (pixel offset and pixel shading) are sampled on the falling edge of MCLK 26.5 periods after the initial reset sample. The processed digital outputs appear on OP0-OP15 41.5 MCLK periods after the initial reset sample. In Figure 18 the system timing diagram shows a negative-going video sample. The polarity of the ADC output signal can be inverted under control of the serial interface. Setup and hold times are specified in the recommended operating conditions table. Table 7. Relevant Register Settings
REGISTER Setup register 1 BITS ENADC BICLIP ADCMX MONO DEFPG DEFPO DNS INVADC CDS Setup register 2 POSCL1,0 WLSEL1,0 THSEL1,0 CDSREF1,0 CHAN1,0 U = User defined VALUE U U 0 1 U U 0 U 1 UU UU UU 00 UU DESCRIPTION ADC standby control Select unipolar clip ADC MUX control Monochrome operation Select default pixel gain Select default pixel offsets Select single-ended mode ADC output polarity Select correlated double sampling mode Pixel offset scaling Select 12-bit output word Three channel Advance one MCLK period Select channel to be sampled
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TLC8044 12-BIT ANALOG-TO-DIGITAL INTERFACE FOR CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS SLAS128 - JUNE 1997
30
n n+1
MCLK
VSMP
Reset Sample
Video Sample
n-1
2.64 MCLK From Reset Sample
POC(11-0)
n-1 n-1 n-1 n n+1 n n+1 n n+1
PSC(11-0)
ONE
Template Release Date: 7-11-94
41.5 MCLK From Reset Sample
n-1 n
OP(15-0)
CC(0)
CC(1) Pixel Period
CC(1,0) Output state defined via serial bus in monochrome mode
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Figure 18. System Timing - CDS Mode at 4-Megasamples/Sec
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