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SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERS
SDAS234 - D2661, DECEMBER 1982 - REVISED AUGUST 1985
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Package Options Include Plastic Small Outline Packages, Both Plastic and Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Buffered 3-State Outputs Drive Bus Lines Directly Cascaded to n-Bits Eight Selectable Transceiver/Port Functions: A to B or B to A Register to A or Register to B Shifted to A or Shifted to B Off-Line Shifts (A and B Ports in High-Impedance State) Register Clear Particularly Suitable for Use in Signature Analysis Circuitry Serial Register Provides: Parallel Storage of Either A or B Input Data Serial Transmission of Data from Either A or B Port Dependable Texas Instruments Quality and Reliability
SN54AS877 . . . JT PACKAGE SN74AS877 . . . DW OR NT PACKAGE (TOP VIEW)
S0 S1 S2 A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC CLK SERIN B1 B2 B3 B4 B5 B6 B7 B8 Q8
SN54AS877 . . . JT PACKAGE SN74AS877 . . . DW OR NT PACKAGE (TOP VIEW)
S2 S1 S0 NC VCC CLK SERIN A1 A2 A3 NC A4 A5 A6
5 6 7 8 4 3 2 1 28 27 26 25 24 23 22
description
9 21 The 'AS877 features two 8-bit I/O ports (A1-A8 10 and B1-B8), an 8-bit parallel-load, serial-in, 20 parallel-out shift register, and control logic. With 11 19 12 13 14 15 16 17 18 these features, this device is capable of performing eight selectable transceiver or port functions, depending on the state of the three select lines S0, S1, and S2. These functions NC - No internal connection include: transferring data from port A to port B or vice versa (i.e., the transceiver function), transferring data from the register to either port, serial shifting data to either port, performing off-line shifts (with A and B ports in high-impedance state), and clearing the register. Synchronous parallel loading of the internal register can be accomplished from either port on the positive transition of the clock while serially shifting data in via the SERIN input. The 'AS877 is ideally suited for applications needing signature-analysis circuitry to enhance system verification and/or fault analysis. All serial data is shifted right. All outputs are buffer-type outputs designed specifically to drive bus lines directly and all are 3-state except for Q8, which is a totem-pole output.
B1 B2 B3 NC B4 B5 B6
The SN54AS877 is characterized for operation over the full military temperature range of - 55C to 125C. The SN74AS877 is characterized for operation from 0C to 70C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
A7 A8 GND NC Q8 B8 B7
Copyright (c) 1985, Texas Instruments Incorporated
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SDAS234 - D2661, DECEMBER 1982 - REVISED AUGUST 1985
SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANSCEIVER PORT CONTROLLERS
FUNCTION TABLE
MODE CLOCK S2 L L L L L L L L H H H S1 L L L L H H H H L L L L L L H H H H H S0 L L H H L L H H L L L H H H L L L H H H or L H or L H or L H or L H or L H or L H or L H or L X X X X X X X X X H L X H L X H L X H Z Z B1 B1 X Z Q1 B1 Z Z Z Q1 H L Z Z Z Z Z Qn A1 Qn B1 Qn A1 Qn B1 Qn H L Qn H L Qn H L Qn H A1 A1 Z Z Q1 A1 X Z Q1 H L Z Z Z Z Z Z Z Z Z Z B2 B2 X Z Q2 B2 Z Z Z Q2 Q1 Q1 Z Z Z Z Z Qn A2 Qn B2 Qn A2 Qn B2 Qn Q1 Q1 Qn Q1 Q1 Qn Q1 Q1 Qn L A2 A2 Z Z Q2 A2 X Z Q2 Q1 Q1 Z Z Z Z Z Z Z Z Z Z B3 B3 X Z Q3 B3 Q3 Q2 Q2 Q3 Q2 Q2 Z Z Z Z Z Qn A3 Qn B3 Qn A3 Qn B3 Qn Q2 Q2 Qn Q2 Q2 Qn Q2 Q2 Qn L A3 A3 Z Z Q3 A3 Z Z Q3 Q2 Q2 Z Z Z Z Z Z Z Z Z Z B4 B4 X Z Q4 B4 Z Z Z Q4 Q3 Q3 Z Z Z Z Z Qn A4 Qn B4 Qn A4 Qn B4 Qn Q3 Q3 Qn Q3 Q3 Qn Q3 Q3 Qn L Q4 Q4 Z Z Q4 A4 Z Z Q4 Q3 Q3 Z Z Z Q4 Q3 Q3 Z Z Z Z B5 B5 X Z Q5 B5 Z Z Z Q5 Q4 Q4 Z Z Z Z Z Qn Q5 Qn B5 Qn A5 Qn B5 Qn Q4 Q4 Qn Q4 Q4 Qn Q4 Q4 Qn L A5 A5 Z Z Q5 A5 X Z Q5 Q4 Q4 Z Z Z Z Z Z Z Z Z Z B6 B6 X Z Q6 B6 Z Z Z Q6 Q5 Q5 Z Z Z Z Z Qn A6 Qn B6 Qn A6 Qn B6 Qn Q5 Q5 Qn Q5 Q5 Qn Q5 Q5 Qn L Q6 Q6 Z Z Q6 A6 Z Z Q6 Q5 Q5 Z Z Z Q6 Q5 Q5 Z Z Z Z B7 B7 X Z Q7 B7 Z Z Z Q7 Q6 Q6 Z Z Z Z Z Qn A7 Qn B7 Qn A7 Qn B7 Qn Q6 Q6 Qn Q6 Q6 Qn Q6 Q6 Qn L Q7 Q7 Z Z Q7 A7 Z Z Q7 Q6 Q6 Z Z Z Q7 Q6 Q6 Z Z Z Z B8 B8 X Z Q8 B8 Z Z Z Q8 Q7 Q7 Z Z Z Z Z Qn A8 Qn B8 Qn A8 Qn B8 Qn Q7 Q7 Qn Q7 Q7 Qn Q7 Q7 Qn L A8 A To B A8 Z B To A Z Q8 A8 X Z Q8 Q7 Q7 Z Z Z Z Z Z Z Clear Z Shift QN To AN Shift To B Shift To A QN To BN SERIN A1 Q1 B1 A2 Q2 B2 A3 Q3 B3 A4 Q4 B4 A5 Q5 B5 A6 Q6 B6 A7 Q7 B7 A8 Q8 B8 PORT FUNCTION
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POST OFFICE BOX 1443 * HOUSTON, TEXAS 77001 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 H H H H H H H H
n = level Of Qn(n = 1, 2 . . . 8) established on most recent transition of CLK. Q1 thru Q8 are the shift register outputs; only Q8 is available externally. The double inversions that take place as data travels from port to port are ignored in this table.
SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANCEIVER PORT CONTROLLERS
SDAS234 - D2661, DECEMBER 1982 - REVISED AUGUST 1985
logic symbol
1 S0 2 S1 3 S2 23 CLK 22 SERIN 4 A1 (PORT CONTROLLER) 0 2 Z9 1 11 12 (1/3/5) 13,1 13 14,(3/5) 1 Z15 15 (1/3/5) 16 16,1 17(3/5) Z11 Z12 0 EN 7 9 9 SRG8 (4/5/6) C10/7R I=0 (4/5/6)10D (0/2)10D 12 (1/3)10D I=0 (0/2)10D 15 (1/3)10D 1 (0/2/4) 0 Z13 2/4 Z14 1 (0/2/4) 0 Z16 2/4 Z17 21 B1
A2
5
20
B2
A3 A4 A5 A6 A7 A8
6 7 8 9 10 11
19 18 17 16 15 14 13
B3 B4 B5 B6 B7 B8 Q8
1 33 (1/3/5) 34,1 34 35(3/5) Z33
I=0 (0/2)10D 33 (1/3)10D
1 (0/2/4) Z34 0 35 2/4 Z35
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for DW, JT, and NT packages.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
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SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANCEIVER PORT CONTROLLERS
SDAS234 - D2661, DECEMBER 1982 - REVISED AUGUST 1985
FAMILY NAME
logic diagram (positive logic)
S0 1
S1
2
S2
3
CLK SERIN
23 22
A1
4
I=1 1D C1
21
B1
A2
5
I=1 1D C1
20
B2
Four Identical Channels Not Shown: Inputs/Outputs Not Shown: 6 A3 19 B3 7 A4 18 B4 8 A5 17 B5 9 A6 16 B6
A7
10
I=1 1D C1
15
B7
A8
11
I=1 1D C1
14
B8
13 Pin numbers shown are for DW, JT, and NT packages.
Q8
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
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SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANCEIVER PORT CONTROLLERS
SDAS234 - D2661, DECEMBER 1982 - REVISED AUGUST 1985
absolute maximum ratings over free-air temperature range
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage: All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range: SN54AS877 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C SN74AS877 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
recommended operating conditions
SN54AS877 MIN VCC VIH VIL IOH IOL fclock tw tsu Supply voltage High-level input voltage Low-level input voltage High-level High level input voltage Low-level input voltage Clock frequency Pulse duration, CLK A1-A8, B1-B8 Setup time before CLK SERIN S0, S1, S2 A1-A8, B1-B8 th TA Hold time, data after CLK Operating free-air temperature SERIN S0, S1, S2 A1-A8, B1-B8 Q8 A1-A8, B1-B8 Q8 0 11 5.5 55 5.5 0 0 - 55 125 4.5 2 0.8 - 12 -2 32 20 45 0 10 5.5 55 5.5 0 0 0 70 C ns NOM 5 MAX 5.5 SN74AS877 MIN 4.5 2 0.8 - 15 -2 48 20 50 MHz ns ns NOM 5 MAX 5.5 UNIT V V V mA mA
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
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SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANCEIVER PORT CONTROLLERS
SDAS234 - D2661, DECEMBER 1982 - REVISED AUGUST 1985
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK A1-A8 VOH B1-B8 All outputs All outputs VOL except Q8 Q8 S0, S1, S2 II CLK and SERIN A1-A8, B1-B8 S0, S1, S2 IIH CLK and SERIN A1-A8, B1-B8 S0, S1, S2 IIL CLK and SERIN A1-A8, B1-B8 IO Except Q8 Q8 VCC = 5 5 V 5.5 V, VO = 2.25 V 2 25 - 30 - 20 VCC = 5.5 V, VI = 0.4 V VCC = 5.5 V, VI = 2.7 V TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5 5 V 5.5 V, VCC = 5.5 V, II = - 18 mA IOH = - 12 mA IOH = - 15 mA IOH = - 2 mA IOL = 32 mA IOL = 48 mA IOL = 20 mA VI = 7 V VI = 5.5 V MIN 2 VCC - 2 0.25 0.25 0.5 0.35 0.5 0.3 0.1 0.2 60 20 70 -1 - 0.5 - 0.75 - 112 - 112 - 30 - 20 0.25 0.5 0.5 0.3 0.1 0.2 60 20 70 -1 - 0.5 - 0.75 - 112 - 112 mA mA A mA V SN54AS877 TYP MAX - 1.2 3.2 2 VCC - 2 3.3 V MIN SN74AS877 TYP MAX - 1.2 UNIT V
ICC VCC = 5.5 V 136 220 136 220 mA All typical values are at VCC = 5 V, TA = 25C. For I/O ports, the parameters IIH and IIL include the output currents IOZH and IOZL, respectively. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
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SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANCEIVER PORT CONTROLLERS
SDAS234 - D2661, DECEMBER 1982 - REVISED AUGUST 1985
switching characteristics (see Note 1)
VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 , PARAMETER FROM (INPUT) TO (OUTPUT) R2 = 500 , TA = MIN to MAX SN54AS877 SN74AS877 MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHZ tPLZ tPZH 45 Any A port Any B port S0 S1 S2 S0, S1, CLk CLK Any B port Any A port Any A or B port Any A or B port QB 2 3 2 3 2 3 2 3 2 3 2 S0, S1, S0 S1 S2 Any A or B y port 3 2 8.5 10.5 9 10.5 11.5 9.5 11 13 10.5 10 7.5 13 9 MAX MIN 50 2 3 2 3 2 3 2 3 2 3 2 3 2 7 9 7.5 9 10 8 9 11.5 8 8.5 6.5 10.5 7 9.5 MAX MHz ns ns ns ns ns ns ns UNIT
tPZL 3 11.5 3 NOTE 1: Load circuit and voltage waveforms are shown in Section 1. The positive transition of S2 will cause low-level data at the A output Bus or stored in the shift register to be invalid for 12 ns.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
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SN54AS877, SN74AS877 8-BIT UNIVERSAL TRANCEIVER PORT CONTROLLERS
SDAS234 - D2661, DECEMBER 1982 - REVISED AUGUST 1985
TYPICAL APPLICATION DATA
BUS A TO BUS B OR SERIAL TRANSMISSION Serial In CLK SERIN REG Serial In CLK SERIN REG BUS B TO BUS A OR SERIAL TRANSMISSION
A
B
A
B
Q8
Q8
SERIN REG
SERIN REG
A
B
A
B
Q8
Q8
Serial Out
Serial Out
SERIAL IN TO A PORT Serial In CLK SERIN REG Serial In CLK
SERIAL IN TO B PORT
SERIN REG
A
B Hi-Z
Hi-Z A
B
Q8
Q8
Serial Out
Serial Out
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
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Copyright (c) 1998, Texas Instruments Incorporated

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