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SN54AS821, SN54AS822, SN74AS821, SN74AS822 10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 - D2825, DECEMBER 1983 - REVISED JANUARY 1986
* * * * * * *
Functionally Equivalent to AMD's AM29821 and AM29822 Provides Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Outputs Have Undershoot Protection Circuitry Powerup High-impedance State Package Options Include Plastic Small Outline Packages, Both Plastic and Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Buffered Control Inputs to Reduce DC Loading Effects Dependable Texas Instruments Quality and Reliability
SN54AS821 . . . JT PACKAGE SN74AS821 . . . DW OR NT PACKAGE (TOP VIEW)
OC 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q VCC
description
These 10-bit flip-flops feature 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock the Q outputs on the 'AS821 will be true, and on the 'AS822 will be complementary to the data input. A buffered output-control input can be used to place the ten outputs in either a normal logic state (high or low levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pullup components. The output control (OC) does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AS' family is characterized for operation over the full military temperature range of - 55C to 125C. The SN74AS' family is characterized for operation from 0C to 70C.
SN54AS821 . . . FK PACKAGE SN74AS821 . . . FN PACKAGE (TOP VIEW) SN54AS822 . . . JT PACKAGE SN74AS822 . . . DW OR NT PACKAGE (TOP VIEW) SN54AS822 . . . FK PACKAGE SN74AS822 . . . FN PACKAGE (TOP VIEW)
2D 1D OC NC VCC 1Q 2Q
3D 4D 5D NC 6D 7D 8D
5 6 7 8 9 10
4
3 2 1 28 27 26
25 24 23 22 21 20
11 19 12 13 14 15 16 17 18
3Q 4Q 5Q NC 6Q 7Q 8Q
9D 10D GND NC CLK 10Q 9Q
12
13
NC-No internal connection
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1986, Texas Instruments Incorporated 5BASIC
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9D 10D GND NC CLK 10Q 9Q
OC 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND
1 2 3 4 5 6 7 8 9 10 11
24 23 22 21 20 19 18 17 16 15 14
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q CLK
2D 1D OC NC VCC 1Q 2Q 3D 4D 5D NC 6D 7D 8D
5 6 7 8 9 10 4 3 2 1 28 27 26 25 24 23 22 21 20 11 19 12 13 14 15 16 17 18
3Q 4Q 5Q NC 6Q 7Q 8Q
1
SN54AS821, SN74AS821 10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 - D2825, DECEMBER 1983 - REVISED JANUARY 1986
'AS821 FUNCTION TABLE (each flip-flop) INPUTS OC L L L H CLK L X D H L X X OUTPUT Q H L Q0 Z
'AS821 logic diagram (positive logic)
1
OC
CLK 1D
13 C1 2 1D 23 1Q
'AS821 logic symbol
2D 1 OC 13 CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 2 3 4 5 6 7 8 9 10 11 EN C1 1D 23 22 21 20 19 18 17 16 15 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q 3D
C1 3 1D C1 4 1D C1 4D 5 1D C1 5D 6 1D C1 6D 7 1D C1 7D 8 1D
22
2Q
21
3Q
20
4Q
19
5Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
18
6Q
17
7Q
C1 8D 9 1D C1 9D 10 1D C1 10D 11 1D
16
8Q
15
9Q
14
10Q
Pin numbers shown are for DW, JT, and NT packages.
2
POST OFFICE BOX 655303
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SN54AS822, SN74AS822 10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 - D2825, DECEMBER 1983 - REVISED JANUARY 1986
'AS822 FUNCTION TABLE (each flip-flop) INPUTS OC L L L H CLK L X D H L X X OUTPUT Q H L Q0 Z
'AS822 logic diagram positive logic
1
OC
CLK 1D
13 C1 2 1D 23 1Q
'AS822 logic symbol
1 OC 13 CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 2 3 4 5 6 7 8 9 10 11 2D EN C1 1D 23 22 21 20 19 18 17 16 15 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q 3D 4 3
C1 1D C1 1D C1 4D 5 1D C1 5D 6 1D C1 6D 7 1D C1 7D 8 1D
22
2Q
21
3Q
20
4Q
19
5Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
18
6Q
17
7Q
C1 8D 9 1D C1 9D 10 1D C1 10D 11 1D
16
8Q
15
9Q
14
10Q
Pin numbers shown are for DW, JT, and NT packages.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54AS821, SN54AS822, SN74AS821, SN74AS822 10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 - D2825, DECEMBER 1983 - REVISED JANUARY 1986
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range: SN54AS821, SN54AS822 . . . . . . . . . . . . . . . . . . . . . - 55C to 125C SN74AS821, SN74AS822 . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
recommended operating conditions
SN54AS821 SN54AS822 MIN VCC VIH VIL IOH IOL tw tsu th TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Pulse duration, CLK high or low Setup time, data before CLK Hold time, data after CLK Operating free-air temperature 9 7 0 -55 125 4.5 2 0.8 - 24 32 8 6 0 0 70 NOM 5 MAX 5.5 SN74AS821 SN74AS822 MIN 4.5 2 0.8 - 24 48 NOM 5 MAX 5.5 V V V mA mA ns ns ns C UNIT
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54AS821 PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, 'AS821 ICC 'AS822 VCC = 5 5 V 5.5 II = - 18 mA IOH = - 2 mA IOH = - 15 mA IOH = - 24 mA IOL = 32 mA IOL = 48 mA VO = 2. 7 V VO = 0.4 V VI = 7 V VI = 2.7 V VI = 0 .4 V VO= 2.25 V Outputs high Outputs low Outputs disabled Outputs high Outputs low Outputs disabled - 30 55 68 70 55 68 70 SN54AS822 MIN TYP MAX - 1.2 VCC - 2 2.4 2 0.25 0.5 0.35 50 - 50 0.1 20 - 0.5 - 112 88 109 113 88 109 113 - 30 55 68 70 55 68 70 0.5 50 - 50 0.1 20 - 0.5 - 112 88 109 113 88 109 mA 3.2 VCC - 2 2.4 2 V A A mA A mA mA 3.2 SN74AS821 MIN SN74AS822 TYP MAX - 1.2 UNIT V V
VOL IOZH IOZL II IIH IIL IO
113 All typical values are at VCC = 5 V, TA = 25C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
4
POST OFFICE BOX 655303
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SN54AS821, SN54AS822, SN74AS821, SN74AS822 10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SDAS230 - D2825, DECEMBER 1983 - REVISED JANUARY 1986
switching characteristics (see Note 1)
VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 , PARAMETER FROM (INPUT) TO (OUTPUT) R2 = 500 , TA = MIN to MAX SN54AS821 SN74AS821 SN54AS822 SN74AS822 MIN tPLH tPHL tPZH tPZL tPHZ tPZL CLK OC OC Any Q Any Q Any Q 3.5 3.5 4 4 2 2 MAX 9 11.5 12 13 10 10 MIN 3.5 3.5 4 4 2 2 MAX 7.5 10.5 11 12 8 8 ns ns ns UNIT
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
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Copyright (c) 1998, Texas Instruments Incorporated

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