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SN54ALS193, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR
SDAS211B - DECEMBER 1982 - REVISED DECEMBER 1994
* * * * *
Look-Ahead Circuitry Enhances Cascaded Counters Fully Synchronous in Count Modes Parallel Asynchronous Load for Modulo-N Count Lengths Asynchronous Clear Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN54ALS193 . . . J PACKAGE SN74ALS193A . . . D OR N PACKAGE (TOP VIEW)
B QB QA DOWN UP QC QD GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC A CLR BO CO LOAD C D
description
The SN54ALS193 and SN74ALS193A are synchronous, reversible, 4-bit up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count/clock (UP or DOWN) input. The direction of the count is determined by which count input is pulsed while the other count input is high.
SN54ALS193 . . . FK PACKAGE (TOP VIEW)
QA DOWN NC UP QC
3 4 5 6 7 8
QB B NC VCC A
2 1 20 19 18 17 16 15 14 9 10 11 12 13
CLR BO NC CO LOAD
NC - No internal connection
All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent of the count and LOAD inputs. The UP, DOWN, and LOAD inputs are buffered to lower the drive requirement, which significantly reduces the loading on, or current required by, clock drivers, etc., for long parallel words. These counters are designed to be cascaded without the need for external circuitry. The borrow (BO) output produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the carry (CO) output produces a low-level pulse while the count is 9 or 15 (all Q outputs high) and the UP input is low. The counters can then be easily cascaded by feeding BO and CO to the count-down and count-up inputs, respectively, of the succeeding counter. The SN54ALS193 is characterized for operation over the full military temperature range of - 55C to 125C. The SN74ALS193A is characterized for operation from 0C to 70C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1994, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
QD GND NC D C
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SN54ALS193, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR
SDAS211B - DECEMBER 1982 - REVISED DECEMBER 1994
logic symbol
14 5 4 11 15 1 10 9 CTRDIV16 CT = 0 2+ G1 1- G2 C3 3D [1] [2] [4] [8] 3 2 6 7 QA QB QC QD 1CT = 15
CLR UP DOWN LOAD A B C D
12
CO
2CT = 0
13
BO
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ALS193, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR
SDAS211B - DECEMBER 1982 - REVISED DECEMBER 1994
logic diagram (positive logic)
CLR 14 12 CO
LOAD
11
13
BO
UP DOWN
5 4 S 15 R S C1 1D R 3
A
QA
B
1 S C1 1D R 2 QB
C
10 S C1 1D R 6 QC
D
9 S C1 1D R
7
QD
Pin numbers shown are for the D, J, and N packages.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54ALS193, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR
SDAS211B - DECEMBER 1982 - REVISED DECEMBER 1994
typical clear, load, and count sequence
Illustrated below is the following sequence: 1. Clear outputs to zero 2. Load (preset) to binary 13 3. Count up to 14, 15 (carry), 0, 1, and 2 4. Count down to 1, 0 (borrow), 15, 14, and 13
CLR LOAD A B C D UP DOWN QA QB QC QD CO BO 0 Sequence Illustrated Clear Preset 13 14 15 0 Count Up 1 2 1 15 14 0 Count Down 13
Data Inputs
Data Outputs
NOTES: A. Clear overrides load, data, and count inputs. B. When counting up, count-down input must be high; when counting down, count-up input must be high.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ALS193, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR
SDAS211B - DECEMBER 1982 - REVISED DECEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS193 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C SN74ALS193A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS193 MIN VCC VIH VIL IOH IOL fclock tw Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Clock frequency CLR high Pulse duration LOAD low UP or DOWN high or low Data before LOAD tsu Setup time CLR inactive before UP or DOWN LOAD inactive before UP or DOWN Data after LOAD th TA Hold time UP high after DOWN DOWN high after UP Operating free-air temperature 0 10 25 30 25 20 20 5 0 0 - 55 125 4.5 2 0.7 - 0.4 4 20 0 10 20 16.5 20 20 20 5 0 0 0 70 C ns ns ns NOM 5 MAX 5.5 SN74ALS193A MIN 4.5 2 0.8 - 0.4 8 30 NOM 5 MAX 5.5 UNIT V V V mA mA MHz
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IIH IIL UP or DOWN All others TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4 5 V 4.5 VCC = 5.5 V, VCC = 5.5 V, VCC = 5 5 V 5.5 V, II = - 18 mA IOH = - 0.4 mA IOL = 4 mA IOL = 8 mA VI = 7 V VI = 2.7 V VI = 0 4 V 0.4 SN54ALS193 MIN TYP MAX - 1.5 VCC - 2 0.25 0.4 0.1 20 - 0.2 - 0.1 VCC - 2 0.25 0.35 0.35 0.4 0.5 0.1 20 - 0.2 - 0.1 SN74ALS193A MIN TYP MAX - 1.5 UNIT V V V mA A mA
IO VCC = 5.5 V, VO = 2.25 V - 20 - 112 - 30 - 112 mA ICC VCC = 5.5 V, See Note 1 12 22 12 22 mA All typical values are at VCC = 5 V, TA = 25C. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with the clear and load inputs grounded and all other inputs at 4.5 V.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN54ALS193, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR
SDAS211B - DECEMBER 1982 - REVISED DECEMBER 1994
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = R2 = 500 , TA = MIN to MAX SN54ALS193 SN74ALS193A MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL 25 UP DOWN UP or DOWN 3 CO BO Any Q Any Q 3 4 5 4 4 8 8 20 21 20 22 27 23 38 37 MAX MIN 30 3 5 4 5 3 4 7 8 5 16 18 16 18 19 17 30 28 17 MAX MHz ns ns ns ns ns
PARAMETER
FROM (INPUT)
TO (OUTPUT)
UNIT
LOAD
CLR Any Q 5 20 For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54ALS193, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR
SDAS211B - DECEMBER 1982 - REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V VCC S1 RL From Output Under Test CL (see Note A) RL Test Point R1 From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) R2 Test Point RL = R1 = R2
LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR 3-STATE OUTPUTS
Timing Input tsu Data Input 1.3 V
3.5 V 1.3 V 0.3 V th 3.5 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
High-Level Pulse
3.5 V 1.3 V tw 1.3 V 0.3 V
Low-Level Pulse
3.5 V 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS
Output Control (low-level enabling) tPZL Waveform 1 S1 Closed (see Note B)
3.5 V 1.3 V 1.3 V 0.3 V tPLZ 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V 3.5 V Input tPLH In-Phase Output 1.3 V 1.3 V 1.3 V 0.3 V tPHL VOH 1.3 V VOL tPLH VOH 1.3 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V VOL
[3.5 V
tPHZ tPZH Waveform 2 S1 Open (see Note B)
tPHL Out-of-Phase Output (see Note C)
[0 V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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