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8-Bit Microcontroller ROMLESS
SDA 30C163-2
Preliminary Data
CMOS IC
1 - - - - -
Features On-chip oscillator and clock circuits Binary or decimal arithmetic Signed-overflow detection and parity computation Integrated Boolean processor for control applications Full depth stack for subroutine return linkage and data storage - Two priority level, nested interrupt structure - 16-MHz oscillator frequency, 0.75 s instruction cycle - 8 data pointer registers
q SAB 8051 Architecture
P-LCC-68
q Serial Interface
- Full duplex UART-interface
q On-Chip RAM
- Direct byte and bit addressability - Four register banks - 256 bytes of data memory, including 128 user-defined software flags - 1024 bytes of data memory accessible with MOVX-instructions
q External Program Memory Interface
- 512 Kbytes of program memory may be addressed by a 8-bit data bus and a 16 + 3-bit address bus - Extension stack depth 32 byte
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05.94
SDA 30C163-2
q 34 Bidirectional I/O-Lines
- - - -
Two 8-bit ports, one comprising up to eight programmable D/A-outputs One 8-bit multifunction port One 8-bit port with open drain output One 2-bit port with optional memory extension function
q Pulse Width Modulation Unit
- Up to eight programmable PWM-output channels for low cost digital-to-analog conversion
q Timers
- Two 16-bit general purpose timers/event counters - Watchdog timer
q Analog-to-Digital Converter
- Four multiplexed input channels to 8-bit resolution
Type SDA 30C163-2
Ordering Code Q????-????
Package P-LCC-68 (SMD)
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Pin Configuration (top view)
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1.1
Pin Definitions and Functions Symbol Input (I) Output (O) Supply (S) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function
Pin No.
23 22 21 20 19 18 17 16 29 30 31 32 33 34 35 36 48 49 50 51 52 53 54 55 37 38 39 40 41 42 43 44
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
Port 0 is an 8-bit open drain bidirectional I/O-port. Port 0 pins that have 1 s written to them float; in this state they can be used as high-impedance inputs.
Port 1 is an 8-bit bidirectional I/O-port with internal pullup resistors. Port 1 pins that have 1 s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. These eight bits also contain the output channels of the pulse width modulation unit. The secondary functions are assigned to the pins of port 1 as follows: PWMi (P1.i): output of PWM-channel i (i = 0, ..., 7). Port 2 is a multifunction port with P2.0 - P2.3 working as digital or analog inputs. Port bits P2.4 - P2.7 are bidirectional I/O-lines with internal pullup resistors.
Port 3 is an 8-bit bidirectional I/O-port with internal pullup resistors. Port 3 pins that have 1 s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. It also contains the interrupt, timer and serial port pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: - - - - - - INT0 (P3.2) INT1 (P3.3) T0 (P3.4) T1 (P3.5) RxD (P3.6) TxD (P3.7) : interrupt 0 input/timer 0 gate control input : interrupt 1 input/timer 1 gate control input : counter 0 input : counter 1 input : serial port receive line : serial port transmit line.
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Pin Definitions and Functions (cont'd) Pin No. Symbol Input (I) Output (O) Supply (S) I/O I/O O Function
46 47 27
P4.0 P4.1 XTAL2
Alternative outputs for port 2 quasi-bidirectional I/O or address bits A17/A18 for memory extension. Output of the inverting oscillator amplifier. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left open. Input to the inverting oscillator amplifier. A low level on this pin resets the processor. Power supply voltage Ground (0 V) Analog reference voltage Analog ground Program Store Enable Address Latch Enable Address bus for external memory
26 28 24 25 6 4 5 45 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 7 15 14 13 12 11 10 9 8
XTAL1 RST
I I S S S S
VDD VSS VAREF VAGND
PSEN ALE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7
Data bus for external memory
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Figure 1 Block Diagram Semiconductor Group 12
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2 2.1
Functional Description Architecture
The CPU manipulates operands in three memory spaces. These are the program memory (512 Kbyte) and (256 + 1024) byte internal data memory spaces. The program memory address space is provided to accommodate relocatable code. The internal data memory address space is further divided into the 256-byte internal data RAM, 1024 bytes XRAM and the 128-byte Special Function Register (SFR) address spaces. Four register banks (each bank has eight registers),128 addressable bits, and the stack reside in the internal data RAM. The stack depth is limited only by the available internal data RAM. Its location is determined by the 8-bit stack pointer. All registers except the program counter and the four 8-register banks reside in the special function register address space. These memory mapped registers include arithmetic registers, pointers, I/O-ports, registers for the interrupt system, timers, pulse width modulator and serial channel. Many locations in the SFR-address space are addressable as bits. Note that reading from unused locations in internal data memory will yield undefined data. Conditional branches are performed relative to the program counter. The register-indirect jump permits branching relative to a 16-bit base register with an offset provided by an 8-bit index register. Sixteen-bit jumps and calls permit branching to any location within one 64 K block of the 512 K program memory address space. There are five methods for addressing source operands: register, direct, register-indirect, immediate, and base-register plus index-register indirect addressing. The first three methods can be used for addressing destination operands. Most instructions have a "destination, source" field that specifies the data type, addressing methods and operands involved. For operations other than moves, the destination operand is also a source operand. Registers in the four 8-register banks can be accessed through register, direct, or register-indirect addressing; the lower 128 bytes of internal data RAM through direct or register-indirect addressing, the upper 128 bytes of internal data RAM through register-indirect addressing; and the special function registers through direct addressing. Look-up tables resident in program memory can be accessed through base-register plus index-register indirect addressing. 2.1.1 CPU-Hardware Instruction Decoder Each program instruction is decoded by the instruction decoder. This unit generates the internal signals that control the functions of each unit within the CPU-section. These signals control the sources and destination of data, as well as the function of the Arithmetic/Logic Unit (ALU). Program Control Section The program control section controls the sequence in which the instructions stored in program memory are executed. The conditional branch logic enables conditions internal and external to the processor to cause a change in the sequence of program execution. The 16-bit program counter holds the address of the instruction to be executed. It is manipulated with the control transfer instructions listed in chapter "Instruction Set". Semiconductor Group 13
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Internal Data RAM The internal data RAM provides a 256-byte scratch pad memory, which includes four register banks and 128 direct addressable software flags. Each register bank contains registers R0 - R7. The addressable flags are located in the 16-byte locations starting at byte address 32 and ending with byte location 47 of the RAM-address space. In addition to this standard internal data RAM the processor contains additional 1024 bytes internal RAM. It can be considered as a part of an external data memory. It is located at addresses 63488 to 64511 of the external data memory address space and is referenced by MOVX-instructions (MOVX A, @DPTR). Arithmetic/Logic Unit (ALU) The arithmetic section of the processor performs many data manipulation functions and includes the Arithmetic/Logic Unit (ALU) and the A, B and PSW-registers. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations of add, subtract, multiply, divide, increment, decrement, BCD-decimal-add-adjust and compare, and the logic operations of and, or, exclusiveor, complement and rotate (right, left, or nibble swap). The A-register is the accumulator, the B-register is dedicated during multiply and divide and serves as both a source and a destination. During all other operations the B-register is simply another location of the special function register space and may be used for any purpose. Boolean Processor The Boolean processor is an integral part of the processor architecture. It is an independent bit processor with its own instruction set, its own accumulator (the carry flag) and its own bitaddressable RAM and l/O. The bit manipulation instructions allow the direct addressing of 128 bits within the internal data RAM and several bits within the special function registers. The special function registers which have addresses exactly divisible by eight contain directly addressable bits. The Boolean processor can perform, on any addressable bit, the bit operations of set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set then-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag it can perform the bit operation of logical AND or logical OR with the result returned to the carry flag.
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Program Status Word Register (PSW) The PSW-flags record processor status information and control the operation of the processor. The carry (CY), auxiliary carry (AC), two user flags (F0 and F1), register bank select (RS0 and RS1), overflow (OV) and parity (P) flags reside in the program status word register. These flags are bitmemory-mapped within the byte-memory-mapped PSW. The CY, AC, and OV flags generally reflect the status of the latest arithmetic operations. The CY-flag is also the Boolean accumulator for bit operations. The P-flag always reflects the parity of the A-register. F0 and F1 are general purpose flags which are pushed onto the stack as part of a PSW-save. The two register bank select bits (RS1 and RS0) determine which one of the four register banks is selected as follows:
RS1 0 0 1 1
RS0 0 1 0 1
Register Bank 0 1 2 3
Register Location 00H - 07H 08H - 0FH 10H - 17H 18H - 1FH
Program Status Word (MSB) CY AC
PSW
SFR-Address D0H (LSB)
F0
RS1
RS0
OV
F1
P
Stack Pointer (SP) The 8-bit stack pointer contains the address at which the last byte was pushed onto the stack. This is also the address of the next byte that will be popped. The SP is incremented during a push. SP can be read or written to under software control. The stack may be located anywhere within the internal data RAM address space and may be as large as 256 bytes. Data Pointer Register (DPTR) The 16-bit Data Pointer Register DPTR is the concatenation of registers DPH (high-order byte) and DPL (low-order byte). The DPTR is used in register-indirect addressing to move program memory constants and to access the extended data memory. DPTR may be manipulated as one 16-bit register or as two independent 8-bit registers DPL and DPH. Eight data pointer registers are available, the active one is selected by a special function register (DPSEL).
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Port 0, Port 1, Port 2, Port 3, Port 4 The five ports provide 34 I/O-lines to interface to the external world. All five ports are both byte and bit addressable. Port 0 and port 2.4 - 2.7 are used for binary l/O only. Port 1 provides eight PWMoutput channels as alternate functions while port 2.0 - 2.3 are digital or analog inputs. Port 3 contains special control signals. Port 4 will usually be selected as memory extension interface. Interrupt Logic Controlled by two special function registers (IE, IP) the interrupt logic provides several interrupt vectors. Each of them may be assigned to high or low priority (see chapter "Interrupt System"). Timer/Counter 0/1 Two general purpose 16-bit timers/counters are controlled by the special function registers TMOD and TCON (see chapter "General Purpose Timers/Counters"). Serial Interface A full duplex serial interface is provided where one of three operation modes may be selected. The serial interface is controlled by two special function registers (SCON, SBUF) as described in chapter "Serial Interface". Watchdog Timer For software- and hardware security, a watchdog timer is supplied, which resets the processor, if not cleared by software within a maximum time period. Pulse Width Modulation Unit Up to eight lines of port 1 may be used as PWM-outputs. The PWM-logic is controlled by registers PWME, PWMC, PWCOUNT, PWCOMP0 ... 7 (see chapter "Pulse Width Modulation Unit"). 2.1.2 CPU-Timing Timing generation is completely self-contained, except for the frequency reference which can be a crystal or external clock source. The on-board oscillator is a parallel anti-resonant circuit with a frequency range of 1.2 MHz to 16 MHz. There is a divide-by-12 internal timing which leads to a minimum instruction cycle of 0.75 s with a 16-MHz crystal. The XTAL2-pin is the output of a high-gain amplifier, while XTAL1 is its input. A crystal connected between XTAL1 and XTAL2 provides the feedback and phase shift required for oscillation. The 1.2 MHz to 16-MHz range is also accommodated when an external clock is applied to XTAL1 as the frequency source. A machine cycle consists of 12 oscillator periods. Most instructions execute in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete. They take four cycles. Normally, two code bytes are fetched from program memory during every machine cycle. The only exception to this is when a MOVX-instruction is executed. MOVX is a 1-byte 2-cycle instruction that accesses XRAM. During a MOVX, two fetches are skipped while the internal XRAM is being addressed.
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2.1.3 Addressing Modes There are five general addressing modes operating on bytes. One of these five addressing modes, however, operates on both bytes and bits: - - - - - register direct (both bytes and bits) register indirect immediate base-register plus index-register indirect
The following table summarizes, which memory spaces may be accessed by each of the addressing modes: Register Addressing R0 - R7 ACC, B, CY (bit), DPTR Direct Addressing RAM (low part) Special Function Registers Register-Indirect Addressing RAM (@R1, @R0, SP) Immediate Addressing Program Memory Base-Register plus Index-Register Indirect Addressing Program Memory (@DPTR + A, @PC + A) Register Addressing Register addressing accesses the eight working registers (R0 - R7) of the selected register bank. The PSW-register flags RS1 and RS0 determine which register bank is enabled. The least significant three bits of the instruction opcode indicate which register is to be used. ACC, B, DPTR and CY, the Boolean processor accumulator, can also be addressed as registers. Direct Addressing Direct byte addressing specifies an on-chip RAM-location (only low part) or a special function register. Direct addressing is the only method of accessing the special function registers. An additional byte is appended to the instruction opcode to provide the memory location address. The highest-order bit of this byte selects one of two groups of addresses: values between 0 and 127 (00H - 7FH) access internal RAM-locations, while values between 128 and 255 (80H - 0FFH) access one of the special function registers. Register-Indirect Addressing Register-indirect addressing uses the contents of either R0 or R1 (in the selected register bank) as a pointer to locations in the 256 bytes of internal RAM. Note that the special function registers are not accessable by this method.
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Execution of PUSH- and POP-instructions also use register-indirect addressing. The stack pointer may reside anywhere in internal RAM. Immediate Addressing Immediate addressing allows constants to be part of the opcode instruction in program memory. An additional byte is appended to the instruction to hold the source variable. In the assembly language and instruction set, a number sign (#) precedes the value to be used, which may refer to a constant, an expression, or a symbolic name. Base-Register plus Index Register-Indirect Addressing Base-register plus index register-indirect addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register (DPTR or PC) and index register, ACC. This mode facilitates accessing to look-up-table resident in program memory. 2.2 Memory Organization
The processor memory is organized into two address spaces. The memory spaces are: - 512-Kbyte external program memory address space - 256 byte plus 128-byte internal data memory address space - 1024-byte additional internal data memory A 16-bit program counter and a dedicated banking logic provide the processor with its 512-Kbyte addressing capabilities (up to 19 address lines are available). The program counter allows the user to execute calls and branches to any location within the program memory space. There are no instructions that permit program execution to move from the program memory space to any of the data memory space. 2.2.1 External Program Memory Certain locations in program memory are reserved for specific programs. Locations 0000 through 0002 are reserved for the initialization program. Following reset, the CPU always begins execution at location 0000. Locations 0003 through 0035 are reserved for the five interrupt-request service programs as indicated in the following table:
Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Interface
Address 03 11 19 27 35 (03H) (0BH) (13H) (1BH) (23H)
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Memory Extension The processor is prepared to extend its external program memory space up to 512 Kbytes (figure 2, 3). For easy handling of existing software and assemblers this space is split into 8 banks of 64 Kbytes each. The extension concept, based on the standard 64 K addressing ability, is provided for high effective and easy memory access with minimum software overhead. There is also no need caring about bank organization during subroutine processing or interrupts. This is done through address bits A16 - 18, which are controlled by a special internal circuitry, performing a `delayed banking'. The operations to the extended memory spaces are controlled by two additional special function registers called MEX1 and MEX2 (figure 4). The address bits A17 and A18 are implemented at Port 4. Programs, using only 128-Kbytes program memory space, may switch the address function off by setting bits NB, IB and bits MB to `1' followed by a LJMP. Then port 4 will work properly in port mode. Whenever full address mode is desired, port 4 bits have to be kept on `1' (table 1). After reset all CB are `0' and P4 latches are set to `1', resulting a `0' at the port 4 pins. Banking of Program Memory After reset the bits for current bank (CB) and next bank (NB) are set to zero. This way the processor starts the same as any 8051 controller at address 00000H. Whenever a jump to another bank is required, the software has to change the bits NB16 - 18 for initializing the bank exchange (bits CB16 - 18 are read only). After operating the next LJMP instruction the NB16 - 18 bits (next bank) are copied to CB16 - 18 (current bank) and will appear at A16 - 18. Only LJMP will do this.
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Figure 2 Connecting External Program Memory
Figure 3 Bank Organization
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MEX1 (94H): 7 - 6
Bank Control 5 CB17 4 CB16 3 - 2 NB18 1 NB17 0 NB16
CB18
MEX2 (95H): 7 MM CB NB MM MB SF IB 6
Mode Control 5 MB17 4 MB16 3 SF 2 IB18 1 IB17 0 IB16
MB18
= Current Bank = Next Bank = Memory Mode = Memory Bank = Stack Full = Interrupt Bank
Read only; CBx = Ax R/W R/W; 1 = use MB R/W Read only; 1 = full R/W
Figure 4 Register Bits MEX1 / MEX2
Table 1 Port 4 Configuration CB 0 0 1 1 MOVC-Handling MOVC-instructions may operate in two different modes, that are selected by bit MM in MEX2. On MM = 0 MOVC will access the current bank. On MM = 1 the bits MB16 - 18 will appear at A16 - A18 during MOVC. P4 Latch 0 1 0 1 P4 Out 0 0 0 1 Comment x Address P4 Addr / P4
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Figure 5 PC and DPTR on Different Banks CALLs and Interrupts For flexible use of CALL and interrupts the control logic holds an own 32 levels-six-bit-stack. Whenever a LCALL or ACALL occurs, CB16 - 18 and NB16 - 18 (MEX1) is copied to this stack and the memory extension stackpointer is incremented. Then NB16 - 18 is copied to CB16 - 18. Leaving subroutines through RET or RETI decrements the stack pointer and reads the old NB and CB contents from the stack. All six bits are required for saving to prevent conflicts on interrupt events. One additional feature simplifies the handling of interrupts: on occurrence the bits IB16 - 18 within MEX2 are copied to CB16 - 18 and NB16 - 18 after pushing their old contents on the stack. This way programmers can place their ISR (Interrupt Service Routine) on specific banks. After reset MM, MB16 - 18 and IB16 - 18 are set to zero. In order to prevent loss of program control during deep subroutine nesting a warning bit `SF' (Stack Full) is set in MEX2 whenever a memory extension stack depth overflow is imminent. For example figure 6 shows the data flows at the memory extension stack during a LCALL. All three bits of NB are copied to the position CB and NB of the next higher stack level (now the current MEX1) while the last CB and NB are held on the stack. Returning from subroutine through RET the memory extension stack pointer decrements and CB and NB of MEX1 has the same contents as before LCALL.
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Figure 6 Processing LCALL (same as ACALL) Examples The standard sequence jumping from one bank to another is simply preceding a `MOV MEX1,#'instruction to an `LJMP / LCALL' as shown in figure 6. To operate programs up to 512 Kbytes with standard assemblers or from C the program can be split into sections, modules or files, that will each run in their own bank. Referencing banks to each other (jumps, calls, data moves) may be done by a simple preprocessing of the source programs or object files. Users, going to program a 512-Kbyte EPROM in assembler, may proceed like this: 1) build up to eight assembler source files (max. 64 K), inter bank operations will refer to dummy labels. 2) do assembler runs on each block and generate label lists. 3) preprocessing: substitute the inter bank labels in the source files with absolute 64 K addresses. 4) second and final assembler runs on each block, generate Hex files. 5) append the Hex files in right order. 6) program an EPROM. More comfortable programming, e.g. based on C-programs, require similar processing of the source programs or object files with respect to special considerations of the compiler. Figure 7 shows an assembler program run, performing the following actions: 1) 2) 3) 4) 5) 6) start at bank 0 at 00000. set ISR-page to bank 2. jump to bank 1 at address 25. being interrupted to bank 2 ISR. call a subprogram at bank 2 address 43. after return read data from bank 2.
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Figure 7 Program Example 2.2.2 Internal Data RAM The internal data memory is divided into four blocks: the lower 128 byte of RAM, the upper 128 byte of RAM, the 128-byte Special Function Register (SFR) area and the 1024-byte additional RAM (figure 8). Because the upper RAM-area and the SFR-area share the same address locations, they are accessed through different addressing modes. The internal data RAM-address space is 0 to 255. Four banks of eight registers each occupy locations 0 through 31. Only one of these banks may be enabled at a time through a two-bit field in the PSW. In addition, 128-bit locations of the on-chip RAM are accessible through direct addressing. These bits reside in internal data RAM at byte locations 32 through 47, as shown in figure 9. The lower 128 bytes of internal data RAM can be accessed through direct or register-indirect addressing, the upper 128 bytes of internal data RAM through register-indirect addressing and the special function registers through direct addressing.
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The stack can be located anywhere in the internal data RAM-address space. The stack depth is limited only by the available internal data RAM, thanks to an 8-bit reloadable stack pointer. The stack is used for storing the program counter during subroutine calls and may also be used for passing parameters. Any byte of internal data RAM or special function registers accessible through direct addressing can be pushed/popped. An additional on-chip RAM-space called `XRAM' extends the internal RAM-capacity up to 1280 bytes. The 1024 bytes of XRAM are accessed by MOVX @DPTR. XRAM is located in the upper area of the address space at 0F800H - 0FBFFH. 2.2.3 Special Function Registers The special function register address space resides between addresses 128 and 255. All registers except the program counter and the four banks of eight working registers reside here. Memory mapping the special function registers allows them to be accessed as easily as the internal RAM. As such, they can be operated on by most instructions. A complete list of the special function registers is given in table 2. In addition, many bit locations within the special function register address space can be accessed using direct addressing. These direct addressable bits are located at byte addresses divisible by eight as shown in figure 10.
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Figure 8 Internal Data Memory Address Space Semiconductor Group 26
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RAM Byte 256
(MSB)
(LSB)
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Bank 3 24 23 Bank 2 16 15 Bank 1 8 7 Bank 0 0 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
FFH
2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 1FH 18H 17H 10H 0FH 08H 07H 00H
Figure 9 Internal RAM-Bit Addresses
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Direct Byte Address F8H F0H E8H E0H D8H D0H C8H C0H B8H B0H A8H A0H 98H 90H 88H 80H FF F7 - E7 DF D7 CF C7 - B7 AF A7 9F 97 8F 87 FE F6 - E6 - D6 CE C6 BE B6 AE A6 9E 96 8E 86 FD F5 - E5 - D5 CD C5 - B5 AD A5 9D 95 8D 85
Bit Address FC F4 - E4 DC D4 CC C4 - B4 AC A4 9C 94 8C 84 FB F3 - E3 DB D3 - C3 - B3 AB A3 9B 93 8B 83 FA F2 - E2 - D2 - C2 - B2 AA A2 9A 92 8A 82 F9 F1 E9 E1 D9 D1 - C1 - B1 A9 A1 99 91 89 81 F8 F0 E8 E0 D8 D0 - C0 - B0 A8 A0 98 90 88 80
Hardware Register Symbol PWCOMP7 B P4 ACC ADCON PSW PWMC PWME WDSTART P3 IE P2 SCON P1 TCON P0
Figure 10 Special Function Register Bit Address Space
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Table 2 Special Function Register Overview
Special Function Register Description Arithmetic Registers Accumulator B-Register Program Status Word System Control Registers Stack Pointer Data Pointer (high byte) Data Pointer (low byte) Data Pointer Select Power Control Memory Extension Bank Memory Extension Mode Advanced Function Register I/O-Port Registers Port 0 Port 1 Port 2 Port 3 Port 4
Symbolic Name
Address Address Bit Address Initial Value Location Location MSB ... LSB after Reset (hex.) (dec.) (hex.) (hex./bin.) E0 F0 D0 81 83 82 A2 87 94 95 A6 80 90 A0 B0 E8 A9 A8 89 88 8D 8C 8B 8A B8 86 84 85 224 240 208 129 131 130 162 135 148 149 166 128 144 160 176 232 169 168 137 136 141 140 139 138 184 134 132 133 E7 - E0 F7 - F0 D7 - D0 - - - - - - - - 87 - 80 97 - 90 A7 - A0 B7 - B0 E9 - E8 - AF - A8 - 8F - 88 - - - - - - - - 00 00 00 07 00 00 xxxx x000 FD 88 00 1xxx xxxx FF FF FF FF xxxx xx00 C0 00 00 00 00 00 00 00 xx 00 00 80
ACC, A B PSW SP DPH DPL DPSEL PCON MEX1 MEX2 AFR P0 P1 P2 P3 P4
Interrupt Control Registers Interrupt Priority Flags IP Interrupt Enable Flags IE Timer 0/1 Registers Timer 0/1 Mode Register Timer 0/1 Control Register Timer 1 (high byte) Timer 0 (high byte) Timer 1 (low byte) Timer 0 (low byte) Watchdog Timer Registers Watchdog Start Register Watchdog Reload Register Watchdog Low Byte Watchdog High Byte TMOD TCON TH1 TH0 TL1 TL0 WDSTART WDTREL WDTL WDTH
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Special Function Register Overview (cont'd)
Special Function Register Description Analog Digital Converter ADC-Control Register ADC-Data Register ADC-Start Register Pulse Width Modulator Registers Control Register Enable Register PWM-Counter Register Compare Register 0 Compare Register 1 Compare Register 2 Compare Register 3 Compare Register 4 Compare Register 5 Compare Register 6 Compare Register 7 Serial Interface Registers Serial Control Register Serial Data Register
Symbolic Name
Address Address Bit Address Initial Value Location Location MSB ... LSB after Reset (hex.) (dec.) (hex.) (hex./bin.) D8 D9 DA 216 217 218 9F - 98 - - 0xx00000 00 xx
ADCON ADDAT DAPR
PWMC PWME PWCOUNT PWCOMP0 PWCOMP1 PWCOMP2 PWCOMP3 PWCOMP4 PWCOMP5 PWCOMP6 PWCOMP7 SCON SBUF
C8 C0 F9 F1 F2 F3 F4 F5 F6 F7 F8 98 99
200 192 249 241 242 243 244 245 246 247 248 144 145
CF - C8 C7 - C0 - - - - - - - - FF - F8 9F - 98 -
80 00 00 FF FF FF FF FF FF FF FF 00 xx
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2.3
Interrupt System
External events and the real-time on-chip peripherals require CPU-service asynchronous to the execution of any particular section of code. To couple the asynchronous activities of these functions to normal program execution, a sophisticated multiple-source, two-priority-level, nested interrupt system is provided. Interrupt response delay ranges from 2 s to 5.25 s when using a 16-MHz crystal. 2.3.1 Interrupt Sources The processor acknowledges interrupt requests from five sources: two from external sources via the INT0 and INT1 pins, one from each of the two internal counters and one from the serial I/O-port. Each of the five sources can be assigned to either of two priority levels and can be independently enabled and disabled. Additionally, all enabled sources can be globally disabled or enabled. Interrupts result in a transfer of control to a new program location. Each interrupt vectors to a separate location in program memory for its service program. The program servicing the request begins at this address. The starting address (interrupt vector) of the interrupt service program for each interrupt source is shown in the following table:
Interrupt Source External Request 0 Internal Timer/Counter 0 External Request 1 Internal Timer/Counter 1 Serial Interface 2.3.2 Interrupt Control
Starting Address 03 11 19 27 35 (03H) (0BH) (13H) (1BH) (23H)
The information flags, which control the entire interrupt system, are stored in four special function registers: TCON IE IP SCON Timer/Counter Control Register Interrupt Enable Register Interrupt Priority Register Serial Control Register 88H A8H A9H 98H
The interrupt system is shown diagrammatically in figure 11. A source requests an interrupt by setting its associated interrupt request flag in the TCON or IFRregister, as detailed in the following table:
Interrupt Source External Request 0 Internal Timer/Counter 0 External Request 1 Internal Timer/Counter 1 Serial Interface
Request Flag IE0 TF0 IE1 TF1 RI/TI
Bit Location TCON.1 TCON.5 TCON.3 TCON.7 SCON0/1
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The timer 0 and timer 1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective timer/counter register, except for timer 0 in mode 3. Within the IE-register there are seven addressable flags. Five flags enable/disable the five interrupt sources when set/cleared. Setting/clearing the seventh flag permits a global enable/disable of all enabled interrupt requests. All the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupt requests can be cancelled by software.
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q q q q q q q
FIVE INTERRUPT SOURCES EACH INTERRUPT CAN BE INDIVIDUALLY ENABLED/DISABLED ENABLED INTERRUPTS CAN BE GLOBALLY ENABLED/DISABLED EACH INTERRUPT CAN BE ASSIGNED TO EITHER OF TWO PRIORITY LEVELS EACH INTERRUPT VECTORS TO A SEPARATE LOCATION IN PROGRAM MEMORY INTERRUPT NESTING TO TWO LEVELS EXTERNAL INTERRUPT REQUESTS CAN BE PROGRAMMED TO BE LEVEL- OR TRANSITION-ACTIVATED
Figure 11 Interrupt System
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Figure 12 Interrupt Enable Register IE Interrupt Enable Register Default after reset: 00H (MSB) EA EA WDT - ES ET1 EX1 ET0 IE SFR-Address A8H (LSB) EX0
Enables or disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Watchdog timer refresh flag (see chapter "Watchdog Timer"). Reserved Enables or disables the serial interface interrupt. If ES = 0, this interrupt will be disabled. Enables or disables the timer 1 overflow interrupt. If ET1 = 0, the timer 1 interrupt is disabled. Enables or disables external interrupt 1. If EX1 = 0, external interrupt 1 is disabled. Enables or disables the timer 0 overflow interrupt. If ET0 = 0, the timer 0 interrupt is disabled. Enables or disables external interrupt 0. If EX0 = 0, external interrupt 0 is disabled.
WDT IE.5 ES ET1 EX1 ET0 EX0
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Figure 13 Interrupt Priority Register IP Interrupt Priority Register Default after reset: 00H (MSB) - IP.7 WDTS IP.5 PS PT1 PX1 PT0 PX0 WDTS Reserved Watchdog timer interrupt flag (see chapter "Watchdog Timer"). Reserved Defines the serial interface interrupt priority level. PS = 1 programs it to the higher priority level. Defines the timer 1 interrupt priority level. PT1 = 1 programs it to the higher priority level. Defines the external interrupt 1 priority level. PX1 = 1 programs it to the higher priority level. Defines the timer 0 interrupt priority level. PT0 = 1 programs it to the higher priority level. Defines the external interrupt 0 priority level. PX0 = 1 programs it to the higher priority level. - PS PT1 PX1 PT0 IP SFR-Address A9H (LSB) PX0
Setting/clearing a bit in the IP-register establishes its associated interrupt request as a high/low priority. If a low-priority level interrupt is being serviced, a high-priority level interrupt will interrupt it. However, an interrupt source cannot interrupt a service program of the same or higher priority level. If two requests of different priority levels are received simultaneously, the request of higher priority level will be serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, as follows:
Source 1. 2. 3. 4. 5. IE0 TF0 IE1/OSD TF1 RI/TI
Priority within Level (highest)
(lowest)
Note that the "priority within level" structure is only used to resolve simultaneous requests of the same priority level.
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2.3.3 Interrupt Nesting The process whereby a high-level interrupt request interrupts a low-level interrupt service program is called nesting. In this case the address of the next instruction in the low-priority service program is pushed onto the stack, the stack pointer is incremented by two and processor control is transferred to the program memory location of the first instruction of the high-level service program. The last instruction of the high-priority interrupt service program must be a RETI-instruction. This instruction clears the higher "priority-level-active" flip-flop. RETI also returns processor control to the next instruction of the low-level interrupt service program. Since the lower "priority-level-active" flip-flop has remained set, high priority interrupts are re-enabled while further low-priority interrupts remain disabled. 2.3.4 External Interrupts The external interrupt request inputs (INT0 and INT1) can be programmed for either transitionactivated or level-activated operation. Control of the external interrupts is provided by the four loworder bits of TCON as shown in figure 14. When IT0 and IT1 are set to one, interrupt requests on INT0 and INT1 are transition-activated (highto-low), else they are low-level activated. IE0 and IE1 are the interrupt request flags. These flags are set when their corresponding interrupt request inputs at INT0 and INT1, respectively, are low when sampled by the processor and the transition-activated scheme is selected by IT0 and IT1.
Figure 14 Function of Lower Nibble Bits in TCON Timer and Interrupt Control Register Default after reset: 00H (MSB) TF1 TCON.4 - TCON.7 IE1 IT1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TCON SFR-Address 88H (LSB)
See chapter "General Purpose Timers/Counters" Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. IT1 = 1 selects transitionactivated (high-to-low) external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. IT0 = 1 selects transitionactivated (high-to-low) external interrupts.
IE0 IT0
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- Transition-Activated Interrupts (IT0 = 1, IT1 = 1) The IE0, IE1 flags are set by a high-to-low transition at INT0, INT1, respectively; they are cleared during entering the corresponding interrupt service routine. For transition-activated operation, the input must remain low for more than twelve oscillator periods, but needs not to be synchronous with the oscillator. The upward transition of a transition-activated input may occur at any time after the twelve oscillator period latching time, but the input must remain high for twelve oscillator periods before reactivation. - Level-Activated Interrupts (IT0 = 0, IT1 = 0) The IE0, IE1 flags are set whenever INT0, INT1 are respectively sampled at low level. Sampling INT0, INT1 at high level clears IE0, IE1, respectively. For level-activated operation, if the input is low during the sampling that occurs fourteen oscillator periods before the end of the instruction in progress, an interrupt subroutine call is made. The levelactivated input needs to be low only during the sampling that occurs fourteen oscillator periods before the end of the instruction in progress and may remain low during the entire execution of the service program. However, the input must be deactivated before the service routine is completed to avoid invoking a second interrupt, or else another interrupt will be generated 2.3.5 Interrupt Task Function The processor records the active priority level(s) by setting internal flip-flop(s). One of these nonaddressable flip-flops is set while a low-level interrupt is being serviced. The other flip-flop is set while the high-level interrupt is being serviced. The appropriate flip-flop is set when the processor transfers control to the service program. The flip-flop corresponding to the interrupt level being serviced is reset when the processor executes a RETI-instruction The sequence of events for an interrupt is: - A source provokes an interrupt by setting its associated interrupt request bit to let the processor know an interrupt condition has occurred. - The CPU's internal hardware latches the internal request in the tenth, twenty-second, thirtyfourth and forty-sixth oscillator period of the instruction in progress. - The interrupt request is conditioned by bits in the interrupt enable and interrupt priority register. - The processor acknowledges the interrupt by setting one of the two internal "priority-level active" flip-flops and performing a hardware subroutine call. This call pushes the PC (but not the PSW) onto the stack and, for most sources, clears the interrupt request flag. - The service program is executed. - Control is returned to the main program when the RETI-instruction is executed. The RETIinstruction also clears one of the internal "priority-level active" flip-flops. Most interrupt request flags IE0, IE1, TF0 and TF1 are cleared when the processor transfers control to the first instruction of the interrupt service program. The RI/TI-interrupt request flag must be cleared as part of the respective interrupt service program. This is also the case for IE0, IE1, if INT0, INT1 are level activated.
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2.3.6 Response Time The highest-priority interrupt request gets serviced at the end of the instruction in progress unless the request is made in the last fourteen oscillator periods of the instruction in progress. Under this circumstance, the next instruction will also execute before the interrupt's subroutine call is made. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. lf the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles, since the longest instructions (MUL and DIV) are only 4 cycles long, and if the instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is MUL or DIV). Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 8 cycles (approximately 5.25 s at 16MHz operation). Examples of the best and worst case conditions are illustrated in the following table.
Instruction External interrupt generated immediately before (best) / after (worst) the pin is sampled (time until end of bus cycle). Current or next instruction finishes in 12oscillator periods Next instruction is MUL or DIV Internal latency for hardware subroutine call
Time (Oscillator Periods) Best Case 2+ Worst Case 2-
12
12
don't care 24 38
48 24 86
If an interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine.
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2.4
Processor Reset and Initialization
Processor initialization is accomplished with activation of the RST pin, which is the input to a Schmitt Trigger. To reset the processor, this pin should be held low for at least two machine cycles, while the oscillator is running. Upon powering up, RST should be held low for at least 10 ms after the power supply stabilizes to allow the oscillator to stabilize. Crystal operation below 6 MHz will increase the time necessary to hold RST low. 24 oscillator periods after receiving of RST, the processor ceases from instruction execution and remains dormant for the duration of the pulse. The high-going transition then initiates a sequence which requires approximately twelve oscillator periods to execute before normal operation commences with the instruction at absolute location 0000H. Program memory locations 0000H through 0002H are reserved for the initialization routine of the microcomputer. This sequence ends with registers initialized as shown in chapter 'Memory Organization'. After the processor is reset, all ports are written with one (1) except Port 4, which is as an extended address output. Outputs are undefined until the reset period is complete. An automatic reset can be obtained when VDD is turned on by connecting the RST-pin to VSS through a 10 F capacitor, providing the VDD rise time does not exceed a millisecond and the oscillator startup time does not exceed 10 milliseconds. When power comes on, the current drawn by RST-pin starts to charge the capacitor. The voltage VRST at RST-pin is the capacitor voltage, and increases to VDD as the capacitor charges. The larger the capacitor, the more slowly VRST decreases. VRST must remain below the lower threshold of the Schmitt Trigger long enough to effect a complete reset. The time required is the oscillator start-up time plus 2 machine cycles. Attention: While reset is active and at least two machine cycles after rising edge of RST, ALE should not be pulled down externally. If during powering off the supply voltage drops below VDD min (4.5 V) and an external reset is not applied, the behaviour of the processor is not defined.
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Figure 15 Power-On Reset Circuit Power-Down Operations The controller provides two modes in which power consumption can be significantly reduced. - Idle mode. The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. - Power-down mode. Operation of the controller is turned off. This mode is used to save the contents of internal RAM with a very low standby current. Both modes are entered by software. Special function register PCON is used to enter one of these modes. Power Control Register PCON SFR-Address 87H (LSB) IDLS - - - PDE IDLE
Default after reset: 000xxx00 (MSB) SMOD PDS IDLS PDE IDLE SMOD PDS
Power-down start bit. The instruction that sets the PDS-flag is the last instruction before entering the power down mode. IDLE start bit. The instruction that sets the PDS-flag is the last instruction before entering the idle mode. Power-down enable bit. When set, starting the power-down mode is enabled. Idle enable bit. When set, starting the idle mode is enabled. Baud rate control for serial interface; if set, the baud rate is doubled.
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The idle mode can be terminated by activation of any enabled interrupt (or a hardware reset). The CPU-operation is resumed, the interrupt will be serviced and the next instruction to be executed after RETI-instruction will be the one following the instruction that set the bit IDLS. The port state and the contents of SFRs are held during idle mode. The only exit from power-down mode is a hardware reset. The reset will redefine all SFRs, but will not change the contents of internal RAM. 2.5 Ports and I/O-Pins
There are 30 I/O-pins configured as three 8-bit ports, one 4-bit-port (P2.4 - 2.7) and one 2-bit port (P4.0 - 4.1). Each pin can be individually and independently programmed as input or output and each can be configured dynamically. An instruction that uses a port's bit/byte as a source operand reads a value that is the logical AND of the last value written to the bit/byte and the polarity being applied to the pin/pins by an external device (this assumes that none of the processor's electrical specifications are being violated). An instruction that reads a bit/byte, operates on the content, and writes the result back to the bit/byte, reads the last value written to the bit/byte instead of the logic level at the pin/pins. Pins comprising a single port can be made a mixed collection of inputs and outputs by writing a "one" to each pin that is to be an input. Each time an instruction uses a port as the destination, the operation must write "ones" to those bits that correspond to the input pins. An input to a port pin needs not to be synchronized to the oscillator. All the port latches have "one" s written to them by the reset function. If a "zero" is subsequently written to a port latch, it can be reconfigured as an input by writing a "one" to it. The instructions that perform a read of, operation on, and write to a port's bit/byte are INC, DEC, CPL, JBC, SETB, CLR, MOV P.X, CJNE, DJNZ, ANL, ORL, and XRL. The source read by these operations is the last value that was written to the port, without regard to the levels being applied at the pins. This insures that bits written to a "one" (for use as inputs) are not inadvertently cleared. Port 0 has an open-drain output. Writing a "one" to the bit latch leaves the output transistor off, so the pin floats. In that condition it can be used as a high-impedance input. Port 0 is considered "true bidirectional", because when configured as an input it floats. Ports 1, 2.4 - 2.7, 3 and 4 have "quasi-bidirectional" output drivers which comprise an internal pullup resistor . When configured as inputs they pull high and will source current when externally pulled low (see DC Characteristics). In ports 1, 2.4 - 2.7, 3 and 4 the output drivers provide source current for two oscillator periods if, and only if, software updates the bit in the output latch from a "zero" to an "one". Sourcing current only on "zero to one" transition prevents a pin, programmed as an input, from sourcing current into the external device that is driving the input pin. Secondary functions can be selected individually and independently for the pins of port 1 and 3. Further information on port 1's secondary functions is given in chapter "Pulse Width Modulation Unit". P3 generates the secondary control signals automatically as long as the pin corresponding to the appropriate signal is programmed as an input, i. e. if the corresponding bit latch in the P3 special function register contains a "one".
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The following alternate functions can be selected when using the corresponding P3 pins: P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 INT0 INT1 T0 T1 RxD TxD (external interrupt 0) (external interrupt 1) (Timer/Counter 0 external input) (Timer/Counter 1 external input) (serial port receive line) (serial port transmit line)
Read Modify-Write Feature "Read-modify-write" commands are instructions that read a value, possibly change it, and then rewrite it to the latch. When the destination operand is a port or a port bit, these instructions read the latch rather than the pin. The read-modify-write instructions are listed in table 3. The read-modify-write instructions are directed to the latch rather than the pin in order to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a "one" is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a 0. Reading the latch rather than the pin will return the correct value of "one".
Table 3 Read-Modify-Write Instructions Mnemonic ANL ORL XRL JBC CPL INC DEC DJNZ MOV PX.Y, C* CLR PX.Y* SET PX.Y* Description logical AND logical OR logical EX - OR jump if bit = 1 and clear bit complement bit increment decrement decrement and jump if not zero move carry bit to bit Y of Port X clear bit Y of Port X set bit Y of Port X Example ANL P1, A ORL P2, A XRL P3, A JBC P1.1, LABEL CPL P3.0 INC P1 DEC P1 DJNZ P3, LABEL MOV P1.7, C CLR P2.6 SET P3.5
* The instruction reads the port byte (all 8 bits), modifies the addressed bit, then writes the new byte back to the latch
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2.6
General Purpose Timers/Counters
Two independent general purpose 16-bit timers/ counters are integrated for use in measuring time intervals, measuring pulse widths, counting events, and causing periodic (repetitive) interrupts. Either can be configured to operate as timer or event counter. In the "timer" function, the registers TLx and/or THx (x = 0, 1) are incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the "counter" function, the registers TLx and/or THx (x = 0, 1) are incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled during every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since it takes 2 machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. Timer/Counter 0: Mode Selection Timer/counter 0 can be configured in one of four operating modes, which are selected by bit-pairs (M1, M0) in TMOD-register (figure 16). - Mode 0 Putting timer/counter 0 into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. Figure 18 shows the mode 0 operation as it applies to timer 0. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1 s to all 0 s, it sets the timer interrupt flag TF0. The counted input is enabled to the timer when TR0 = 1 and either GATE = 0 or INT0 = 1. (Setting GATE = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width measurements.) TR0 is a control bit in the special function register TCON (figure 17). GATE is contained in register TMOD (figure 16). The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. - Mode 1 Mode 1 is the same as mode 0, except that the timer/counter 0 register is being run with all 16 bits. - Mode 2 Mode 2 configures the timer/counter 0 register as an 8-bit counter (TL0) with automatic reload, as shown in figure 19. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. - Mode 3 Timer/counter 0 in mode 3 establishes TL0 and TH0 as two separate counters. The logic for mode 3 on timer 0 is shown in figure 20. TL0 uses the timer 0 control bits: C/T, GATE, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the "timer 1" interrupt.
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Mode 3 is provided for applications requiring an extra 8-bit timer or counter. With timer 0 in mode 3, the processor can operate as if it has three timers/counters. When timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used in any application not requiring an interrupt. Timer/Counter 1: Mode Selection Timer/counter 1 can also be configured in one of four modes, which are selected by its own bitpairs (M1, M0) in TMOD-register. The serial port receives a pulse each time that timer/counter 1 overflows. This pulse rate is divided to generate the transmission rate of the serial port. Modes 0 and 1 are the same as for counter 0. - Mode 2 The "reload" mode is reserved to determine the frequency of the serial clock signal (not implemented). - Mode 3 When counter 1's mode is reprogrammed to mode 3 (from mode 0, 1 or 2), it disables the increment counter. This mode is provided as an alternative to using the TR1 bit (in TCON-register) to start and stop timer/counter 1. Configuring the Timer/Counter Input The use of the timer/counter is determined by two 8-bit registers, TMOD (timer mode) and TCON (timer control), as shown in figure 16 and 17. The input to the counter circuitry is from an external reference (for use as a counter), or from the on-chip oscillator (for use as a timer), depending on whether TMOD's C/T-bit is set or cleared, respectively. When used as a time base, the on-chip oscillator frequency is divided by twelve (12) before being used as the counter input. When TMOD's GATE bit is set (1), the external reference input (T1, T0) or the oscillator input is gated to the counter conditional upon a second external input (INT0), (INT1) being high. When the GATE bit is zero (0), the external reference, or oscillator input, is unconditionally enabled. In either case, the normal interrupt function of INT0 and INT1 is not affected by the counter's operation. If enabled, an interrupt will occur when the input at INT0 or INT1 is low. The counters are enabled for incrementing when TCON's TR1 and TR0 bits are set. When the counters overflow, the TF1 and TF0 bits in TCON get set, and interrupt requests are generated. The counter circuitry counts up to all 1's and then overflows to either 0's or the reload value. Upon overflow, TF1 or TF0 is set. When an instruction changes the timer's mode or alters its control bits, the actual change occurs at the end of the instruction's execution. The T1 and T0 inputs are sampled near the falling-edge of ALE in the tenth, twenty-second, thirtyfourth and forty-sixth oscillator periods of the instruction-in-progress. Thus, an external reference's high and low times must each be a minimum of twelve oscillator periods in duration. There is a twelve oscillator period delay from the time when a toggled input (transition from high to low) is sampled to the time when the counter is incremented.
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Figure 16 Timer/Counter Mode Register Timer 0/1 Mode Register TMOD Default after reset: 00H (MSB) GATE C/T M1 Timer 1 GATE M0 GATE C/T M1 Timer 0 M0 SFR-Address 89H (LSB)
Gating control when set. Timer/counter "x" is enabled only while "INTx" pin is high and "TRx" control pin is set. When cleared, timer "x" is enabled, whenever "TRx" control bit is set. Timer or counter selector. Cleared for timer operation (input from internal system clock). Set for Counter operation (input from "Tx" input pin).
C/T
M1 0 0 1 1
M0 0 1 0 1
Operating Mode SAB 8048 timer: "TLx" serves as five-bit prescaler. 16-bit timer/counter: "THx" and "TLx" are cascaded, there is no prescaler. 8-bit auto-reload timer/counter: "THx" holds a value which is to be reloaded into "TLx" each time it overflows. (Timer 0) TL0 is an eight-bit timer/counter controlled by the standard timer 0 control bits; TH0 is an eight-bit timer only controlled by timer 1 control bits. (Timer 1) timer/counter 1 is stopped.
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Figure 17 Timer/Counter Control Register Timer 0/1 Control Register Default after reset: 00H (MSB) TF1 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TCON SFR-Address 88H (LSB)
Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn timer/counter on/off. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 run control bit. Set/cleared by software to turn timer/counter on/off. Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
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Figure 18 Timer/Counter 0 Mode 0: 13-Bit Counter
Figure 19 Timer/Counter 0 Mode 2: 8-Bit Auto-Reload
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Figure 20 Timer/Counter 0 Mode 3: Two 8-Bit Counters
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2.7
Watchdog Timer
To protect the systems against software upset, the user's program has to clear this watchdog within a previously programmed time period. If the software fails to do this periodical refresh of the watchdog timer, an internal hardware reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. The watchdog timer is a 15-bit timer, which is incremented by a count rate of either fCYCLE/2 or fCYCLE/128. The latter is enabled by setting bit WDTREL.7. Immediately after start, the watchdog timer is initialized to the reload value programmed to WDTREL.0 - WDTREL.6. After an external reset register WDTREL is cleared to 00H. The lower seven bits of WDTREL can be loaded by software at any time. The watchdog timer is started by software by setting bit SWDT in special function register WDSTART (bit 6). If the counter is stopped, and WDTREL is loaded with a new value, WDTH (highbyte of the watchdog timer) is updated immediately. WDTL (low-byte of the watchdog timer) is always zero, if the counter is stopped. Once started the watchdog timer cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDT (IE.6) and by the next instruction setting SWDT (WDSTART.6). Bit WDT will automatically be cleared during the third machine cycle after having been set. This double instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog. If the software fails to clear the watchdog in time, an internally generated watchdog reset is entered at the counter state 7FFCH. The duration of the reset signal then depends on the prescaler selection. This internal reset differs from an external reset only in so far as the watchdog timer is not disabled and bit WDTS (IP.6) is set. Bit WDTS allows the software to examine from which source the reset was activated. The watchdog timer status flag can also be cleared by software. With WDTREL = 80H a maximum time period of about 3.1 s at 16-MHz oscillator frequency can be achieved. Watchdog Timer Control Bits Watchdog Timer Reload Register Default after reset: 00H (MSB) WDTREL SFR-Address 86H (LSB)
WDTREL.7 WDTREL.0 - WDTREL.6
Prescaler bit. When set, the watchdog is clocked through an additional divide by 64 prescaler. Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT.
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Interrupt Enable Register Default after reset: 00H (MSB) WDT WDT
IE
SFR-Address A8H (LSB)
Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to the watchdog timer.
See chapter `Interrupt System' for the description of the remaining bits.
Watchdog Timer Start Register Default after reset: xxH (MSB) SWDT SWDT
WDSTART
SFR-Address B8H (LSB)
Watchdog timer start flag. Set to activate the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed.
Interrupt Enable Register Default after reset: xxH (MSB) WDTS WDTS
IP
SFR-Address A9H (LSB)
Watchdog timer reset flag. If bit WDTS is `1' after reset, the reset has been initiated by the watchdog timer. After external reset, WDTS is reset to `0'.
See chapter `Interrupt System' for the description of the remaining bits.
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2.8
Serial Interface
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receivebuffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The frequencies and baud rates described in this chapter depend on the internal system clock, used by the serial interface. The internal system clock frequency of the serial interface is defined by the oscillator frequency fOSC, the setting of bit CDC in the Advanced Function Register AFR of the special function registers (see chapter "Advanced Function Register"), and the setting of bit PSC in the ADC Control Register ADCON of the special function registers (see chapter "Analog Digital Converter"). Both bits are software switches to activate or deactivate clock dividers by 2. The frequencies and baud rates specified in this chapter apply to bit CDC = 1 and bit PSC = 0. For other combinations of CDC and PSC see the following table:
CDC 0 0 1 1
PSC 0 1 0 1
Frequencies and Baud Rates of this Chapter double the specified values values as specified values as specified halve the specified values
The serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RxD (P3.6). TxD (P3.7) outputs the shift clock at 1/12 of the oscillator frequency. Mode 1: 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB8 in special function register SCON. The baud rate is variable. Mode 2: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On reception, the 9th data bit goes into RB8 in the special function register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency. Mode 3: 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (1 ). In fact, mode 3 is the same as mode 2 in all respects except the baud rate. The baud rate in mode 3 is variable.
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Figure 21 Serial Port Control Register SCON (98H) SM0 9FH Symbol SMO SM1 SM2 SM1 9EH Position SCON.7 SCON.6 SCON.5 SM2 9DH Function Serial Port Mode Selection, see table 4. REN 9CH TB8 9BH RB8 9AH TI 99H RI 98H Bit Address
Enables the multiprocessor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Cleared by software to disable reception. Is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired. In modes 2 and 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through stop bit time in the other modes, in any serial reception. Must be cleared by software.
REN
SCON.4
TB8
SCON.3
RB8
SCON.2
TI
SCON.1
RI
SCON.0
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Table 4 Serial Port Mode Selection SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift Reg. 8-bit UART 9-bit UART 9-bit UART Baud Rate
fOSC/12
Variable
fOSC/64 - fOSC/32
Variable
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in mode 0 by the condition Rl = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. The control, mode, and status bits of the serial port in special function register SCON are illustrated in figure 21. 2.8.1 Multiprocessor Communication Modes 2 and 3 of the serial interface of the controller have a special provision for multiprocessor communication. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor communications is as follows. When the master processor wants to transmit a block of data to one of the several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren't addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.
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2.8.2 Baud Rates The baud rate in mode 0 is fixed: Mode 0 baud rate =
fOSC
12 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON (bit 7). If SMOD = 0 (which is the value on reset), the baud rate is 1/64 of the oscillator frequency. If SMOD = 1, the baud rate is 1/32 of the oscillator frequency. Contrary to the SAB 8051 SMOD is placed on SFR-address 97H. Mode 2 baud rate = 2SMOD 64 x fOSC
The baud rates in modes 1 and 3 are determined by the timer 1 overflow rate or can be generated by the internal baud rate generator. When timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of SMOD as follows: Modes 1,3 baud rate = 2SMOD 32 x Time 1 overflow rate
The timer 1 interrupt should be disabled in this application. The timer itself can be configured for either "timer" or "counter" operation, and in any of the 3 running modes. In the most typical applications, it is configured for "timer" operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case, the baud rate is given by the formula: Modes 1,3 baud rate = 2SMOD fOSC x 32 12 x (256 - TH1)
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One can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, configuring the timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the timer 1 interrupt to do a 16-bit software reload. Table 5 lists various commonly used baud rates and how they can be obtained from timer 1.
Table 5 Generated Commonly Used Baud Rates Baud Rate
fOSC
MHz
SMOD CT X 1 1 1 0 0 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0
Timer 1 Mode X X 2 2 2 2 2 2 2 2 1 Reload Value X X FFH FDH FDH FAH F4H E8H 1DH 72H FEEBH
Mode 0 max: Mode 2 max: Mode 1, 3:
1.33 MHz 500 Kbaud 62.5 Kbaud 19.2 Kbaud 9.6 Kbaud 4.8 Kbaud 2.4 Kbaud 1.2 Kbaud 137.5 Baud 110 Baud 110 Baud
16.0 16.0 12.0 11.059 11.059 11.059 11.059 11.059 11.986 6.0 12.0
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2.8.3 More about Mode 0 Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/ received: 8 data bits (LSB first). The baud rate is fixed at 1/12 of the oscillator frequency. Figure 22 shows a simplified functional diagram of the serial port in mode 0, and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-to SBUF" signal at S6P2 also loads a 1 into the 9th bit position of the transmit shift register and tells the TX-control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between "write-to-SBUF" and activation of SEND.SEND enables the output of the shift register to the alternate output function line of P3.6, and also enables SHIFT CLOCK to the alternate output function, line of P3.7. SHIFT CLOCK is low during S3, S4 and S5 of every machine cycle, and high during S6, S1, and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift register is shifted one position to the right. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX-control block to do one last shift and then deactivate SEND and set Tl. Both of these actions occur at S1P1 in the 10th machine cycle after "write-to-SBUF". Reception is initiated by the condition REN = 1 and Rl = 0. At S6P2 in the next machine cycle, the RX-control unit writes the bits 1111 1110 to the receive shift register, and the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.7. SHIFT CLOCK makes transitions at S3P1 and S6P1 in every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the Receive Shift register are shifted one position to the left. The value that comes in from the right is the value that was sampled at the P3.6 pin at S5P2 in the same machine cycle. As data bits come in from the right, 1 s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX-control block to do one last shift and load SBUF. At S1P1 in the 10th machine cycle after the write to SCON that cleared Rl, RECEIVE is cleared and Rl is set.
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2.8.4 More about Mode 1 Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first) and a stop bit (1). On reception, the stop bit goes into RB8 in SCON. The baud rate is determined by the timer 1 overflow rate. Figure 23 shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit and receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-to SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TXcontrol block that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the "write-to-SBUF" signal). The transmission begins with activation of SEND, which puts the start bit to TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just left of the MSB, and all positions to the left of that contain zeros. This condition flags the TXcontrol unit to do one last shift and then deactivate SEND and set Tl. This occurs at the 10th divideby-16 rollover after "write-to-SBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divideby-16 counter is immediately reset, and 1 FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1 s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX-control block to do one last shift, load SBUF and RB8, and set Rl. The signal to load SBUF and RB8, and to set Rl, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) Rl = 0, and 2) either SM2 = 0 or the received stop bit = 1 If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF and Rl is activated. At this time, no matter whether the above conditions are met or not, the unit goes back looking for a 1-to-0transition in RxD.
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2.8.5 More about Modes 2 and 3 11 bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit, (1). On transmission, the 9th data bit (TB8) can be assigned the value of 0 or 1. On reception, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency in mode 2. Mode 3 may have a variable baud rate generated from timer 1. Figure 24 and 25 show a functional diagram of the serial port in modes 2 and 3 and associated timings. The receive portion is exactly the same as in mode 1. The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-toSBUF" signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TXcontrol unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the "write-to-SBUF" signal). The transmission begins with activation of SEND, which puts the start bit to TxD. One bit time later, DATA is activated which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just left of the TB8, and all positions to the left of that contain zeros. This condition flags the TX-control unit to do one last shift and then deactivate SEND and set Tl. This occurs at the 11th divide-by-16 rollover after "write-to-SBUF". Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divideby-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1 s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the RX-control block to do one last shift, load SBUF and RB8, and set Rl. The signal to load SBUF and RB8, and to set Rl, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) Rl = 0, and 2) either SM2 = 0 or the received 9th data bit = 1 If either of these two conditions is not met, the received frame is irretrievably lost, and Rl is not set. If both conditions are met, the received 9th data bit goes into RB8, the first 8 data bits go into SBUF. One bit time later, no matter whether the above conditions are met or not, the unit goes back looking for a 1-to-0-transition at the RxD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8 or Rl.
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Figure 22 a Serial Port Mode 0, Functional Diagram
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Figure 22 b Serial Port Mode 0, Timing
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Figure 23 a Serial Port Mode 1, Functional Diagram
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Figure 23 b Serial Port Mode 1, Timing
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Figure 24 a Serial Port Mode 2, Functional Diagram
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Figure 24 b Serial Port Mode 2, Timing
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Figure 25 a Serial Port Mode 3, Functional Diagram
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Figure 25 b Serial Port Mode 3, Timing
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