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PCI2050 Evaluation Module
User's Guide
2000
PCIBus Solutions
SCPU006
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
Information About Cautions and Warnings
Preface
Read This First
About This Manual
This manual is designed to assist the user of the PCI2050 evaluation module (EVM). It provides descriptions of parts, features, and operating requirements of the EVM that are necessary or useful to obtain maximum benefit from EVM use.
How to Use This Manual
This document contains the following chapters: Chapter 1, Introduction, provides a brief description of the EVM, and a bill of materials for the EVM kit. Chapter 2, Software Requirements, details the minimum software requirements for any PC system on which the PCI2050 EVM is to be run. Chapter 3, Configuration, explains secondary bus masters and interrupt routing as related to the edge connectors on the board. Chapter 4, Board Configuration, describes the location and purpose of board components such as pins, jumpers, connectors, and LEDs.
Information About Cautions and Warnings
This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment.
This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you.
Read This First
iii
Trademarks
The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully.
Related Documentation From Texas Instruments
PCI2050 PCI-to-PCI Bridge Data Manual, TI Literature Number - SCPS053 PCI2050 Implementation Guide, TI Literature Number - SCPU009
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.
Trademarks
Windows is a registered trademark of Microsoft Corporation. (WindowsTM 95, WindowsTM) Windows NT is a registered trademark of Microsoft Corporation. (Windows NTTM ) CompactPCI is a trademark of PICMG - PCI Industrial Computer Manufacturers Group, Inc. (CompactPCITM) Other trademarks are the property of their respective owners.
iv
Running Title--Attribute Reference
Contents
1.1 1.2 2.1 3.1 4.1 4.2 4.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evaluation Kit Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI2050 Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 CompactPCI Hot-Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 D1 ENUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 D2 HSLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 D3 C1_PRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 D4 C2_PRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 D5 C3_PRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 D6 EVM3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 D7 PCU3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undetected Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mictor Connector Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-2 2-2 3-2 4-2 4-3 4-3 4-4 4-4 4-4 4-4 4-4 4-4 4-4 4-4 4-5 4-5 4-6 4-7
4.4 4.5 4.6 4.7
Chapter Title--Attribute Reference
v
Running Title--Attribute Reference
Figures
4-1 4-2 Part and Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Tables
3-1 3-2 4-1 4-2 4-3 4-4 4-5 Edge Connector Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Edge Connector Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Jumper Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Mode Select Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Socket Clock Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 HP Logic Analyzer POD Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 PCI2050 EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
vi
Chapter 1
Introduction
This chapter provides a brief overview of the PCI2050 evaluation module, along with a bill of materials for the EVM kit.
Topic
1.1 1.2
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Evaluation Kit Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Introduction
1-1
Introduction
1.1 Introduction
This document is intended to assist the user of the PCI2050 evaluation module (EVM), EVM2050A. Included within this document are instructions detailing the proper setup and configuration necessary to operate the PCI2050 EVM. The PCI2050 EVM is a universal add-in card and can be used in either 3.3-V or 5-V signaling environments.
1.2 Evaluation Kit Bill of Materials
The PCI2050 EVM consists of the following items:
Item EVM2050A 3.5" Diskette Nomenclature PCI to PCI Adapter Card Assembly PCIBus and PCIBus95 Utility Programs Quantity 1 1
1-2
Chapter 2
Software Requirements
This chapter provides the minimum software requirements for any PC system on which the PCI2050 EVM is to be used.
Topic
2.1
Page
Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Software Requirements
2-1
Software Requirements
2.1 Software Requirements
The EVM2050A evaluation board will work in any system that meets the following requirements: 1) BIOS which supports the PCI Bridge Specification 1.0. 2) Operating system that supports the PCI Bridge Specification 1.0. In the majority of today's computer systems, bridge support is built into the BIOS. Many operating systems, like WindowsTM 95/98 and Windows NTTM, have support for bridges.
2-2
Chapter 3
Configuration
This chapter explains secondary bus masters and interrupt routing as related to edge connectors on the board.
Topic
3.1
Page
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Configuration
3-1
Configuration
3.1 Configuration
The PCI2050 supports nine secondary bus masters. Due to board space, only three masters are supported with the EVM2050A board. The three supported masters can be plugged into three edge connectors labeled P1, P2, and P3. These edge connectors are configured as listed in Table 3-1.
Table 3-1. Edge Connector Device ID
Edge Connector P1 Resistor Installed R19 R20 (default) R21 R22 (default) R23 R24 R25 (default) R26 R27 Slot ID 0 4 (default) 8 1 (default) 5 9 2 (default) 6 A
P2
P3
The interrupts for each connector on the secondary bus are routed according to the PCI Local Bus Specification 2.2, subsection 2.2.6. Table 3-2 depicts how the interrupts are routed on the EVM2050A evaluation board.
Table 3-2. Edge Connector Interrupt Routing
Edge Connector P1 Interrupt INTA INTB INTC INTD INTA INTB INTC INTD INTA INTB INTC INTD Routed on INTX on PI INTA INTB INTC INTD INTB INTC INTD INTA INTC INTD INTA INTB
P2
P3
3-2
Chapter 4
Board Configuration
This chapter describes the location and purpose of board components such as pins, jumpers, connectors, and LEDs.
Topic
4.1 4.2 4.3 4.4 4.5 4.6 4.7
Page
Board Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 PCI2050 Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Undetected Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Mictor Connector Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Board Configuration
4-1
Board Jumpers
4.1 Board Jumpers
Built into the evaluation board is the ability to monitor and test all the capabilities of the PCI2050. There are many jumpers located on the evaluation board (J1 through J9) which allow an engineer to perform tests ranging from measuring power to changing the arbitration of the PCI2050. All of these jumpers are defined in Table 4-1.
Table 4-1. Jumper Definitions
Jumper J1 J2 and J3 J4 J5 J6 J7 J8 J9 Description This four-pin jumper header is used either to test or to set the signal level of the four general-purpose I/O terminals on the PCI2050. Jumpers J2 and J3 are used to control the mode-select inputs to the PCI2050. This five-pin jumper header is used to access the JTAG interface on the PCI2050. Arbitration support. By cutting the trace across this jumper and installing R5, an external arbiter can be used. S_VCCP for the PCI2050. This jumper can be used to measure the power consumed through the S_VCCP. P_VCCP for the PCI2050. This jumper can be used to measure the power consumed through the P_VCCP. Core VCC for the PCI2050. This jumper can be used to measure the power consumed by the PCI2050 core logic. S_VIO select. This jumper is used to select between 3.3-V and 5-V signaling environments on the secondary bus.
4-2
PCI2050 Mode Select Pins
4.2 PCI2050 Mode Select Pins
The PCI2050 has three modes of operation based on the value of the mode select pins MS0/MS1. Table 4-2 shows the jumper settings for the different modes of operation.
Table 4-2. Mode Select Jumper Settings
J3 2-3 2-3 1-2 J2 2-3 1-2 X Mode TI hot-swap TI power management Intel 21150 mode
4.2.1
CompactPCITM Hot-Swap
When hot-swap mode is selected, the GPIO3 test point can be used to control HS_SWITCH.
Board Configuration
4-3
LED Indicators
4.3 LED Indicators
4.3.1 D1 ENUM
When the PCI2050 is configured in CompactPCI mode, this LED indicator lights when the ENUM signal is driven low.
4.3.2
D2 HSLED
When the PCI2050 is configured in CompactPCI mode, this LED indicator lights when the HSLED signal is driven low.
4.3.3
D3 C1_PRES
D3 lights when a PCI board that has the PRSNT2 pin tied to ground is inserted in connector P1.
4.3.4
D4 C2_PRES
D4 lights when a PCI board that has the PRSNT2 pin tied to ground is inserted in connector P2.
4.3.5
D5 C3_PRES
D5 lights when a PCI board that has the PRSNT2 pin tied to ground is inserted in connector P3.
4.3.6
D6 EVM3V
D6 lights to indicate that 3.3 V is available on the secondary bus.
4.3.7
D7 PCU3V
D7 lights to indicate that the PCI2050 has power applied to the core logic.
4-4
Power Measurements
4.4 Power Measurements
In order to measure the current drawn by the core logic or one of the VIO rails of the PCI2050, it is necessary to isolate the power supplied to these terminals from the rest of the system. This can be done by cutting the traces that connect the power terminals to the system. Jumpers J6, J7, and J8 have default traces that are provided for this purpose. After the traces are cut, an external power supply can be used along with a current meter to measure the current used by the selected power rail. The power rail can then be reconnected to the system by placing a jumper where the trace was cut.
4.5 Undetected Cards
The PCI2050 EVM board uses the PRSNT2 terminal to determine if a card is inserted in a socket, and to enable the clock to that socket. If the PRSNT2 terminal is not connected to GND before reset is deasserted, then the clock to that socket is disabled and the card will not be configured. The present LEDs C1_PRES, C2_PRES, and C3_PRES indicate whether the PRSNT2 terminal on a board is connected to ground. If the present LED for a slot is off, the clock to that socket is not enabled. If a card cannot be seen by the system when it is inserted in the PCI2050 EVM board and the present LED for that socket is on, the user should check the secondary clock control register at PCI offset 68h to determine if the clock to the socket is enabled. A bit set to 0 indicates that the corresponding clock is turned on. Table 4-3 shows the relationship of the bits in the secondary clock control register and the clock to each socket. If the clock is not enabled, a blue wire can be placed on the PCI2050 EVM board from the PRSNT2 terminal on the socket to ground, forcing the clock to turn on. PRSNT2 is terminal B11 on the PCI socket.
Table 4-3. Socket Clock Control Bits
Socket Number P1 P2 P3 Secondary Clock Control Register Bits 0, 1 2, 3 4, 5
Board Configuration
4-5
Mictor Connector Definition
4.6 Mictor Connector Definition
Connectors MC1 and MC2 can be used to connect a logic analyzer to the secondary PCI bus. See Table 4-4 for a listing of the signals for each logic analyzer POD.
Table 4-4. HP Logic Analyzer POD Definition
Pin Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Note:
POD 1 S_AD0 S_AD1 S_AD2 S_AD3 S_AD4 S_AD5 S_AD6 S_AD7 S_AD8 S_AD9 S_AD10 S_AD11 S_AD12 S_AD13 S_AD14 S_AD15
POD 2 S_AD16 S_AD17 S_AD18 S_AD19 S_AD20 S_AD21 S_AD22 S_AD23 S_AD24 S_AD25 S_AD26 S_AD27 S_AD28 S_AD29 S_AD30 S_AD31
POD 3 S_PAR S_SERR S_PERR S_STOP S_DEVSEL S_C/BE0 S_C/BE1 S_C/BE2 S_C/BE3 S_RST INTA INTB INTC INTD NC NC
POD 4 S_REQ64 S_ACK64 C1_INDSEL C1_GNT C1_REQ C2_IDSEL C2_GNT S_FRAME S_IRDY C2_REQ S_TRDY C3_IDSEL C3_GNT C3_REQ NC NC
The secondary bus clock is connected to the POD 3 clock line. This clock must be enabled in the clock control register.
4-6
Board Description
4.7 Board Description
The board layout is shown in Figure 4-1. The schematic diagram of the board is in Figure 4-2. Table 4-5, Bill of Materials, is a list of the parts used to assemble the board.
Figure 4-1. Part and Jumper Locations
P2B1
11 10 9 S_AD11 S_AD10 S_AD09 3 2 1 S_AD03 S_AD02 S_AD01 11 10 9 S_AD27 S_AD26 S_AD25 3 2 1 S_AD19 S_AD18 S_AD17 11 10 9 INTB INTA S_RST 3 2 1 S_STOP S_PERR S_SERR 11 10 9 C3_IDSEL S_TRDY C2_REQ 3 2 1 C1_GNT C1_IDSEL S_ACK64 13 12 15 14 POD1 8 S_AD08 0 S_AD00 8 S_AD24 0 S_AD16 8 S_C/BE3 0 S_PAR 8 S_IRDY 0 S_REQ64
S_AD13 S_AD12 5 4 S_AD05 S_AD04 13 12 S_AD29 S_AD28 5 4 S_AD21 S_AD20 13 12 INTD INTC 5 4 S_C/BE0 S_DEVSEL 13 12 C3_REQ C3_GNT 5 4 C2_IDSEL C1_REQ
S_AD15 S_AD14 7 6 S_AD07 S_AD06 15 14 S_AD31 S_AD30 7 6 S_AD23 S_AD22 15 14 NC MSK_IN 7 6 S_C/BE2 S_C/BE1 15 14 NC NC 7 6 S_FRAME C2_GNT POD 3 CLK C1_PCLK
D1
ENUM
P3B1
HSLED POD2 POD3 POD4
D2 D3
C1_PRES
P3A1
D4
C2_PRES
P1A1 P1B1 MC1 MC2
D5
C3_PRES
D6
EVM3V
D7
PCU3V
POD1 & POD2
POD3 & POD4
U4
EVM3V S_VIO EVM5V
J8
PCU3V EVM3V
U1 J4
TCLK TDI TDO TMS TRST
U3 U2
J9 TP2
EVM3V
TP3
GND
J1
GPIO0 GPIO1 GPIO2 GPIO3 GND MS1/BPCC
J2 J3
GND MSO S_VIO
J6
S_CFN GND S_VCCP
J5
J7
P_VCCP
S_VIO
TP1
EVM5V
P4B1
Board Configuration
4-7
4-8
EVM3V S_VIO EVM12V EVM5V EVM-12V S_AD[0..31] S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR# S_C/BE#[0..3] S_IRDY# S_RST# S_FRAME# S_LOCK# S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR# P1B1 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# RESERVED GND CLK GND REQ# +V I/O AD[31] AD[29] GND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GND AD[12] AD[10] GND AD[08] AD[07] +3.3V AD[05] AD[03] GND AD[01] +V I/O ACK64# +5V +5V PCI Connector B P1A1 TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +V I/O RESERVED RESERVED RST# +V I/O GNT# GND RESERVED AD[30] +3.3V AD[28] AD[26] GND AD[24] IDSEL +3.3V AD[22] AD[20] GND AD[18] AD[16] +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD[15] +3.3V AD[13] AD[11] GND AD[09] EVM3V S_VIO EVM12V EVM5V EVM-12V S_C/BE#[0..3] S_IRDY# S_RST# S_FRAME# S_LOCK# C1_CLK C1_REQ# S_AD31 S_AD29 C1_REQ# C1_GNT# C1_CLK C1_IDSEL C1_PRES C1_REQ# C1_GNT# C1_CLK C1_IDSEL C1_PRES S_AD27 S_AD25 S_C/BE#3 S_AD23 S_AD21 S_AD19 S_AD17 S_C/BE#2 S_IRDY# S_DEVSEL# S_LOCK# S_PERR# S_SERR# S_C/BE#1 S_AD14 S_AD12 S_AD10 C1_PRES 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 S_RST# C1_GNT# S_AD30 S_AD28 S_AD26 S_AD24 C1_IDSEL S_AD22 S_AD20 S_AD18 S_AD16 S_FRAME# S_TRDY# S_STOP# S_PAR S_AD15 S_AD13 S_AD11 S_AD9 S_C/BE#0 S_AD6 S_AD4 S_AD2 S_AD0 S_REQ64# S_AD8 S_AD7 S_AD5 S_AD3 S_AD1 S_ACK64# C/BE[0]# +3.3V AD[06] AD[04] GND AD[02] AD[00] +V I/O REQ64# +5V +5V PCI Connector A INTA# INTB# INTC# INTD# INTA INTB INTC INTD
Board Description
EVM5V C1 .1uF C2 .1uF C3 .1uF C4 .1uF C5 .1uF
EVM3V C6 .1uF C7 .1uF C8 .1uF C9 .1uF C10 .1uF
S_VIO C11 .1uF C12 .1uF C13 .1uF
EVM12V C14 .1uF
S_ACK64# S_REQ64#
S_ACK64# S_REQ64#
Figure 4-2. Schematic Diagram (Sheet 1 of 8)
EVM5V EVM3V S_VIO EVM12V EVM5V EVM-12V S_AD[0..31] S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR# S_C/BE#[0..3] S_IRDY# S_RST# S_FRAME# S_LOCK# C2_CLK C2_REQ# S_AD31 S_AD29 C2_REQ# C2_GNT# C2_CLK C2_IDSEL C2_PRES S_AD27 S_AD25 S_C/BE#3 S_AD23 S_AD21 S_AD19 S_AD17 S_C/BE#2 S_IRDY# S_DEVSEL# S_LOCK# S_PERR# S_SERR# S_C/BE#1 S_AD14 S_AD12 S_AD10 P1B2 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# RESERVED GND CLK GND REQ# +V I/O AD[31] AD[29] GND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GND AD[12] AD[10] GND AD[08] AD[07] +3.3V AD[05] AD[03] GND AD[01] +V I/O ACK64# +5V +5V PCI Connector B P1A2 TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +V I/O RESERVED RESERVED RST# +V I/O GNT# GND RESERVED AD[30] +3.3V AD[28] AD[26] GND AD[24] IDSEL +3.3V AD[22] AD[20] GND AD[18] AD[16] +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD[15] +3.3V AD[13] AD[11] GND AD[09] S_ACK64# C/BE[0]# +3.3V AD[06] AD[04] GND AD[02] AD[00] +V I/O REQ64# +5V +5V PCI Connector A S_REQ64# EVM3V C20 .1uF C21 .1uF C22 .1uF C23 .1uF C24 .1uF C15 .1uF C16 .1uF C17 .1uF C18 .1uF C19 .1uF
C2_PRES
1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62
1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62
S_VIO C25 .1uF C26 .1uF C27 .1uF
EVM12V C28 .1uF
S_RST# C2_GNT# S_AD30 S_AD28 S_AD26 S_AD24 C2_IDSEL S_AD22 S_AD20 S_AD18 S_AD16 S_FRAME# S_TRDY# S_STOP#
S_PAR S_AD15 S_AD13 S_AD11 S_AD9 S_C/BE#0 S_AD6 S_AD4 S_AD2 S_AD0 S_REQ64#
S_AD8 S_AD7
Board Configuration
4-9
S_AD5 S_AD3 S_AD1 S_ACK64#
INTB# INTC# INTD# INTA#
INTA
Board Description
INTB INTC INTD
Figure 4-2. Schematic Diagram (Sheet 2 of 8)
4-10
S_IRDY# S_RST# C3_REQ# C3_GNT# C3_CLK
Board Description
EVM3V S_VIO EVM12V EVM5V EVM-12V S_AD[0..31] S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR# S_C/BE#[0..3]
EVM3V S_VIO EVM12V EVM5V EVM-12V S_AD[0..31] S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR#
EVM5V C29 .1uF C30 .1uF C31 .1uF C32 .1uF C33 .1uF
EVM3V C34 .1uF 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 P1B3 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# RESERVED GND CLK GND REQ# +V I/O AD[31] AD[29] GND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GND AD[12] AD[10] GND AD[08] AD[07] +3.3V AD[05] AD[03] GND AD[01] +V I/O ACK64# +5V +5V PCI Connector B 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 P1A3 TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +V I/O RESERVED RESERVED RST# +V I/O GNT# GND RESERVED AD[30] +3.3V AD[28] AD[26] GND AD[24] IDSEL +3.3V AD[22] AD[20] GND AD[18] AD[16] +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD[15] +3.3V AD[13] AD[11] GND AD[09] S_ACK64# S_AD8 S_AD7 S_AD5 S_AD3 S_AD1 S_ACK64# S_C/BE#0 S_AD6 S_AD4 S_AD2 S_AD0 S_REQ64# C/BE[0]# +3.3V AD[06] AD[04] GND AD[02] AD[00] +V I/O REQ64# +5V +5V PCI Connector A S_REQ64# S_ACK64# S_REQ64# C35 .1uF C36 .1uF C37 .1uF C38 .1uF
S_VIO C39 .1uF C40 .1uF C41 .1uF
S_C/BE#[0..3] S_IRDY# S_RST# S_FRAME# S_LOCK# C3_CLK C3_REQ# S_AD31 S_AD29 C3_REQ# C3_GNT# C3_CLK C3_IDSEL C3_PRES S_AD27 S_AD25 S_C/BE#3 S_AD23 S_AD21 S_AD19 S_AD17 S_C/BE#2 S_IRDY# S_DEVSEL# S_LOCK# S_PERR# S_SERR# S_C/BE#1 S_AD14 S_AD12 S_AD10
EVM12V C42 .1uF
C3_PRES
S_FRAME# S_LOCK#
S_RST# C3_GNT# S_AD30 S_AD28 S_AD26 S_AD24 C3_IDSEL S_AD22 S_AD20 S_AD18 S_AD16 S_FRAME# S_TRDY# S_STOP#
C3_IDSEL C3_PRES
S_PAR S_AD15 S_AD13 S_AD11 S_AD9
INTC# INTD# INTA# INTB#
INTA INTB INTC INTD
Figure 4-2. Schematic Diagram (Sheet 3 of 8)
S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24 S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16
MC1 1 NC1 3 NC3 5 CLKe 7 D15e 9 D14e 11 D13e 13 D12e 15 D11e 17 D10e 19 D9e 21 D8e 23 D7e 25 D6e 27 D5e 29 D4e 31 D3e 33 D2e 35 D1e 37 D0e
NC2 NC4 CLKo D15o D14o D13o D12o D11o D10o D9o D8o D7o D6o D5o D4o D3o D2o D1o D0o
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
S_AD[0..31] S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD9 S_AD8 S_AD7 S_AD6 S_AD5 S_AD4 S_AD3 S_AD2 S_AD1 S_AD0 S_C/BE#[0..3]
S_AD[0..31] S_C/BE#[0..3]
S_RST# S_FRAME# S_IRDY# S_PERR# S_SERR# S_DEVSEL# S_PAR S_TRDY# S_STOP# C1_IDSEL C1_REQ# C1_GNT# C2_IDSEL C2_REQ# C2_GNT# C3_IDSEL C3_REQ# C3_GNT# S_CLKOUT3
MICTOR CONNECTOR Note: 5 thru-holes are GNDs MC2 1 NC1 3 NC3 5 CLKe 7 D15e 9 D14e 11 D13e 13 D12e 15 D11e 17 D10e 19 D9e 21 D8e 23 D7e 25 D6e 27 D5e 29 D4e 31 D3e 33 D2e 35 D1e 37 D0e
C3_REQ# C3_GNT# C3_IDSEL S_TRDY# C2_REQ# S_IRDY# S_FRAME# C2_GNT# C2_IDSEL C1_REQ# C1_GNT# C1_IDSEL S_ACK64# S_REQ64#
NC2 NC4 CLKo D15o D14o D13o D12o D11o D10o D9o D8o D7o D6o D5o D4o D3o D2o D1o D0o
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
R1
MSK_IN INTD# INTC# INTB# INTA# S_RST# S_C/BE#3 S_C/BE#2 S_C/BE#1 S_C/BE#0 S_DEVSEL# S_STOP# S_PERR# S_SERR# S_PAR
0
INTA# INTB# INTC# INTD# MSK_IN S_REQ64# S_ACK64#
Board Configuration
4-11
MICTOR CONNECTOR Note: 5 thru-holes are GNDs
Board Description
Figure 4-2. Schematic Diagram (Sheet 4 of 8)
S_VIO
EVM3V R2 10K GPIO0 GPIO1 GPIO2 GPIO3 1 2 3 4 J1 J2 1 2 3 HDR4X1 M .1 S_VIO S_VIO R5 HDR3X1 M .1 MS1 MS0
EVM3V
.01uF S_REQ#3 S_GNT#3 S_REQ#4 S_GNT#4 S_REQ#5 S_GNT#5 S_REQ#6 S_GNT#6 S_REQ#7 S_GNT#7 S_REQ#8 S_GNT#8 R31 R32 R33 R34 R35 R36 R37 R39 R42 R43 R46 R48 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K S_VIO EVM5V
D0 D1 D2 D3 D4 D5 D6 D7
Q7
S_REQ#2 S_GNT#2
R29 R30
10K 10K
U1 C44 2 3 4 5 10 11 12 14
13
DS
1
13
C1_PRES C2_PRES C3_PRES
D0 D1 D2 D3 D4 D5 D6 D7
Q7
DS
1
4-12
Board Description
J3 1 2 3 HDR3X1 M .1
HS_ENUM#
S_ACK64# S_REQ64#
R3 R4
10K 10K
S_FRAME# S_IRDY# S_TRDY# S_DEVSEL# S_STOP# S_LOCK# S_PERR# S_SERR# S_RST# GPIO3
R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
10K 10K 10K 10K 10K 10K 10K 10K 10K 10K
S_VIO S_CFN# S_CFN#
47-NF 1 J5 2 TCLK TDI TDO TMS TRST#
C43 .01uF
HDR2X1 M .1 -NF
1 2 3 4 5
J4
HDR5X1 M .1 Default Trace S_AD[0..31]
INSTALL ONLY ONE RESISTOR / IDSEL
S_AD16
S_AD24
S_AD17
S_AD21
S_AD25
S_AD20
S_AD18
S_AD22
S_AD26
S_REQ#0 S_GNT#0 S_REQ#1 S_GNT#1
R16 R17 R18 R28
10K 10K 10K 10K S_VIO
MSK_IN R19 74F166 6 CE# 7 CP 9 MR# 15 PE# VCC GND 16 8 47 R20 R21 R22 R23 R24 47 R25 47 R26 47-NF R27 47-NF 47-NF 47-NF 47-NF 47-NF
GPIO0 GPIO2 EVM5V C1_IDSEL C2_IDSEL C3_IDSEL C1_IDSEL C2_IDSEL C3_IDSEL
74F166
C45
C46 S_CLKOUT0 S_REQ#0 S_GNT#0 S_CLKOUT1 S_REQ#1 S_GNT#1 S_CLKOUT2 S_REQ#2 S_GNT#2 R38 R40 R41 R44 R45 R47 R49 R50 R51
.01uF .01uF 74F166 C47 .01uF 2 3 4 5 10 11 12 14 U2 6 CE# 7 CP 9 MR# 15 PE# VCC GND 16 8 C48 C49
0 0 0 0 0 0 0 0 0
C1_CLK C1_REQ# C1_GNT# C2_CLK C2_REQ# C2_GNT# C3_CLK C3_REQ# C3_GNT#
GPIO0 GPIO2 EVM5V
74F166
.01uF .01uF
S_LOCK# S_FRAME# S_IRDY# S_TRDY# S_DEVSEL# S_STOP# S_PERR# S_RST# S_ACK64# S_REQ64# S_SERR#
EVM5V C50 C51 C52 C53 C54 C55 C56 C57 C58 C59
.01uF .01uF .01uF .01uF .01uF .01uF .01uF .01uF .01uF .01uF
P_LOCK#
PULL-UP
INTERFACE & CONTROL
MODE
Figure 4-2. Schematic Diagram (Sheet 5 of 8)
P_VCCP PCI12V PCI5V PCI-12V P_AD[0..31] P_DEVSEL# P_TRDY# P_STOP# P_PAR
P_VCCP PCI12V PCI5V PCI-12V
P_AD[0..31] P_DEVSEL# P_TRDY# P_STOP# P_PAR
P_TDO
P1B4 1 2 3 4 5 6 7 8 9 10 11 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# 1 2 3 4 5 6 7 8 9 10 11
P1A4 TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +V I/O RESERVED
P_C/BE#[0..3]
P_C/BE#[0..3]
P_IRDY# P_IDSEL P_FRAME#
P_TDI
P_IRDY# P_IDSEL P_FRAME#
P_REQ# P_GNT# P_PERR# P_SERR#
P_GNT# P_PERR# P_SERR#
P_LOCK#
P_LOCK# P_RST# P_PCLK
P_PCLK P_REQ# P_AD31 P_AD29 P_AD27 P_AD25 P_C/BE#3 P_AD23 P_AD21 P_AD19 P_AD17 P_C/BE#2 P_IRDY# P_DEVSEL# P_LOCK# P_PERR# P_SERR# P_C/BE#1 P_AD14 P_AD12 P_AD10
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
RESERVED GND CLK GND REQ# +V I/O AD[31] AD[29] GND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GND AD[12] AD[10] GND
P_RST# P_GNT#
P_AD30 P_AD28 P_AD26 P_AD24 P_IDSEL P_AD22 P_AD20 P_AD18 P_AD16 P_FRAME# P_TRDY# P_STOP#
P_PAR P_AD15 P_AD13 P_AD11 P_AD9
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
P_RST# P_PCLK
RESERVED RST# +V I/O GNT# GND RESERVED AD[30] +3.3V AD[28] AD[26] GND AD[24] IDSEL +3.3V AD[22] AD[20] GND AD[18] AD[16] +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD[15] +3.3V AD[13] AD[11] GND AD[09]
Board Configuration
4-13
P_AD8 P_AD7 P_AD5 P_AD3 P_AD1
52 53 54 55 56 57 58 59 60 61 62
AD[08] AD[07] +3.3V AD[05] AD[03] GND AD[01] +V I/O ACK64# +5V +5V PCI Connector B
P_C/BE#0 P_AD6 P_AD4 P_AD2 P_AD0
52 53 54 55 56 57 58 59 60 61 62
C/BE[0]# +3.3V AD[06] AD[04] GND AD[02] AD[00] +V I/O REQ64# +5V +5V
Board Description
PCI Connector A
INTA# INTB# INTC# INTD#
INTA INTB INTC INTD
Figure 4-2. Schematic Diagram (Sheet 6 of 8)
S_CLKOUT0 S_CLKOUT1 S_CLKOUT2 S_CLKOUT3
HSLED HS_ENUM#
MSK_IN
GPIO0 GPIO1 GPIO2 GPIO3
MS0 MS1
R52
128 127
126
155 106
102 125
12 20 31 37 44 48 52 54 59 66 72 78 86 94 100 104 111 117 123 136 142 148 156 158 160 166 174 181 187 193 199 205
PCI2050 28 27 25 24 U3
GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31
GPIO0 GPIO1 GPIO2 GPIO3/HSSWITCH
SCLKOUT0 SCLKOUT1 SCLKOUT2 SCLKOUT3 SCLKOUT4 SCLKOUT5 SCLKOUT6 SCLKOUT7 SCLKOUT8 SCLKOUT9
HSLED HSENUM#
MSK_IN
MS0 MS1
NC0 NC1
P_C/BE#3 P_C/BE#2 P_C/BE#1 P_C/BE#0 P_AD31 P_AD30 P_AD29 P_AD28 P_AD27 P_AD26 P_AD25 P_AD24 P_AD23 P_AD22 P_AD21 P_AD20 P_AD19 P_AD18 P_AD17 P_AD16 P_AD15 P_AD14 P_AD13 P_AD12 P_AD11 P_AD10 P_AD9 P_AD8 P_AD7 P_AD6 P_AD5 P_AD4 P_AD3 P_AD2 P_AD1 P_AD0
PRIMARY PCI
P_C/BE#[0..3]
SECONDARY PCI
S_REQ#0 S_REQ#1 S_REQ#2 S_REQ#3 S_REQ#4 S_REQ#5 S_REQ#6 S_REQ#7 S_REQ#8
133 129 130 132 134
1 26 34 40 51 53 56 62 69 75 81 91 97 103 105 108 114 120 131 139 145 151 157 163 170 178 184 190 196 202 208
124 135
207 2 3 4 5 6 7 8 9
23
10 11 13 14 15 16 17 18 19
S_GNT#0 S_GNT#1 S_GNT#2 S_GNT#3 S_GNT#4 S_GNT#5 S_GNT#6 S_GNT#7 S_GNT#8
S_CFN#
VCC_P VCC_S
VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30
TCLK TDI TDO TMS TRST#
4-14
P_RST# P_FRAME# P_DEVSEL# P_IRDY# P_TRDY# P_STOP# P_LOCK# P_PAR P_IDSEL P_GNT# P_REQ# P_PERR# P_SERR# R53 75 P_PCLK C60 15pF P_AD[0..31] C62 .1uF C63 .1uF C64 .1uF C65 .1uF C66 .1uF C67 .1uF C68 .1uF
Board Description
29 30 32 33 35 36 38 39 41 42
0
43 45 80 84 82 83 85 87 90 65 46 47 88 89 64 79 92 110 49 50 55 57 58 60 61 63 67 68 70 71 73 74 76 77 93 95 96 98 99 101 107 109 112 113 115 116 118 119 121 122
P_RST# P_CLK P_FRAME# P_DEVSEL# P_IRDY# P_TRDY# P_STOP# P_LOCK# P_PAR P_IDSEL P_GNT# P_REQ# P_PERR# P_SERR# P_CBE#3 P_CBE#2 P_CBE#1 P_CBE#0 P_AD31 P_AD30 P_AD29 P_AD28 P_AD27 P_AD26 P_AD25 P_AD24 P_AD23 P_AD22 P_AD21 P_AD20 P_AD19 P_AD18 P_AD17 P_AD16 P_AD15 P_AD14 P_AD13 P_AD12 P_AD11 P_AD10 P_AD9 P_AD8 P_AD7 P_AD6 P_AD5 P_AD4 P_AD3 P_AD2 P_AD1 P_AD0
S_RST# S_CLK S_FRAME# S_DEVSEL# S_IRDY# S_TRDY# S_STOP# S_LOCK# S_PAR S_PERR# S_SERR# S_M66EN S_CBE#3 S_CBE#2 S_CBE#1 S_CBE#0 S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24 S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16 S_AD15 S_AD14 S_AD13 A_AD12 S_AD11 S_AD10 S_AD9 S_AD8 S_AD7 S_AD6 S_AD5 S_AD4 S_AD3 S_AD2 S_AD1 S_AD0
22 21 179 175 177 176 173 172 168 171 169 153 194 180 167 149 206 204 203 201 200 198 197 195 192 191 189 188 186 185 183 182 165 164 162 161 159 154 152 150 147 146 144 143 141 140 138 137 S_C/BE#3 S_C/BE#2 S_C/BE#1 S_C/BE#0 S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24 S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16 S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD9 S_AD8 S_AD7 S_AD6 S_AD5 S_AD4 S_AD3 S_AD2 S_AD1 S_AD0
S_RST# S_FRAME# S_DEVSEL# S_IRDY# S_TRDY# S_STOP# S_LOCK# S_PAR S_PERR# S_SERR#
MISC
GND
CLOCKS
S_C/BE#[0..3]
S_AD[0..31]
PCI2050
JTAG
POWER
ARBITER
Default Trace J6
1 S_REQ#8 S_REQ#7 S_REQ#6 S_REQ#5 S_REQ#4 S_REQ#3 S_REQ#2 S_REQ#1 S_REQ#0 S_GNT#8 S_GNT#7 S_GNT#6 S_GNT#5 S_GNT#4 S_GNT#3 S_GNT#2 S_GNT#1 S_GNT#0
2
S_CFN#
S_VIO
TRST# TMS TDO TDI TCLK PCU3V
HDR2X1 M .1-NF
C61 .1uF
Default Trace C69 .1uF C70 .1uF C71 .1uF C72 .1uF C73 .1uF C74 .1uF C75 .1uF C76 .1uF C77 .1uF C78 .1uF C79 .1uF C80 .1uF C81 .1uF C82 .1uF C83 .1uF C84 .1uF C85 .1uF C86 .1uF C87 .1uF C88 .1uF C89 .1uF C90 .1uF C91 1 .1uF HDR2X1 M .1-NF J7 2 P_VCCP C92 .1uF
Figure 4-2. Schematic Diagram (Sheet 7 of 8)
TP1 TP2
EVM5V C93 15uF
3 1
U4 IN OUT ADJ LT1086C
2 R54 121 2 C94 15uF
F1 EVM3V Default Trace 15uF F2 PCI-12V 1 FUSE R55 196 C97 PCU3V .1uF EVM-12V .1uF PCI12V FUSE J8 C95 C96 EVM12V
HDR2X1 M .1-NF
F3 PCI5V FUSE TP3 C98 47uF C99 .1uF HDR3X1 M .1 SHORTED 15uF EVM5V J9 3 2 1 EVM3V EVM5V C100 S_VIO
EVM3V
R56
330
D1 HS_ENUM# Red D2 HSLED BLUE
EVM3V
R57
330
S_VIO
R58
D3 330 Yellow C1_PRES
S_VIO
R59
330
D4 C2_PRES Yellow
S_VIO
R60
330
D5 C3_PRES Yellow D6 Green D7 Green
EVM3V
R61
330
Board Configuration
4-15
PCU3V
R62
330
Board Description
Figure 4-2. Schematic Diagram (Sheet 8 of 8)
Board Description
Table 4-5. PCI2050 EVM Bill of Materials
Item Qty
1 77
Reference
C1 - C42, C61 - C92, C96, C97, C99 C43 - C59 C60 C93,C94, C95, C100 C98 D1
Part
0.1 F 0.01 F 15 pF 15 F 47 F Red
Pkg
805
MFG
Phillips
Part No.
08052R104K9BB0
2 3 4 5 6
17 1 4 1 1
805 805 6032 6032 See Diagram See Diagram See Diagram See Diagram TH
MMC MMC NIC NIC Lumex
CE103K2NR CE150J2NO NTC-T156K20TRC NTC-T476K6.3TRC
7
1
D2
Red
Lumex
8
3
D3, D4, D5
Yellow
Lumex
9
2
D6,D7
Green
Lumex
10 11
3 1
F1, F2, F3 J1
FUSE HDR4X1 M 0.1 nF HDR3X1 M 0.1 nF HDR2X1 M 0.1 nF HDR5X1 M 0.1 nF Mictor Connector
LittleFuse AMP
251.75 103321-4
12
3
J2,J3,J9
AMP
103321-3
13
4
J5 - J8
AMP
103321-2
14
1
J4
AMP
103321-5
15
2
MC2, MC1
AMP
2-767004-2
16 17 18
2 1 31
P1A1/P1B1, P1A3/P1B3 P1A2/P1B2 R2 - R4, R6 - R18, R28 - R37, R39, R41, R42, R45, R47 R5, R19, R21, R22, R23, R26, R27 R1, R38, R40, R43, R44, R46, R48, R49, R50, R51 R20, R24, R25 R52 R53 R54 R55 - R61 TP1, TP2, TP3
PCI Connector N/A PCI Connector N/A 10K 805
AMP Capstone KOA
145154-8 CEE2X60SMV-3Z14W RM73B2A103J
19
7
47 nF
805
KOA
RM73B2A470J
20
10
0
805
KOA
RM73Z2A000
21 22 23 24 25 26
3 1 1 1 7 3
47 75 121 196 330 TEST POINT
805 805 TH TH 805
KOA KOA NIC NIC KOA AMP
RM73B2A470J RM73B2A750J NMR25F1210B NMR25F1960B RM73B2A331J
4-16
Board Description
Table 4-5. PCI2050 EVM Bill of Materials (Continued)
Item Qty
27 2
Reference
U1, U2
Part
74F166
Pkg
See Drawing See Drawing TO-220
MFG
Philips Semiconductor Texas Instruments DigiKey
Part No.
74F166
28
1
U3
PCI2050
PCI2050
29
1
U4
LT1086C
LT1086C
Board Configuration
4-17
4-18

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