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| PCI2250 Evaluation Module User's Guide 2000 PCI Bus Solutions SCPU005 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated Information About Cautions and Warnings Preface Read This First About This Manual This manual is designed to assist the user of the PCI2250 evaluation module (EVM). It provides descriptions of parts, features, and operating requirements of the EVM that are necessary or useful to obtain maximum benefit from EVM use. How to Use This Manual This document contains the following chapters: Chapter 1, Introduction, provides a brief description of the EVM, and a bill of materials for the EVM kit. Chapter 2, Software Requirements, details the minimum software requirements for any PC system on which the PCI2250 EVM is to be run. Chapter 3, Configuration, explains secondary bus masters and interrupt routing as related to the edge connectors on the board. Chapter 4, Board Configuration, describes the location and purpose of board components such as pins, jumpers, connectors, and LEDs. Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. Read This First iii Trademarks The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments PCI2250 PCI-to-PCI Bridge Data Manual, TI Literature Number - SCPS051 PCI2250 Implementation Guide, SCPU008 Connecting ENUM Terminal to an External Open-Drain Buffer, TI Literature Number - SCPA027 FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Trademarks Intel is a trademark of Intel Corporation. Windows is a trademark of Microsoft Corporation. (WindowsTM 95, WindowsTM) Windows NT is a trademark of Microsoft Corporation. (Windows NTTM ) CompactPCI is a trademark of PICMG - PCI Industrial Computer Manufacturers Group, Inc. Other trademarks are the property of their respective owners. iv Running Title--Attribute Reference Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Evaluation Kit Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Board Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Board Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 PCI2250 Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Clock Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 CompactPCITM Hot Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 IntelTM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 D1 ENUM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 D2 HSLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 D3 C1_PRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 D4 C2_PRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 D5 C3_PRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 D6 EVM3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 D7 PCU3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Mictor Connector Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2 4-3 4-3 4-3 4-3 4-4 4-4 4-4 4-4 4-4 4-4 4-4 4-4 4-4 4-5 4-6 2 3 4 Chapter Title--Attribute Reference v Running Title--Attribute Reference Figures 4-1 4-2 Part and Jumper Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Tables 3-1 3-2 4-1 4-2 4-3 4-4 Edge Connector Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Edge Connector Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Jumper Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Mode Select Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 HP Logic Analyzer POD Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 PCI2250 EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 vi Chapter 1 Introduction This chapter provides a brief overview of the PCI2250 evaluation module, along with a bill of materials for the EVM kit. Topic 1.1 1.2 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Evaluation Kit Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-1 Introduction 1.1 Introduction This document is intended to assist the user of the PCI2250 evaluation module (EVM), EVM2250B. Included within this document are instructions detailing the proper setup and configuration necessary to operate the PCI2250 EVM. 1.2 Evaluation Kit Bill of Materials The PCI2250 EVM consists of the following items: Item EVM2250B 3.5" Diskette Nomenclature PCI to PCI adapter card assembly PCIBus and PCIBus95 utility programs Quantity 1 1 1-2 Chapter 2 Software Requirements This chapter provides the minimum software requirements for any PC system on which the PCI2250 EVM is to be used. Topic 2.1 Page Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Software Requirements 2-1 Software Requirements 2.1 Software Requirements The EVM2250B evaluation board will work in any system that meets the following requirements: - BIOS which supports the PCI Bridge Specification 1.0. - Operating system that supports the PCI Bridge Specification 1.0. In the majority of today's computer systems, bridge support is built into the BIOS. Many operation systems, like Windows 95/98TM and Windows NTTM, have support for bridges. 2-2 Chapter 3 Configuration This chapter explains secondary bus masters and interrupt routing as related to edge connectors on the board. Topic 3.1 Page Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Configuration 3-1 Configuration 3.1 Configuration The PCI2250 supports four secondary bus masters. Due to board space, only three masters are supported with the EVM2250B board. The three supported masters can be plugged into three edge connectors labeled P1, P2, and P3. These edge connectors are configured based on the Table 3-1. Table 3-1. Edge Connector Device ID Edge Connector P1 Resistor Installed R20 R21 (default) R22 R23 (default) R24 R25 R26 (default) R27 R28 Slot ID 0 4 (default) 8 1 (default) 5 9 2 (default) 6 A P2 P3 The interrupts for each connector on the secondary bus are routed according to the PCI Local Bus Specification Revision 2.2, section 2.2.6. Table 3-2 depicts how the interrupts are routed on the EVM2250B evaluation board. Table 3-2. Edge Connector Interrupt Routing Edge Connector P1 Interrupt INTA INTB INTC INTD INTA INTB INTC INTD INTA INTB INTC INTD Routed on INTX on P1 INTA INTB INTC INTD INTB INTC INTD INTA INTC INTD INTA INTB P2 P3 3-2 Chapter 4 Board Configuration This chapter describes the location and purpose of board components such as pins, jumpers, connectors, and LEDs. Topic 4.1 4.2 4.3 4.4 4.5 4.6 Page Board Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 PCI2250 Mode Select Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Power Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Mictor Connector Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Board Configuration 4-1 Board Jumpers 4.1 Board Jumpers Built into the evaluation board is the ability to monitor and test all the capabilities of the PCI2250. There are many jumpers located on the evaluation board (J1 through J12), which allow an engineer to perform tests ranging from measuring power to changing the arbitration of the PCI2250. All of these jumpers are defined in Table 4-1. Table 4-1. Jumper Definitions Jumper J1 J5 & J6 J7 J8 J9 J10 J11 J12 Description P_MFUNC select. This jumper is used to select whether to route P_MFUNC to P_LOCK or P_CLKRUN/HS_ENUM. Jumpers J5 and J6 are used to control the mode select inputs to the PCI2250. S_MFUNC select. This jumper is used to select whether to route S_MFUNC to S_LOCK or S_CLKRUN/HS_SWITCH. Arbitration support. By cutting the trace across this jumper and installing R10 an external arbiter can be used. S_VCCP for the PCI2250. This jumper can be used to measure the power consumed through the S_VCCP. P_VCCP for the PCI2250. This jumper can be used to measure the power consumed through the P_VCCP. Core VCC for the PCI2250. This jumper can be used to measure the power consumed by the PCI2250 core logic. S_VIO select. This jumper is used to select between 3.3-V and 5.0-V signaling environments on the secondary bus. 4-2 PCI2250 Mode Select Pins 4.2 PCI2250 Mode Select Pins The PCI2250 has three modes of operation based on the value of the mode select pins MS0 (J6-2) and MS1 (J5-2). Table 4-2 shows the jumper settings for the different modes of operation. Table 4-2. Mode Select Jumper Settings J6 2-3 2-3 1-2 1-2 J5 2-3 1-2 2-3 1-2 P_MFUNC HS_ENUM P_CLKRUN P_LOCK P_LOCK S_MFUNC HS_SWITCH S_CLKRUN S_LOCK S_LOCK Mode TI hot-swap TI clock run Intel B2 support Intel B3 support 4.2.1 Clock Run Mode When the PCI2250 is in clock run mode, jumpers J1 and J7 should not be jumpered. The clock run signals can be pulled directly from pin 2 of the jumper headers. 4.2.2 CompactPCITM Hot Swap When hot-swap mode is selected, jumpers J1 and J7 should have a jumper between pins 2 and 3, routing the multifunction pins to the CompactPCI test points. 4.2.3 IntelTM Mode When Intel mode is selected, jumpers J1 and J7 should have a jumper between pins 1 and 2, routing the multifunction pins to the LOCK pins on the connectors. Board Configuration 4-3 LED Indicators 4.3 LED Indicators 4.3.1 D1 ENUM When the PCI2250 is configured in CompactPCI mode, this LED lights when the ENUM signal is driven low. 4.3.2 D2 HSLED When the PCI2250 is configured in Compact PCI mode, this LED lights when the HSLED signal is driven low. 4.3.3 D3 C1_PRES D3 lights when a PCI board that has the PRSNT2 pin tied to ground is inserted in connector P1. 4.3.4 D4 C2_PRES D4 lights when a PCI board that has the PRSNT2 pin tied to ground is inserted in connector P2. 4.3.5 D5 C3_PRES D5 lights when a PCI board that has the PRSNT2 pin tied to ground is inserted in connector P3. 4.3.6 D6 EVM3V D6 lights to indicate that 3.3 V is available on the secondary bus. 4.3.7 D7 PCU3V D7 lights to indicate that the PCI2250 has power applied to the core logic. 4.4 Power Measurements In order to measure the current drawn by the core logic or one of the VIO rails of the PCI2250 it is necessary to isolate the power supplied to these pins from the rest of the system. This can be done by cutting the trace that connects the power pins to the system. Jumpers J6, J7, and J8 have default traces that are provided for this purpose. After the traces are cut, an external power supply can be used along with a current meter to measure the current used by the selected power rail. The power rail can then be reconnected to the system by placing a jumper across the cut trace. 4-4 Mictor Connector Definition 4.5 Mictor Connector Definition Connectors MC1 and MC2 can be used to connect a logic analyzer to the secondary PCI bus. See Table 4-3 for a listing of the signals for each logic analyzer POD. Table 4-3. HP Logic Analyzer POD Definition Pin Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 POD 1 S_AD0 S_AD1 S_AD2 S_AD3 S_AD4 S_AD5 S_AD6 S_AD7 S_AD8 S_AD9 S_AD10 S_AD11 S_AD12 S_AD13 S_AD14 S_AD15 POD 2 S_AD16 S_AD17 S_AD18 S_AD19 S_AD20 S_AD21 S_AD22 S_AD23 S_AD24 S_AD25 S_AD26 S_AD27 S_AD28 S_AD29 S_AD30 S_AD31 POD 3 S_PAR S_SERR S_PERR S_STOP S_DEVSEL S_C/BE0 S_C/BE1 S_C/BE2 S_C/BE3 S_RST INTA INTB INTC INTD NC NC POD 4 S_REQ64 S_ACK64 C1_IDSEL C1_GNT C1_REQ C2_IDSEL C2_GNT S_FRAME S_IRDY C2_REQ S_TRDY C3_IDSEL C3_GNT C3_REQ NC NC Board Configuration 4-5 The board layout is shown in Figure 4-1. The schematic diagram of the board is in Figure 4-2. Table 4-4, bill of materials, is a list of the parts used to assemble the board. TP3 GND D1 D2 D3 D4 D5 D6 D7 C1_PRES C2_PRES C3_PRES EVM3V ENUM PCU3V HSLED J5 J4 TP2 GND MS1/BPCC S_VIO MSO S_VIO GND U6 EVM3V S_VIO EVM5V EVM3V TP1 J10 J8 HS_SWITCH HS_ENUM S_MFUNC P_VCCP S_CFN GND S_LOCK POD3 & POD4 PCU3V EVM3V MC2 J11 Figure 4-1. Part and Jumper Locations POD1 & POD2 P_LOCK P_MFUNC U5 J12 4.6 Board Description MC1 P2B1 P3B1 P3A1 P4A1 POD1 15 14 13 12 11 10 9 8 S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD09 S_AD08 7 6 5 4 3 2 1 0 S_AD07 S_AD06 S_AD05 S_AD04 S_AD03 S_AD02 S_AD01 S_AD00 P4B1 POD2 15 14 13 12 11 10 9 8 S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24 7 6 5 4 3 2 1 0 S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16 POD3 15 14 13 12 11 10 9 8 NC NC INTD INDC INTB INTA S_RST C/BE3 7 6 5 4 3 2 1 0 S_C/BE2 S_C/BE1 S_C/BE0 S_DEVSEL S_STOP S_PERR S_SERR S_PAR POD4 15 14 13 12 11 10 9 8 NC NC C3_REQ C3_GNT C3_IDSEL S_TRDY C2_REQ S_IRDY 7 6 5 4 3 2 1 0 S_FRAME C2_GNT C2_IDSEL C1_REQ C1_GNT C1_IDSEL S_ACK64 S_REQ64 POD 3 CLK C1_PCLK Board Description J1 J7 S_VCCP P1B1 J9 EVM5V 4-6 EVM5V C1 .1uF .1uF .1uF .1uF C2 C3 C4 C5 .1uF EVM3V EVM3V S_VIO S_VIO EVM12V EVM3V C6 .1uF .1uF .1uF C7 C8 EVM12V EVM5V EVM5V EVM-12V EVM-12V C9 .1uF C10 .1uF S_AD[0..31] S_VIO C11 .1uF C12 .1uF C13 .1uF S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR# S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR# S_C/BE#[0..3] EVM12V S_C/BE#[0..3] S_IRDY# S_RST# C1_PRES S_IRDY# S_RST# 1 2 3 4 5 6 7 8 9 10 11 P1B1 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# 1 2 3 4 5 6 7 8 9 10 11 P1A1 TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +V I/O RESERVED C14 .1uF S_FRAME# S_RST# C1_GNT# S_AD30 S_AD28 S_AD26 S_AD24 C1_IDSEL S_AD22 S_AD20 S_AD18 S_AD16 S_FRAME# S_TRDY# S_STOP# C1_PCLK C1_REQ# S_AD31 S_AD29 S_AD27 S_AD25 S_C/BE#3 S_AD23 S_AD21 S_AD19 S_AD17 S_C/BE#2 S_IRDY# S_DEVSEL# S_LOCK# S_PERR# S_SERR# S_C/BE#1 S_AD14 S_AD12 S_AD10 S_AD13 S_AD11 S_AD9 S_C/BE#0 S_AD6 S_AD4 S_AD2 S_AD0 S_REQ64# S_PAR S_AD15 S_FRAME# S_LOCK# S_LOCK# C1_REQ# C1_GNT# C1_REQ# C1_GNT# C1_PCLK C1_PCLK C1_IDSEL C1_PRES C1_IDSEL C1_PRES 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 RESERVED GND CLK GND REQ# +V I/O AD[31] AD[29] GND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GND AD[12] AD[10] GND RESERVED RST# +V I/O GNT# GND RESERVED AD[30] +3.3V AD[28] AD[26] GND AD[24] IDSEL +3.3V AD[22] AD[20] GND AD[18] AD[16] +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD[15] +3.3V AD[13] AD[11] GND AD[09] 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 S_ACK64# S_AD8 S_AD7 S_AD5 S_AD3 S_AD1 S_ACK64# AD[08] AD[07] +3.3V AD[05] AD[03] GND AD[01] +V I/O ACK64# +5V +5V PCI Connector B 52 53 54 55 56 57 58 59 60 61 62 52 53 54 55 56 57 58 59 60 61 62 C/BE[0]# +3.3V AD[06] AD[04] GND AD[02] AD[00] +V I/O REQ64# +5V +5V PCI Connector A S_REQ64# S_ACK64# S_REQ64# INTA# INTB INTC INTD INTA INTB# INTC# Board Configuration INTD# Mictor Connector Definition Figure 4-2. Schematic Diagram (Sheet 1 of 8) 4-7 EVM5V C15 .1uF .1uF .1uF .1uF .1uF C16 C17 C18 C19 EVM3V 4-8 EVM3V C20 .1uF .1uF .1uF .1uF C21 C22 C23 C24 .1uF S_VIO C25 .1uF C26 .1uF C27 .1uF C2_PRES 1 2 3 4 5 6 7 8 9 10 11 EVM12V C28 .1uF P1B2 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# 1 2 3 4 5 6 7 8 9 10 11 P1A2 TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +V I/O RESERVED S_RST# C2_GNT# S_AD30 S_AD28 S_AD26 S_AD24 C2_IDSEL S_AD22 S_AD20 S_AD18 S_AD16 S_FRAME# S_TRDY# S_STOP# C2_PCLK C2_REQ# S_AD31 S_AD29 S_AD27 S_AD25 S_C/BE#3 S_AD23 S_AD21 S_AD19 S_AD17 S_C/BE#2 S_IRDY# S_DEVSEL# S_LOCK# S_PERR# S_SERR# S_C/BE#1 S_AD14 S_AD12 S_AD10 S_AD9 S_C/BE#0 S_AD6 S_AD4 S_AD2 S_AD0 S_REQ64# S_AD13 S_AD11 S_PAR S_AD15 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 RESERVED GND CLK GND REQ# +V I/O AD[31] AD[29] GND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GND AD[12] AD[10] GND RESERVED RST# +V I/O GNT# GND RESERVED AD[30] +3.3V AD[28] AD[26] GND AD[24] IDSEL +3.3V AD[22] AD[20] GND AD[18] AD[16] +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD[15] +3.3V AD[13] AD[11] GND AD[09] S_ACK64# S_REQ64# 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 S_AD8 S_AD7 S_AD5 S_AD3 S_AD1 S_ACK64# AD[08] AD[07] +3.3V AD[05] AD[03] GND AD[01] +V I/O ACK64# +5V +5V PCI Connector B 52 53 54 55 56 57 58 59 60 61 62 52 53 54 55 56 57 58 59 60 61 62 C/BE[0]# +3.3V AD[06] AD[04] GND AD[02] AD[00] +V I/O REQ64# +5V +5V PCI Connector A INTA INTB INTC INTD S_VIO EVM12V EVM5V EVM-12V S_AD[0..31] S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR# S_C/BE#[0..3] Mictor Connector Definition S_IRDY# S_RST# S_FRAME# Board Configuration S_LOCK# C2_REQ# C2_GNT# C2_PCLK C2_IDSEL C2_PRES INTB# INTC# INTD# INTA# Figure 4-2. Schematic Diagram (Sheet 2 of 8) EVM3V C29 .1uF .1uF .1uF .1uF C30 C31 C32 C33 .1uF EVM3V EVM5V S_VIO S_VIO EVM12V EVM12V EVM5V EVM3V C34 .1uF .1uF .1uF C35 C36 EVM5V EVM-12V EVM-12V S_AD[0..31] S_AD[0..31] C37 .1uF C38 .1uF S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR# S_VIO S_DEVSEL# S_TRDY# S_STOP# S_PAR S_PERR# S_SERR# C39 .1uF C40 .1uF C41 .1uF S_C/BE#[0..3] EVM12V S_C/BE#[0..3] S_IRDY# S_RST# C3_PRES S_IRDY# S_RST# 1 2 3 4 5 6 7 8 9 10 11 P1B3 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# 1 2 3 4 5 6 7 8 9 10 11 P1A3 TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +V I/O RESERVED S_FRAME# S_RST# C3_GNT# S_AD30 S_AD28 S_AD26 S_AD24 C3_IDSEL S_AD22 S_AD20 S_AD18 S_AD16 S_FRAME# S_TRDY# S_STOP# C3_PCLK C3_REQ# S_AD31 S_AD29 S_AD27 S_AD25 S_C/BE#3 S_AD23 S_AD21 S_AD19 S_AD17 S_C/BE#2 S_IRDY# S_DEVSEL# S_LOCK# S_PERR# S_SERR# S_C/BE#1 S_AD14 S_AD12 S_AD10 S_AD9 S_C/BE#0 S_AD6 S_AD4 S_AD2 S_AD0 S_REQ64# S_AD13 S_AD11 S_PAR S_AD15 C42 .1uF S_FRAME# S_LOCK# S_LOCK# C3_REQ# C3_GNT# C3_REQ# C3_GNT# C3_PCLK C3_PCLK C3_IDSEL C3_PRES C3_IDSEL C3_PRES 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 RESERVED GND CLK GND REQ# +V I/O AD[31] AD[29] GND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GND AD[12] AD[10] GND RESERVED RST# +V I/O GNT# GND RESERVED AD[30] +3.3V AD[28] AD[26] GND AD[24] IDSEL +3.3V AD[22] AD[20] GND AD[18] AD[16] +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD[15] +3.3V AD[13] AD[11] GND AD[09] 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 S_ACK64# S_AD8 S_AD7 S_AD5 S_AD3 S_AD1 S_ACK64# AD[08] AD[07] +3.3V AD[05] AD[03] GND AD[01] +V I/O ACK64# +5V +5V PCI Connector B 52 53 54 55 56 57 58 59 60 61 62 52 53 54 55 56 57 58 59 60 61 62 C/BE[0]# +3.3V AD[06] AD[04] GND AD[02] AD[00] +V I/O REQ64# +5V +5V PCI Connector A S_REQ64# S_ACK64# S_REQ64# INTC# INTB INTC INTD INTA INTD# INTA# Board Configuration INTB# Mictor Connector Definition Figure 4-2. Schematic Diagram (Sheet 3 of 8) 4-9 4-10 S_AD[0..31] S_AD[0..31] S_C/BE#[0..3] S_RST# S_FRAME# S_IRDY# S_PERR# S_SERR# S_DEVSEL# S_PAR S_TRDY# S_STOP# C1_IDSEL C1_REQ# C1_GNT# S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD9 S_AD8 S_AD7 S_AD6 S_AD5 S_AD4 S_AD3 S_AD2 S_AD1 S_AD0 S_C/BE#[0..3] S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24 S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16 MICTOR CONNECTOR Note: 5 thru-holes are GNDs C2_IDSEL C2_REQ# C2_GNT# C3_IDSEL C3_REQ# C3_GNT# S_CLKOUT3 S_CLKOUT3 INTA# INTB# INTC# INTD# MC1 1 NC1 3 NC3 5 CLKe 7 D15e 9 11 D14e 13 D13e 15 D12e 17 D11e 19 D10e 21 D9e 23 D8e 25 D7e 27 D6e 29 D5e 31 D4e 33 D3e 35 D2e 37 D1e D0e NC2 NC4 CLKo D15o D14o D13o D12o D11o D10o D9o D8o D7o D6o D5o D4o D3o D2o D1o D0o 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 C3_REQ# C3_GNT# C3_IDSEL S_TRDY# C2_REQ# S_IRDY# S_FRAME# C2_GNT# C2_IDSEL C1_REQ# C1_GNT# C1_IDSEL S_ACK64# S_REQ64# MICTOR CONNECTOR Note: 5 thru-holes are GNDs MC2 1 NC1 3 NC3 5 CLKe 7 D15e 9 11 D14e D13e 13 15 D12e 17 D11e 19 D10e 21 D9e 23 D8e 25 D7e 27 D6e 29 D5e 31 D4e 33 D3e 35 D2e 37 D1e D0e NC2 NC4 CLKo D15o D14o D13o D12o D11o D10o D9o D8o D7o D6o D5o D4o D3o D2o D1o D0o INTD# INTC# INTB# INTA# S_RST# S_C/BE#3 S_C/BE#2 S_C/BE#1 S_C/BE#0 S_DEVSEL# S_STOP# S_PERR# S_SERR# S_PAR 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 S_REQ64# S_ACK64# Mictor Connector Definition Board Configuration Figure 4-2. Schematic Diagram (Sheet 4 of 8) S_VIO HS_ENUM# R1 10K HS_ENUM# P_LOCK# P_MFUNC HS_ENUM# 1 2 3 J1 HDR3X1 M .1 S_ACK64# S_REQ64# R2 R3 10K 10K S_VIO S_FRAME# S_IRDY# S_TRDY# S_DEVSEL# S_STOP# S_LOCK# S_PERR# S_SERR# S_RST# HS_SWITCH S_CFN# R4 R5 R6 R7 R8 R9 R11 R12 R13 R14 R15 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K S_VIO S_VIO C43 .01uF S_CFN# R10 47-NFDefault Trace J8 1 2 HDR2X1 M .1-NF S_AD[0..31] S_AD16 S_AD24 S_AD17 S_AD21 S_AD25 S_AD20 INSTALL ONLY ONE RESISTOR / IDSEL S_LOCK# S_MFUNC HS_SWITCH 1 2 3 4 J7 J5 1 2 3 MS1/BPCC MS0 1 2 3 S_VIO J6 HDR4X1 M .1 HDR3X1 M .1 HDR3X1 M .1 S_CFN# S_AD18 S_AD22 S_AD26 S_REQ#0 S_GNT#0 S_REQ#1 S_GNT#1 S_REQ#2 S_GNT#2 S_REQ#3 S_GNT#3 S_REQ#3 S_GNT#3 R18 R20 R21 R31 R32 R33 R34 R35 10K 10K 10K 10K 10K 10K 10K 10K R22 S_VIO S_CLKOUT1 C44 .01uF S_CLKOUT0 R17 0 C2_PCLK R19 0 C1_PCLK C1_IDSEL C2_IDSEL C3_IDSEL R23 R24 47-NF R25 R26 R27 47 R28 47 R29 47-NF R30 47-NF 47-NF47 47-NF 47-NF C1_IDSEL C2_IDSEL C3_IDSEL S_VIO S_REQ#0 S_GNT#0 C47 .01uF S_CLKOUT2 R36 0 C3_PCLK S_REQ#1 S_GNT#1 S_REQ#2 S_GNT#2 R37 R38 R39 R40 R41 R42 0 0 0 0 0 0 C1_REQ# C1_GNT# C2_REQ# C2_GNT# C3_REQ# C3_GNT# S_LOCK# S_FRAME# S_IRDY# S_TRDY# S_DEVSEL# S_STOP# S_PERR# S_RST# S_MFUNC S_ACK64# S_REQ64# S_SERR# Board Configuration 4-11 Mictor Connector Definition P_LOCK# P_MFUNC PULL-UP INTERFACE & CONTROL MODE Figure 4-2. Schematic Diagram (Sheet 5 of 8) P_VCCP P_VCCP PCI12V PCI12V 4-12 P_TDO P1B4 P_IRDY# P_IDSEL P_FRAME# P1A4 P_C/BE#[0..3] P_C/BE#[0..3] P_TDI P_IRDY# P_IDSEL P_FRAME# 1 2 3 4 5 6 7 8 9 10 11 -12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2# P_LOCK# TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +V I/O RESERVED 1 2 3 4 5 6 7 8 9 10 11 P_LOCK# P_RST# P_PCLK P_RST# P_PCLK P_RST# P_GNT# P_PCLK P_REQ# P_AD31 P_AD29 P_AD27 P_AD25 P_C/BE#3 P_AD23 P_AD21 P_AD19 P_AD17 P_C/BE#2 P_FRAME# P_TRDY# P_STOP# P_IRDY# P_DEVSEL# P_LOCK# P_PERR# P_SERR# P_C/BE#1 P_AD14 P_AD12 P_AD10 P_AD18 P_AD16 P_AD22 P_AD20 P_AD24 P_IDSEL P_AD28 P_AD26 P_AD30 P_PAR P_AD15 P_AD13 P_AD11 P_AD9 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 RESERVED GND CLK GND REQ# +V I/O AD[31] AD[29] GND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GND AD[12] AD[10] GND P_C/BE#0 P_AD6 P_AD4 RESERVED RST# +V I/O GNT# GND RESERVED AD[30] +3.3V AD[28] AD[26] GND AD[24] IDSEL +3.3V AD[22] AD[20] GND AD[18] AD[16] +3.3V FRAME# GND TRDY# GND STOP# +3.3V SDONE SBO# GND PAR AD[15] +3.3V AD[13] AD[11] GND AD[09] 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 P_AD8 P_AD7 P_AD5 P_AD3 P_AD1 52 53 54 55 56 57 58 59 60 61 62 AD[08] AD[07] +3.3V AD[05] AD[03] GND AD[01] +V I/O ACK64# +5V +5V PCI Connector B P_AD2 P_AD0 52 53 54 55 56 57 58 59 60 61 62 C/BE[0]# +3.3V AD[06] AD[04] GND AD[02] AD[00] +V I/O REQ64# +5V +5V PCI Connector A INTA INTB INTC INTD PCI5V PCI5V PCI-12V PCI-12V P_AD[0..31] P_AD[0..31] P_DEVSEL# P_TRDY# P_STOP# P_PAR P_DEVSEL# P_TRDY# P_STOP# P_PAR Mictor Connector Definition Board Configuration P_REQ# P_GNT# P_PERR# P_SERR# P_GNT# P_PERR# P_SERR# INTA# INTB# INTC# INTD# Figure 4-2. Schematic Diagram (Sheet 6 of 8) S_C/BE#[0..3] P_C/BE#[0..3] S_AD[0..31] S_C/BE#3 S_C/BE#2 S_C/BE#1 S_C/BE#0 P_C/BE#0 P_C/BE#1 P_C/BE#2 P_C/BE#3 P_AD[0..31] S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24 S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16 S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD9 S_AD8 S_AD7 S_AD6 S_AD5 S_AD4 S_AD3 S_AD2 S_AD1 S_AD0 P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 U5 134 136 137 138 140 141 142 144 146 148 149 150 152 153 155 156 14 16 17 18 20 21 22 24 26 28 29 31 32 33 35 36 145 158 13 25 82 95 107 122 P_C/BE#3 P_C/BE#2 P_C/BE#1 P_C/BE#0 PCI2250 70 72 73 74 76 77 78 79 84 85 87 88 89 91 92 93 109 110 111 113 114 115 117 118 123 124 126 127 129 130 132 133 P_AD31 P_AD30 P_AD29 P_AD28 P_AD27 P_AD26 P_AD25 P_AD24 P_AD23 P_AD22 P_AD21 P_AD20 P_AD19 P_AD18 P_AD17 P_AD16 P_AD15 P_AD14 P_AD13 P_AD12 P_AD11 P_AD10 P_AD9 P_AD8 P_AD7 P_AD6 P_AD5 P_AD4 P_AD3 P_AD2 P_AD1 P_AD0 S_AD0 S_AD1 S_AD2 S_AD3 S_AD4 S_AD5 S_AD6 S_AD7 S_AD8 S_AD9 S_AD10 S_AD11 S_AD12 S_AD13 S_AD14 S_AD15 S_AD16 S_AD17 S_AD18 S_AD19 S_AD20 S_AD21 S_AD22 S_AD23 S_AD24 S_AD25 S_AD26 S_AD27 S_AD28 S_AD29 S_AD30 S_AD31 S_FRAME# S_IRDY# S_TRDY# S_DEVSEL# S_STOP# S_PERR# S_SERR# S_PAR S_RST# S_CFN# S_MFUNC S_CLKOUT4 11 10 9 7 6 4 3 2 48 49 5 51 61 37 43 53 38 44 55 39 45 57 42 47 59 S_FRAME# S_IRDY# S_TRDY# S_DEVSEL# S_STOP# S_PERR# S_SERR# S_PAR# S_RST# S_CFN# S_MFUNC S_CLK S_CLKOUT4 S_REQ#0 S_GNT#0 S_CLKOUT0 S_REQ#1 S_GNT#1 S_CLKOUT1 S_REQ#2 S_GNT#2 S_CLKOUT2 S_REQ#3 S_GNT#3 S_CLKOUT3 S_VCCP S_C/BE#0 S_C/BE#1 S_C/BE#2 S_C/BE#3 SECONDARY PRIMARY P_IDSEL# P_FRAME# P_IRDY# P_TRDY# P_DEVSEL# P_STOP# P_PERR# P_SERR# P_PAR# P_MFUNC P_GNT# P_REQ# P_RST# P_CLK 83 96 97 99 100 101 104 105 106 102 68 69 64 66 63 62 120 159 P_IDSEL P_FRAME# P_IRDY# P_TRDY# P_DEVSEL# P_STOP# P_PERR# P_SERR# P_PAR P_MFUNC P_GNT# P_REQ# P_RST# EVM3V NO/HSLED MS0 MS1/BPCC S_REQ#0 S_GNT#0 S_CLKOUT0 S_REQ#1 S_GNT#1 S_CLKOUT1 S_REQ#2 S_GNT#2 S_CLKOUT2 S_REQ#3 S_GNT#3 S_CLKOUT3 P_VCCP GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 1 12 19 27 34 41 50 54 58 65 71 81 86 94 103 112 119 121 128 135 143 151 157 8 15 23 30 40 46 56 60 75 80 90 98 108 116 125 131 139 147 154 160 52 67 ARBITER & CDC GOZ# NO/HSLED MS0 MS1/BPCC R45 75 P_PCLK C50 15pF S_VIO 1 J9 2 1 J10 2 P_VCCP HDR2X1 M .1-NF PCU3V HDR2X1 M .1-NF Board Configuration 4-13 C51 .1uF C52 .1uF C53 .1uF C54 .1uF C55 .1uF C56 .1uF C57 .1uF C58 .1uF C59 .1uF C60 .1uF C61 .1uF C62 .1uF C63 .1uF C64 .1uF C65 .1uF C66 .1uF C67 .1uF C68 .1uF C69 .1uF C70 .1uF C71 .1uF C72 .1uF C73 .1uF Mictor Connector Definition Figure 4-2. Schematic Diagram (Sheet 7 of 8) TP1 TP2 15uF LT1086C F2 HDR2X1 M .1-NF PCI-12V FUSE R47 196 C78 PCU3V .1uF EVM-12V 1 15uF J11 15uF .1uF Mictor Connector Definition ADJ 2 4-14 3 C74 1 R46 121 C75 FUSE C76 C77 OUT EVM3V PCI12V EVM12V 2 F1 U6 IN F3 EVM5V J12 EVM3V EVM5V C81 HDR3X1 M .1-NF SHORTED 15uF S_VIO 3 2 1 FUSE TP3 C79 47uF .1uF C80 R48 330 HS_ENUM# Red D2 NO/HSLED Red R50 330 C1_PRES Red R51 C2_PRES Red R52 330 C3_PRES Red D6 Green D7 Green D5 330 D4 D3 D1 R49 330 R53 330 R54 330 EVM5V Board Configuration PCI5V EVM3V EVM3V S_VIO S_VIO S_VIO EVM3V PCU3V Figure 4-2. Schematic Diagram (Sheet 8 of 8) Board Description Table 4-4. PCI2250 EVM Bill of Materials Item Qty 1 68 Reference C1 - C42, C51 - C73, C77, C78, C80 C43 C44 C43, C44, C47 C50 C74 - C76, C81 C79 D1 - D5 Part 0.1 F 0 01 F 0.01 F 15 pF 15 F 47 F Red Pkg 805 MFG Phillips Philli s Part No. 08052R104K9BB0 2 3 4 5 6 3 1 4 1 5 805 805 6032 6032 See Diagram See Diagram TH MMC MMC NIC NIC Lumex CE103K2NR CE150J2NO NTC-T156K20TRC NTC-T476K6.3TRC 7 2 D6, D7 Green Lumex 8 9 3 3 F1 - F3 J1, J5, J6 Fuse HDR3X1 M 0.1 HDR4X1 M 0.1 HDR2X1 M 0.1-nF HDR3X1 M 0.1-nF Mictor Connector LittleFuse AMP 251.75 103321-3 10 1 J7 AMP 103321-4 11 4 J8 - J11 AMP 103321-2 12 1 J12 AMP 103321-3 13 2 MC1, MC2 AMP 2-767004-2 14 15 16 2 1 22 P1A1/P1B1, P1A3/P1B3 P1A2/P1B2 R1 - R9, R11 - R15, R18, R20, R21, R31 - R35 R10, R22, R24-R26, R29, R30 R17, R19, R36 - R42 R23, R27, R28 R45 R46 P1A2/P1B2 R47 R48 - R54 TP1-TP3 U5 PCI Connector N/A PCI Connector 10K 805 AMP Capstone KOA 145154-8 CEE2X60SMV-3Z14W RM73B2A103J 17 7 47 nF 805 KOA RM73B2A470J 18 19 20 21 21 22 23 24 25 9 3 1 1 1 1 7 3 1 0 47 75 121 805 805 805 TH KOA KOA KOA NIC Capstone NIC KOA AMP RM73Z2A000 RM73B2A470J RM73B2A750J NMR25F1210B CEE2X60SMV-3Z14W NMR25F1960B RM73B2A331J PCI Connector N/A 196 330 Test Point PCI2250 See Drawing TO-220 TH 805 Texas Instruments Digi-Key PCI2250 26 1 U6 LT1086C LT1086C Board Configuration 4-15 4-16 |
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