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PCI930 3-TO-1 ZOOMED VIDEO SWITCH
SCPS018B - OCTOBER 1997 - REVISED DECEMBER 1997
D D D D
Zoomed Video Switch - Supports up to 3 ZV Sources Designed for Use With the TITM PCI1220/1221 Leadership PC Card Controllers First two (2) ZV Inputs are Controlled by PCI1220/1221 Control Signal Outputs 100% Compliant With the PCMCIA Zoomed Video Standard
D D D D
Status Bit Indicates ZV Activity - Can be Used to Switch a Fourth External ZV Source Switching can be Software Programmed Using Registers in the PCI1220/1221 Low Power 3.3-Volt Core Logic Small Form Factor 128-Pin TQFP Package
description
The 3-to-1 ZV switch is a companion chip to the PCI1220/1221 PC Card controllers; however, it can be used in other applications where multiple ZV sources require external buffering. The ZV switch is a 3:1 multiplexer for the 23 pins defined in the PCMCIA zoomed video interface. The ZV interface includes both the video and audio data as defined by the Zoomed Video Specification. The three ZV source interfaces are referred to as A, B, and C. ZV sources A and B are intended for use with the PCI1220/1221 PC Card zoom video outputs. The third source, C, may be from a variety of external ZV sources. An advanced CMOS process is used to achieve low system-power consumption.
Socket A PC CardTM Socket B 68 PC Card PCI1220 PC Card Controller 68 (See Note 1) PCI Bus
23 23
2 Control Pins
Third ZV Source 23
PCI930 3-to-1 ZV Switch
23
ZV Output to VGA Controller and Audio CODEC
Control Pin (See Note 2) NOTES: 1. The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed video signals too the VGA controller. 2. Control pin for third ZV source (Can Use GPO From PCI1220).
Figure 1. System-Level Diagram for PCI930 with the PCI1220 PC Card Controller
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
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PCI930 3-TO-1 ZOOMED VIDEO SWITCH
SCPS018B - OCTOBER 1997 - REVISED DECEMBER 1997
functional block diagram
PCI Card Sources Source A Source B Switch Circuit Source C
A_xx 23 B_xx 23
C_xx 23 A/B_STAT A/B_SEL C_STAT
Switch Control
ZV_OE RESET
Switch output 23
ZV_STAT ZV_xx
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SCPS018B - OCTOBER 1997 - REVISED DECEMBER 1997
terminal assignments
PCI930 (TOP VIEW)
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
NC A_Y7 A_Y6 A_Y5 A_Y4 VCC A_Y3 A_Y2 A_Y1 A_Y0 A_VSYNC A_HREF RESET GND ZV_OE ZV_STAT ZV_PCLK ZV_SDATA ZV_LRCLK VCC ZV_MCLK ZV_SCLK ZV_UV7 ZV_UV6 ZV_UV5 ZV_UV4 ZV_UV3 GND ZV_UV2 VCCS ZV_UV1 NC NC A_UV0 A_UV1 VCCS GND A_UV2 A_UV3 A_UV4 A_UV5 A_UV6 A_UV7 A_SCLK VCC A_MCLK A_LRCLK A_SDATA A_PCLK B_HREF GND B_VSYNC B_Y0 B_Y1 B_Y2 B_Y3 B_Y4 B_Y5 VCC B_Y6 B_Y7 B_UV0 B_UV1 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC ZV_UV0 ZV_Y7 ZV_Y6 ZV_Y5 VCC ZV_Y4 ZV_Y3 ZV_Y2 ZV_Y1 ZV_Y0 ZV_VSYNC ZV_HREF GND GND GND C_PCLK C_SDATA C_LRCLK VCC C_MCLK C_SCLK C_UV7 C_UV6 C_UV5 C_UV4 C_UV3 GND C_UV2 VCCS C_UV1 NC
NC VCCS B_UV2 B_UV3 GND B_UV4 B_UV5 B_UV6 B_UV7 B_SCLK B_MCLK B_LRCLK VCC B_SDATA B_PCLK A/B_STAT A/B_SEL C_STAT GND C_HREF C_VSYNC C_Y0 C_Y1 C_Y2 C_Y3 C_Y4 VCC C_Y5 C_Y6 C_Y7 C_UV0 NC
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PCI930 3-TO-1 ZOOMED VIDEO SWITCH
SCPS018B - OCTOBER 1997 - REVISED DECEMBER 1997
Table 1. Terminal Assignments Sorted by Pin Number
TERMINAL NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC A_UV0 A_UV1 VCCS GND A_UV2 A_UV3 A_UV4 A_UV5 A_UV6 A_UV7 A_SCLK VCC A_MCLK A_LRCLK A_SDATA A_PCLK B_HREF GND B_VSYNC B_Y0 B_Y1 B_Y2 B_Y3 B_Y4 B_Y5 VCC B_Y6 B_Y7 B_UV0 B_UV1 NC NC VCCS B_UV2 B_UV3 GND B_UV4 B_UV5 B_UV6 B_UV7 B_SCLK B_MCLK NAME NO. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 TERMINAL NAME B_LRCLK VCC B_SDATA B_PCLK A/B_STAT A/B_SEL C_STAT GND C_HREF C_VSYNC C_Y0 C_Y1 C_Y2 C_Y3 C_Y4 VCC C_Y5 C_Y6 C_Y7 C_UV0 NC NC C_UV1 VCCS C_UV2 GND C_UV3 C_UV4 C_UV5 C_UV6 C_UV7 C_SCLK C_MCLK VCC C_LRCLK C_SDATA C_PCLK GND GND GND ZV_HREF ZV_VSYNC ZV_Y0 NO. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 *** TERMINAL NAME ZV_Y1 ZV_Y2 ZV_Y3 ZV_Y4 VCC ZV_Y5 ZV_Y6 ZV_Y7 ZV_UV0 NC NC ZV_UV1 VCCS ZV_UV2 GND ZV_UV3 ZV_UV4 ZV_UV5 ZV_UV6 ZV_UV7 ZV_SCLK ZV_MCLK VCC ZV_LRCLK ZV_SDATA ZV_PCLK ZV_STAT ZV_OE GND RESET A_HREF A_VSYNC A_Y0 A_Y1 A_Y2 A_Y3 VCC A_Y4 A_Y5 A_Y6 A_Y7 NC ***
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Table 2. Terminal Assignments Sorted by Pin Name
TERMINAL NO. 49 48 117 15 14 17 12 16 2 3 6 7 8 9 10 11 118 119 120 121 122 124 125 126 127 18 44 43 47 42 46 30 31 35 36 38 39 40 41 20 21 22 23 NAME A/B_SEL A/B_STAT A_HREF A_LRCLK A_MCLK A_PCLK A_SCLK A_SDATA A_UV0 A_UV1 A_UV2 A_UV3 A_UV4 A_UV5 A_UV6 A_UV7 A_VSYNC A_Y0 A_Y1 A_Y2 A_Y3 A_Y4 A_Y5 A_Y6 A_Y7 B_HREF B_LRCLK B_MCLK B_PCLK B_SCLK B_SDATA B_UV0 B_UV1 B_UV2 B_UV3 B_UV4 B_UV5 B_UV6 B_UV7 B_VSYNC B_Y0 B_Y1 B_Y2 NO. 24 25 26 28 29 52 78 76 80 75 79 50 63 66 68 70 71 72 73 74 53 54 55 56 57 58 60 61 62 5 19 37 51 69 81 82 83 101 115 1 32 33 64 TERMINAL NAME B_Y3 B_Y4 B_Y5 B_Y6 B_Y7 C_HREF C_LRCLK C_MCLK C_PCLK C_SCLK C_SDATA C_STAT C_UV0 C_UV1 C_UV2 C_UV3 C_UV4 C_UV5 C_UV6 C_UV7 C_VSYNC C_Y0 C_Y1 C_Y2 C_Y3 C_Y4 C_Y5 C_Y6 C_Y7 GND GND GND GND GND GND GND GND GND GND NC NC NC NC NO. 65 96 97 128 116 13 27 45 59 77 91 109 123 4 34 67 99 84 110 108 114 112 107 111 113 85 95 98 100 102 103 104 105 106 86 87 88 89 90 92 93 94 *** NC NC NC NC RESET VCC VCC VCC VCC VCC VCC VCC VCC VCCS VCCS VCCS VCCS ZV_HREF ZV_LRCLK ZV_MCLK ZV_OE ZV_PCLK ZV_SCLK ZV_SDATA ZV_STAT ZV_VSYNC ZV_UV0 ZV_UV1 ZV_UV2 ZV_UV3 ZV_UV4 ZV_UV5 ZV_UV6 ZV_UV7 ZV_Y0 ZV_Y1 ZV_Y2 ZV_Y3 ZV_Y4 ZV_Y5 ZV_Y6 ZV_Y7 *** TERMINAL NAME
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PCI930 3-TO-1 ZOOMED VIDEO SWITCH
SCPS018B - OCTOBER 1997 - REVISED DECEMBER 1997
Table 3. ZV Switch Control and Status Terminals
TERMINAL NAME RESET A/B_STAT NO. 116 48 TYPE I I FUNCTION Chip reset. When asserted (driven low), the chip three-states all outputs. In addition, the PCI930 checks for a pullup resistor on the A/B STAT pin as denoted under ZV_xx terminal function. PC Card ZV (Socket 0 or 1) active. This input indicates that either the A or B source from the PC Card controller is active. This signal is used with A/B_SEL to determine which socket ZV source drives the ZV_xx outputs. The A or B source can be passed to ZV_xx if the C source is either of lower precedence, or is not sourcing valid ZV data, as indicated by the C_STAT signal. Socket A/B select. When this pin and A/B_STAT are high, the PC Card socket A ZV data is valid. When this pin is low, and the A/B_STAT input is high, the PC Card socket B ZV data is valid. This input has no meaning if the A/B_STAT input is low. C source status. When this input is high, the ZV source from interface C is valid, and can be driven to the ZV_xx outputs. The C source can be passed to ZV_xx if the A and B sources are either of lower precedence, or A or B is not sourcing valid ZV data. ZV output I/F enable. When this terminal is low, the ZV switch drives the ZV_xx terminals. ZV output status. This terminal is driven high when the ZV switch drives the ZV_xx terminals. When a pullup resistor is present on the A/B_STAT pin during RESET, then the ZV_xx interface is three-stated if the ZV_xx interface is inactive. During the default state, no pullup resistor, a reset drives the ZV_xx interface to a logic low state when inactive.
A/B_SEL
49
I
C_STAT
50
I
ZV_OE ZV_STAT ZV_xx State
114 113 N/A
I O N/A
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Terminal Functions
Table 4. Power Supply Terminal Functions
TERMINAL NAME GND VCC VCCS NO. 5, 19, 51, 69, 81, 82, 83, 101, 115 13, 27, 45, 59, 77, 91, 109, 123 4, 34, 67, 99 TYPE I I I Device ground terminals. 3.3V power supply input for core. Rail input for 5V tolerance on zoom video streams FUNCTION
Table 5. ZV Stream Interface
TERMINAL NAME HREF VSYNC NO. 18, 52, 84, 117 20, 53, 85, 118 A_ = 127, 126, 125, 124, 122, 121, 120, 119 B_ = 29, 28, 26, 25, 24, 23, 22, 21 C_ = 62, 61, 60, 58, 57, 56, 55, 54 ZV_ = 94, 93, 92, 90, 89, 88, 87, 86 A_ = 11, 10, 9, 8, 7, 6, 3, 2 B_ = 41, 40, 39, 38, 36, 35, 31, 30 C_ = 74, 73, 72, 71, 70, 68, 66, 63 ZV_ = 106, 105, 104, 103, 102, 100, 98, 95 12, 42, 75, 107 14, 43, 76, 108 17, 47, 80, 112 15, 44, 78, 110 16, 46, 79, 111 TYPE I I I O I I I O FUNCTION Horizontal sync to ZV port. Vertical sync to ZV port. Video data to ZV port YUV:4:2:2 format. Video data to ZV port YUV:4:2:2 format. Video data to ZV port YUV:4:2:2 format. Video data YUV:4:2:2 format. Video data to ZV port YUV:4:2:2 format. Video data to ZV port YUV:4:2:2 format. Video data to ZV port YUV:4:2:2 format. Video data YUV:4:2:2 format. Audio SCLK PCM signal. Audio MCLK PCM signal. Pixel clock to ZV port. Audio LRCLK PCM signal. Audio PCM data signal.
Y7:0
UV7:0
SCLK MCLK PCLK LRCLK SDATA
Inputs on A, B, and C source ports; Outputs to ZV_xx interface
control settings for ZV switch routing
Table 6 lists termination conditions that can exercise control over the ZV switch and shows the results. Table 6. Termination Conditions
FUNCTION ZV_xx ZV xx inactive state C precedence control CONDITION Pullup resistor on A/B_STAT No pullup resistor on A/B_STAT Pullup resistor on A/B_SEL No pullup resistor on A/B_SEL ZV_xx driven L C takes precedence over A/B. A/B takes precedence over C. RESULT ZV_xx three-stated
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PCI930 3-TO-1 ZOOMED VIDEO SWITCH
SCPS018B - OCTOBER 1997 - REVISED DECEMBER 1997
Table 7 and Table 8 define the control settings that allow the PCI930 to route the ZV data from the three inputs (A_xx, B_xx, or C_xx) to the output (ZV_xx). The Tables are separated based upon the configuration of the PCI930.
D D
Table 7: Table 8:
Output when inputs A/B have precedence over C Output when input C has precedence over A/B Table 7. Output When Inputs A/B Have Precedence Over Input C
INPUTS CONTROL SETTINGS C_XX X Non ZV data ZV data Non ZV data ZV data Non ZV data ZV data Non ZV data A/B_STAT X 0 0 1 1 0 1 1 0 1 1 1 1 0 A/B_SEL X X X 0 0 X 1 1 X 1 0 1 0 X C_STAT X 0 1 X X 1 X X 1 X X X X 1 ZV_OE 1 X X 0 0 0 0 0 0 0 0 0 0 0
A_XX X Non ZV data Non ZV data Non ZV data Non ZV data ZV data ZV data ZV data
B_XX X Non ZV data Non ZV data ZV data ZV data Non ZV data Non ZV data ZV data
OUTPUT at ZV_xx C_xx B_xx B_xx C_xx A_xx A_xx C_xx A_xx B_xx A_xx B_xx C_xx
ZV data Inactive state
ZV data
ZV data
Table 8. Output When Input C Has Precedence Over A/B
INPUTS A_XX X Non ZV data Non ZV data Non ZV data Non ZV data ZV data ZV data ZV data B_XX X Non ZV data Non ZV data ZV data ZV data Non ZV data Non ZV data ZV data C_XX X Non ZV data ZV data Non ZV data ZV data Non ZV data ZV data Non ZV data A/B_STAT X 0 X 1 1 X 1 1 X 1 1 1 ZV data Inactive state ZV data ZV data 1 X CONTROL SETTINGS A/B_SEL X X X 0 0 X 1 1 X 1 0 1 0 X C_STAT X 0 1 0 0 1 0 0 1 0 0 0 0 1 ZV_OE 1 X 0 0 0 0 0 0 0 0 0 0 0 0 OUTPUT at ZV_xx C_xx B_xx B_xx C_xx A_xx A_xx C_xx A_xx B_xx A_xx B_xx C_xx
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SCPS018B - OCTOBER 1997 - REVISED DECEMBER 1997
typical system configuration with PCI1220 PC Card controller
Socket A 68 PC Card Socket B 68 PC Card MFUNC5 GPO4 (160) MFUNC2 ZVSTAT (157) MFUNC4 ZVSEL1 (159) Optional Pullup to Set ZV_xx Inactive VCC 23 23 Optional Pullup to Set C Precedence VCC C_STAT A/B_STAT A/B_SEL A_xx Third ZV Source RESET B_xx C_xx 23 ZV_STAT AZ_OE PCI930 ZV_xx 23 ZV Output to VGA Controller and Audio CODEC System Reset Control PCI1220 PCI Bus
ZV Status Pin
ZV_xx Output Enable
Figure 2. Typical System Configuration for PCI930 With TI PCI1220 PC Card Controller
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V Supply voltage range, VCCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input Clamp Current, IIK (VI < 0 or VI > VCC) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output Clamp Current, IOK (VO < 0 or VO > VCC) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 3. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. ZV terminals are measured with respect to VCCS. The limit specified applies for a DC condition. 4. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. ZV terminals are measured with respect to VCCS. The limit specified applies for a DC condition.
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PCI930 3-TO-1 ZOOMED VIDEO SWITCH
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recommended operating conditions (see Note 5)
PARAMETER VCC VCCS VIH VIL VI VO tt TA TJ Core voltage - Commercial I/O voltage - Commercial High-level input voltage Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time, see Figure 3 Operating ambient temperature range Virtual junction temperature OPERATION 3.3 V 5V MIN 3 4.75 2 0 0 0 0 0 0 25 25 NOM 3.3 5 MAX 3.6 5.25 VCCS 0.8 VCCS VCCS 25 70 115 UNIT V V V V V V ns C C
NOTE 5: Unused or floating pins (input or I/O) must be held high or low. Applies for external input and bidirectional buffers without hysteresis Applies for external output buffers. These junction temperatures reflect simulation conditions. Customer is responsible for verifying junction temperature.
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VOH VOL IOZL IOZH IIL IIH High-level output voltage Low-level output voltage 3-state-output Hi-Z current 3-state-output Hi-Z current Low-level input current# input pins High-level input current A/B_STAT 5.5 V 5.0 V 5.5 V 5.5 V OPERATION TEST CONDITIONS IOH = -3.6 mA IOL = 6.48 mA VI = GND VI = VCC VI = GND VI = VCC VI = 3.0 V MIN 2.15 0.5 -10 10 -1 1 230 230 A MAX UNIT V V A A A
A/B_SEL 5.0 V VI = 3.0 V IOZ is not tested on ZV_STAT(pin 113) due to no Z state. # IIL is not tested on A/B_STAT (pin 48), and A/B_SEL (pin 49) due to internal pulldown resistor.
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PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ tpd CLOAD (pF) 50 50 50 IOL (mA) 8 8 8 IOH (mA) -8 -8 -8 VLOAD (V) 0 3 1.5 From Output Under Test Test Point VLOAD CLOAD IOH IOL
CLOAD includes the typical load-circuit distributed capacitance VLOAD - VOL = 50 , where V OL = 0.6 V, IOL = 8 mA IOL LOAD CIRCUIT Timing Input (see Note A) tsu 90% VCC Data Input 10% VCC tr 50% VCC VCC 50% VCC 0V th VCC 50% VCC tf 0V Low-Level Input tw 50% VCC High-Level Input 50% VCC
VCC 50% VCC 0V
VCC 50% VCC 0V
VOLTAGE WAVEFORMS SETUP AND HOLD TIMES INPUT RISE AND FALL TIMES Output Control (low-level enabling) tPZL 0V tpd In-Phase Output tpd Out-of-Phase Output 50% VCC 50% VCC tpd VOH 50% VCC VOL tpd VOH 50% VCC VOL Waveform 1 (see Notes B and C) tPZH Waveform 2 (see Notes B and C)
VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC 50% VCC 0V tPLZ VCC 50% VCC VOL + 0.3 V VOL VOH VOH - 0.3 V 50% VCC 0V
Input (see Note A)
VCC 50% VCC 50% VCC
50% VCC tPHZ
50% VCC
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the following characteristics: PRR = 1 MHz, ZO = 50 , tr = 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ, VOL and VOH are measured values.
Figure 3. Load Circuit and Voltage Waveforms
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PCI930 3-TO-1 ZOOMED VIDEO SWITCH
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MECHANICAL DATA
PBK (S-PQFP-G128)
0,23 0,13 65
PLASTIC QUAD FLATPACK
0,40 96
0,07 M
97
64
128
33
0,13 NOM
1 12,40 TYP 14,20 SQ 13,80 16,20 SQ 15,80 1,45 1,35
32 Gage Plane
0,05 MIN
0,25 0- 7 0,75 0,45
Seating Plane 1,60 MAX 0,08 4040279-3 / C 11/96 NOTES: D. All linear dimensions are in millimeters. E. This drawing is subject to change without notice. F. Falls within JEDEC MS-026
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Copyright (c) 1998, Texas Instruments Incorporated

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