View SCLS191B_1001102.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS191B - FEBRUARY 1993 - REVISED APRIL 1996
D D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) 2- Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25C Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs
SN54LV164 . . . J OR W PACKAGE SN74LV164 . . . D, DB, OR PW PACKAGE (TOP VIEW)
A B QA QB QC QD GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC QH QG QF QE CLR CLK
SN54LV164 . . . FK PACKAGE (TOP VIEW)
B A NC VCC QH QA NC QB NC QC
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
description
These 8-bit parallel-out serial shift registers are designed for 2.7-V to 5.5-V VCC operation.
QG NC QF NC QE
The 'LV164 feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated serial inputs permit complete control over incoming data as a low at either input inhibits NC - No internal connection entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of the clock (CLK) input. The SN74LV164 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LV164 is characterized for operation over the full military temperature range of -55C to 125C. The SN74LV164 is characterized for operation from -40C to 85C.
QD GND NC CLK CLR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 1996, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
1
SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS191B - FEBRUARY 1993 - REVISED APRIL 1996
FUNCTION TABLE INPUTS CLR L H H H H CLK X L A X X H L X B X X H X L QA L QA0 H L L OUTPUTS QB . . . QH L QB0 QAn QAn QAn L QH0 QGn QGn QGn
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the indicated steady-state inputs conditions were established QAn, QGn = the level of QA or QG before the most recent transition of the clock: indicates a 1-bit shift
logic symbol
CLR CLK 9 8 SRG8 R C1/
A B
1 2
& 1D
3 4 5 6 10 11 12 13
QA QB QC QD QE QF QG QH
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, DB, J, PW, and W packages.
logic diagram (positive logic)
CLK 8
A B
1 2
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
C1 1D R
CLR
9 3 QA 4 QB 5 QC 6 QD 10 QE 11 QF 12 QG 13 QH
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS191B - FEBRUARY 1993 - REVISED APRIL 1996
typical clear, shift, and clear sequences
CLK Serial Inputs A B CLR QA QB QC Outputs QD QE QF QG QH
Clear
Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB or PW package . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS191B - FEBRUARY 1993 - REVISED APRIL 1996
recommended operating conditions (see Note 4)
SN54LV164 MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level High level input voltage Low-level Low level input voltage Input voltage Output voltage High-level High level output current Low-level Low level output current Input transition rise or fall rate VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V 0 -55 VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 2.7 2 3.15 0.8 1.65 VCC VCC -6 -12 6 12 100 125 0 -40 0 0 MAX 5.5 SN74LV164 MIN 2.7 2 3.15 0.8 1.65 VCC VCC -6 -12 6 12 100 85 MAX 5.5 UNIT V V V V V mA mA ns/V C
TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -100 A IOH = -6 mA IOH = -12 mA IOL = 100 A VOL IOL = 6 mA IOL = 12 mA VI = VCC or GND VI = VCC or GND, GND IO = 0 VCC MIN to MAX 3V 4.5 V MIN to MAX 3V 4.5 V 3.6 V 5.5 V 3.6 V 5.5 V 3 V to 3.6 V 3.3 V 5V 2.5 3 SN54LV164 MIN TYP MAX VCC - 0.2 2.4 3.6 0.2 0.4 0.55 1 1 20 20 500 2.5 3 SN74LV164 MIN TYP MAX VCC - 0.2 2.4 3.6 0.2 0.4 0.55 1 1 20 20 500 A A A pF F V UNIT
VOH
V
II ICC
nICC
Ci
One input at VCC - 0.6 V, Other inputs at VCC or GND VI = VCC or GND
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS191B - FEBRUARY 1993 - REVISED APRIL 1996
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
SN54LV164 VCC = 5.5 V 0.5 V MIN fclock tw tsu th Clock frequency Pulse duration CLR low CLK high or low Data Setup time, data before CLK time Hold time, data after CLK CLR inactive 0 14 14 8 5 3 MAX 40 VCC = 3.3 V 0.3 V MIN 0 16 16 10 6 3 MAX 35 VCC = 2.7 V MIN 0 18 18 12 7 3 MAX 30 MHz ns ns ns UNIT
timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
SN74LV164 VCC = 5.5 V 0.5 V MIN fclock tw tsu th Clock frequency Pulse duration CLR low CLK high or low Data Setup time, data before CLK time Hold time, data after CLK CLR inactive 0 14 14 8 5 3 MAX 40 VCC = 3.3 V 0.3 V MIN 0 16 16 10 6 3 MAX 35 VCC = 2.7 V MIN 0 18 18 12 7 3 MAX 30 MHz ns ns ns UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LV164 PARAMETER fmax tpd tPHL CLK CLR Q Q FROM (INPUT) TO (OUTPUT) VCC = 5.5 V 0.5 V MIN TYP MAX 40 90 10 12 20 20 VCC = 3.3 V 0.3 V MIN TYP MAX 35 75 14 16 26 26 VCC = 2.7 V MIN MAX 30 32 32 UNIT MHz ns ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74LV164 PARAMETER fmax tpd tPHL CLK CLR Q Q FROM (INPUT) TO (OUTPUT) VCC = 5.5 V 0.5 V MIN TYP MAX 40 90 10 12 20 20 VCC = 3.3 V 0.3 V MIN TYP MAX 35 75 14 16 26 26 VCC = 2.7 V MIN MAX 30 32 32 UNIT MHz ns ns
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN54LV164, SN74LV164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS191B - FEBRUARY 1993 - REVISED APRIL 1996
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation ca acitance dissi ation capacitance TEST CONDITIONS CL = 50 pF F, f = 10 MHz 5V 75 TYP 3.3 V TYP 74 pF F UNIT
PARAMETER MEASUREMENT INFORMATION
From Output Under Test CL = 50 pF (see Note A) 1 k S1 Vz Open GND 1 k WAVEFORM CONDITION Vm Vi Vz VCC = 4.5 V to 5.5 V 0.5 x VCC VCC 2 x VCC VCC = 2.7 V to 3.6 V 1.5 V 2.7 V 6V Vi Timing Input tw Vi Input Vm Vm 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Vi Vm tPZL VOH Output Vm Vm VOL Output tPHL Vm tPLH VOH Vm VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at Vz (see Note B) tPZH tPLZ Vm tPHZ VOH - 0.3 V VOH 0.5 x Vz VOL + 0.3 V VOL Vm 0V Data Input Vm 0V tsu Vm th Vi Vm 0V TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open Vz GND
LOAD CIRCUIT
Vi Input tPLH Vm Vm 0V tPHL
Output Control
Vm
[0V
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SCLS191B

	To Download SCLS191B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .