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Design Summary for 56GQL (48- and 56-pin functions) MicroStar Junior TM BGA
PCB Design Guidelines
Package Via to Board Land Area Configuration
Package ball via 0.20.05mm Land on PCB PCB A B MicroStar Junior Package Near-Sn/Pb eutectic solder with liquidus temperature of 178C to 210C
Trace Width/Spacing Dimensions (mm [in.]) Non-Solder Mask Defined Pad
0.65 [.0256] 0.30 [.0118] Solder Pad 0.117 [.0046] Trace 0.117 [.0046] min. space 0.65 [.0256]
Trace width/spacing for non-solder mask defined = 0.1167 [.0046] Trace width/spacing for solder mask defined with 0.33 solder pad = 0.0733 [.0029]
(Not to scale) A = Via diameter on package = 0.33 mm (for 0.65-mm pitch) B = Land diameter on PCB Ratio A/B should equal 1.0 for optimum reliability
Solder Ball Collapse
0.2 mm typical
Overall Height < 1.0 mm PCB (Not to scale)
Recommended Board Routing
VCC
Recommended Routing for VFBGA-48 GND VCC
Note: Typical for most devices. Refer to data sheet for specific applications.
VCC
VFBGA Recommended Land Pad Design
Solder Mask Defined Pad
) B
A = 0.43 mm B = 0.33 mm
0.117 MAX [.0042]
GND
0.320 MAX [.0126]
B Recommended Routing for VFBGA-56 GND VCC
Note: Typical for most devices. Refer to data sheet for specific applications.
A Non Solder M ask Defined Pad A = 0.30 mm B = 0.45 mm B A
)
*
0.117 MAX [.0042]
GND
0.320 MAX [.0126]
Geometric Dimensional Tolerances Coplanarity
This geometric dimensioning and tolerancing (GD & T) term 0,08 mm means that this package meets a coplanarity of 0.08 mm as shown below. Coplanarity is defined as a unilateral tolerance zone measured upward from the seating plane. (Reference ASME Y14.51994).
0.08 mm
Position Tolerance
This GD & T term
0,05
is described below:
This is the symbol for true position. True position is defined as the theoretically exact centerline location of the solder ball(s). 0,05 This symbol/number represents how much the centerline of the solder ball(s) is allowed to vary from it's true position. This symbol/letter is defined as the maximum material condition of the solder ball(s) which is 0.45 mm DIA.
The graphic representation is shown below for the top, left solder ball of this package.
Package End
*0.575 mm Package Side Pattern locating boundary for the centerline of the solder ball. (0.05 mm DIA.) True position of the solder ball. Pattern locating boundary containing the collective dimensions of the maximum size of the solder ball (0.45 mm) and the maximum variance of the centerline of the solder ball (0.05 mm) for a total boundary of 0.50 mm DIA. I.E., the solder ball, regardless of size, must fall within this boundary. (Defined as virtual condition per ASME standard Y14.5 - 1994). Please note that a smaller diameter solder ball will have more tolerance in this boundary than the maximum diameter solder ball.
*0.625 mm
* These two dimensions are calculated based on a package with nominal body width and length dimensions.
IR Reflow Profile
Ideal (1st and 2nd) Reflow Profile
Temperature (C)
250 200 150 100 50 0 0 50 100 150 200 Time (seconds) 250 300
Room Temp to 140C: 140C to 160C: Time above 200C: Peak Temp: Time within 5C Peak Temp: Ramp down rate:
60 - 90 sec. 90 - 120 sec. 30 - 60 sec. 235C 5C 10-20 sec. 1 - 3C/sec. max.
Stencil Vitals
Solder Paste
TI recommends the use of paste when mounting MicroStar Junior BGAs. The use of paste offers the following advantages: It acts as a flux to aid wetting of the solder ball to the PCB land. The adhesive properties of the paste will hold the component in place during reflow. Paste contributes to the final volume of solder in the joint, and thus allows this volume to be varied to give an optimum joint. Paste selection is normally driven by overall system assembly requirements. In general, the "no clean" compositions are preferred due to the difficulty in cleaning under the mounted components.
0.3 3m m
0.3 3
mm
Packaging Tape and Reel
12 125 5 t to o1 1 50 50 mi mic cro ro ns ns
T 0.30 0.05
1.55 0.05
D0
2.0 0.1
Y
P2
4.0 0.1
P0
Pin 1 Quadrant E
1.75 0.1
0.2
R 0.3 Typical
45
K0 Y 3.8 P1 A0
1.2
1.6 0.1
D1
6.3
F
B0
A0 B0 K0 F P1 W
4.80 0.1 7.30 0.1 1.50 0.1 7.50 0.1 8.00 0.1 16.00 0.3
Balls face down in pocket Dimensions in millimeters
Feed Direction
Reel Width 16.0
Quantity per reel = 1,000 Dimensions in millimeters (Not to scale)
Reel Diameter 330
Cover Tape Width 13.5
W
48/56GQL (4.5 x 7.0 mm, 0.65 mm pitch)
Package Outline
4,60 4,40 3,25 TYP 0,325 K J 3X Via Hole Without Ball 0,65 H G F E Missing V ia Hole Indicates Pin A1 Quadrant 0,325 D C B A 1,00 MAX 1 Seating Plane 0,45 0,35 0,05 M 0,08 2 3 4 5 6
Pinout
Pinout for 48-pin functions
6 5 4 3 2
5,85 TYP
0,65
A48 NC NC NC NC A1 A
A46 A47 *A45 *A4 A2 A3 B
A43 A44 A42 A7 A5 A6 C
A40 A41 *A39 *A10 A8 A9 D
A37 A38
A36 A35
A33 A32 *A34 *A15
A30 A29 A31 A18 A20 A19 H
A27 A26 *A28 *A21 A23 A22 J
A25 NC NC NC NC A24 K
7,10 6,90
DEVICE YMLLLLS
A11 A12 E
A14 A13 F
A17 A16 G
1
Control
* GND
VCC
Note: This is a topside view
Pinout for 56-pin functions
6 5 4 3 2 1 A54 A55 A56 A1 A2 A3 A A51 A52 A53 A4 A5 A6 B A48 A49 A50 A7 A8 A9 C A45 A47 *A46 *A11 A10 A12 D A13 A14 E A16 A15 F A43 A44 A42 A41 A40 A38 *A39 *A18 A19 A17 G A37 A36 A35 A22 A21 A20 H A34 A33 *A32 *A25 A24 A23 J A31 A30 A29 A28 A27 A26 K
0,25 0,15
Electrical Characteristics
R(ohms) Min. Mean Max. 0.048 0.066 0.116 L(nH) 1.470 2.257 3.965 C(pF) 0.182 0.264 0.430
Control
* GND
VCC
Note: This is a topside view
Package Reliability Data
Test Chip: ALVCH16501, 'B' Die Revision, 85 x 107 mils Preconditioning: JEDEC Level 2 (85C/60% 168 hr + 3IRR 220C)
Thermal Characteristics
Eight Thermal Vias, High K
6.00 5.50 0 lfm @ Tj=150C 150 lfm @ Tj=150C 250 lfm @ Tj=150C 500 lfm @ Tj=150C
Required Sample Size / #Fails 39 / 0 39 / 0 77 / 0 77 / 0 8/0 5/0 5/0 26 / 0 5/0 15 / 0 pass
ALVCH16501GQL Actual Sample Size / # Fails 39 / 0 39 / 0 77 / 0 77 / 0 8/0 5/0 5/0 26 / 0 5/0 15 / 0 pass
Power Dissipation (W)
5.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 20 30 40 50 60 70
Simultaneous Switching Life Test (SSLT), 150C, 300 Hours Highly Accelerated Life Test (HAST), 130C, 85% RH, 100 Hours Temperature Cycle Test, -65C to 150C, 1000 Hours Autoclave, 121C, 96 Hours Solderability, 8 Hours Flammability (UL) Flammability (IEC) Thermal Shock X-Ray, Top View Only
80
90
Ambient Temperature (C) Without Thermal Vias, High K
4.50 4.00 3.50 3.00 2.50 2.00 1.50 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 0 lfm @ Tj=150C 150 lfm @ Tj=150C 250 lfm @ Tj=150C 500 lfm @ Tj=150C
Power Dissipation (W)
Physical Dimensions Manufacturability
Board Level Reliability Data
56 GQL Package Sample Size = 32 Temp Cycle Range -40C to 125C No Underfill
Ambient Temperature (C)
Daisy Chain Net List
56GQL TOP VIEW
6 5 4 3 2 1 A B CD E F G H J K
A1-B3 A2-A3 A4-A5 A6-B4 B5-B6 C6-D5 C4-C5 D4-D6 E5-E6 F5-F6 G4-G6 H4-H5 G5-H6 J5-J6 J4-K6 K4-K5 K2-K3 J3-K1 J1-J2 G2-H1 H2-H3 G1-G3 F1-F2 E1-E2 D1-D3 C2-C3 C1-D1 B1-B2
Board Thickness (mm) 0 cycle 250 cycle 500 cycle 750 cycle 1000 cycle 1250 cycle 1500 cycle 1750 cycle 2000 cycle
* First failure at 951 cycles t = 0.8 mm, with Au, 50% failure = 1733 cycles
1.6 0 0 0 0 2* 15 19 N/A N/A
0.8 0 0 0 0 0 1 8 20 N/A
0.8, no Au 0 0 0 0 0 0 0 1 0
Sockets
Yamaichi Socket Numbers:
VFBGA-56 PN# IC280-056-237
Questions and Answers
Board Design/Electrical Issues
Q. Where can the decoupling capacitors go for the VFBGA package? A. The recommended capacitance value and number of capacitors for decoupling is a 0.1 mF capacitor for each VCC on the VFBGA package. The decoupling capacitors should be connected as close as possible to the GROUND and VCC planes. Q. Any EMI concerns for traces under the package and how can customers design their board to minimize EMI? A. EMI can be controlled by minimizing any complex current loops on the PCB trace. Some helpful hints include: Solid ground and power planes be used in the design. Partitioned ground and power planes must be avoided. These ground and power partitions may create complex current loops increasing radiation. Avoid right angles or "T" crosses on the trace. Right angles can cause impedance mismatch and increase trace capacitance causing signal degradation. Minimize power supply loops by keeping power and ground traces parallel and adjancent to each other. Significant package EMI can be reduced by using this method. Use decoupling capacitors as described in the previous question.
Q. Should I use underfill? A. No, the package qualification results show that this is not necessary and is only an added process expense. Q. Can the boards be repaired? A. Yes, there are rework and repair tools and profiles available (see references 4 and 7). We strongly recommend that removed packages be discarded. Q. How do the board assembly yields of MicroStar Junior BGAs compare to TSSOPs? A. Many customers are initially concerned about assembly yields. However, once they had MicroStar Junior BGAs in production, most of them report improved process yields compared to TSSOPs. This is due to the elimination of bent and misoriented leads, the wider terminal pitch than with 0.5-mm pitch TSSOPs, and the ability of these packages to self align during reflow. The collapsing solder balls also mean that the coplanarity is improved over leaded components. Q. What alignment accuracy is possible? A. Alignment accuracy for the 0.65-mm pitch package is dependent upon board level pad tolerance, placement accuracy, and solder ball position tolerance. Nominal ball position tolerances are specified at 50 microns. These packages are self-aligning during solder reflow, so final alignment accuracy may be better than placement accuracy. Q. Are there specific recommendations for SMT processing? A. Texas Instruments recommends alignment with the solder balls for the CSP package, although it is possible to use the package outline for alignment. Most customers have found they do not need to change their reflow profile. Q. Can the solder joints be inspected after reflow? A. Process yields of 5-ppm rejects are typically seen, so no final inline inspection is required. Some customers are achieving satisfactory results during process setup with lamographic X-ray techniques.
Package (Incoming Inspection)
Q. Is package repair possible? Are tools available? A. Yes, some limited package repair is possible, and there are some semi-auto M/C tools available. However, TI does not guarantee the reliability of repaired packages. Q. Do the solder balls come off during shipping? A. No, this has never been observed. The balls are 100 percent inspected for coplanarity, diameter and other physical properties prior to packing for shipment. Because solder is used during the ball attachment process, uniformly high ball attachment strengths are developed. Also, the ball attachment strength is monitored frequently in the assembly process to prevent ball loss from vibration and other shipping forces.
Lead-Free
Q. Is TI developing a lead-free version of MicroStar Junior BGAs? A. Yes, Texas Instruments is working toward eliminating lead in the solder balls to comply with lead-free environmental policies. The lead-free solder is in final evaluation. Only the solder will change, not the package structure or the mechanical dimensions. The solder system under development is based on Sn-Cu-Ag metallurgy. Check with your local TI Field Sales representative for sample availability.
References
Recommended References:
1. MicroStar BGA Packaging Reference Guide - SSYZ015 2. 96 and 114 ball LFBGA Application Note - IDT, Philips Semiconductor and Texas Instruments 3. Board Level Reliability Evaluations of 40, 32 and 30 Mil Pitch Ball Grid Array Packages Over -40 to 125C - Puligandla Viswanadham, Steve Dunford and Ted Carper, Circuit Card Assemblies Center of Excellence Raytheon Systems Co. 4. Comprehensive User's Guide for BGA*Packages www.intel.com/design/flcomp/packdata/297846.htm 5. Solder Paste Printing Guidelines for BGA and CSP Assemblies - Donald C. Burr, published in SMTJanuary 1999. 6. Maintaining BGA Reliability During Rework - Stuart Downes and Robert Farrell, published in SMT January 1999. 7. BGA Rework Considerations - Jennie S. Hwang, published in SMT November 1998.
Assembly Process/Yield Considerations
Q. What size land diameter for these packages should I design on my board? A. Land size is the key to board-level reliability, and Texas Instruments strongly recommends following the design rules included in this bulletin. Q. Can customers mount MicroStar Junior BGA packages on the bottom side of the PCB board? A. Yes, they can and the ideal 2nd reflow profile is the same as the 1st (IR profile is recommended in the bulletin). The root causes for solder ball off are: Excess amount of solder paste during customers board assembly. TI recommends minimizing the amount of solder paste on the bottom side by using a stencil thickness of 0.15 mm with 0.33-mm aperture opening. Moisture absorption also affects the ball off issue. The package was qualified at Moisture Level 2, and has been released at Moisture Level 2A. The first and second reflow must be completed within 4 weeks.
TI Worldwide Technical Support Internet
TI Semiconductor Home Page
www.ti.com/sc
MicroStar Junior BGA Home Page
www.ti.com/sc/msjunior
TI Distributors
www.ti.com/sc/docs/general/distrib.htm
Logic Overview Page
www.ti.com/sc/logic
Product Information Centers
Americas
Phone Fax Internet +1(972) 644-5580 +1(214) 480-7800 www.ti.com/sc/ampic Phone International Domestic Australia China Hong Kong India Indonesia Korea Malaysia New Zealand Philippines Singapore Taiwan Thailand Fax Email Internet +886-2-23786800 Local Access Code 1-800-881-011 10810 800-96-1111 000-117 001-801-10 080-551-2804 1-800-800-011 000-911 105-11 800-0111-111 080-006800 0019-991-1111 886-2-2378-6808 tiasia@ti.com www.ti.com/sc/apic
Europe, Middle East, and Africa
Phone Belgium (English) France Germany Israel (English) Italy Netherlands (English) Spain Sweden (English) United Kingdom Fax Email Internet +32 (0) 27 45 55 32 +33 (0) 1 30 70 11 64 +49 (0) 8161 80 33 11 1800 949 0107 800 79 11 37 +31 (0) 546 87 95 45 +34 902 35 40 28 +46 (0) 8587 555 22 +44 (0) 1604 66 33 99 +44 (0) 1604 66 33 34 epic@ti.com www.ti.com/sc/epic
TI Number -800-800-1450 -800-800-1450 -800-800-1450 -800-800-1450 -800-800-1450 -800-800-1450 -800-800-1450 -800-800-1450 -800-800-1450 -800-800-1450
Japan
Phone International Domestic Fax International Domestic Internet International Domestic +81-3-3344-5311 0120-81-0026 +81-3-3344-5317 0120-81-0036 www.ti.com/sc/jpic www.tij.co.jp/pic
Important Notice: The products and services of Texas Instruments and its subsidiaries described herein are sold subject to TIs standard terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before placing orders. TI assumes no liability for applications assistance, customers applications or product designs, software performance, or infringement of patents. The publication of information regarding any other companys products or services does not constitute TIs approval, warranty or endorsement thereof.
Asia
MicroStar BGA and MicroStar Junior are trademarks of Texas Instruments Incorporated
(c) Copyright 2000 Texas instruments Incorporated
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